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Fixed BD initialization. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13859 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2020-09-19 10:23:08 +00:00
parent d659db7440
commit 5a80fa2049
3 changed files with 39 additions and 18 deletions
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2
demos/STM32/RT-STM32G474RE-NUCLEO64/cfg/mcuconf.h
View File

@ -86,7 +86,7 @@
#define STM32_ADC12SEL STM32_ADC12SEL_PLLPCLK
#define STM32_ADC345SEL STM32_ADC345SEL_PLLPCLK
#define STM32_QSPISEL STM32_QSPISEL_SYSCLK
#define STM32_RTCSEL STM32_RTCSEL_NOCLOCK
#define STM32_RTCSEL STM32_RTCSEL_LSE
/*
* IRQ system settings.

26
os/hal/ports/STM32/STM32G4xx/hal_lld.c
View File

@ -46,9 +46,22 @@ uint32_t SystemCoreClock = STM32_HCLK;
/* Driver local functions. */
/*===========================================================================*/
/**
* @brief Resets the backup domain.
*/
__STATIC_INLINE void bd_reset(void) {
/* Reset BKP domain if different clock source selected.*/
if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
/* Backup domain reset.*/
RCC->BDCR = RCC_BDCR_BDRST;
RCC->BDCR = 0U;
}
}
/**
* @brief Initializes the backup domain.
* @note WARNING! Changing RTC clock source impossible without resetting
* @note WARNING! Changing RTC clock source impossible without reset
* of the whole BKP domain.
*/
__STATIC_INLINE void bd_init(void) {
@ -57,14 +70,6 @@ __STATIC_INLINE void bd_init(void) {
/* Current settings.*/
bdcr = RCC->BDCR;
/* Reset BKP domain if different clock source selected.*/
if ((bdcr & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
/* Backup domain reset.*/
RCC->BDCR = RCC_BDCR_BDRST;
RCC->BDCR = 0U;
bdcr = 0U;
}
#if HAL_USE_RTC
/* RTC clock enabled.*/
if ((bdcr & RCC_BDCR_RTCEN) == 0) {
@ -146,6 +151,9 @@ void stm32_clock_init(void) {
PWR->CR4 = STM32_PWR_CR4;
PWR->CR5 = STM32_CR5BITS;
/* Backup domain reset.*/
bd_reset();
/* Clocks setup.*/
lse_init();
lsi_init();

29
os/hal/ports/STM32/STM32L5xx/hal_lld.c
View File

@ -52,20 +52,30 @@ uint32_t SystemCoreClock = STM32_HCLK;
/* Driver local functions. */
/*===========================================================================*/
/**
* @brief Resets the backup domain.
*/
__STATIC_INLINE void bd_reset(void) {
/* Reset BKP domain if different clock source selected.*/
if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
/* Backup domain reset.*/
RCC->BDCR = RCC_BDCR_BDRST;
RCC->BDCR = 0U;
}
}
/**
* @brief Initializes the backup domain.
* @note WARNING! Changing RTC clock source impossible without reset
* of the whole BKP domain.
*/
__STATIC_INLINE void bd_init(void) {
uint32_t bdcr;
/* Current settings.*/
bdcr = RCC->BDCR;
/* Reset BKP domain if different clock source selected.*/
if ((bdcr & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
/* Backup domain reset.*/
RCC->BDCR = RCC_BDCR_BDRST;
RCC->BDCR = 0U;
bdcr = 0U;
}
#if HAL_USE_RTC
/* RTC enable.*/
if ((bdcr & RCC_BDCR_RTCEN) == 0U) {
@ -165,6 +175,9 @@ void stm32_clock_init(void) {
PWR->CR3 = STM32_PWR_CR3;
PWR->CR4 = STM32_PWR_CR4;
/* Backup domain reset.*/
bd_reset();
/* Setting the wait states required by MSI clock.*/
flash_ws_init(STM32_MSI_FLASHBITS);