mirror of https://github.com/rusefi/ChibiOS.git
STM32G0 clock initialization rework, to be tested.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14322 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio
parent
1e046d1ca4
commit
70b210860e
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@ -148,6 +148,7 @@
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#error "invalid STM32_MSISRANGE value specified"
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#endif
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/* Some headers do not have this definition.*/
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#if !defined(RCC_CFGR_SWS_MSI)
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#define RCC_CFGR_SWS_MSI 0U
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#endif
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@ -34,7 +34,7 @@
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/**
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* @brief CMSIS system core clock variable.
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* @note It is declared in system_stm32l4xx.h.
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* @note It is declared in system_stm32g0xx.h.
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*/
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uint32_t SystemCoreClock = STM32_HCLK;
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@ -47,46 +47,42 @@ uint32_t SystemCoreClock = STM32_HCLK;
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/*===========================================================================*/
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/**
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* @brief Initializes the backup domain.
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* @note WARNING! Changing RTC clock source impossible without resetting
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* of the whole BKP domain.
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* @brief Resets the backup domain.
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*/
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static void hal_lld_backup_domain_init(void) {
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__STATIC_INLINE void bd_reset(void) {
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/* Reset BKP domain if different clock source selected.*/
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if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
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/* Backup domain reset.*/
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RCC->BDCR = RCC_BDCR_BDRST;
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RCC->BDCR = 0;
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RCC->BDCR = 0U;
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}
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}
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#if STM32_LSE_ENABLED
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/* LSE activation.*/
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#if defined(STM32_LSE_BYPASS)
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/* LSE Bypass.*/
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RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
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#else
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/* No LSE Bypass.*/
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RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
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#endif
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while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
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; /* Wait until LSE is stable. */
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#endif
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/**
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* @brief Initializes the backup domain.
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* @note WARNING! Changing RTC clock source impossible without reset
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* of the whole BKP domain.
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*/
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__STATIC_INLINE void bd_init(void) {
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uint32_t bdcr;
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/* Current settings.*/
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bdcr = RCC->BDCR;
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#if HAL_USE_RTC
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/* If the backup domain hasn't been initialized yet then proceed with
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initialization.*/
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if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
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/* Selects clock source.*/
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RCC->BDCR |= STM32_RTCSEL;
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/* RTC clock enabled.*/
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RCC->BDCR |= RCC_BDCR_RTCEN;
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if ((bdcr & RCC_BDCR_RTCEN) == 0) {
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bdcr |= RCC_BDCR_RTCEN;
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}
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#endif /* HAL_USE_RTC */
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/* Low speed output mode.*/
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RCC->BDCR |= STM32_LSCOSEL;
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/* Selectors.*/
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bdcr &= ~(STM32_RTCSEL_MASK | STM32_LSCOSEL_MASK);
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bdcr |= STM32_RTCSEL | STM32_LSCOSEL;
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/* Final settings.*/
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RCC->BDCR = bdcr;
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}
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/*===========================================================================*/
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@ -104,27 +100,16 @@ static void hal_lld_backup_domain_init(void) {
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*/
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void hal_lld_init(void) {
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/* Reset of all peripherals.*/
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rccResetAHB(~0);
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rccResetAPBR1(~RCC_APBRSTR1_PWRRST);
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rccResetAPBR2(~0);
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/* PWR clock enabled.*/
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rccEnablePWRInterface(true);
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/* Initializes the backup domain.*/
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hal_lld_backup_domain_init();
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/* DMA subsystems initialization.*/
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#if defined(STM32_DMA_REQUIRED)
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dmaInit();
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#endif
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/* NVIC initialization.*/
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nvicInit();
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/* IRQ subsystem initialization.*/
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irqInit();
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/* Programmable voltage detector settings.*/
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PWR->CR2 = STM32_PWR_CR2;
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}
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/**
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@ -137,76 +122,40 @@ void hal_lld_init(void) {
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void stm32_clock_init(void) {
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#if !STM32_NO_INIT
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/* PWR clock enable.*/
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#if defined(HAL_USE_RTC) && defined(RCC_APBENR1_RTCAPBEN)
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RCC->APBENR1 = RCC_APBENR1_PWREN | RCC_APBENR1_RTCAPBEN;
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#else
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RCC->APBENR1 = RCC_APBENR1_PWREN;
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#endif
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/* Reset of all peripherals.*/
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rccResetAHB(~0);
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rccResetAPBR1(~0);
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rccResetAPBR2(~0);
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/* SYSCFG clock enabled here because it is a multi-functional unit shared
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among multiple drivers.*/
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rccEnableAPBR2(RCC_APBENR2_SYSCFGEN, false);
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/* PWR clock enable, backup domain made accessible.*/
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rccEnablePWRInterface(false);
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/* Core voltage setup.*/
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PWR->CR1 = STM32_VOS;
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PWR->CR1 = STM32_VOS | PWR_CR1_DBP;
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while ((PWR->SR2 & PWR_SR2_VOSF) != 0) /* Wait until regulator is */
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; /* stable. */
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#if STM32_HSI16_ENABLED
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/* HSI activation.*/
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RCC->CR |= RCC_CR_HSION | STM32_HSIDIV;
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while ((RCC->CR & RCC_CR_HSIRDY) == 0)
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; /* Wait until HSI16 is stable. */
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#endif
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/* Additional PWR configurations.*/
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PWR->CR2 = STM32_PWR_CR2;
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#if STM32_HSE_ENABLED
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#if defined(STM32_HSE_BYPASS)
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/* HSE Bypass.*/
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RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
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#endif
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/* HSE activation.*/
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RCC->CR |= RCC_CR_HSEON;
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while ((RCC->CR & RCC_CR_HSERDY) == 0)
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; /* Wait until HSE is stable. */
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#endif
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/* Backup domain reset.*/
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bd_reset();
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#if STM32_LSI_ENABLED
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/* LSI activation.*/
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RCC->CSR |= RCC_CSR_LSION;
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while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
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; /* Wait until LSI is stable. */
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#endif
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/* Clocks setup.*/
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lse_init();
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lsi_init();
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hsi16_init();
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hse_init();
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/* Backup domain access enabled and left open.*/
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PWR->CR1 |= PWR_CR1_DBP;
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/* Backup domain initializations.*/
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bd_init();
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#if STM32_LSE_ENABLED
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/* LSE activation.*/
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#if defined(STM32_LSE_BYPASS)
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/* LSE Bypass.*/
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RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
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#else
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/* No LSE Bypass.*/
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RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
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#endif
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while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
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; /* Wait until LSE is stable. */
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#endif
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#if STM32_ACTIVATE_PLL
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/* PLLM and PLLSRC are common to all PLLs.*/
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RCC->PLLCFGR = STM32_PLLR | STM32_PLLREN |
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STM32_PLLQ | STM32_PLLQEN |
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STM32_PLLP | STM32_PLLPEN |
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STM32_PLLN | STM32_PLLM |
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STM32_PLLSRC;
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#endif
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#if STM32_ACTIVATE_PLL
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/* PLL activation.*/
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RCC->CR |= RCC_CR_PLLON;
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/* Waiting for PLL lock.*/
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while ((RCC->CR & RCC_CR_PLLRDY) == 0)
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;
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#endif
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/* PLLs activation, if required.*/
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pll_init();
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/* Other clock-related settings (dividers, MCO etc).*/
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RCC->CFGR = STM32_MCOPRE | STM32_MCOSEL | STM32_PPRE | STM32_HPRE;
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STM32_CECSEL | STM32_USART2SEL | STM32_USART1SEL |
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STM32_LPUART1SEL;
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/* Set flash WS's for SYSCLK source */
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/* Set flash WS's for SYSCLK source.*/
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FLASH->ACR = FLASH_ACR_DBG_SWEN | FLASH_ACR_ICEN | FLASH_ACR_PRFTEN |
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STM32_FLASHBITS;
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while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=
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@ -235,10 +184,6 @@ void stm32_clock_init(void) {
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#endif
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#endif /* STM32_NO_INIT */
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/* SYSCFG clock enabled here because it is a multi-functional unit shared
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among multiple drivers.*/
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rccEnableAPBR2(RCC_APBENR2_SYSCFGEN, true);
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}
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/** @} */
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@ -68,14 +68,6 @@
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#endif
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/** @} */
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/**
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* @name Internal clock sources
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* @{
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*/
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#define STM32_HSI16CLK 16000000U /**< 16MHz internal clock. */
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#define STM32_LSICLK 32000U /**< Low speed internal clock. */
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/** @} */
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/**
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* @name PWR_CR1 register bits definitions
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* @{
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#define STM32_SW_LSI (3U << 0U) /**< SYSCLK source is LSI. */
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#define STM32_SW_LSE (4U << 0U) /**< SYSCLK source is LSE. */
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#define STM32_HPRE_MASK (15U << 8U) /**< HPRE field mask. */
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#define STM32_HPRE_FIELD(n) ((n) << 8U) /**< HPRE field value. */
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#define STM32_HPRE_DIV1 STM32_HPRE_FIELD(0U)
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#define STM32_HPRE_DIV2 STM32_HPRE_FIELD(8U)
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#define STM32_HPRE_DIV4 STM32_HPRE_FIELD(9U)
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#define STM32_HPRE_DIV8 STM32_HPRE_FIELD(10U)
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#define STM32_HPRE_DIV16 STM32_HPRE_FIELD(11U)
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#define STM32_HPRE_DIV64 STM32_HPRE_FIELD(12U)
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#define STM32_HPRE_DIV128 STM32_HPRE_FIELD(13U)
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#define STM32_HPRE_DIV256 STM32_HPRE_FIELD(14U)
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#define STM32_HPRE_DIV512 STM32_HPRE_FIELD(15U)
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#define STM32_PPRE_MASK (7U << 12U) /**< PPRE field mask. */
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#define STM32_PPRE_FIELD(n) ((n) << 12U) /**< PPRE field value. */
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#define STM32_PPRE_DIV1 STM32_PPRE_FIELD(0U)
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#define STM32_PPRE_DIV2 STM32_PPRE_FIELD(4U)
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#define STM32_PPRE_DIV4 STM32_PPRE_FIELD(5U)
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#define STM32_PPRE_DIV8 STM32_PPRE_FIELD(6U)
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#define STM32_PPRE_DIV16 STM32_PPRE_FIELD(7U)
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#define STM32_MCOSEL_MASK (7U << 24U) /**< MCOSEL field mask. */
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#define STM32_MCOSEL_NOCLOCK (0U << 24U) /**< No clock on MCO pin. */
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#define STM32_MCOSEL_SYSCLK (1U << 24U) /**< SYSCLK on MCO pin. */
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@ -708,6 +680,61 @@
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#define STM32_ADCCLK_MAX 350000000
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/** @} */
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/**
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* @name PLL limits
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* @{
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*/
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/**
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* @brief Maximum PLLM value.
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*/
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#define STM32_PLLM_VALUE_MAX 8
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/**
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* @brief Minimum PLLM value.
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*/
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#define STM32_PLLM_VALUE_MIN 1
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/**
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* @brief Maximum PLLN value.
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*/
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#define STM32_PLLN_VALUE_MAX 86
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/**
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* @brief Minimum PLLN value.
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*/
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#define STM32_PLLN_VALUE_MIN 8
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/**
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* @brief Maximum PLLR value.
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*/
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#define STM32_PLLR_VALUE_MAX 8
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/**
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* @brief Minimum PLLR value.
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*/
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#define STM32_PLLR_VALUE_MIN 2
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/**
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* @brief Maximum PLLQ value.
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*/
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#define STM32_PLLQ_VALUE_MAX 8
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/**
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* @brief Minimum PLLQ value.
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*/
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#define STM32_PLLQ_VALUE_MIN 2
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/**
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* @brief Maximum PLLP value.
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*/
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#define STM32_PLLP_VALUE_MAX 32
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/**
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* @brief Minimum PLLP value.
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*/
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#define STM32_PLLP_VALUE_MIN 2
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/** @} */
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/**
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* @name Flash Wait states
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* @{
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@ -754,6 +781,12 @@
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#error "invalid STM32_VOS value specified"
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#endif
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/* Clock handlers.*/
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#include "stm32_lse.inc"
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#include "stm32_lsi.inc"
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#include "stm32_hsi16.inc"
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#include "stm32_hse.inc"
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/*
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* HSI16 related checks.
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*/
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@ -819,21 +852,6 @@
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* HSE related checks.
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*/
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#if STM32_HSE_ENABLED
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#if STM32_HSECLK == 0
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#error "HSE frequency not defined"
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#else /* STM32_HSECLK != 0 */
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#if defined(STM32_HSE_BYPASS)
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#if (STM32_HSECLK < STM32_HSECLK_BYP_MIN) || (STM32_HSECLK > STM32_HSECLK_BYP_MAX)
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#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_BYP_MIN...STM32_HSECLK_BYP_MAX)"
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#endif
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#else /* !defined(STM32_HSE_BYPASS) */
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#if (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
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#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
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#endif
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#endif /* !defined(STM32_HSE_BYPASS) */
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#endif /* STM32_HSECLK != 0 */
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#else /* !STM32_HSE_ENABLED */
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#if STM32_SW == STM32_SW_HSE
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@ -880,15 +898,6 @@
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* LSE related checks.
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*/
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#if STM32_LSE_ENABLED
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#if (STM32_LSECLK == 0)
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#error "LSE frequency not defined"
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#endif
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#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
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#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
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#endif
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#else /* !STM32_LSE_ENABLED */
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#if STM32_RTCSEL == STM32_RTCSEL_LSE
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@ -910,34 +919,32 @@
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*/
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#if (STM32_HSIDIV_VALUE == 1) || defined(__DOXYGEN__)
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#define STM32_HSIDIV STM32_HSIDIV_1
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#elif STM32_HSIDIV_VALUE == 2
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#define STM32_HSIDIV STM32_HSIDIV_2
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#elif STM32_HSIDIV_VALUE == 4
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#define STM32_HSIDIV STM32_HSIDIV_4
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#elif STM32_HSIDIV_VALUE == 8
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#define STM32_HSIDIV STM32_HSIDIV_8
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#elif STM32_HSIDIV_VALUE == 16
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#define STM32_HSIDIV STM32_HSIDIV_16
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#elif STM32_HSIDIV_VALUE == 32
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#define STM32_HSIDIV STM32_HSIDIV_32
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#elif STM32_HSIDIV_VALUE == 64
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#define STM32_HSIDIV STM32_HSIDIV_64
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#elif STM32_HSIDIV_VALUE == 128
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#define STM32_HSIDIV STM32_HSIDIV_128
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#else
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#error "invalid STM32_HSIDIV_VALUE value specified"
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#endif
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/**
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* @brief STM32_PLLM field.
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*/
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#if ((STM32_PLLM_VALUE >= 1) && (STM32_PLLM_VALUE <= 8)) || \
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defined(__DOXYGEN__)
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#define STM32_PLLM ((STM32_PLLM_VALUE - 1) << 4)
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#else
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#error "invalid STM32_PLLM_VALUE value specified"
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#endif
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/**
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* @brief PLL input clock frequency.
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*/
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@ -954,14 +961,6 @@
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#error "invalid STM32_PLLSRC value specified"
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#endif
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/*
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* PLL input frequency range check.
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*/
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#if (STM32_PLLCLKIN != 0) && \
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((STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX))
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#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
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#endif
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/*
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* PLL enable check.
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*/
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@ -973,59 +972,15 @@
|
|||
(STM32_ADCSEL == STM32_ADCSEL_PLLPCLK) || \
|
||||
(STM32_I2S1SEL == STM32_I2S1SEL_PLLPCLK) || \
|
||||
defined(__DOXYGEN__)
|
||||
|
||||
#if STM32_PLLCLKIN == 0
|
||||
#error "PLL activation required but no PLL clock selected"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLL activation flag.
|
||||
*/
|
||||
#define STM32_ACTIVATE_PLL TRUE
|
||||
|
||||
#else
|
||||
#define STM32_ACTIVATE_PLL FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief STM32_PLLN field.
|
||||
*/
|
||||
#if ((STM32_PLLN_VALUE >= 8) && (STM32_PLLN_VALUE <= 86)) || \
|
||||
defined(__DOXYGEN__)
|
||||
#define STM32_PLLN (STM32_PLLN_VALUE << 8)
|
||||
#else
|
||||
#error "invalid STM32_PLLN_VALUE value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief STM32_PLLR field.
|
||||
*/
|
||||
#if ((STM32_PLLR_VALUE >= 2) && (STM32_PLLR_VALUE <= 8)) || \
|
||||
defined(__DOXYGEN__)
|
||||
#define STM32_PLLR ((STM32_PLLR_VALUE - 1) << 29)
|
||||
#else
|
||||
#error "invalid STM32_PLLR_VALUE value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief STM32_PLLQ field.
|
||||
*/
|
||||
#if ((STM32_PLLQ_VALUE >= 2) && (STM32_PLLQ_VALUE <= 8)) || \
|
||||
defined(__DOXYGEN__)
|
||||
#define STM32_PLLQ ((STM32_PLLQ_VALUE - 1) << 25)
|
||||
#else
|
||||
#error "invalid STM32_PLLQ_VALUE value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief STM32_PLLP field.
|
||||
*/
|
||||
#if ((STM32_PLLP_VALUE >= 2) && (STM32_PLLP_VALUE <= 32)) || \
|
||||
defined(__DOXYGEN__)
|
||||
#define STM32_PLLP ((STM32_PLLP_VALUE - 1) << 17)
|
||||
#else
|
||||
#error "invalid STM32_PLLP_VALUE value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief STM32_PLLREN field.
|
||||
*/
|
||||
|
|
@ -1060,57 +1015,8 @@
|
|||
#define STM32_PLLPEN (0 << 16)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLL VCO frequency.
|
||||
*/
|
||||
#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLN_VALUE)
|
||||
|
||||
/*
|
||||
* PLL VCO frequency range check.
|
||||
*/
|
||||
#if STM32_ACTIVATE_PLL && \
|
||||
((STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX))
|
||||
#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLL R output clock frequency.
|
||||
*/
|
||||
#define STM32_PLL_R_CLKOUT (STM32_PLLVCO / STM32_PLLR_VALUE)
|
||||
|
||||
/**
|
||||
* @brief PLL Q output clock frequency.
|
||||
*/
|
||||
#define STM32_PLL_Q_CLKOUT (STM32_PLLVCO / STM32_PLLQ_VALUE)
|
||||
|
||||
/**
|
||||
* @brief PLL P output clock frequency.
|
||||
*/
|
||||
#define STM32_PLL_P_CLKOUT (STM32_PLLVCO / STM32_PLLP_VALUE)
|
||||
|
||||
/*
|
||||
* PLL-R output frequency range check.
|
||||
*/
|
||||
#if STM32_ACTIVATE_PLL && \
|
||||
((STM32_PLL_R_CLKOUT < STM32_PLLR_MIN) || (STM32_PLL_R_CLKOUT > STM32_PLLR_MAX))
|
||||
#error "STM32_PLL_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)"
|
||||
#endif
|
||||
|
||||
/*
|
||||
* PLL-Q output frequency range check.
|
||||
*/
|
||||
#if STM32_ACTIVATE_PLL && \
|
||||
((STM32_PLL_Q_CLKOUT < STM32_PLLQ_MIN) || (STM32_PLL_Q_CLKOUT > STM32_PLLQ_MAX))
|
||||
#error "STM32_PLL_Q_CLKOUT outside acceptable range (STM32_PLLQ_MIN...STM32_PLLQ_MAX)"
|
||||
#endif
|
||||
|
||||
/*
|
||||
* PLL-P output frequency range check.
|
||||
*/
|
||||
#if STM32_ACTIVATE_PLL && \
|
||||
((STM32_PLL_P_CLKOUT < STM32_PLLP_MIN) || (STM32_PLL_P_CLKOUT > STM32_PLLP_MAX))
|
||||
#error "STM32_PLL_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)"
|
||||
#endif
|
||||
/* Inclusion of PLL-related checks and calculations.*/
|
||||
#include <stm32_pll_v2.inc>
|
||||
|
||||
/**
|
||||
* @brief HSISYS clock frequency.
|
||||
|
|
@ -1142,73 +1048,9 @@
|
|||
#error "invalid STM32_SW value specified"
|
||||
#endif
|
||||
|
||||
/* Check on the system clock.*/
|
||||
#if STM32_SYSCLK > STM32_SYSCLK_MAX
|
||||
#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief AHB frequency.
|
||||
*/
|
||||
#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
|
||||
#define STM32_HCLK (STM32_SYSCLK / 1)
|
||||
|
||||
#elif STM32_HPRE == STM32_HPRE_DIV2
|
||||
#define STM32_HCLK (STM32_SYSCLK / 2)
|
||||
|
||||
#elif STM32_HPRE == STM32_HPRE_DIV4
|
||||
#define STM32_HCLK (STM32_SYSCLK / 4)
|
||||
|
||||
#elif STM32_HPRE == STM32_HPRE_DIV8
|
||||
#define STM32_HCLK (STM32_SYSCLK / 8)
|
||||
|
||||
#elif STM32_HPRE == STM32_HPRE_DIV16
|
||||
#define STM32_HCLK (STM32_SYSCLK / 16)
|
||||
|
||||
#elif STM32_HPRE == STM32_HPRE_DIV64
|
||||
#define STM32_HCLK (STM32_SYSCLK / 64)
|
||||
|
||||
#elif STM32_HPRE == STM32_HPRE_DIV128
|
||||
#define STM32_HCLK (STM32_SYSCLK / 128)
|
||||
|
||||
#elif STM32_HPRE == STM32_HPRE_DIV256
|
||||
#define STM32_HCLK (STM32_SYSCLK / 256)
|
||||
|
||||
#elif STM32_HPRE == STM32_HPRE_DIV512
|
||||
#define STM32_HCLK (STM32_SYSCLK / 512)
|
||||
|
||||
#else
|
||||
#error "invalid STM32_HPRE value specified"
|
||||
#endif
|
||||
|
||||
/*
|
||||
* AHB frequency check.
|
||||
*/
|
||||
#if STM32_HCLK > STM32_SYSCLK_MAX
|
||||
#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief APB frequency.
|
||||
*/
|
||||
#if (STM32_PPRE == STM32_PPRE_DIV1) || defined(__DOXYGEN__)
|
||||
#define STM32_PCLK (STM32_HCLK / 1)
|
||||
|
||||
#elif STM32_PPRE == STM32_PPRE_DIV2
|
||||
#define STM32_PCLK (STM32_HCLK / 2)
|
||||
|
||||
#elif STM32_PPRE == STM32_PPRE_DIV4
|
||||
#define STM32_PCLK (STM32_HCLK / 4)
|
||||
|
||||
#elif STM32_PPRE == STM32_PPRE_DIV8
|
||||
#define STM32_PCLK (STM32_HCLK / 8)
|
||||
|
||||
#elif STM32_PPRE == STM32_PPRE_DIV16
|
||||
#define STM32_PCLK (STM32_HCLK / 16)
|
||||
|
||||
#else
|
||||
#error "invalid STM32_PPRE value specified"
|
||||
#endif
|
||||
/* Bus handlers.*/
|
||||
#include "stm32_ahb.inc"
|
||||
#include "stm32_apb.inc"
|
||||
|
||||
/*
|
||||
* Compatibility definitions.
|
||||
|
|
@ -1216,13 +1058,6 @@
|
|||
#define STM32_PCLK1 STM32_PCLK
|
||||
#define STM32_PCLK2 STM32_PCLK
|
||||
|
||||
/*
|
||||
* APB frequency check.
|
||||
*/
|
||||
#if STM32_PCLK > STM32_PCLK_MAX
|
||||
#error "STM32_PCLK exceeding maximum frequency (STM32_PCLK_MAX)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief MCO divider clock frequency.
|
||||
*/
|
||||
|
|
@ -1306,12 +1141,16 @@
|
|||
*/
|
||||
#if (STM32_USART1SEL == STM32_USART1SEL_PCLK) || defined(__DOXYGEN__)
|
||||
#define STM32_USART1CLK STM32_PCLK
|
||||
|
||||
#elif STM32_USART1SEL == STM32_USART1SEL_SYSCLK
|
||||
#define STM32_USART1CLK STM32_SYSCLK
|
||||
|
||||
#elif STM32_USART1SEL == STM32_USART1SEL_HSI16
|
||||
#define STM32_USART1CLK STM32_HSI16CLK
|
||||
|
||||
#elif STM32_USART1SEL == STM32_USART1SEL_LSE
|
||||
#define STM32_USART1CLK STM32_LSECLK
|
||||
|
||||
#else
|
||||
#error "invalid source selected for USART1 clock"
|
||||
#endif
|
||||
|
|
@ -1321,12 +1160,16 @@
|
|||
*/
|
||||
#if (STM32_USART2SEL == STM32_USART2SEL_PCLK) || defined(__DOXYGEN__)
|
||||
#define STM32_USART2CLK STM32_PCLK
|
||||
|
||||
#elif STM32_USART2SEL == STM32_USART2SEL_SYSCLK
|
||||
#define STM32_USART2CLK STM32_SYSCLK
|
||||
|
||||
#elif STM32_USART2SEL == STM32_USART2SEL_HSI16
|
||||
#define STM32_USART2CLK STM32_HSI16CLK
|
||||
|
||||
#elif STM32_USART2SEL == STM32_USART2SEL_LSE
|
||||
#define STM32_USART2CLK STM32_LSECLK
|
||||
|
||||
#else
|
||||
#error "invalid source selected for USART2 clock"
|
||||
#endif
|
||||
|
|
@ -1351,12 +1194,16 @@
|
|||
*/
|
||||
#if (STM32_LPUART1SEL == STM32_LPUART1SEL_PCLK) || defined(__DOXYGEN__)
|
||||
#define STM32_LPUART1CLK STM32_PCLK
|
||||
|
||||
#elif STM32_LPUART1SEL == STM32_LPUART1SEL_SYSCLK
|
||||
#define STM32_LPUART1CLK STM32_SYSCLK
|
||||
|
||||
#elif STM32_LPUART1SEL == STM32_LPUART1SEL_HSI16
|
||||
#define STM32_LPUART1CLK STM32_HSI16CLK
|
||||
|
||||
#elif STM32_LPUART1SEL == STM32_LPUART1SEL_LSE
|
||||
#define STM32_LPUART1CLK STM32_LSECLK
|
||||
|
||||
#else
|
||||
#error "invalid source selected for LPUART1 clock"
|
||||
#endif
|
||||
|
|
@ -1366,8 +1213,10 @@
|
|||
*/
|
||||
#if (STM32_CECSEL == STM32_CECSEL_HSI16DIV) || defined(__DOXYGEN__)
|
||||
#define STM32_CECCLK (STM32_HSI16CLK / 448)
|
||||
|
||||
#elif STM32_CECSEL == STM32_CECSEL_LSE
|
||||
#define STM32_CECCLK STM32_LSECLK
|
||||
|
||||
#else
|
||||
#error "invalid source selected for CEC clock"
|
||||
#endif
|
||||
|
|
@ -1377,10 +1226,13 @@
|
|||
*/
|
||||
#if (STM32_I2C1SEL == STM32_I2C1SEL_PCLK) || defined(__DOXYGEN__)
|
||||
#define STM32_I2C1CLK STM32_PCLK
|
||||
|
||||
#elif STM32_I2C1SEL == STM32_I2C1SEL_SYSCLK
|
||||
#define STM32_I2C1CLK STM32_SYSCLK
|
||||
|
||||
#elif STM32_I2C1SEL == STM32_I2C1SEL_HSI16
|
||||
#define STM32_I2C1CLK STM32_HSI16CLK
|
||||
|
||||
#else
|
||||
#error "invalid source selected for I2C1 clock"
|
||||
#endif
|
||||
|
|
@ -1390,12 +1242,16 @@
|
|||
*/
|
||||
#if (STM32_I2S1SEL == STM32_I2S1SEL_SYSCLK) || defined(__DOXYGEN__)
|
||||
#define STM32_I2S1CLK STM32_SYSCLK
|
||||
|
||||
#elif STM32_I2S1SEL == STM32_I2S1SEL_PLLPCLK
|
||||
#define STM32_I2S1CLK STM32_PLL_P_CLKOUT
|
||||
|
||||
#elif STM32_I2S1SEL == STM32_I2S1SEL_HSI16
|
||||
#define STM32_I2S1CLK STM32_HSI16CLK
|
||||
|
||||
#elif STM32_I2S1SEL == STM32_I2S1SEL_CKIN
|
||||
#define STM32_I2S1CLK 0 /* Unknown, would require a board value */
|
||||
|
||||
#else
|
||||
#error "invalid source selected for I2S1 clock"
|
||||
#endif
|
||||
|
|
@ -1405,12 +1261,16 @@
|
|||
*/
|
||||
#if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_PCLK) || defined(__DOXYGEN__)
|
||||
#define STM32_LPTIM1CLK STM32_PCLK
|
||||
|
||||
#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSI
|
||||
#define STM32_LPTIM1CLK STM32_LSICLK
|
||||
|
||||
#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_HSI16
|
||||
#define STM32_LPTIM1CLK STM32_HSI16CLK
|
||||
|
||||
#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSE
|
||||
#define STM32_LPTIM1CLK STM32_LSECLK
|
||||
|
||||
#else
|
||||
#error "invalid source selected for LPTIM1 clock"
|
||||
#endif
|
||||
|
|
@ -1420,12 +1280,16 @@
|
|||
*/
|
||||
#if (STM32_LPTIM2SEL == STM32_LPTIM2SEL_PCLK) || defined(__DOXYGEN__)
|
||||
#define STM32_LPTIM2CLK STM32_PCLK
|
||||
|
||||
#elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_LSI
|
||||
#define STM32_LPTIM2CLK STM32_LSICLK
|
||||
|
||||
#elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_HSI16
|
||||
#define STM32_LPTIM2CLK STM32_HSI16CLK
|
||||
|
||||
#elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_LSE
|
||||
#define STM32_LPTIM2CLK STM32_LSECLK
|
||||
|
||||
#else
|
||||
#error "invalid source selected for LPTIM2 clock"
|
||||
#endif
|
||||
|
|
@ -1435,12 +1299,16 @@
|
|||
*/
|
||||
#if (STM32_RNGDIV_VALUE == 1) || defined(__DOXYGEN__)
|
||||
#define STM32_RNGDIV (0U << 28U)
|
||||
|
||||
#elif STM32_RNGDIV_VALUE == 2
|
||||
#define STM32_RNGDIV (1U << 28U)
|
||||
|
||||
#elif STM32_RNGDIV_VALUE == 4
|
||||
#define STM32_RNGDIV (2U << 28U)
|
||||
|
||||
#elif STM32_RNGDIV_VALUE == 8
|
||||
#define STM32_RNGDIV (3U << 28U)
|
||||
|
||||
#else
|
||||
#error "invalid STM32_RNGDIV_VALUE value specified"
|
||||
#endif
|
||||
|
|
@ -1450,12 +1318,17 @@
|
|||
*/
|
||||
#if (STM32_RNGSEL == STM32_RNGSEL_NOCLOCK) || defined(__DOXYGEN__)
|
||||
#define STM32_RNGCLK 0
|
||||
|
||||
#elif STM32_RNGSEL == STM32_RNGSEL_HSI16
|
||||
#define STM32_RNGCLK (STM32_HSI16CLK / STM32_RNGDIV_VALUE)
|
||||
|
||||
#elif STM32_RNGSEL == STM32_RNGSEL_SYSCLK
|
||||
#define STM32_RNGCLK (STM32_SYSCLK / STM32_RNGDIV_VALUE)
|
||||
|
||||
#elif STM32_RNGSEL == STM32_RNGSEL_PLLQCLK
|
||||
#define STM32_RNGCLK (STM32_PLL_Q_CLKOUT / STM32_RNGDIV_VALUE)
|
||||
|
||||
|
||||
#else
|
||||
#error "invalid source selected for RNG clock"
|
||||
#endif
|
||||
|
|
@ -1465,10 +1338,13 @@
|
|||
*/
|
||||
#if (STM32_ADCSEL == STM32_ADCSEL_SYSCLK) || defined(__DOXYGEN__)
|
||||
#define STM32_ADCCLK STM32_SYSCLK
|
||||
|
||||
#elif STM32_ADCSEL == STM32_ADCSEL_PLLPCLK
|
||||
#define STM32_ADCCLK STM32_PLL_P_CLKOUT
|
||||
|
||||
#elif STM32_ADCSEL == STM32_ADCSEL_HSI16
|
||||
#define STM32_ADCCLK STM32_HSI16CLK
|
||||
|
||||
#else
|
||||
#error "invalid source selected for ADC clock"
|
||||
#endif
|
||||
|
|
@ -1478,6 +1354,7 @@
|
|||
*/
|
||||
#if (STM32_PPRE == STM32_PPRE_DIV1) || defined(__DOXYGEN__)
|
||||
#define STM32_TIMPCLK (STM32_PCLK * 1)
|
||||
|
||||
#else
|
||||
#define STM32_TIMPCLK (STM32_PCLK * 2)
|
||||
#endif
|
||||
|
|
@ -1487,8 +1364,10 @@
|
|||
*/
|
||||
#if (STM32_TIM1SEL == STM32_TIM1SEL_TIMPCLK) || defined(__DOXYGEN__)
|
||||
#define STM32_TIM1CLK STM32_TIMPCLK
|
||||
|
||||
#elif STM32_TIM1SEL == STM32_TIM1SEL_PLLQCLK
|
||||
#define STM32_TIM1CLK STM32_PLL_Q_CLKOUT
|
||||
|
||||
#else
|
||||
#error "invalid source selected for TIM1 clock"
|
||||
#endif
|
||||
|
|
@ -1498,8 +1377,10 @@
|
|||
*/
|
||||
#if (STM32_TIM15SEL == STM32_TIM15SEL_TIMPCLK) || defined(__DOXYGEN__)
|
||||
#define STM32_TIM15CLK STM32_TIMPCLK
|
||||
|
||||
#elif STM32_TIM15SEL == STM32_TIM15SEL_PLLQCLK
|
||||
#define STM32_TIM15CLK STM32_PLL_Q_CLKOUT
|
||||
|
||||
#else
|
||||
#error "invalid source selected for TIM15 clock"
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@ include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/driver.mk
|
|||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/driver.mk
|
||||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk
|
||||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/driver.mk
|
||||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/RCCv1/driver.mk
|
||||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/RNGv1/driver.mk
|
||||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv3/driver.mk
|
||||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver.mk
|
||||
|
|
|
|||
|
|
@ -84,6 +84,23 @@
|
|||
#define STM32_HAS_CRYP1 FALSE
|
||||
#endif
|
||||
|
||||
/* RCC attributes (common).*/
|
||||
#define STM32_RCC_HAS_HSI16 TRUE
|
||||
#define STM32_RCC_HAS_HSI48 FALSE
|
||||
#define STM32_RCC_HAS_MSI FALSE
|
||||
#define STM32_RCC_HAS_LSI TRUE
|
||||
#define STM32_RCC_HAS_LSI_PRESCALER FALSE
|
||||
#define STM32_RCC_HAS_LSE TRUE
|
||||
#define STM32_RCC_HAS_HSE TRUE
|
||||
|
||||
#define STM32_RCC_HAS_PLL TRUE
|
||||
#define STM32_RCC_PLL_HAS_P TRUE
|
||||
/*#define STM32_RCC_PLL_HAS_Q TRUE*/ /* Varies, see below.*/
|
||||
#define STM32_RCC_PLL_HAS_R TRUE
|
||||
|
||||
#define STM32_RCC_HAS_PLLSAI1 FALSE
|
||||
#define STM32_RCC_HAS_PLLSAI2 FALSE
|
||||
|
||||
/* SPI attributes. */
|
||||
#define STM32_HAS_SPIR FALSE
|
||||
|
||||
|
|
@ -161,6 +178,9 @@
|
|||
/* QUADSPI attributes.*/
|
||||
#define STM32_HAS_QUADSPI1 FALSE
|
||||
|
||||
/* RCC attributes.*/
|
||||
#define STM32_RCC_PLL_HAS_Q FALSE
|
||||
|
||||
/* SDMMC attributes.*/
|
||||
#define STM32_HAS_SDMMC1 FALSE
|
||||
#define STM32_HAS_SDMMC2 FALSE
|
||||
|
|
@ -339,6 +359,9 @@
|
|||
/* QUADSPI attributes.*/
|
||||
#define STM32_HAS_QUADSPI1 FALSE
|
||||
|
||||
/* RCC attributes.*/
|
||||
#define STM32_RCC_PLL_HAS_Q TRUE
|
||||
|
||||
/* SDMMC attributes.*/
|
||||
#define STM32_HAS_SDMMC1 FALSE
|
||||
#define STM32_HAS_SDMMC2 FALSE
|
||||
|
|
|
|||
|
|
@ -133,6 +133,10 @@ void stm32_clock_init(void) {
|
|||
rccResetAPB1R2(~0);
|
||||
rccResetAPB2(~0);
|
||||
|
||||
/* SYSCFG clock enabled here because it is a multi-functional unit shared
|
||||
among multiple drivers.*/
|
||||
rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, false);
|
||||
|
||||
/* PWR clock enable.*/
|
||||
#if (HAL_USE_RTC == TRUE) && defined(RCC_APBENR1_RTCAPBEN)
|
||||
rccEnableAPB1R1(RCC_APB1ENR1_PWREN | RCC_APB1ENR1_RTCAPBEN, false)
|
||||
|
|
@ -180,7 +184,7 @@ void stm32_clock_init(void) {
|
|||
STM32_USART1SEL;
|
||||
RCC->CCIPR2 = STM32_QSPISEL | STM32_I2C4SEL;
|
||||
|
||||
/* Set flash WS's for SYSCLK source */
|
||||
/* Set flash WS's for SYSCLK source.*/
|
||||
FLASH->ACR = FLASH_ACR_DBG_SWEN | FLASH_ACR_DCEN | FLASH_ACR_ICEN |
|
||||
FLASH_ACR_PRFTEN | STM32_FLASHBITS;
|
||||
while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) !=
|
||||
|
|
@ -195,10 +199,6 @@ void stm32_clock_init(void) {
|
|||
;
|
||||
#endif
|
||||
|
||||
/* SYSCFG clock enabled here because it is a multi-functional unit shared
|
||||
among multiple drivers.*/
|
||||
rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true);
|
||||
|
||||
#endif /* STM32_NO_INIT */
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -136,13 +136,13 @@ void stm32_clock_init(void) {
|
|||
FLASH->ACR = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_PRFTEN |
|
||||
STM32_MSI_FLASHBITS;
|
||||
|
||||
/* PWR clock enabled.*/
|
||||
rccEnablePWRInterface(false);
|
||||
|
||||
/* SYSCFG clock enabled here because it is a multi-functional unit shared
|
||||
among multiple drivers.*/
|
||||
rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, false);
|
||||
|
||||
/* PWR clock enabled.*/
|
||||
rccEnablePWRInterface(false);
|
||||
|
||||
/* Core voltage setup, backup domain access enabled and left open.*/
|
||||
PWR->CR1 = STM32_VOS | PWR_CR1_DBP;
|
||||
while ((PWR->SR2 & PWR_SR2_VOSF) != 0) /* Wait until regulator is */
|
||||
|
|
|
|||
|
|
@ -136,13 +136,13 @@ void stm32_clock_init(void) {
|
|||
FLASH->ACR = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_PRFTEN |
|
||||
STM32_MSI_FLASHBITS;
|
||||
|
||||
/* PWR clock enabled.*/
|
||||
rccEnablePWRInterface(false);
|
||||
|
||||
/* SYSCFG clock enabled here because it is a multi-functional unit shared
|
||||
among multiple drivers.*/
|
||||
rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, false);
|
||||
|
||||
/* PWR clock enabled.*/
|
||||
rccEnablePWRInterface(false);
|
||||
|
||||
/* Core voltage setup, backup domain access enabled and left open.*/
|
||||
PWR->CR1 = STM32_VOS | PWR_CR1_DBP;
|
||||
while ((PWR->SR2 & PWR_SR2_VOSF) != 0) /* Wait until regulator is */
|
||||
|
|
|
|||
|
|
@ -158,6 +158,10 @@ void stm32_clock_init(void) {
|
|||
secflags = RCC->SECSR;
|
||||
#endif
|
||||
|
||||
/* SYSCFG clock enabled here because it is a multi-functional unit shared
|
||||
among multiple drivers.*/
|
||||
rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, false);
|
||||
|
||||
/* PWR clock enable.*/
|
||||
#if defined(HAL_USE_RTC) && defined(RCC_APB1ENR1_RTCAPBEN)
|
||||
RCC->APB1ENR1 = RCC_APB1ENR1_PWREN | RCC_APB1ENR1_RTCAPBEN;
|
||||
|
|
@ -268,10 +272,6 @@ void stm32_clock_init(void) {
|
|||
/* Cache enable.*/
|
||||
icache_init();
|
||||
|
||||
/* SYSCFG clock enabled here because it is a multi-functional unit shared
|
||||
among multiple drivers.*/
|
||||
rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true);
|
||||
|
||||
#endif /* STM32_NO_INIT */
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue