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ChibiOS
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More changes caused by #913. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11346 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio 2018-01-19 11:01:48 +00:00
parent 0c379c379b
commit 86fed9342d
13 changed files with 13 additions and 12 deletions
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2
demos/STM32/NIL-STM32F746G-DISCOVERY/mcuconf.h
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@ -90,7 +90,7 @@
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_CECSEL STM32_CECSEL_LSE
#define STM32_CK48MSEL STM32_CK48MSEL_PLL
#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK
#define STM32_SDMMC1SEL STM32_SDMMC1SEL_PLL48CLK
#define STM32_SRAM2_NOCACHE FALSE
/*

2
demos/STM32/RT-STM32F746G-DISCOVERY/mcuconf.h
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@ -90,7 +90,7 @@
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_CECSEL STM32_CECSEL_LSE
#define STM32_CK48MSEL STM32_CK48MSEL_PLL
#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK
#define STM32_SDMMC1SEL STM32_SDMMC1SEL_PLL48CLK
#define STM32_SRAM2_NOCACHE FALSE
/*

2
demos/STM32/RT-STM32F746ZG-NUCLEO144/mcuconf.h
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@ -90,7 +90,7 @@
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_CECSEL STM32_CECSEL_LSE
#define STM32_CK48MSEL STM32_CK48MSEL_PLL
#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK
#define STM32_SDMMC1SEL STM32_SDMMC1SEL_PLL48CLK
#define STM32_SRAM2_NOCACHE FALSE
/*

2
os/hal/ports/STM32/STM32L4xx/hal_lld.h
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@ -2103,7 +2103,7 @@
/**
* @brief SDMMC frequency.
*/
#define STM32_SDMMCCLK STM32_48CLK
#define STM32_SDMMC1CLK STM32_48CLK
/**
* @brief Clock of timers connected to APB1

1
readme.txt
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@ -166,6 +166,7 @@
dependencies and configuration directories. This makes possible
to have multiple non-conflicting makefiles in the same project.
Updated the various platform.mk implementing "smart build" mode.
- HAL: Fixed Clock selection for SDMMC2 missing in STM32F7 HAL (bug #913).
- HAL: Fixed STM32 SDMMCv1 driver not setting DMA channel properly for SDCD2
instance (bug #912)(backported to 17.6.4).
- LIB: Fixed inner semaphore not updated in chGuardedPoolAllocI() function

2
testhal/STM32/STM32F7xx/GPT-ADC/mcuconf.h
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@ -90,7 +90,7 @@
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_CECSEL STM32_CECSEL_LSE
#define STM32_CK48MSEL STM32_CK48MSEL_PLL
#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK
#define STM32_SDMMC1SEL STM32_SDMMC1SEL_PLL48CLK
#define STM32_SRAM2_NOCACHE FALSE
/*

2
testhal/STM32/STM32F7xx/IRQ_STORM/mcuconf.h
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@ -90,7 +90,7 @@
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_CECSEL STM32_CECSEL_LSE
#define STM32_CK48MSEL STM32_CK48MSEL_PLL
#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK
#define STM32_SDMMC1SEL STM32_SDMMC1SEL_PLL48CLK
#define STM32_SRAM2_NOCACHE FALSE
/*

2
testhal/STM32/STM32F7xx/PWM-ICU/mcuconf.h
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@ -90,7 +90,7 @@
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_CECSEL STM32_CECSEL_LSE
#define STM32_CK48MSEL STM32_CK48MSEL_PLL
#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK
#define STM32_SDMMC1SEL STM32_SDMMC1SEL_PLL48CLK
#define STM32_SRAM2_NOCACHE FALSE
/*

2
testhal/STM32/STM32F7xx/SPI/mcuconf.h
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@ -90,7 +90,7 @@
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_CECSEL STM32_CECSEL_LSE
#define STM32_CK48MSEL STM32_CK48MSEL_PLL
#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK
#define STM32_SDMMC1SEL STM32_SDMMC1SEL_PLL48CLK
#define STM32_SRAM2_NOCACHE FALSE
/*

2
testhal/STM32/STM32F7xx/USB_RAW/mcuconf.h
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@ -90,7 +90,7 @@
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_CECSEL STM32_CECSEL_LSE
#define STM32_CK48MSEL STM32_CK48MSEL_PLL
#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK
#define STM32_SDMMC1SEL STM32_SDMMC1SEL_PLL48CLK
#define STM32_SRAM2_NOCACHE FALSE
/*

2
testhal/STM32/multi/PAL/cfg-stm32f746_discovery/mcuconf.h
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@ -90,7 +90,7 @@
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_CECSEL STM32_CECSEL_LSE
#define STM32_CK48MSEL STM32_CK48MSEL_PLL
#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK
#define STM32_SDMMC1SEL STM32_SDMMC1SEL_PLL48CLK
#define STM32_SRAM2_NOCACHE FALSE
/*

2
testhal/STM32/multi/UART/cfg-stm32f746_discovery/mcuconf.h
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@ -90,7 +90,7 @@
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_CECSEL STM32_CECSEL_LSE
#define STM32_CK48MSEL STM32_CK48MSEL_PLL
#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK
#define STM32_SDMMC1SEL STM32_SDMMC1SEL_PLL48CLK
#define STM32_SRAM2_NOCACHE FALSE
/*

2
testhal/STM32/multi/USB_CDC/cfg-stm32f746_discovery/mcuconf.h
View File

@ -90,7 +90,7 @@
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_CECSEL STM32_CECSEL_LSE
#define STM32_CK48MSEL STM32_CK48MSEL_PLL
#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK
#define STM32_SDMMC1SEL STM32_SDMMC1SEL_PLL48CLK
#define STM32_SRAM2_NOCACHE FALSE
/*