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Enforced PWR_CR1_DBP for default configuration. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14392 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2021-05-19 07:00:59 +00:00
parent da9a06d3c3
commit b9f314c50b
1 changed files with 1 additions and 1 deletions
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2
os/hal/ports/STM32/STM32G4xx/hal_lld.c
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@ -65,7 +65,7 @@ const halclkcfg_t hal_clkcfg_reset = {
* @brief Default clock configuration.
*/
const halclkcfg_t hal_clkcfg_default = {
.pwr_cr1 = STM32_VOS_RANGE1,
.pwr_cr1 = STM32_VOS_RANGE1 | PWR_CR1_DBP,
.pwr_cr2 = STM32_PWR_CR2,
.pwr_cr3 = STM32_PWR_CR3,
.pwr_cr4 = STM32_PWR_CR4,