mirror of https://github.com/rusefi/ChibiOS.git
CP4 FPU support apparently working.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3592 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio
parent
26dc203d65
commit
c17fbc9313
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***************************************************************************
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Options: -O2 -fomit-frame-pointer -falign-functions=16
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Settings: SYSCLK=168, ACR=0x705 (5 wait states)
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***************************************************************************
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*** ChibiOS/RT test suite
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***
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*** Kernel: 2.3.5unstable
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*** Compiled: Dec 11 2011 - 17:14:07
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*** Compiler: GCC 4.6.2
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*** Architecture: ARMv7-ME
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*** Core Variant: Cortex-M4F
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*** Port Info: Advanced kernel mode
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*** Platform: STM32F4 High Performance & DSP
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*** Test Board: ST STM32F4-Discovery
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----------------------------------------------------------------------------
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--- Test Case 1.1 (Threads, enqueuing test #1)
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 1.2 (Threads, enqueuing test #2)
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 1.3 (Threads, priority change)
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 1.4 (Threads, delays)
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 2.1 (Semaphores, enqueuing)
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 2.2 (Semaphores, timeout)
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 2.3 (Semaphores, atomic signal-wait)
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 2.4 (Binary Semaphores, functionality)
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 3.1 (Mutexes, priority enqueuing test)
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 3.2 (Mutexes, priority inheritance, simple case)
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 3.3 (Mutexes, priority inheritance, complex case)
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 3.4 (Mutexes, priority return)
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 3.5 (Mutexes, status)
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 3.6 (CondVar, signal test)
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 3.7 (CondVar, broadcast test)
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 3.8 (CondVar, boost test)
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 4.1 (Messages, loop)
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 5.1 (Mailboxes, queuing and timeouts)
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 6.1 (Events, registration and dispatch)
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 6.2 (Events, wait and broadcast)
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 6.3 (Events, timeouts)
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 7.1 (Heap, allocation and fragmentation test)
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 8.1 (Memory Pools, queue/dequeue)
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 9.1 (Dynamic APIs, threads creation from heap)
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool)
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 9.3 (Dynamic APIs, registry and references)
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 10.1 (Queues, input queues)
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 10.2 (Queues, output queues)
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.1 (Benchmark, messages #1)
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--- Score : 559399 msgs/S, 1118798 ctxswc/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.2 (Benchmark, messages #2)
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--- Score : 476758 msgs/S, 953516 ctxswc/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.3 (Benchmark, messages #3)
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--- Score : 476757 msgs/S, 953514 ctxswc/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.4 (Benchmark, context switch)
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--- Score : 1639312 ctxswc/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.5 (Benchmark, threads, full cycle)
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--- Score : 371289 threads/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.6 (Benchmark, threads, create only)
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--- Score : 496514 threads/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads)
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--- Score : 151014 reschedules/S, 906084 ctxswc/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.8 (Benchmark, round robin context switching)
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--- Score : 1018620 ctxswc/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.9 (Benchmark, I/O Queues throughput)
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--- Score : 1766592 bytes/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.10 (Benchmark, virtual timers set/reset)
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--- Score : 1997950 timers/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.11 (Benchmark, semaphores wait/signal)
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--- Score : 2601996 wait+signal/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.12 (Benchmark, mutexes lock/unlock)
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--- Score : 1766592 lock+unlock/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.13 (Benchmark, RAM footprint)
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--- System: 648 bytes
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--- Thread: 72 bytes
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--- Timer : 20 bytes
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--- Semaph: 12 bytes
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--- EventS: 4 bytes
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--- EventL: 12 bytes
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--- Mutex : 16 bytes
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--- CondV.: 8 bytes
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--- Queue : 32 bytes
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--- MailB.: 40 bytes
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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Final result: SUCCESS
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@ -33,10 +33,10 @@
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*/
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#if CORTEX_USE_FPU || defined(__DOXYGEN__)
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#define PUSH_CONTEXT() { \
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asm volatile ("vpush {s16-s31}" \
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: : : "memory"); \
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asm volatile ("push {r4, r5, r6, r7, r8, r9, r10, r11, lr}" \
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: : : "memory"); \
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asm volatile ("vpush {s16-s31}" \
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: : : "memory"); \
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}
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#else /* !CORTEX_USE_FPU */
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#define PUSH_CONTEXT() { \
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@ -50,10 +50,10 @@
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*/
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#if CORTEX_USE_FPU || defined(__DOXYGEN__)
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#define POP_CONTEXT() { \
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asm volatile ("pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}" \
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: : : "memory"); \
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asm volatile ("vpop {s16-s31}" \
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: : : "memory"); \
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asm volatile ("pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}" \
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: : : "memory"); \
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}
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#else /* !CORTEX_USE_FPU */
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#define POP_CONTEXT() { \
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@ -99,21 +99,20 @@ CH_IRQ_HANDLER(SysTickVector) {
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*/
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void SVCallVector(void) {
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uint32_t *psp;
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register struct extctx *ctxp;
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/* Current PSP value.*/
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asm volatile ("mrs %0, PSP" : "=r" (psp) : : "memory");
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/* Discarding the current exception context and positioning the stack to
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point to the real one.*/
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psp = (uint32_t *)((struct extctx *)psp + 1);
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#if CORTEX_USE_FPU
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/* Restoring the special registers SCB_FPCCR and FPCAR.*/
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SCB_FPCAR = *psp++;
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SCB_FPCCR = *psp++;
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#endif
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/* Discarding the current exception context and positioning the stack to
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point to the real one.*/
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ctxp = (struct extctx *)psp + 1;
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asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory");
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asm volatile ("msr PSP, %0" : : "r" (psp) : "memory");
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port_unlock_from_isr();
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}
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#endif /* !CORTEX_SIMPLIFIED_PRIORITY */
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@ -127,21 +126,20 @@ void SVCallVector(void) {
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*/
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void PendSVVector(void) {
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uint32_t *psp;
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register struct extctx *ctxp;
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/* Current PSP value.*/
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asm volatile ("mrs %0, PSP" : "=r" (psp) : : "memory");
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/* Discarding the current exception context and positioning the stack to
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point to the real one.*/
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psp = (uint32_t *)((struct extctx *)psp + 1);
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#if CORTEX_USE_FPU
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/* Restoring the special registers SCB_FPCCR and FPCAR.*/
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SCB_FPCAR = *psp++;
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SCB_FPCCR = *psp++;
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#endif
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/* Discarding the current exception context and positioning the stack to
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point to the real one.*/
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ctxp = (struct extctx *)psp + 1;
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asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory");
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asm volatile ("msr PSP, %0" : : "r" (psp) : "memory");
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}
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#endif /* CORTEX_SIMPLIFIED_PRIORITY */
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SCB_FPDSCR = reg;
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/* Initializing the FPU context save in lazy mode.*/
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SCB_FPCCR = FPCCR_LSPEN;
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SCB_FPCCR = FPCCR_ASPEN | FPCCR_LSPEN;
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#endif
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/* Initialization of the system vectors used by the port.*/
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@ -210,7 +208,7 @@ void _port_irq_epilogue(void) {
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/* Adding an artificial exception return context, there is no need to
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populate it fully.*/
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ctxp = (struct extctx *)psp - 1;
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ctxp = ((struct extctx *)psp) - 1;
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asm volatile ("msr PSP, %0" : : "r" (ctxp) : "memory");
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ctxp->pc = _port_switch_from_isr;
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ctxp->xpsr = (regarm_t)0x01000000;
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@ -47,7 +47,7 @@
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* @details Activating this option will make the Kernel work in compact mode.
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*/
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#if !defined(CORTEX_USE_FPU)
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#define CORTEX_USE_FPU FALSE/*CORTEX_HAS_FPU*/
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#define CORTEX_USE_FPU CORTEX_HAS_FPU
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#elif CORTEX_USE_FPU && !CORTEX_HAS_FPU
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/* This setting requires an FPU presence check in case it is externally
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redefined.*/
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@ -183,22 +183,12 @@ struct extctx {
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regarm_t s13;
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regarm_t s14;
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regarm_t s15;
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regarm_t s16;
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regarm_t fpscr;
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regarm_t reserved;
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#endif /* CORTEX_USE_FPU */
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};
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struct intctx {
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regarm_t r4;
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regarm_t r5;
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regarm_t r6;
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regarm_t r7;
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regarm_t r8;
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regarm_t r9;
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regarm_t r10;
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regarm_t r11;
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regarm_t lr;
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#if CORTEX_USE_FPU || defined(__DOXYGEN__)
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regarm_t s16;
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regarm_t s17;
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@ -217,6 +207,15 @@ struct intctx {
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regarm_t s30;
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regarm_t s31;
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#endif /* CORTEX_USE_FPU */
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regarm_t r4;
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regarm_t r5;
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regarm_t r6;
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regarm_t r7;
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regarm_t r8;
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regarm_t r9;
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regarm_t r10;
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regarm_t r11;
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regarm_t lr;
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};
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#endif
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@ -80,6 +80,7 @@
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structures and stacks in the CCM RAM instead normal RAM. It is done using
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a special .ld file that can be customized to decide how to allocate data
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in the various RAM sections.
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- NEW: Added support for the Cortex-M4 FPU (default when the FPU is present).
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- NEW: Improved I2C driver model and STM32 implementation by Barthess.
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*** 2.3.4 ***
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