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Delete bogus clock pll entry

This commit is contained in:
jflyper 2018-12-03 22:52:23 +09:00
parent b6408b3a32
commit ac02ee4cf2
1 changed files with 0 additions and 1 deletions
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src/main/target/system_stm32f4xx.c
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@ -440,7 +440,6 @@ static const pllConfig_t overclockLevels[] = {
{ 216, 432, 2, 9 }, // 216 MHz { 216, 432, 2, 9 }, // 216 MHz
{ 240, 480, 2, 10 } // 240 MHz { 240, 480, 2, 10 } // 240 MHz
#elif defined(STM32F411xE) #elif defined(STM32F411xE)
{ 84, 336, 4, 7 }, // 84 MHz
{ 96, 384, 4, 8 }, // 96 MHz { 96, 384, 4, 8 }, // 96 MHz
{ 108, 432, 4, 9 }, // 108 MHz { 108, 432, 4, 9 }, // 108 MHz
{ 120, 480, 4, 10 }, // 120 MHz { 120, 480, 4, 10 }, // 120 MHz