2014-09-21 08:41:11 -07:00
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/*
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2016-11-04 07:18:34 -07:00
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Copyright 2016 Benjamin Vedder benjamin@vedder.se
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2014-09-21 08:41:11 -07:00
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2016-11-04 07:18:34 -07:00
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This file is part of the VESC firmware.
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The VESC firmware is free software: you can redistribute it and/or modify
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2014-09-21 08:41:11 -07:00
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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2016-11-04 07:18:34 -07:00
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The VESC firmware is distributed in the hope that it will be useful,
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2014-09-21 08:41:11 -07:00
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "timeout.h"
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2015-12-08 12:01:23 -08:00
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#include "mc_interface.h"
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2019-01-24 07:19:44 -08:00
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#include "stm32f4xx_conf.h"
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2019-12-09 01:57:33 -08:00
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#include "shutdown.h"
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2014-09-21 08:41:11 -07:00
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// Private variables
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2019-12-05 10:50:17 -08:00
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static volatile bool init_done = false;
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2014-09-21 08:41:11 -07:00
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static volatile systime_t timeout_msec;
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static volatile systime_t last_update_time;
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static volatile float timeout_brake_current;
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static volatile bool has_timeout;
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2019-01-24 07:19:44 -08:00
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static volatile uint32_t feed_counter[MAX_THREADS_MONITOR];
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2014-09-21 08:41:11 -07:00
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// Threads
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2015-10-08 14:09:39 -07:00
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static THD_WORKING_AREA(timeout_thread_wa, 512);
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static THD_FUNCTION(timeout_thread, arg);
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2014-09-21 08:41:11 -07:00
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void timeout_init(void) {
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timeout_msec = 1000;
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last_update_time = 0;
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timeout_brake_current = 0.0;
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has_timeout = false;
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2019-12-05 10:50:17 -08:00
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init_done = true;
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2014-09-21 08:41:11 -07:00
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2019-03-01 12:36:58 -08:00
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IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
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2019-01-24 08:16:28 -08:00
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2019-03-01 12:36:58 -08:00
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// IWDG counter clock: LSI/4
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IWDG_SetPrescaler(IWDG_Prescaler_4);
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2019-01-24 08:16:28 -08:00
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2019-03-01 12:36:58 -08:00
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/* Set counter reload value to obtain 12ms IWDG TimeOut.
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*
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* LSI timer per datasheet is 32KHz typical, but 17KHz min
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* and 47KHz max over the complete range of operating conditions,
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* so reload time must ensure watchdog will work correctly under
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* all conditions.
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*
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* Timeout threads runs every 10ms. Take 20% margin so wdt should
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* be fed every 12ms. The worst condition occurs when the wdt clock
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* runs at the max freq (47KHz) due to oscillator tolerances.
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*
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* t_IWDG(ms) = t_LSI(ms) * 4 * 2^(IWDG_PR[2:0]) * (IWDG_RLR[11:0] + 1)
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* t_LSI(ms) [MAX] = 0.021276ms
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* 12ms = 0.0212765 * 4 * 1 * (140 + 1)
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*
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* Counter Reload Value = 140
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*
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* When LSI clock runs the slowest, the IWDG will expire every 33.17ms
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*/
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IWDG_SetReload(140);
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IWDG_ReloadCounter();
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/* Enable IWDG (the LSI oscillator will be enabled by hardware) */
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IWDG_Enable();
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chThdSleepMilliseconds(10);
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2014-09-21 08:41:11 -07:00
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chThdCreateStatic(timeout_thread_wa, sizeof(timeout_thread_wa), NORMALPRIO, timeout_thread, NULL);
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}
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void timeout_configure(systime_t timeout, float brake_current) {
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timeout_msec = timeout;
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timeout_brake_current = brake_current;
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}
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void timeout_reset(void) {
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last_update_time = chVTGetSystemTime();
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}
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bool timeout_has_timeout(void) {
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return has_timeout;
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}
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2015-04-30 16:57:55 -07:00
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systime_t timeout_get_timeout_msec(void) {
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return timeout_msec;
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}
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2015-06-08 21:11:41 -07:00
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float timeout_get_brake_current(void) {
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return timeout_brake_current;
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}
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2019-01-24 07:19:44 -08:00
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void timeout_feed_WDT(uint8_t index) {
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++feed_counter[index];
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}
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void timeout_configure_IWDT_slowest(void) {
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if (!init_done) {
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return;
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}
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2019-12-09 01:57:33 -08:00
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// As we expect to lock the CPU for a couple of ms make sure that shutdown is not sampling the button input,
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// as that can cause a shutdown.
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SHUTDOWN_SET_SAMPLING_DISABLED(true);
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2019-02-19 09:55:18 -08:00
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while(((IWDG->SR & IWDG_SR_RVU) != 0) || ((IWDG->SR & IWDG_SR_PVU) != 0)) {
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// Continue to kick the dog
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IWDG_ReloadCounter();
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}
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// Unlock register
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IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
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// Update configuration
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IWDG_SetReload(4000);
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IWDG_SetPrescaler(IWDG_Prescaler_256);
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// Wait for the new configuration to be taken into account
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while(((IWDG->SR & IWDG_SR_RVU) != 0) || ((IWDG->SR & IWDG_SR_PVU) != 0)) {
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// Continue to kick the dog
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IWDG_ReloadCounter();
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}
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}
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void timeout_configure_IWDT(void) {
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if (!init_done) {
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return;
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}
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2019-12-09 01:57:33 -08:00
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SHUTDOWN_SET_SAMPLING_DISABLED(false);
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2019-02-19 09:55:18 -08:00
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while(((IWDG->SR & IWDG_SR_RVU) != 0) || ((IWDG->SR & IWDG_SR_PVU) != 0)) {
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// Continue to kick the dog
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IWDG_ReloadCounter();
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}
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// Unlock register
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IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
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// Update configuration
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IWDG_SetReload(140);
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IWDG_SetPrescaler(IWDG_Prescaler_4);
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// Wait for the new configuration to be taken into account
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while(((IWDG->SR & IWDG_SR_RVU) != 0) || ((IWDG->SR & IWDG_SR_PVU) != 0)) {
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// Continue to kick the dog
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IWDG_ReloadCounter();
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}
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}
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bool timeout_had_IWDG_reset(void) {
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// Check if the system has resumed from IWDG reset
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if (RCC_GetFlagStatus(RCC_FLAG_IWDGRST) != RESET) {
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/* IWDGRST flag set */
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/* Clear reset flags */
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RCC_ClearFlag();
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return true;
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}
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2019-02-19 09:55:18 -08:00
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return false;
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}
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2015-10-08 14:09:39 -07:00
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static THD_FUNCTION(timeout_thread, arg) {
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2014-09-21 08:41:11 -07:00
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(void)arg;
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chRegSetThreadName("Timeout");
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for(;;) {
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2015-10-08 14:09:39 -07:00
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if (timeout_msec != 0 && chVTTimeElapsedSinceX(last_update_time) > MS2ST(timeout_msec)) {
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2015-12-08 12:01:23 -08:00
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mc_interface_unlock();
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2020-03-16 10:32:39 -07:00
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mc_interface_select_motor_thread(1);
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mc_interface_set_brake_current(timeout_brake_current);
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mc_interface_select_motor_thread(2);
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2015-12-08 12:01:23 -08:00
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mc_interface_set_brake_current(timeout_brake_current);
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2014-09-21 08:41:11 -07:00
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has_timeout = true;
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} else {
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has_timeout = false;
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}
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2019-01-24 07:19:44 -08:00
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bool threads_ok = true;
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// Monitored threads (foc, can, timer) must report at least one iteration,
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// otherwise the watchdog won't be feed and MCU will reset. All threads should
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// be monitored
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2019-02-19 09:55:18 -08:00
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if(feed_counter[THREAD_MCPWM] < MIN_THREAD_ITERATIONS) {
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threads_ok = false;
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}
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2019-02-19 05:59:38 -08:00
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#if CAN_ENABLE
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if(feed_counter[THREAD_CANBUS] < MIN_THREAD_ITERATIONS) {
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threads_ok = false;
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}
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2019-02-19 05:59:38 -08:00
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#endif
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2019-02-19 09:55:18 -08:00
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if(feed_counter[THREAD_TIMER] < MIN_THREAD_ITERATIONS) {
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threads_ok = false;
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2019-02-19 09:55:18 -08:00
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}
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2019-01-24 07:19:44 -08:00
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2019-02-19 09:55:18 -08:00
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for( int i = 0; i < MAX_THREADS_MONITOR; i++) {
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2019-01-24 07:19:44 -08:00
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feed_counter[i] = 0;
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2019-02-19 09:55:18 -08:00
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}
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2019-01-24 07:19:44 -08:00
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if (threads_ok == true) {
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2019-03-01 12:36:58 -08:00
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// Feed WDT
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2019-01-24 08:16:28 -08:00
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IWDG_ReloadCounter(); // must reload in <12ms
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2019-02-19 09:55:18 -08:00
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} else {
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2019-01-24 07:19:44 -08:00
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// not reloading the watchdog will produce a reset.
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// This can be checked from the GUI logs as
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// "FAULT_CODE_BOOTING_FROM_WATCHDOG_RESET"
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}
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2014-09-21 08:41:11 -07:00
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chThdSleepMilliseconds(10);
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}
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}
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