mirror of https://github.com/rusefi/bldc.git
Merge pull request #303 from Jfriesen222/master
Added things for 100D_V2 hardware variant
This commit is contained in:
Benjamin Vedder
GitHub
commit
be439a2a55
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@ -409,6 +409,25 @@ make -j8 build_args='-DDISABLE_HW_LIMITS -DHW_SOURCE=\"hw_stormcore_100d.c\" -DH
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cd $DIR
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cp $FWPATH/build/BLDC_4_ChibiOS.bin $COPYDIR/VESC_default_no_hw_limits.bin
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#################### STORMCORE_100D_V2 ########################
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COPYDIR=STORMCORE_100D_V2
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rm -f $COPYDIR/*
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# default
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cd $FWPATH
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touch conf_general.h
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make -j8 build_args='-DHW_SOURCE=\"hw_stormcore_100d.c\" -DHW_HEADER=\"hw_stormcore_100d.h\" -DHW_VER_IS_100D_V2' USE_VERBOSE_COMPILE=no
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cd $DIR
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cp $FWPATH/build/BLDC_4_ChibiOS.bin $COPYDIR/VESC_default.bin
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# default with HW limits disabled
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cd $FWPATH
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touch conf_general.h
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make -j8 build_args='-DDISABLE_HW_LIMITS -DHW_SOURCE=\"hw_stormcore_100d.c\" -DHW_HEADER=\"hw_stormcore_100d.h\" -DHW_VER_IS_100D_V2' USE_VERBOSE_COMPILE=no
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cd $DIR
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cp $FWPATH/build/BLDC_4_ChibiOS.bin $COPYDIR/VESC_default_no_hw_limits.bin
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#################### STORMCORE_100S ########################
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COPYDIR=STORMCORE_100S
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@ -145,6 +145,7 @@
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//#define HW_HEADER "hw_uxv_sr.h"
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//#define HW_DUAL_CONFIG_PARALLEL
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//#define HW_VER_IS_100D_V2
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//#define HW_SOURCE "hw_stormcore_100d.c"
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//#define HW_HEADER "hw_stormcore_100d.h"
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@ -60,6 +60,17 @@ void hw_init_gpio(void) {
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE);
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOE, ENABLE);
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#ifdef HW_VER_IS_100D_V2
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palSetPadMode(PHASE_FILTER_GPIO, PHASE_FILTER_PIN,
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PAL_MODE_OUTPUT_PUSHPULL |
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PAL_STM32_OSPEED_HIGHEST);
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PHASE_FILTER_OFF();
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palSetPadMode(PHASE_FILTER_GPIO_M2, PHASE_FILTER_PIN_M2,
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PAL_MODE_OUTPUT_PUSHPULL |
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PAL_STM32_OSPEED_HIGHEST);
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PHASE_FILTER_OFF_M2();
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#endif
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@ -25,6 +25,8 @@
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#ifdef HW_HAS_DUAL_PARALLEL
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#define HW_NAME "STORMCORE_100D_PARALLEL"
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#elif defined(HW_VER_IS_100D_V2)
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#define HW_NAME "STORMCORE_100D_V2"
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#else
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#define HW_NAME "STORMCORE_100D"
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#endif
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@ -69,6 +71,18 @@
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#define SMART_SWITCH_MSECS_PRESSED_OFF 2000
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#ifdef HW_VER_IS_100D_V2
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#define HW_HAS_PHASE_FILTERS
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#define PHASE_FILTER_GPIO GPIOE
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#define PHASE_FILTER_PIN 1
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#define PHASE_FILTER_GPIO_M2 GPIOE
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#define PHASE_FILTER_PIN_M2 4
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#define PHASE_FILTER_ON() palSetPad(PHASE_FILTER_GPIO, PHASE_FILTER_PIN)
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#define PHASE_FILTER_OFF() palClearPad(PHASE_FILTER_GPIO, PHASE_FILTER_PIN)
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#define PHASE_FILTER_ON_M2() palSetPad(PHASE_FILTER_GPIO_M2, PHASE_FILTER_PIN_M2)
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#define PHASE_FILTER_OFF_M2() palClearPad(PHASE_FILTER_GPIO_M2, PHASE_FILTER_PIN_M2)
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#endif
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#define HW_SHUTDOWN_HOLD_ON();
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@ -96,6 +110,17 @@
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#define HW_UART_P_RX_PORT GPIOA
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#define HW_UART_P_RX_PIN 10
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#ifdef HW_VER_IS_100D_V2
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//Pins for Third UART
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#define HW_UART_3_BAUD 115200
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#define HW_UART_3_DEV SD2
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#define HW_UART_3_GPIO_AF GPIO_AF_USART2
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#define HW_UART_3_TX_PORT GPIOD
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#define HW_UART_3_TX_PIN 6
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#define HW_UART_3_RX_PORT GPIOD
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#define HW_UART_3_RX_PIN 5
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#endif
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// SPI for DRV8301
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#define DRV8323S_MOSI_GPIO GPIOC
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#define DRV8323S_MOSI_PIN 12
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@ -226,12 +251,23 @@
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#ifndef VIN_R2
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#define VIN_R2 2200.0
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#endif
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#ifdef HW_VER_IS_100D_V2
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#ifndef CURRENT_AMP_GAIN
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#define CURRENT_AMP_GAIN 20.0
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#endif
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#ifndef CURRENT_SHUNT_RES
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#define CURRENT_SHUNT_RES 0.0005
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#endif
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#else
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#ifndef CURRENT_AMP_GAIN
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#define CURRENT_AMP_GAIN 10.0
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#endif
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#ifndef CURRENT_SHUNT_RES
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#define CURRENT_SHUNT_RES 0.001
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#endif
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#endif
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#define VBATT_R1 360000.0
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#define VBATT_R2 10000.0
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@ -334,10 +370,17 @@
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#define NRF_PIN_MISO 10
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// NRF SWD
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#ifdef HW_VER_IS_100D_V2
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#define NRF5x_SWDIO_GPIO GPIOD
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#define NRF5x_SWDIO_PIN 9
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#define NRF5x_SWCLK_GPIO GPIOD
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#define NRF5x_SWCLK_PIN 8
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#else
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#define NRF5x_SWDIO_GPIO GPIOD
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#define NRF5x_SWDIO_PIN 6
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#define NRF5x_SWCLK_GPIO GPIOD
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#define NRF5x_SWCLK_PIN 5
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#endif
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#ifndef MCCONF_DEFAULT_MOTOR_TYPE
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#define MCCONF_DEFAULT_MOTOR_TYPE MOTOR_TYPE_FOC
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