Ensures the memory addresses used for flash memory integrity check
are initially 0xFFFFFFFF, so the application can write a new CRC in the
first boot.
Signed-off-by: Marcos Chaparro <mchaparro@powerdesigns.ca>
Create a new, low priority thread that checks that the CRC of the
flash memory matches the CRC stored in flash.
8kB chunks are computed every 50 milliseconds. A reset is invoked if
CRC does not match.
Signed-off-by: Marcos Chaparro <mchaparro@powerdesigns.ca>
Only unlock when it is necessary to write it. This prevents memory
corruptions caused by software or EMI glitches.
Signed-off-by: Marcos Chaparro <mchaparro@powerdesigns.ca>
The check only covers address 0x08008000 to 0x805FFFF, where application
code is stored. It excludes virtual eeprom area (first 0x8000 bytes)
because it is modified on runtime with user configurations.
After a fresh flash programming the CRC is read as 0xFFFFFFFF and firmware
computes and stores the new CRC and a reset is invoked.
After reset the CRC will be available for checking code integrity.
Linker file had a wrong flash2 size, it was set to 480kB, thus allowing
the linking of binaries larger than 393216 (x3 128kB sectors).
The bootloader won't program binaries that span more than 3 sectors.
Now flash2 length is set as (393216 - 8) to ensure that the last 8 bytes
are left blank (0xFFFF) and reserved for CRC information.
Signed-off-by: Marcos Chaparro <mchaparro@powerdesigns.ca>
Use m_foc prefix so in VESC Tool they are edited in
FOC->Encoder.
Generate confgenerator.c and .h using VESC Tool.
Signed-off-by: Marcos Chaparro <mchaparro@powerdesigns.ca>
This commit adds a motor model running within the vesc firmware,and
from the vesc terminal a user or a test script can set the
mechanical load torque, inertia, phase resistance, Lq and Ld phase
inductances (this generic model includes IPM motors), flux linkage
and battery voltage.
Virtual motor parameters set at the command line should match with
vesc configuration, for example phase resistance, inductance and
flux linkage should match and have the correct observer gain.
Observer works with the virtual motor, with some hiccups during
startup
For solid results its better to use sensored mode. If vesc is
configured to use an SPI encoder the virtual motor phase angle
will be injected as an encoder angle readout.
For safety PWM outputs are disabled during simulation.
Signed-off-by: Maximiliano Cordoba <mcordoba@powerdesigns.ca>
Sin/Cos signals are checked to make sure the module of the vector
is larger than 1V and smaller than 1.65V. A working encoder will
never have both sin and cos signals at 0V (zero amplitude module).
Both sin and cos at 3.3V is also not a possible value.
Errors are logged independently for signals too large and for
signals too small, provinding the user more insight when an encoder
fault happens. In the terminal, the 'encoder' command will show
the error counts and error rates of the encoder being used.
Signed-off-by: Marcos Chaparro <mchaparro@powerdesigns.ca>
Reads sine and cosine on ADC_IND_EXT and ADC_IND_EXT2, usually
used for ACCEL and REGEN inputs. Provides offset and gain
compensation and is implemented using floating point math.
Note it includes the full mc_interface.h into encoder.c only
to access the ADC readings, and no filtering is performed on
the signals.
Signed-off-by: Marcos Chaparro <mchaparro@powerdesigns.ca>
Benjamin Vedder
Marcos Chaparro
Gavin Miller
Maximiliano Cordoba
vadim