rusefi
/
hw_microRusEfi
mirror of https://github.com/rusefi/hw_microRusEfi.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

draft

This commit is contained in:
jharvey 2020-05-14 06:09:46 -04:00
parent a16111c736
commit 68d5c1c0b2
3 changed files with 3722 additions and 3440 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6150
zMRETestFixture.kicad_pcb
View File

File diff suppressed because it is too large Load Diff

110
zMRETestFixture.pro
View File

@ -1,4 +1,4 @@
update=5/12/2020 8:38:58 PM
update=5/14/2020 5:45:00 AM
version=1
last_client=kicad
[general]
@ -12,6 +12,16 @@ NetIExt=net
version=1
LibDir=
[eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=rusefi_lib_external/Border.kicad_wks
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=rusefi_lib_external/Border.kicad_wks
@ -266,101 +276,3 @@ uViaDrill=0.127
dPairWidth=0.2032
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/2]
Name=2.5A EXTERNAL
Clearance=0.1905
TrackWidth=1.0668
ViaDiameter=0.6858
ViaDrill=0.3302
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.2032
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/3]
Name=3,5A EXT HIGH VOLTAGE
Clearance=1.016
TrackWidth=1.6764
ViaDiameter=0.6858
ViaDrill=0.3302
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.2032
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/4]
Name=3.5A EXTERNAL
Clearance=0.1905
TrackWidth=1.651
ViaDiameter=1.0922
ViaDrill=0.6858
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.2032
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/5]
Name=5A EXTERNAL
Clearance=0.2159
TrackWidth=1.0668
ViaDiameter=1.54178
ViaDrill=1.18618
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.2032
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/6]
Name=CUSTOM
Clearance=0.1524
TrackWidth=0.25
ViaDiameter=0.6
ViaDrill=0.3
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.2032
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/7]
Name=CUSTOM 0.6
Clearance=0.1524
TrackWidth=0.6
ViaDiameter=1
ViaDrill=0.4
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.2032
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/8]
Name=MIN_EXTERN_188A
Clearance=0.1524
TrackWidth=0.2032
ViaDiameter=0.6858
ViaDrill=0.3302
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.2032
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/9]
Name=MIN_EXTERN_241A
Clearance=0.1524
TrackWidth=0.2159
ViaDiameter=0.6
ViaDrill=0.3
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.2032
dPairGap=0.25
dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=rusefi_lib_external/Border.kicad_wks
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1

902
zMRETestFixture.sch
View File

File diff suppressed because it is too large Load Diff