mirror of https://github.com/rusefi/hw_modular.git
188 lines
3.3 KiB
INI
188 lines
3.3 KiB
INI
update=08.01.2020 22:31:13
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version=1
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last_client=kicad
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[general]
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version=1
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RootSch=
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BoardNm=
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[cvpcb]
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version=1
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NetIExt=net
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[eeschema]
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version=1
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LibDir=
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[eeschema/libraries]
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[pcbnew]
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version=1
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PageLayoutDescrFile=
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LastNetListRead=Analog_Input_Module.net
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CopperLayerCount=2
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BoardThickness=1.6
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AllowMicroVias=0
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AllowBlindVias=0
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RequireCourtyardDefinitions=0
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ProhibitOverlappingCourtyards=1
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MinTrackWidth=0.1524
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MinViaDiameter=0
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MinViaDrill=0.3
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MinMicroViaDiameter=0.508
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MinMicroViaDrill=0.127
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MinHoleToHole=0.25
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TrackWidth1=0.1524
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TrackWidth2=0.1524
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TrackWidth3=0.2159
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TrackWidth4=0.2159
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TrackWidth5=0.3048
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TrackWidth6=0.6
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TrackWidth7=1.0668
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TrackWidth8=1.651
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TrackWidth9=1.6764
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TrackWidth10=2.7178
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ViaDiameter1=0.6
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ViaDrill1=0.3
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ViaDiameter2=0.6
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ViaDrill2=0.3
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ViaDiameter3=0.78994
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ViaDrill3=0.43434
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ViaDiameter4=1
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ViaDrill4=0.5
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ViaDiameter5=1.54178
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ViaDrill5=1.18618
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dPairWidth1=0.2
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dPairGap1=0.25
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dPairViaGap1=0.25
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SilkLineWidth=0.25
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SilkTextSizeV=0.5
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SilkTextSizeH=0.5
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SilkTextSizeThickness=0.09999999999999999
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SilkTextItalic=0
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SilkTextUpright=1
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CopperLineWidth=0.2
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CopperTextSizeV=1.5
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CopperTextSizeH=1.5
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CopperTextThickness=0.3
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CopperTextItalic=0
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CopperTextUpright=1
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EdgeCutLineWidth=0.15
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CourtyardLineWidth=0.05
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OthersLineWidth=0.15
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OthersTextSizeV=1
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OthersTextSizeH=1
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OthersTextSizeThickness=0.15
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OthersTextItalic=0
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OthersTextUpright=1
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SolderMaskClearance=5.1e-05
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SolderMaskMinWidth=0
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SolderPasteClearance=0
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SolderPasteRatio=0
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[pcbnew/Netclasses]
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[pcbnew/Netclasses/1]
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Name=1A EXTERNAL
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Clearance=0.1905
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TrackWidth=0.3048
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ViaDiameter=0.6858
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ViaDrill=0.3302
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uViaDiameter=0.508
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uViaDrill=0.127
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dPairWidth=0.2
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dPairGap=0.25
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dPairViaGap=0.25
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[pcbnew/Netclasses/2]
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Name=2.5A EXTERNAL
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Clearance=0.2159
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TrackWidth=1.0668
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ViaDiameter=0.6858
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ViaDrill=0.3302
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uViaDiameter=0.508
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uViaDrill=0.127
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dPairWidth=0.2
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dPairGap=0.25
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dPairViaGap=0.25
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[pcbnew/Netclasses/3]
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Name=3,5A EXT HIGH VOLTAGE
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Clearance=1.016
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TrackWidth=1.6764
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ViaDiameter=0.6858
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ViaDrill=0.3302
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uViaDiameter=0.508
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uViaDrill=0.127
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dPairWidth=0.2
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dPairGap=0.25
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dPairViaGap=0.25
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[pcbnew/Netclasses/4]
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Name=3.5A EXTERNAL
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Clearance=0.2159
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TrackWidth=1.651
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ViaDiameter=1.0922
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ViaDrill=0.6858
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uViaDiameter=0.508
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uViaDrill=0.127
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dPairWidth=0.2
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dPairGap=0.25
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dPairViaGap=0.25
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[pcbnew/Netclasses/5]
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Name=5A EXTERNAL
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Clearance=0.2159
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TrackWidth=1.0668
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ViaDiameter=1.54178
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ViaDrill=1.18618
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uViaDiameter=0.508
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uViaDrill=0.127
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dPairWidth=0.2
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dPairGap=0.25
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dPairViaGap=0.25
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[pcbnew/Netclasses/6]
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Name=CUSTOM
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Clearance=0.1524
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TrackWidth=0.25
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ViaDiameter=0.6
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ViaDrill=0.3
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uViaDiameter=0.508
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uViaDrill=0.127
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dPairWidth=0.2
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dPairGap=0.25
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dPairViaGap=0.25
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[pcbnew/Netclasses/7]
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Name=CUSTOM 0.6
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Clearance=0.1524
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TrackWidth=0.6
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ViaDiameter=1
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ViaDrill=0.4
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uViaDiameter=0.508
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uViaDrill=0.127
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dPairWidth=0.2
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dPairGap=0.25
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dPairViaGap=0.25
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[pcbnew/Netclasses/8]
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Name=MIN_EXTERN_188A
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Clearance=0.1524
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TrackWidth=0.1524
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ViaDiameter=0.6858
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ViaDrill=0.3302
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uViaDiameter=0.508
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uViaDrill=0.127
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dPairWidth=0.2
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dPairGap=0.25
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dPairViaGap=0.25
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[pcbnew/Netclasses/9]
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Name=MIN_EXTERN_241A
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Clearance=0.1524
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TrackWidth=0.2159
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ViaDiameter=0.6
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ViaDrill=0.3
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uViaDiameter=0.508
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uViaDrill=0.127
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dPairWidth=0.2
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dPairGap=0.25
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dPairViaGap=0.25
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[schematic_editor]
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version=1
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PageLayoutDescrFile=
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PlotDirectoryName=./
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SubpartIdSeparator=0
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SubpartFirstId=65
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NetFmtName=
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SpiceAjustPassiveValues=0
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LabSize=50
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ERC_TestSimilarLabels=1
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