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- Added CAN support to the STM32Fxx port and the Olimex STM32-P207 demo programs. 

git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@146 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
This commit is contained in:
Frank Voorburg 2016-07-23 16:30:55 +00:00
parent 0656616db9
commit 6a6d2555a4
15 changed files with 3084 additions and 2214 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

BIN
Target/Demo/ARMCM3_STM32F2_Olimex_STM32P207_GCC/Boot/bin/openblt_stm32f207.elf
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1284
Target/Demo/ARMCM3_STM32F2_Olimex_STM32P207_GCC/Boot/bin/openblt_stm32f207.map
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2048
Target/Demo/ARMCM3_STM32F2_Olimex_STM32P207_GCC/Boot/bin/openblt_stm32f207.srec
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27
Target/Demo/ARMCM3_STM32F2_Olimex_STM32P207_GCC/Boot/blt_conf.h
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@ -56,6 +56,33 @@
/****************************************************************************************
* C O M M U N I C A T I O N I N T E R F A C E C O N F I G U R A T I O N
****************************************************************************************/
/* The CAN communication interface is selected by setting the BOOT_COM_CAN_ENABLE
* configurable to 1. Configurable BOOT_COM_CAN_BAUDRATE selects the communication speed
* in bits/second. Two CAN messages are reserved for communication with the host. The
* message identifier for sending data from the target to the host is configured with
* BOOT_COM_CAN_TXMSG_ID. The one for receiving data from the host is configured with
* BOOT_COM_CAN_RXMSG_ID. The maximum amount of data bytes in a message for data
* transmission and reception is set through BOOT_COM_CAN_TX_MAX_DATA and
* BOOT_COM_CAN_RX_MAX_DATA, respectively. It is common for a microcontroller to have more
* than 1 CAN controller on board. The zero-based BOOT_COM_CAN_CHANNEL_INDEX selects the
* CAN controller channel.
*
*/
/** \brief Enable/disable CAN transport layer. */
#define BOOT_COM_CAN_ENABLE (1)
/** \brief Configure the desired CAN baudrate. */
#define BOOT_COM_CAN_BAUDRATE (500000)
/** \brief Configure CAN message ID target->host. */
#define BOOT_COM_CAN_TX_MSG_ID (0x7E1)
/** \brief Configure number of bytes in the target->host CAN message. */
#define BOOT_COM_CAN_TX_MAX_DATA (8)
/** \brief Configure CAN message ID host->target. */
#define BOOT_COM_CAN_RX_MSG_ID (0x667)
/** \brief Configure number of bytes in the host->target CAN message. */
#define BOOT_COM_CAN_RX_MAX_DATA (8)
/** \brief Select the desired CAN peripheral as a zero based index. */
#define BOOT_COM_CAN_CHANNEL_INDEX (0)
/* The UART communication interface is selected by setting the BOOT_COM_UART_ENABLE
* configurable to 1. Configurable BOOT_COM_UART_BAUDRATE selects the communication speed
* in bits/second. The maximum amount of data bytes in a message for data transmission

9
Target/Demo/ARMCM3_STM32F2_Olimex_STM32P207_GCC/Boot/ide/stm32f207.depend
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@ -811,7 +811,7 @@
1469267887 source:c:\work\software\openblt\target\source\armcm3_stm32f2\gcc\cstart.s
1469286137 source:c:\work\software\openblt\target\demo\armcm3_stm32f2_olimex_stm32p207_gcc\boot\hooks.c
1469286972 source:c:\work\software\openblt\target\demo\armcm3_stm32f2_olimex_stm32p207_gcc\boot\hooks.c
"boot.h"
"led.h"
"stm32f2xx.h"
@ -833,7 +833,7 @@
1462050329 c:\work\software\openblt\target\source\assert.h
1469285352 c:\work\software\openblt\target\demo\armcm3_stm32f2_olimex_stm32p207_gcc\boot\\blt_conf.h
1469290552 c:\work\software\openblt\target\demo\armcm3_stm32f2_olimex_stm32p207_gcc\boot\\blt_conf.h
1469095224 c:\work\software\openblt\target\source\plausibility.h
@ -868,7 +868,7 @@
1469268835 c:\work\software\openblt\target\source\armcm3_stm32f2\flash.h
1469285339 source:c:\work\software\openblt\target\demo\armcm3_stm32f2_olimex_stm32p207_gcc\boot\main.c
1469290821 source:c:\work\software\openblt\target\demo\armcm3_stm32f2_olimex_stm32p207_gcc\boot\main.c
"boot.h"
"stm32f2xx.h"
@ -961,3 +961,6 @@
1456845502 c:\work\software\openblt\target\source\third_party\fatfs\src\option\ccsbcs.c
"../ff.h"
1469290576 source:c:\work\software\openblt\target\source\armcm3_stm32f2\can.c
"boot.h"

4
Target/Demo/ARMCM3_STM32F2_Olimex_STM32P207_GCC/Boot/ide/stm32f207.ebp
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@ -312,6 +312,10 @@
<Option compilerVar="CC" />
<Option virtualFolder="Sources\" />
</Unit>
<Unit filename="..\..\..\..\Source\ARMCM3_STM32F2\can.c">
<Option compilerVar="CC" />
<Option virtualFolder="Sources\Core\" />
</Unit>
<Unit filename="..\..\..\..\Source\ARMCM3_STM32F2\cpu.c">
<Option compilerVar="CC" />
<Option virtualFolder="Sources\Core\" />

11
Target/Demo/ARMCM3_STM32F2_Olimex_STM32P207_GCC/Boot/ide/stm32f207.elay
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@ -1,9 +1,9 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<EmBitz_layout_file>
<ActiveTarget name="Debug" />
<File name="..\blt_conf.h" open="0" top="0" tabpos="4" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
<File name="..\blt_conf.h" open="0" top="0" tabpos="1" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
<Cursor>
<Cursor1 position="5914" topLine="60" />
<Cursor1 position="4969" topLine="51" />
</Cursor>
</File>
<File name="..\hooks.c" open="0" top="0" tabpos="6" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
@ -33,7 +33,12 @@
</File>
<File name="..\main.c" open="1" top="1" tabpos="1" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
<Cursor>
<Cursor1 position="2" topLine="6" />
<Cursor1 position="2697" topLine="41" />
</Cursor>
</File>
<File name="..\..\..\..\Source\ARMCM3_STM32F2\can.c" open="0" top="0" tabpos="2" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
<Cursor>
<Cursor1 position="9731" topLine="218" />
</Cursor>
</File>
<File name="..\..\..\..\Source\ARMCM3_STM32F2\flash.c" open="0" top="0" tabpos="0" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">

18
Target/Demo/ARMCM3_STM32F2_Olimex_STM32P207_GCC/Boot/main.c
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@ -132,6 +132,24 @@ static void Init(void)
/* enable UART */
USART_Cmd(USART3, ENABLE);
#endif
#if (BOOT_COM_CAN_ENABLE > 0)
/* enable clocks for CAN1 transmitter and receiver pins */
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE);
/* select alternate function for the CAN2 pins */
GPIO_PinAFConfig(GPIOB, GPIO_PinSource8, GPIO_AF_CAN1);
GPIO_PinAFConfig(GPIOB, GPIO_PinSource9, GPIO_AF_CAN1);
/* configure CAN1 RX and TX pins */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
GPIO_Init(GPIOB, &GPIO_InitStructure);
/* enable CAN clock */
RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE);
#endif
} /*** end of Init ***/

BIN
Target/Demo/ARMCM3_STM32F2_Olimex_STM32P207_GCC/Prog/bin/demoprog_stm32f207.elf
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732
Target/Demo/ARMCM3_STM32F2_Olimex_STM32P207_GCC/Prog/bin/demoprog_stm32f207.map
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@ -105,7 +105,7 @@ Discarded input sections
.text.IrqInterruptRestore
0x00000000 0x28 ..\obj\irq.o
.debug_macro 0x00000000 0x862 ..\obj\irq.o
.debug_macro 0x00000000 0x87 ..\obj\irq.o
.debug_macro 0x00000000 0xb7 ..\obj\irq.o
.debug_macro 0x00000000 0x4c ..\obj\irq.o
.debug_macro 0x00000000 0x3a ..\obj\irq.o
.debug_macro 0x00000000 0x16 ..\obj\irq.o
@ -180,7 +180,7 @@ Discarded input sections
.data 0x00000000 0x0 ..\obj\led.o
.bss 0x00000000 0x0 ..\obj\led.o
.debug_macro 0x00000000 0x862 ..\obj\led.o
.debug_macro 0x00000000 0x87 ..\obj\led.o
.debug_macro 0x00000000 0xb7 ..\obj\led.o
.debug_macro 0x00000000 0x4c ..\obj\led.o
.debug_macro 0x00000000 0x3a ..\obj\led.o
.debug_macro 0x00000000 0x16 ..\obj\led.o
@ -508,14 +508,6 @@ Discarded input sections
.text 0x00000000 0x0 ..\obj\lib\spl\src\stm32f2xx_can.o
.data 0x00000000 0x0 ..\obj\lib\spl\src\stm32f2xx_can.o
.bss 0x00000000 0x0 ..\obj\lib\spl\src\stm32f2xx_can.o
.text.CAN_DeInit
0x00000000 0x44 ..\obj\lib\spl\src\stm32f2xx_can.o
.text.CAN_Init
0x00000000 0x1a4 ..\obj\lib\spl\src\stm32f2xx_can.o
.text.CAN_FilterInit
0x00000000 0x164 ..\obj\lib\spl\src\stm32f2xx_can.o
.text.CAN_StructInit
0x00000000 0x54 ..\obj\lib\spl\src\stm32f2xx_can.o
.text.CAN_SlaveStartBank
0x00000000 0x60 ..\obj\lib\spl\src\stm32f2xx_can.o
.text.CAN_DBGFreeze
@ -528,12 +520,8 @@ Discarded input sections
0x00000000 0xd4 ..\obj\lib\spl\src\stm32f2xx_can.o
.text.CAN_CancelTransmit
0x00000000 0x50 ..\obj\lib\spl\src\stm32f2xx_can.o
.text.CAN_Receive
0x00000000 0x170 ..\obj\lib\spl\src\stm32f2xx_can.o
.text.CAN_FIFORelease
0x00000000 0x38 ..\obj\lib\spl\src\stm32f2xx_can.o
.text.CAN_MessagePending
0x00000000 0x4c ..\obj\lib\spl\src\stm32f2xx_can.o
.text.CAN_OperatingModeRequest
0x00000000 0xfc ..\obj\lib\spl\src\stm32f2xx_can.o
.text.CAN_Sleep
@ -558,12 +546,6 @@ Discarded input sections
0x00000000 0xdc ..\obj\lib\spl\src\stm32f2xx_can.o
.text.CheckITStatus
0x00000000 0x30 ..\obj\lib\spl\src\stm32f2xx_can.o
.debug_info 0x00000000 0xba4 ..\obj\lib\spl\src\stm32f2xx_can.o
.debug_abbrev 0x00000000 0x1f8 ..\obj\lib\spl\src\stm32f2xx_can.o
.debug_aranges
0x00000000 0xe0 ..\obj\lib\spl\src\stm32f2xx_can.o
.debug_ranges 0x00000000 0xd0 ..\obj\lib\spl\src\stm32f2xx_can.o
.debug_macro 0x00000000 0x1e8 ..\obj\lib\spl\src\stm32f2xx_can.o
.debug_macro 0x00000000 0x862 ..\obj\lib\spl\src\stm32f2xx_can.o
.debug_macro 0x00000000 0x4c ..\obj\lib\spl\src\stm32f2xx_can.o
.debug_macro 0x00000000 0x3a ..\obj\lib\spl\src\stm32f2xx_can.o
@ -599,12 +581,6 @@ Discarded input sections
.debug_macro 0x00000000 0x82 ..\obj\lib\spl\src\stm32f2xx_can.o
.debug_macro 0x00000000 0x35 ..\obj\lib\spl\src\stm32f2xx_can.o
.debug_macro 0x00000000 0x3c9 ..\obj\lib\spl\src\stm32f2xx_can.o
.debug_line 0x00000000 0x7bd ..\obj\lib\spl\src\stm32f2xx_can.o
.debug_str 0x00000000 0x54a62 ..\obj\lib\spl\src\stm32f2xx_can.o
.comment 0x00000000 0x47 ..\obj\lib\spl\src\stm32f2xx_can.o
.ARM.attributes
0x00000000 0x33 ..\obj\lib\spl\src\stm32f2xx_can.o
.debug_frame 0x00000000 0x2d4 ..\obj\lib\spl\src\stm32f2xx_can.o
.group 0x00000000 0x8 ..\obj\lib\spl\src\stm32f2xx_crc.o
.group 0x00000000 0x8 ..\obj\lib\spl\src\stm32f2xx_crc.o
.group 0x00000000 0x8 ..\obj\lib\spl\src\stm32f2xx_crc.o
@ -2748,8 +2724,6 @@ Discarded input sections
0x00000000 0x3c ..\obj\lib\spl\src\stm32f2xx_rcc.o
.text.RCC_AHB3PeriphResetCmd
0x00000000 0x3c ..\obj\lib\spl\src\stm32f2xx_rcc.o
.text.RCC_APB1PeriphResetCmd
0x00000000 0x3c ..\obj\lib\spl\src\stm32f2xx_rcc.o
.text.RCC_APB2PeriphResetCmd
0x00000000 0x3c ..\obj\lib\spl\src\stm32f2xx_rcc.o
.text.RCC_AHB1PeriphClockLPModeCmd
@ -4060,7 +4034,7 @@ Discarded input sections
.data 0x00000000 0x0 ..\obj\main.o
.bss 0x00000000 0x0 ..\obj\main.o
.debug_macro 0x00000000 0x862 ..\obj\main.o
.debug_macro 0x00000000 0x87 ..\obj\main.o
.debug_macro 0x00000000 0xb7 ..\obj\main.o
.debug_macro 0x00000000 0x4c ..\obj\main.o
.debug_macro 0x00000000 0x3a ..\obj\main.o
.debug_macro 0x00000000 0x16 ..\obj\main.o
@ -4139,7 +4113,7 @@ Discarded input sections
.text.TimerDeinit
0x00000000 0x18 ..\obj\timer.o
.debug_macro 0x00000000 0x862 ..\obj\timer.o
.debug_macro 0x00000000 0x87 ..\obj\timer.o
.debug_macro 0x00000000 0xb7 ..\obj\timer.o
.debug_macro 0x00000000 0x4c ..\obj\timer.o
.debug_macro 0x00000000 0x3a ..\obj\timer.o
.debug_macro 0x00000000 0x16 ..\obj\timer.o
@ -4213,7 +4187,7 @@ LOAD c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-
0x00000000 __HEAP_SIZE = 0x0
0x00000100 __STACK_SIZE = 0x100
.text 0x08008000 0xe74
.text 0x08008000 0x162c
*(.isr_vector)
.isr_vector 0x08008000 0x188 ..\obj\startup_stm32f2xx.o
0x08008000 __isr_vector
@ -4225,195 +4199,222 @@ LOAD c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-
.text.NVIC_SystemReset
0x08008250 0x28 ..\obj\boot.o
.text.BootComInit
0x08008278 0xc ..\obj\boot.o
0x08008278 0x10 ..\obj\boot.o
0x08008278 BootComInit
.text.BootComCheckActivationRequest
0x08008284 0xc ..\obj\boot.o
0x08008284 BootComCheckActivationRequest
0x08008288 0x10 ..\obj\boot.o
0x08008288 BootComCheckActivationRequest
.text.BootActivate
0x08008290 0xc ..\obj\boot.o
0x08008290 BootActivate
0x08008298 0xc ..\obj\boot.o
0x08008298 BootActivate
.text.BootComUartInit
0x0800829c 0xa0 ..\obj\boot.o
0x080082a4 0xa0 ..\obj\boot.o
.text.BootComUartCheckActivationRequest
0x0800833c 0x7c ..\obj\boot.o
0x08008344 0x7c ..\obj\boot.o
.text.UartReceiveByte
0x080083b8 0x38 ..\obj\boot.o
0x080083c0 0x38 ..\obj\boot.o
.text.CanGetSpeedConfig
0x080083f8 0xc0 ..\obj\boot.o
.text.BootComCanInit
0x080084b8 0xf0 ..\obj\boot.o
.text.BootComCanCheckActivationRequest
0x080085a8 0x44 ..\obj\boot.o
.text.IrqInterruptEnable
0x080083f0 0x10 ..\obj\irq.o
0x080083f0 IrqInterruptEnable
.text.LedInit 0x08008400 0x44 ..\obj\led.o
0x08008400 LedInit
0x080085ec 0x10 ..\obj\irq.o
0x080085ec IrqInterruptEnable
.text.LedInit 0x080085fc 0x44 ..\obj\led.o
0x080085fc LedInit
.text.LedToggle
0x08008444 0x60 ..\obj\led.o
0x08008444 LedToggle
0x08008640 0x60 ..\obj\led.o
0x08008640 LedToggle
.text.CAN_DeInit
0x080086a0 0x44 ..\obj\lib\spl\src\stm32f2xx_can.o
0x080086a0 CAN_DeInit
.text.CAN_Init
0x080086e4 0x1a4 ..\obj\lib\spl\src\stm32f2xx_can.o
0x080086e4 CAN_Init
.text.CAN_FilterInit
0x08008888 0x164 ..\obj\lib\spl\src\stm32f2xx_can.o
0x08008888 CAN_FilterInit
.text.CAN_StructInit
0x080089ec 0x54 ..\obj\lib\spl\src\stm32f2xx_can.o
0x080089ec CAN_StructInit
.text.CAN_Receive
0x08008a40 0x170 ..\obj\lib\spl\src\stm32f2xx_can.o
0x08008a40 CAN_Receive
.text.CAN_MessagePending
0x08008bb0 0x4c ..\obj\lib\spl\src\stm32f2xx_can.o
0x08008bb0 CAN_MessagePending
.text.GPIO_Init
0x080084a4 0x11c ..\obj\lib\spl\src\stm32f2xx_gpio.o
0x080084a4 GPIO_Init
0x08008bfc 0x11c ..\obj\lib\spl\src\stm32f2xx_gpio.o
0x08008bfc GPIO_Init
.text.GPIO_SetBits
0x080085c0 0x1c ..\obj\lib\spl\src\stm32f2xx_gpio.o
0x080085c0 GPIO_SetBits
0x08008d18 0x1c ..\obj\lib\spl\src\stm32f2xx_gpio.o
0x08008d18 GPIO_SetBits
.text.GPIO_ResetBits
0x080085dc 0x1c ..\obj\lib\spl\src\stm32f2xx_gpio.o
0x080085dc GPIO_ResetBits
0x08008d34 0x1c ..\obj\lib\spl\src\stm32f2xx_gpio.o
0x08008d34 GPIO_ResetBits
.text.GPIO_PinAFConfig
0x080085f8 0x8c ..\obj\lib\spl\src\stm32f2xx_gpio.o
0x080085f8 GPIO_PinAFConfig
0x08008d50 0x8c ..\obj\lib\spl\src\stm32f2xx_gpio.o
0x08008d50 GPIO_PinAFConfig
.text.RCC_GetClocksFreq
0x08008684 0x154 ..\obj\lib\spl\src\stm32f2xx_rcc.o
0x08008684 RCC_GetClocksFreq
0x08008ddc 0x154 ..\obj\lib\spl\src\stm32f2xx_rcc.o
0x08008ddc RCC_GetClocksFreq
.text.RCC_AHB1PeriphClockCmd
0x080087d8 0x3c ..\obj\lib\spl\src\stm32f2xx_rcc.o
0x080087d8 RCC_AHB1PeriphClockCmd
0x08008f30 0x3c ..\obj\lib\spl\src\stm32f2xx_rcc.o
0x08008f30 RCC_AHB1PeriphClockCmd
.text.RCC_APB1PeriphClockCmd
0x08008814 0x3c ..\obj\lib\spl\src\stm32f2xx_rcc.o
0x08008814 RCC_APB1PeriphClockCmd
0x08008f6c 0x3c ..\obj\lib\spl\src\stm32f2xx_rcc.o
0x08008f6c RCC_APB1PeriphClockCmd
.text.RCC_APB1PeriphResetCmd
0x08008fa8 0x3c ..\obj\lib\spl\src\stm32f2xx_rcc.o
0x08008fa8 RCC_APB1PeriphResetCmd
.text.USART_Init
0x08008850 0x174 ..\obj\lib\spl\src\stm32f2xx_usart.o
0x08008850 USART_Init
0x08008fe4 0x174 ..\obj\lib\spl\src\stm32f2xx_usart.o
0x08008fe4 USART_Init
.text.USART_Cmd
0x080089c4 0x40 ..\obj\lib\spl\src\stm32f2xx_usart.o
0x080089c4 USART_Cmd
0x08009158 0x40 ..\obj\lib\spl\src\stm32f2xx_usart.o
0x08009158 USART_Cmd
.text.USART_ReceiveData
0x08008a04 0x20 ..\obj\lib\spl\src\stm32f2xx_usart.o
0x08008a04 USART_ReceiveData
0x08009198 0x20 ..\obj\lib\spl\src\stm32f2xx_usart.o
0x08009198 USART_ReceiveData
.text.USART_GetFlagStatus
0x08008a24 0x38 ..\obj\lib\spl\src\stm32f2xx_usart.o
0x08008a24 USART_GetFlagStatus
0x080091b8 0x38 ..\obj\lib\spl\src\stm32f2xx_usart.o
0x080091b8 USART_GetFlagStatus
.text.SystemInit
0x08008a5c 0x4c ..\obj\lib\system_stm32f2xx.o
0x08008a5c SystemInit
0x080091f0 0x4c ..\obj\lib\system_stm32f2xx.o
0x080091f0 SystemInit
.text.SetSysClock
0x08008aa8 0xd8 ..\obj\lib\system_stm32f2xx.o
.text.main 0x08008b80 0x18 ..\obj\main.o
0x08008b80 main
.text.Init 0x08008b98 0x14 ..\obj\main.o
.text 0x08008bac 0x10c ..\obj\startup_stm32f2xx.o
0x08008bac Reset_Handler
0x08008bfa NMI_Handler
0x08008bfc HardFault_Handler
0x08008bfe MemManage_Handler
0x08008c00 BusFault_Handler
0x08008c02 UsageFault_Handler
0x08008c04 SVC_Handler
0x08008c06 DebugMon_Handler
0x08008c08 PendSV_Handler
0x08008c0c Default_Handler
0x08008c0e WWDG_IRQHandler
0x08008c10 PVD_IRQHandler
0x08008c12 TAMP_STAMP_IRQHandler
0x08008c14 RTC_WKUP_IRQHandler
0x08008c16 FLASH_IRQHandler
0x08008c18 RCC_IRQHandler
0x08008c1a EXTI0_IRQHandler
0x08008c1c EXTI1_IRQHandler
0x08008c1e EXTI2_IRQHandler
0x08008c20 EXTI3_IRQHandler
0x08008c22 EXTI4_IRQHandler
0x08008c24 DMA1_Stream0_IRQHandler
0x08008c26 DMA1_Stream1_IRQHandler
0x08008c28 DMA1_Stream2_IRQHandler
0x08008c2a DMA1_Stream3_IRQHandler
0x08008c2c DMA1_Stream4_IRQHandler
0x08008c2e DMA1_Stream5_IRQHandler
0x08008c30 DMA1_Stream6_IRQHandler
0x08008c32 ADC_IRQHandler
0x08008c34 CAN1_TX_IRQHandler
0x08008c36 CAN1_RX0_IRQHandler
0x08008c38 CAN1_RX1_IRQHandler
0x08008c3a CAN1_SCE_IRQHandler
0x08008c3c EXTI9_5_IRQHandler
0x08008c3e TIM1_BRK_TIM9_IRQHandler
0x08008c40 TIM1_UP_TIM10_IRQHandler
0x08008c42 TIM1_TRG_COM_TIM11_IRQHandler
0x08008c44 TIM1_CC_IRQHandler
0x08008c46 TIM2_IRQHandler
0x08008c48 TIM3_IRQHandler
0x08008c4a TIM4_IRQHandler
0x08008c4c I2C1_EV_IRQHandler
0x08008c4e I2C1_ER_IRQHandler
0x08008c50 I2C2_EV_IRQHandler
0x08008c52 I2C2_ER_IRQHandler
0x08008c54 SPI1_IRQHandler
0x08008c56 SPI2_IRQHandler
0x08008c58 USART1_IRQHandler
0x08008c5a USART2_IRQHandler
0x08008c5c USART3_IRQHandler
0x08008c5e EXTI15_10_IRQHandler
0x08008c60 RTC_Alarm_IRQHandler
0x08008c62 OTG_FS_WKUP_IRQHandler
0x08008c64 TIM8_BRK_TIM12_IRQHandler
0x08008c66 TIM8_UP_TIM13_IRQHandler
0x08008c68 TIM8_TRG_COM_TIM14_IRQHandler
0x08008c6a TIM8_CC_IRQHandler
0x08008c6c DMA1_Stream7_IRQHandler
0x08008c6e FSMC_IRQHandler
0x08008c70 SDIO_IRQHandler
0x08008c72 TIM5_IRQHandler
0x08008c74 SPI3_IRQHandler
0x08008c76 UART4_IRQHandler
0x08008c78 UART5_IRQHandler
0x08008c7a TIM6_DAC_IRQHandler
0x08008c7c TIM7_IRQHandler
0x08008c7e DMA2_Stream0_IRQHandler
0x08008c80 DMA2_Stream1_IRQHandler
0x08008c82 DMA2_Stream2_IRQHandler
0x08008c84 DMA2_Stream3_IRQHandler
0x08008c86 DMA2_Stream4_IRQHandler
0x08008c88 ETH_IRQHandler
0x08008c8a ETH_WKUP_IRQHandler
0x08008c8c CAN2_TX_IRQHandler
0x08008c8e CAN2_RX0_IRQHandler
0x08008c90 CAN2_RX1_IRQHandler
0x08008c92 CAN2_SCE_IRQHandler
0x08008c94 OTG_FS_IRQHandler
0x08008c96 DMA2_Stream5_IRQHandler
0x08008c98 DMA2_Stream6_IRQHandler
0x08008c9a DMA2_Stream7_IRQHandler
0x08008c9c USART6_IRQHandler
0x08008c9e I2C3_EV_IRQHandler
0x08008ca0 I2C3_ER_IRQHandler
0x08008ca2 OTG_HS_EP1_OUT_IRQHandler
0x08008ca4 OTG_HS_EP1_IN_IRQHandler
0x08008ca6 OTG_HS_WKUP_IRQHandler
0x08008ca8 OTG_HS_IRQHandler
0x08008caa DCMI_IRQHandler
0x08008cac CRYP_IRQHandler
0x08008cae HASH_RNG_IRQHandler
0x0800923c 0xd8 ..\obj\lib\system_stm32f2xx.o
.text.main 0x08009314 0x18 ..\obj\main.o
0x08009314 main
.text.Init 0x0800932c 0x14 ..\obj\main.o
.text 0x08009340 0x10c ..\obj\startup_stm32f2xx.o
0x08009340 Reset_Handler
0x0800938e NMI_Handler
0x08009390 HardFault_Handler
0x08009392 MemManage_Handler
0x08009394 BusFault_Handler
0x08009396 UsageFault_Handler
0x08009398 SVC_Handler
0x0800939a DebugMon_Handler
0x0800939c PendSV_Handler
0x080093a0 Default_Handler
0x080093a2 WWDG_IRQHandler
0x080093a4 PVD_IRQHandler
0x080093a6 TAMP_STAMP_IRQHandler
0x080093a8 RTC_WKUP_IRQHandler
0x080093aa FLASH_IRQHandler
0x080093ac RCC_IRQHandler
0x080093ae EXTI0_IRQHandler
0x080093b0 EXTI1_IRQHandler
0x080093b2 EXTI2_IRQHandler
0x080093b4 EXTI3_IRQHandler
0x080093b6 EXTI4_IRQHandler
0x080093b8 DMA1_Stream0_IRQHandler
0x080093ba DMA1_Stream1_IRQHandler
0x080093bc DMA1_Stream2_IRQHandler
0x080093be DMA1_Stream3_IRQHandler
0x080093c0 DMA1_Stream4_IRQHandler
0x080093c2 DMA1_Stream5_IRQHandler
0x080093c4 DMA1_Stream6_IRQHandler
0x080093c6 ADC_IRQHandler
0x080093c8 CAN1_TX_IRQHandler
0x080093ca CAN1_RX0_IRQHandler
0x080093cc CAN1_RX1_IRQHandler
0x080093ce CAN1_SCE_IRQHandler
0x080093d0 EXTI9_5_IRQHandler
0x080093d2 TIM1_BRK_TIM9_IRQHandler
0x080093d4 TIM1_UP_TIM10_IRQHandler
0x080093d6 TIM1_TRG_COM_TIM11_IRQHandler
0x080093d8 TIM1_CC_IRQHandler
0x080093da TIM2_IRQHandler
0x080093dc TIM3_IRQHandler
0x080093de TIM4_IRQHandler
0x080093e0 I2C1_EV_IRQHandler
0x080093e2 I2C1_ER_IRQHandler
0x080093e4 I2C2_EV_IRQHandler
0x080093e6 I2C2_ER_IRQHandler
0x080093e8 SPI1_IRQHandler
0x080093ea SPI2_IRQHandler
0x080093ec USART1_IRQHandler
0x080093ee USART2_IRQHandler
0x080093f0 USART3_IRQHandler
0x080093f2 EXTI15_10_IRQHandler
0x080093f4 RTC_Alarm_IRQHandler
0x080093f6 OTG_FS_WKUP_IRQHandler
0x080093f8 TIM8_BRK_TIM12_IRQHandler
0x080093fa TIM8_UP_TIM13_IRQHandler
0x080093fc TIM8_TRG_COM_TIM14_IRQHandler
0x080093fe TIM8_CC_IRQHandler
0x08009400 DMA1_Stream7_IRQHandler
0x08009402 FSMC_IRQHandler
0x08009404 SDIO_IRQHandler
0x08009406 TIM5_IRQHandler
0x08009408 SPI3_IRQHandler
0x0800940a UART4_IRQHandler
0x0800940c UART5_IRQHandler
0x0800940e TIM6_DAC_IRQHandler
0x08009410 TIM7_IRQHandler
0x08009412 DMA2_Stream0_IRQHandler
0x08009414 DMA2_Stream1_IRQHandler
0x08009416 DMA2_Stream2_IRQHandler
0x08009418 DMA2_Stream3_IRQHandler
0x0800941a DMA2_Stream4_IRQHandler
0x0800941c ETH_IRQHandler
0x0800941e ETH_WKUP_IRQHandler
0x08009420 CAN2_TX_IRQHandler
0x08009422 CAN2_RX0_IRQHandler
0x08009424 CAN2_RX1_IRQHandler
0x08009426 CAN2_SCE_IRQHandler
0x08009428 OTG_FS_IRQHandler
0x0800942a DMA2_Stream5_IRQHandler
0x0800942c DMA2_Stream6_IRQHandler
0x0800942e DMA2_Stream7_IRQHandler
0x08009430 USART6_IRQHandler
0x08009432 I2C3_EV_IRQHandler
0x08009434 I2C3_ER_IRQHandler
0x08009436 OTG_HS_EP1_OUT_IRQHandler
0x08009438 OTG_HS_EP1_IN_IRQHandler
0x0800943a OTG_HS_WKUP_IRQHandler
0x0800943c OTG_HS_IRQHandler
0x0800943e DCMI_IRQHandler
0x08009440 CRYP_IRQHandler
0x08009442 HASH_RNG_IRQHandler
.text.NVIC_SetPriority
0x08008cb8 0x54 ..\obj\timer.o
0x0800944c 0x54 ..\obj\timer.o
.text.SysTick_Config
0x08008d0c 0x44 ..\obj\timer.o
0x080094a0 0x44 ..\obj\timer.o
.text.TimerInit
0x08008d50 0x28 ..\obj\timer.o
0x08008d50 TimerInit
0x080094e4 0x28 ..\obj\timer.o
0x080094e4 TimerInit
.text.TimerSet
0x08008d78 0x1c ..\obj\timer.o
0x08008d78 TimerSet
0x0800950c 0x1c ..\obj\timer.o
0x0800950c TimerSet
.text.TimerGet
0x08008d94 0x18 ..\obj\timer.o
0x08008d94 TimerGet
0x08009528 0x18 ..\obj\timer.o
0x08009528 TimerGet
.text.SysTick_Handler
0x08008dac 0x1c ..\obj\timer.o
0x08008dac SysTick_Handler
.text.exit 0x08008dc8 0x28 c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7-m\libg_n.a(lib_a-exit.o)
0x08008dc8 exit
0x08009540 0x1c ..\obj\timer.o
0x08009540 SysTick_Handler
.text.exit 0x0800955c 0x28 c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7-m\libg_n.a(lib_a-exit.o)
0x0800955c exit
.text.__libc_init_array
0x08008df0 0x4c c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7-m\libg_n.a(lib_a-init.o)
0x08008df0 __libc_init_array
.text.memset 0x08008e3c 0x10 c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7-m\libg_n.a(lib_a-memset.o)
0x08008e3c memset
.text 0x08008e4c 0x2 c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7-m\libnosys_s.a(_exit.o)
0x08008e4c _exit
0x08009584 0x4c c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7-m\libg_n.a(lib_a-init.o)
0x08009584 __libc_init_array
.text.memset 0x080095d0 0x10 c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7-m\libg_n.a(lib_a-memset.o)
0x080095d0 memset
.text 0x080095e0 0x2 c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7-m\libnosys_s.a(_exit.o)
0x080095e0 _exit
*(.init)
*fill* 0x08008e4e 0x2
.init 0x08008e50 0x4 c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7-m/crti.o
0x08008e50 _init
.init 0x08008e54 0x8 c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7-m/crtn.o
*fill* 0x080095e2 0x2
.init 0x080095e4 0x4 c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7-m/crti.o
0x080095e4 _init
.init 0x080095e8 0x8 c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7-m/crtn.o
*(.fini)
.fini 0x08008e5c 0x4 c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7-m/crti.o
0x08008e5c _fini
.fini 0x08008e60 0x8 c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7-m/crtn.o
.fini 0x080095f0 0x4 c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7-m/crti.o
0x080095f0 _fini
.fini 0x080095f4 0x8 c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7-m/crtn.o
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend.o *crtend?.o) .ctors)
@ -4425,45 +4426,47 @@ LOAD c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
.rodata.canTiming
0x080095fc 0x24 ..\obj\boot.o
.rodata.str1.1
0x08008e68 0x2 c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7-m\libg_n.a(lib_a-impure.o)
*fill* 0x08008e6a 0x2
0x08009620 0x2 c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7-m\libg_n.a(lib_a-impure.o)
*fill* 0x08009622 0x2
.rodata._global_impure_ptr
0x08008e6c 0x4 c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7-m\libg_n.a(lib_a-impure.o)
0x08008e6c _global_impure_ptr
0x08009624 0x4 c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7-m\libg_n.a(lib_a-impure.o)
0x08009624 _global_impure_ptr
*(.eh_frame*)
.eh_frame 0x08008e70 0x0 c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7-m/crtbegin.o
.eh_frame 0x08008e70 0x4 c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7-m/crtend.o
.eh_frame 0x08009628 0x0 c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7-m/crtbegin.o
.eh_frame 0x08009628 0x4 c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7-m/crtend.o
.glue_7 0x08008e74 0x0
.glue_7 0x0800962c 0x0
.glue_7 0x00000000 0x0 linker stubs
.glue_7t 0x08008e74 0x0
.glue_7t 0x0800962c 0x0
.glue_7t 0x00000000 0x0 linker stubs
.vfp11_veneer 0x08008e74 0x0
.vfp11_veneer 0x0800962c 0x0
.vfp11_veneer 0x00000000 0x0 linker stubs
.v4_bx 0x08008e74 0x0
.v4_bx 0x0800962c 0x0
.v4_bx 0x00000000 0x0 linker stubs
.iplt 0x08008e74 0x0
.iplt 0x0800962c 0x0
.iplt 0x00000000 0x0 c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7-m/crtbegin.o
.ARM.extab
*(.ARM.extab* .gnu.linkonce.armextab.*)
0x08008e74 __exidx_start = .
0x0800962c __exidx_start = .
.ARM.exidx 0x08008e74 0x8
.ARM.exidx 0x0800962c 0x8
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
.ARM.exidx 0x08008e74 0x8 c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7-m/crt0.o
0x08008e7c __exidx_end = .
0x08008e7c __etext = .
.ARM.exidx 0x0800962c 0x8 c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7-m/crt0.o
0x08009634 __exidx_end = .
0x08009634 __etext = .
.rel.dyn 0x08008e7c 0x0
.rel.dyn 0x08009634 0x0
.rel.iplt 0x00000000 0x0 c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7-m/crtbegin.o
.data 0x20000000 0x7c load address 0x08008e7c
.data 0x20000000 0x7c load address 0x08009634
0x20000000 __data_start__ = .
*(vtable)
*(.data*)
@ -4493,22 +4496,22 @@ LOAD c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-
0x2000007c . = ALIGN (0x4)
0x2000007c __data_end__ = .
.jcr 0x2000007c 0x0 load address 0x08008ef8
.jcr 0x2000007c 0x0 load address 0x080096b0
.jcr 0x2000007c 0x0 c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7-m/crtbegin.o
.igot.plt 0x2000007c 0x0 load address 0x08008ef8
.igot.plt 0x2000007c 0x0 load address 0x080096b0
.igot.plt 0x00000000 0x0 c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7-m/crtbegin.o
.bss 0x2000007c 0x74 load address 0x08008ef8
.bss 0x2000007c 0x74 load address 0x080096b0
0x2000007c __bss_start__ = .
*(.bss*)
.bss 0x2000007c 0x1c c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7-m/crtbegin.o
.bss.xcpCtoRxInProgress.7886
.bss.xcpCtoRxInProgress.7890
0x20000098 0x1 ..\obj\boot.o
*fill* 0x20000099 0x3
.bss.xcpCtoReqPacket.7884
.bss.xcpCtoReqPacket.7888
0x2000009c 0x44 ..\obj\boot.o
.bss.xcpCtoRxLength.7885
.bss.xcpCtoRxLength.7889
0x200000e0 0x1 ..\obj\boot.o
*fill* 0x200000e1 0x3
.bss.timer_counter_last.7869
@ -4602,39 +4605,42 @@ OUTPUT(..\bin\demoprog_stm32f207.elf elf32-littlearm)
.ARM.attributes
0x000000cb 0x33 ..\obj\led.o
.ARM.attributes
0x000000fe 0x33 ..\obj\lib\spl\src\stm32f2xx_gpio.o
0x000000fe 0x33 ..\obj\lib\spl\src\stm32f2xx_can.o
.ARM.attributes
0x00000131 0x33 ..\obj\lib\spl\src\stm32f2xx_rcc.o
0x00000131 0x33 ..\obj\lib\spl\src\stm32f2xx_gpio.o
.ARM.attributes
0x00000164 0x33 ..\obj\lib\spl\src\stm32f2xx_usart.o
0x00000164 0x33 ..\obj\lib\spl\src\stm32f2xx_rcc.o
.ARM.attributes
0x00000197 0x33 ..\obj\lib\system_stm32f2xx.o
0x00000197 0x33 ..\obj\lib\spl\src\stm32f2xx_usart.o
.ARM.attributes
0x000001ca 0x33 ..\obj\main.o
0x000001ca 0x33 ..\obj\lib\system_stm32f2xx.o
.ARM.attributes
0x000001fd 0x1b ..\obj\startup_stm32f2xx.o
0x000001fd 0x33 ..\obj\main.o
.ARM.attributes
0x00000218 0x33 ..\obj\timer.o
0x00000230 0x1b ..\obj\startup_stm32f2xx.o
.ARM.attributes
0x0000024b 0x2d c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7-m\libg_n.a(lib_a-exit.o)
0x0000024b 0x33 ..\obj\timer.o
.ARM.attributes
0x00000278 0x2d c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7-m\libg_n.a(lib_a-impure.o)
0x0000027e 0x2d c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7-m\libg_n.a(lib_a-exit.o)
.ARM.attributes
0x000002a5 0x2d c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7-m\libg_n.a(lib_a-init.o)
0x000002ab 0x2d c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7-m\libg_n.a(lib_a-impure.o)
.ARM.attributes
0x000002d2 0x2d c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7-m\libg_n.a(lib_a-memset.o)
0x000002d8 0x2d c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7-m\libg_n.a(lib_a-init.o)
.ARM.attributes
0x000002ff 0x2d c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7-m\libnosys_s.a(_exit.o)
0x00000305 0x2d c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7-m\libg_n.a(lib_a-memset.o)
.ARM.attributes
0x0000032c 0x2d c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7-m/crtend.o
0x00000332 0x2d c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/../../../../arm-none-eabi/lib/armv7-m\libnosys_s.a(_exit.o)
.ARM.attributes
0x00000359 0x1d c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7-m/crtn.o
0x0000035f 0x2d c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7-m/crtend.o
.ARM.attributes
0x0000038c 0x1d c:/program files (x86)/embitz/0.42/share/em_armgcc/bin/../lib/gcc/arm-none-eabi/4.8.4/armv7-m/crtn.o
.comment 0x00000000 0x46
.comment 0x00000000 0x46 ..\obj\boot.o
0x47 (size before relaxing)
.comment 0x00000000 0x47 ..\obj\irq.o
.comment 0x00000000 0x47 ..\obj\led.o
.comment 0x00000000 0x47 ..\obj\lib\spl\src\stm32f2xx_can.o
.comment 0x00000000 0x47 ..\obj\lib\spl\src\stm32f2xx_gpio.o
.comment 0x00000000 0x47 ..\obj\lib\spl\src\stm32f2xx_rcc.o
.comment 0x00000000 0x47 ..\obj\lib\spl\src\stm32f2xx_usart.o
@ -4642,156 +4648,166 @@ OUTPUT(..\bin\demoprog_stm32f207.elf elf32-littlearm)
.comment 0x00000000 0x47 ..\obj\main.o
.comment 0x00000000 0x47 ..\obj\timer.o
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186
Target/Demo/ARMCM3_STM32F2_Olimex_STM32P207_GCC/Prog/boot.c
View File

@ -39,6 +39,10 @@
static void BootComUartInit(void);
static void BootComUartCheckActivationRequest(void);
#endif
#if (BOOT_COM_CAN_ENABLE > 0)
static void BootComCanInit(void);
static void BootComCanCheckActivationRequest(void);
#endif
/************************************************************************************//**
** \brief Initializes the communication interface.
@ -50,6 +54,9 @@ void BootComInit(void)
#if (BOOT_COM_UART_ENABLE > 0)
BootComUartInit();
#endif
#if (BOOT_COM_CAN_ENABLE > 0)
BootComCanInit();
#endif
} /*** end of BootComInit ***/
@ -64,6 +71,9 @@ void BootComCheckActivationRequest(void)
#if (BOOT_COM_UART_ENABLE > 0)
BootComUartCheckActivationRequest();
#endif
#if (BOOT_COM_CAN_ENABLE > 0)
BootComCanCheckActivationRequest();
#endif
} /*** end of BootComCheckActivationRequest ***/
@ -205,6 +215,182 @@ static unsigned char UartReceiveByte(unsigned char *data)
#endif /* BOOT_COM_UART_ENABLE > 0 */
#if (BOOT_COM_CAN_ENABLE > 0)
/****************************************************************************************
* C O N T R O L L E R A R E A N E T W O R K I N T E R F A C E
****************************************************************************************/
/****************************************************************************************
* Type definitions
****************************************************************************************/
/** \brief Structure type for grouping CAN bus timing related information. */
typedef struct t_can_bus_timing
{
unsigned char tseg1; /**< CAN time segment 1 */
unsigned char tseg2; /**< CAN time segment 2 */
} tCanBusTiming;
/****************************************************************************************
* Local constant declarations
****************************************************************************************/
/** \brief CAN bittiming table for dynamically calculating the bittiming settings.
* \details According to the CAN protocol 1 bit-time can be made up of between 8..25
* time quanta (TQ). The total TQ in a bit is SYNC + TSEG1 + TSEG2 with SYNC
* always being 1. The sample point is (SYNC + TSEG1) / (SYNC + TSEG1 + SEG2) *
* 100%. This array contains possible and valid time quanta configurations with
* a sample point between 68..78%.
*/
static const tCanBusTiming canTiming[] =
{ /* TQ | TSEG1 | TSEG2 | SP */
/* ------------------------- */
{ 5, 2 }, /* 8 | 5 | 2 | 75% */
{ 6, 2 }, /* 9 | 6 | 2 | 78% */
{ 6, 3 }, /* 10 | 6 | 3 | 70% */
{ 7, 3 }, /* 11 | 7 | 3 | 73% */
{ 8, 3 }, /* 12 | 8 | 3 | 75% */
{ 9, 3 }, /* 13 | 9 | 3 | 77% */
{ 9, 4 }, /* 14 | 9 | 4 | 71% */
{ 10, 4 }, /* 15 | 10 | 4 | 73% */
{ 11, 4 }, /* 16 | 11 | 4 | 75% */
{ 12, 4 }, /* 17 | 12 | 4 | 76% */
{ 12, 5 }, /* 18 | 12 | 5 | 72% */
{ 13, 5 }, /* 19 | 13 | 5 | 74% */
{ 14, 5 }, /* 20 | 14 | 5 | 75% */
{ 15, 5 }, /* 21 | 15 | 5 | 76% */
{ 15, 6 }, /* 22 | 15 | 6 | 73% */
{ 16, 6 }, /* 23 | 16 | 6 | 74% */
{ 16, 7 }, /* 24 | 16 | 7 | 71% */
{ 16, 8 } /* 25 | 16 | 8 | 68% */
};
/************************************************************************************//**
** \brief Search algorithm to match the desired baudrate to a possible bus
** timing configuration.
** \param baud The desired baudrate in kbps. Valid values are 10..1000.
** \param prescaler Pointer to where the value for the prescaler will be stored.
** \param tseg1 Pointer to where the value for TSEG2 will be stored.
** \param tseg2 Pointer to where the value for TSEG2 will be stored.
** \return 1 if the CAN bustiming register values were found, 0 otherwise.
**
****************************************************************************************/
static unsigned char CanGetSpeedConfig(unsigned short baud, unsigned short *prescaler,
unsigned char *tseg1, unsigned char *tseg2)
{
unsigned char cnt;
/* loop through all possible time quanta configurations to find a match */
for (cnt=0; cnt < sizeof(canTiming)/sizeof(canTiming[0]); cnt++)
{
if (((BOOT_CPU_SYSTEM_SPEED_KHZ/4) % (baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1))) == 0)
{
/* compute the prescaler that goes with this TQ configuration */
*prescaler = (BOOT_CPU_SYSTEM_SPEED_KHZ/4)/(baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1));
/* make sure the prescaler is valid */
if ( (*prescaler > 0) && (*prescaler <= 1024) )
{
/* store the bustiming configuration */
*tseg1 = canTiming[cnt].tseg1;
*tseg2 = canTiming[cnt].tseg2;
/* found a good bus timing configuration */
return 1;
}
}
}
/* could not find a good bus timing configuration */
return 0;
} /*** end of CanGetSpeedConfig ***/
/************************************************************************************//**
** \brief Initializes the CAN communication interface.
** \return none.
**
****************************************************************************************/
static void BootComCanInit(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
CAN_InitTypeDef CAN_InitStructure;
CAN_FilterInitTypeDef CAN_FilterInitStructure;
unsigned short prescaler;
unsigned char tseg1, tseg2;
/* enable clocks for CAN1 transmitter and receiver pins */
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE);
/* select alternate function for the CAN2 pins */
GPIO_PinAFConfig(GPIOB, GPIO_PinSource8, GPIO_AF_CAN1);
GPIO_PinAFConfig(GPIOB, GPIO_PinSource9, GPIO_AF_CAN1);
/* configure CAN1 RX and TX pins */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
GPIO_Init(GPIOB, &GPIO_InitStructure);
/* enable CAN clock */
RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE);
/* CAN register init */
CAN_DeInit(CAN1);
CAN_StructInit(&CAN_InitStructure);
/* obtain the bittiming configuration for this baudrate */
CanGetSpeedConfig(BOOT_COM_CAN_BAUDRATE/1000, &prescaler, &tseg1, &tseg2);
/* CAN controller init */
CAN_InitStructure.CAN_TTCM = DISABLE;
CAN_InitStructure.CAN_ABOM = DISABLE;
CAN_InitStructure.CAN_AWUM = DISABLE;
CAN_InitStructure.CAN_NART = DISABLE;
CAN_InitStructure.CAN_RFLM = DISABLE;
CAN_InitStructure.CAN_TXFP = DISABLE;
CAN_InitStructure.CAN_Mode = CAN_Mode_Normal;
/* CAN Baudrate init */
CAN_InitStructure.CAN_SJW = CAN_SJW_1tq;
CAN_InitStructure.CAN_BS1 = tseg1 - 1;
CAN_InitStructure.CAN_BS2 = tseg2 - 1;
CAN_InitStructure.CAN_Prescaler = prescaler;
CAN_Init(CAN1, &CAN_InitStructure);
/* CAN filter init - receive all messages */
CAN_FilterInitStructure.CAN_FilterNumber = 0;
CAN_FilterInitStructure.CAN_FilterMode = CAN_FilterMode_IdMask;
CAN_FilterInitStructure.CAN_FilterScale = CAN_FilterScale_32bit;
CAN_FilterInitStructure.CAN_FilterIdHigh = 0x0000;
CAN_FilterInitStructure.CAN_FilterIdLow = 0x0000;
CAN_FilterInitStructure.CAN_FilterMaskIdHigh = 0x0000;
CAN_FilterInitStructure.CAN_FilterMaskIdLow = 0x0000;
CAN_FilterInitStructure.CAN_FilterFIFOAssignment = 0;
CAN_FilterInitStructure.CAN_FilterActivation = ENABLE;
CAN_FilterInit(&CAN_FilterInitStructure);
} /*** end of BootComCanInit ***/
/************************************************************************************//**
** \brief Receives the CONNECT request from the host, which indicates that the
** bootloader should be activated and, if so, activates it.
** \return none.
**
****************************************************************************************/
static void BootComCanCheckActivationRequest(void)
{
CanRxMsg RxMessage;
/* check if a new message was received */
if (CAN_MessagePending(CAN1, CAN_FIFO0) > 0)
{
/* receive the message */
CAN_Receive(CAN1, CAN_FIFO0, &RxMessage);
if (RxMessage.StdId == BOOT_COM_CAN_RX_MSG_ID)
{
/* check if this was an XCP CONNECT command */
if ((RxMessage.Data[0] == 0xff) && (RxMessage.Data[1] == 0x00))
{
/* connection request received so start the bootloader */
BootActivate();
}
}
}
} /*** end of BootComCanCheckActivationRequest ***/
#endif /* BOOT_COM_CAN_ENABLE > 0 */
/*********************************** end of boot.c *************************************/

4
Target/Demo/ARMCM3_STM32F2_Olimex_STM32P207_GCC/Prog/ide/stm32f207.depend
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@ -807,7 +807,7 @@
1469192680 source:c:\work\software\openblt\target\demo\armcm3_stm32f2_olimex_stm32p207_gcc\boot\startup_stm32f2xx.s
1469278605 source:c:\work\software\openblt\target\demo\armcm3_stm32f2_olimex_stm32p207_gcc\prog\boot.c
1469291235 source:c:\work\software\openblt\target\demo\armcm3_stm32f2_olimex_stm32p207_gcc\prog\boot.c
"header.h"
1469272998 c:\work\software\openblt\target\demo\armcm3_stm32f2_olimex_stm32p207_gcc\prog\header.h
@ -818,7 +818,7 @@
"led.h"
"timer.h"
1469285352 c:\work\software\openblt\target\demo\armcm3_stm32f2_olimex_stm32p207_gcc\boot\blt_conf.h
1469290552 c:\work\software\openblt\target\demo\armcm3_stm32f2_olimex_stm32p207_gcc\boot\blt_conf.h
1469192681 c:\work\software\openblt\target\demo\armcm3_stm32f2_olimex_stm32p207_gcc\prog\lib\stm32f2xx.h
"core_cm3.h"

4
Target/Demo/ARMCM3_STM32F2_Olimex_STM32P207_GCC/Prog/ide/stm32f207.elay
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@ -3,7 +3,7 @@
<ActiveTarget name="Debug" />
<File name="..\boot.c" open="0" top="0" tabpos="9" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
<Cursor>
<Cursor1 position="4350" topLine="87" />
<Cursor1 position="15257" topLine="291" />
</Cursor>
</File>
<File name="..\header.h" open="0" top="0" tabpos="0" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
@ -28,7 +28,7 @@
</File>
<File name="..\main.c" open="1" top="1" tabpos="1" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">
<Cursor>
<Cursor1 position="2662" topLine="22" />
<Cursor1 position="2435" topLine="22" />
</Cursor>
</File>
<File name="..\startup_stm32f2xx.S" open="0" top="0" tabpos="0" split="0" active="1" splitpos="0" zoom_1="0" zoom_2="0">

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Target/Source/ARMCM3_STM32F2/can.c Normal file
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@ -0,0 +1,384 @@
/************************************************************************************//**
* \file Source\ARMCM3_STM32F2\can.c
* \brief Bootloader CAN communication interface source file.
* \ingroup Target_ARMCM3_STM32F2
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2016 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
#if (BOOT_COM_CAN_ENABLE > 0)
/****************************************************************************************
* Type definitions
****************************************************************************************/
/** \brief CAN transmission mailbox layout. */
typedef struct
{
volatile blt_int32u TIR;
volatile blt_int32u TDTR;
volatile blt_int32u TDLR;
volatile blt_int32u TDHR;
} tCanTxMailBox;
/** \brief CAN reception FIFO mailbox layout. */
typedef struct
{
volatile blt_int32u RIR;
volatile blt_int32u RDTR;
volatile blt_int32u RDLR;
volatile blt_int32u RDHR;
} tCanRxFIFOMailBox;
/** \brief CAN filter register layout. */
typedef struct
{
volatile blt_int32u FR1;
volatile blt_int32u FR2;
} tCanFilter;
/** \brief CAN controller register layout. */
typedef struct
{
volatile blt_int32u MCR;
volatile blt_int32u MSR;
volatile blt_int32u TSR;
volatile blt_int32u RF0R;
volatile blt_int32u RF1R;
volatile blt_int32u IER;
volatile blt_int32u ESR;
volatile blt_int32u BTR;
blt_int32u RESERVED0[88];
tCanTxMailBox sTxMailBox[3];
tCanRxFIFOMailBox sFIFOMailBox[2];
blt_int32u RESERVED1[12];
volatile blt_int32u FMR;
volatile blt_int32u FM1R;
blt_int32u RESERVED2;
volatile blt_int32u FS1R;
blt_int32u RESERVED3;
volatile blt_int32u FFA1R;
blt_int32u RESERVED4;
volatile blt_int32u FA1R;
blt_int32u RESERVED5[8];
tCanFilter sFilterRegister[28];
} tCanRegs;
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/** \brief Reset request bit. */
#define CAN_BIT_RESET ((blt_int32u)0x00008000)
/** \brief Initialization request bit. */
#define CAN_BIT_INRQ ((blt_int32u)0x00000001)
/** \brief Initialization acknowledge bit. */
#define CAN_BIT_INAK ((blt_int32u)0x00000001)
/** \brief Sleep mode request bit. */
#define CAN_BIT_SLEEP ((blt_int32u)0x00000002)
/** \brief Filter 0 selection bit. */
#define CAN_BIT_FILTER0 ((blt_int32u)0x00000001)
/** \brief Filter 14 selection bit. */
#define CAN_BIT_FILTER14 ((blt_int32u)0x00004000)
/** \brief Filter init mode bit. */
#define CAN_BIT_FINIT ((blt_int32u)0x00000001)
/** \brief Transmit mailbox 0 empty bit. */
#define CAN_BIT_TME0 ((blt_int32u)0x04000000)
/** \brief Transmit mailbox request bit. */
#define CAN_BIT_TXRQ ((blt_int32u)0x00000001)
/** \brief Release FIFO 0 mailbox bit. */
#define CAN_BIT_RFOM0 ((blt_int32u)0x00000020)
/****************************************************************************************
* Register definitions
****************************************************************************************/
#if (BOOT_COM_CAN_CHANNEL_INDEX == 0)
/** \brief Macro for accessing CAN1 controller registers. */
#define CANx ((tCanRegs *) (blt_int32u)0x40006400)
#else
/** \brief Macro for accessing CAN2 controller registers. */
#define CANx ((tCanRegs *) (blt_int32u)0x40006800)
#endif
/** \brief Macro for accessing CAN1 controller registers. */
#define CAN1 ((tCanRegs *) (blt_int32u)0x40006400)
/****************************************************************************************
* Type definitions
****************************************************************************************/
/** \brief Structure type for grouping CAN bus timing related information. */
typedef struct t_can_bus_timing
{
blt_int8u tseg1; /**< CAN time segment 1 */
blt_int8u tseg2; /**< CAN time segment 2 */
} tCanBusTiming;
/****************************************************************************************
* Local constant declarations
****************************************************************************************/
/** \brief CAN bittiming table for dynamically calculating the bittiming settings.
* \details According to the CAN protocol 1 bit-time can be made up of between 8..25
* time quanta (TQ). The total TQ in a bit is SYNC + TSEG1 + TSEG2 with SYNC
* always being 1. The sample point is (SYNC + TSEG1) / (SYNC + TSEG1 + SEG2) *
* 100%. This array contains possible and valid time quanta configurations with
* a sample point between 68..78%.
*/
static const tCanBusTiming canTiming[] =
{
/* TQ | TSEG1 | TSEG2 | SP */
/* ------------------------- */
{ 5, 2 }, /* 8 | 5 | 2 | 75% */
{ 6, 2 }, /* 9 | 6 | 2 | 78% */
{ 6, 3 }, /* 10 | 6 | 3 | 70% */
{ 7, 3 }, /* 11 | 7 | 3 | 73% */
{ 8, 3 }, /* 12 | 8 | 3 | 75% */
{ 9, 3 }, /* 13 | 9 | 3 | 77% */
{ 9, 4 }, /* 14 | 9 | 4 | 71% */
{ 10, 4 }, /* 15 | 10 | 4 | 73% */
{ 11, 4 }, /* 16 | 11 | 4 | 75% */
{ 12, 4 }, /* 17 | 12 | 4 | 76% */
{ 12, 5 }, /* 18 | 12 | 5 | 72% */
{ 13, 5 }, /* 19 | 13 | 5 | 74% */
{ 14, 5 }, /* 20 | 14 | 5 | 75% */
{ 15, 5 }, /* 21 | 15 | 5 | 76% */
{ 15, 6 }, /* 22 | 15 | 6 | 73% */
{ 16, 6 }, /* 23 | 16 | 6 | 74% */
{ 16, 7 }, /* 24 | 16 | 7 | 71% */
{ 16, 8 } /* 25 | 16 | 8 | 68% */
};
/************************************************************************************//**
** \brief Search algorithm to match the desired baudrate to a possible bus
** timing configuration.
** \param baud The desired baudrate in kbps. Valid values are 10..1000.
** \param prescaler Pointer to where the value for the prescaler will be stored.
** \param tseg1 Pointer to where the value for TSEG2 will be stored.
** \param tseg2 Pointer to where the value for TSEG2 will be stored.
** \return BLT_TRUE if the CAN bustiming register values were found, BLT_FALSE
** otherwise.
**
****************************************************************************************/
static blt_bool CanGetSpeedConfig(blt_int16u baud, blt_int16u *prescaler,
blt_int8u *tseg1, blt_int8u *tseg2)
{
blt_int8u cnt;
/* loop through all possible time quanta configurations to find a match */
for (cnt=0; cnt < sizeof(canTiming)/sizeof(canTiming[0]); cnt++)
{
if (((BOOT_CPU_SYSTEM_SPEED_KHZ/4) % (baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1))) == 0)
{
/* compute the prescaler that goes with this TQ configuration */
*prescaler = (BOOT_CPU_SYSTEM_SPEED_KHZ/4)/(baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1));
/* make sure the prescaler is valid */
if ((*prescaler > 0) && (*prescaler <= 1024))
{
/* store the bustiming configuration */
*tseg1 = canTiming[cnt].tseg1;
*tseg2 = canTiming[cnt].tseg2;
/* found a good bus timing configuration */
return BLT_TRUE;
}
}
}
/* could not find a good bus timing configuration */
return BLT_FALSE;
} /*** end of CanGetSpeedConfig ***/
/************************************************************************************//**
** \brief Initializes the CAN controller and synchronizes it to the CAN bus.
** \return none.
**
****************************************************************************************/
void CanInit(void)
{
blt_int16u prescaler=0;
blt_int8u tseg1=0, tseg2=0;
blt_bool result;
/* the current implementation supports CAN1 and 2. throw an assertion error in case a
* different CAN channel is configured.
*/
ASSERT_CT((BOOT_COM_CAN_CHANNEL_INDEX == 0 || BOOT_COM_CAN_CHANNEL_INDEX == 1));
/* obtain bittiming configuration information */
result = CanGetSpeedConfig(BOOT_COM_CAN_BAUDRATE/1000, &prescaler, &tseg1, &tseg2);
ASSERT_RT(result == BLT_TRUE);
/* disable all can interrupt. this driver works in polling mode */
CANx->IER = (blt_int32u)0;
/* set request to reset the can controller */
CANx->MCR |= CAN_BIT_RESET ;
/* wait for acknowledge that the can controller was reset */
while ((CANx->MCR & CAN_BIT_RESET) != 0)
{
/* keep the watchdog happy */
CopService();
}
/* exit from sleep mode, which is the default mode after reset */
CANx->MCR &= ~CAN_BIT_SLEEP;
/* set request to enter initialisation mode */
CANx->MCR |= CAN_BIT_INRQ ;
/* wait for acknowledge that initialization mode was entered */
while ((CANx->MSR & CAN_BIT_INAK) == 0)
{
/* keep the watchdog happy */
CopService();
}
/* configure the bittming */
CANx->BTR = (blt_int32u)((blt_int32u)(tseg1 - 1) << 16) | \
(blt_int32u)((blt_int32u)(tseg2 - 1) << 20) | \
(blt_int32u)(prescaler - 1);
/* set request to leave initialisation mode */
CANx->MCR &= ~CAN_BIT_INRQ;
/* wait for acknowledge that initialization mode was exited */
while ((CANx->MSR & CAN_BIT_INAK) != 0)
{
/* keep the watchdog happy */
CopService();
}
#if (BOOT_COM_CAN_CHANNEL_INDEX == 0)
/* enter initialisation mode for the acceptance filter */
CAN1->FMR |= CAN_BIT_FINIT;
/* deactivate filter 0 */
CAN1->FA1R &= ~CAN_BIT_FILTER0;
/* 32-bit scale for the filter */
CAN1->FS1R |= CAN_BIT_FILTER0;
/* open up the acceptance filter to receive all messages */
CAN1->sFilterRegister[0].FR1 = 0;
CAN1->sFilterRegister[0].FR2 = 0;
/* select id/mask mode for the filter */
CAN1->FM1R &= ~CAN_BIT_FILTER0;
/* FIFO 0 assignation for the filter */
CAN1->FFA1R &= ~CAN_BIT_FILTER0;
/* filter activation */
CAN1->FA1R |= CAN_BIT_FILTER0;
/* leave initialisation mode for the acceptance filter */
CAN1->FMR &= ~CAN_BIT_FINIT;
#else
/* enter initialisation mode for the acceptance filter */
CAN1->FMR |= CAN_BIT_FINIT;
/* deactivate filter 14 */
CAN1->FA1R &= ~CAN_BIT_FILTER14;
/* 32-bit scale for the filter */
CAN1->FS1R |= CAN_BIT_FILTER14;
/* open up the acceptance filter to receive all messages */
CAN1->sFilterRegister[14].FR1 = 0;
CAN1->sFilterRegister[14].FR2 = 0;
/* select id/mask mode for the filter */
CAN1->FM1R &= ~CAN_BIT_FILTER14;
/* FIFO 0 assignation for the filter */
CAN1->FFA1R &= ~CAN_BIT_FILTER14;
/* filter activation */
CAN1->FA1R |= CAN_BIT_FILTER14;
/* leave initialisation mode for the acceptance filter */
CAN1->FMR &= ~CAN_BIT_FINIT;
#endif
} /*** end of CanInit ***/
/************************************************************************************//**
** \brief Transmits a packet formatted for the communication interface.
** \param data Pointer to byte array with data that it to be transmitted.
** \param len Number of bytes that are to be transmitted.
** \return none.
**
****************************************************************************************/
void CanTransmitPacket(blt_int8u *data, blt_int8u len)
{
/* make sure that transmit mailbox 0 is available */
ASSERT_RT((CANx->TSR&CAN_BIT_TME0) == CAN_BIT_TME0);
/* store the 11-bit message identifier */
CANx->sTxMailBox[0].TIR &= CAN_BIT_TXRQ;
CANx->sTxMailBox[0].TIR |= ((blt_int32u)BOOT_COM_CAN_TX_MSG_ID << 21);
/* store the message date length code (DLC) */
CANx->sTxMailBox[0].TDTR = len;
/* store the message data bytes */
CANx->sTxMailBox[0].TDLR = (((blt_int32u)data[3] << 24) | \
((blt_int32u)data[2] << 16) | \
((blt_int32u)data[1] << 8) | \
((blt_int32u)data[0]));
CANx->sTxMailBox[0].TDHR = (((blt_int32u)data[7] << 24) | \
((blt_int32u)data[6] << 16) | \
((blt_int32u)data[5] << 8) | \
((blt_int32u)data[4]));
/* request the start of message transmission */
CANx->sTxMailBox[0].TIR |= CAN_BIT_TXRQ;
/* wait for transmit completion */
while ((CANx->TSR&CAN_BIT_TME0) == 0)
{
/* keep the watchdog happy */
CopService();
}
} /*** end of CanTransmitPacket ***/
/************************************************************************************//**
** \brief Receives a communication interface packet if one is present.
** \param data Pointer to byte array where the data is to be stored.
** \return BLT_TRUE is a packet was received, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool CanReceivePacket(blt_int8u *data)
{
blt_int32u rxMsgId;
blt_bool result = BLT_FALSE;
/* check if a new message was received */
if ((CANx->RF0R&(blt_int32u)0x00000003) > 0)
{
/* read out the message identifier */
rxMsgId = (blt_int32u)0x000007FF & (CANx->sFIFOMailBox[0].RIR >> 21);
/* is this the packet identifier */
if (rxMsgId == BOOT_COM_CAN_RX_MSG_ID)
{
result = BLT_TRUE;
/* store the received packet data */
data[0] = (blt_int8u)0xFF & CANx->sFIFOMailBox[0].RDLR;
data[1] = (blt_int8u)0xFF & (CANx->sFIFOMailBox[0].RDLR >> 8);
data[2] = (blt_int8u)0xFF & (CANx->sFIFOMailBox[0].RDLR >> 16);
data[3] = (blt_int8u)0xFF & (CANx->sFIFOMailBox[0].RDLR >> 24);
data[4] = (blt_int8u)0xFF & CANx->sFIFOMailBox[0].RDHR;
data[5] = (blt_int8u)0xFF & (CANx->sFIFOMailBox[0].RDHR >> 8);
data[6] = (blt_int8u)0xFF & (CANx->sFIFOMailBox[0].RDHR >> 16);
data[7] = (blt_int8u)0xFF & (CANx->sFIFOMailBox[0].RDHR >> 24);
}
/* release FIFO0 */
CANx->RF0R |= CAN_BIT_RFOM0;
}
return result;
} /*** end of CanReceivePacket ***/
#endif /* BOOT_COM_CAN_ENABLE > 0 */
/*********************************** end of can.c **************************************/