rusefi
/
openblt
mirror of https://github.com/rusefi/openblt.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Refs #817. Reintegrating branch where the S32K11 port was developed. 

git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@773 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
This commit is contained in:
Frank Voorburg 2020-03-26 11:29:46 +00:00
parent d78ae71cdb
commit 88e47a8b23
128 changed files with 78378 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

152
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/.cproject Normal file
View File

@ -0,0 +1,152 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.1550428572">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.1550428572" moduleId="org.eclipse.cdt.core.settings" name="Debug">
<externalSettings/>
<extensions>
<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="com.freescale.s32ds.cdt.core.errorParsers.S32DSGNULinkerErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactExtension="elf" artifactName="openblt_s32k118" buildArtefactType="com.nxp.s32ds.cle.arm.mbs.arm32.bare.buildArtefact.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.nxp.s32ds.cle.arm.mbs.arm32.bare.buildArtefact.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" description="" id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.1550428572" name="Debug" parent="com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug">
<folderInfo id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.1550428572." name="/" resourcePath="">
<toolChain id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.toolchain.debug.851553752" name="ARM Bare-Metal 32-bit Target Binary Toolchain" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.toolchain.debug">
<option defaultValue="true" id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.addtools.printsize.460010568" name="Print size" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.addtools.printsize" valueType="boolean"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.libraries.424331727" name="Libraries support" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.libraries" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.libraries.newlib_nano_noio" valueType="enumerated"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.fpu.abi.213152626" name="Float ABI" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.fpu.abi" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.fpu.abi.soft" valueType="enumerated"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.mcpu.862900411" name="ARM family" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.mcpu" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.mcpu.cortex-m0plus" valueType="enumerated"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.addtools.createflash.1032999626" name="Create flash image" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.addtools.createflash" value="true" valueType="boolean"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.fpu.unit.1264167907" name="FPU Type" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.fpu.unit"/>
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="cdt.managedbuild.targetPlatform.gnu.cross.34837333" isAbstract="false" osList="all" superClass="cdt.managedbuild.targetPlatform.gnu.cross"/>
<builder buildPath="${workspace_loc:/Boot}/Debug_FLASH" id="com.freescale.s32ds.cross.gnu.builder.468435066" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="FSL Make Builder" superClass="com.freescale.s32ds.cross.gnu.builder"/>
<tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.1117844436" name="Standard S32DS C Compiler" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler">
<option defaultValue="gnu.c.optimization.level.none" id="gnu.c.compiler.option.optimization.level.106710569" name="Optimization Level" superClass="gnu.c.compiler.option.optimization.level" useByScannerDiscovery="false" value="gnu.c.optimization.level.optimize" valueType="enumerated"/>
<option id="gnu.c.compiler.option.debugging.level.520978429" name="Debug Level" superClass="gnu.c.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.c.debugging.level.max" valueType="enumerated"/>
<option id="com.freescale.s32ds.cross.gnu.tool.c.compiler.option.optimization.functionsections.829506989" name="Function sections (-ffunction-sections)" superClass="com.freescale.s32ds.cross.gnu.tool.c.compiler.option.optimization.functionsections" useByScannerDiscovery="true" value="true" valueType="boolean"/>
<option id="com.freescale.s32ds.cross.gnu.tool.c.compiler.option.optimization.datasections.627929103" name="Data sections (-fdata-sections)" superClass="com.freescale.s32ds.cross.gnu.tool.c.compiler.option.optimization.datasections" useByScannerDiscovery="true" value="true" valueType="boolean"/>
<option id="com.freescale.s32ds.cross.gnu.tool.c.compiler.option.debugging.format.113146235" name="Debug format" superClass="com.freescale.s32ds.cross.gnu.tool.c.compiler.option.debugging.format" useByScannerDiscovery="true"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.libraries.1592706191" name="Libraries support" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.libraries" useByScannerDiscovery="false" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.libraries.newlib_nano_noio" valueType="enumerated"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.sysroot.1677949601" name="Sysroot" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.sysroot" useByScannerDiscovery="false" value="--sysroot=&quot;${S32DS_ARM32_NEWLIB_DIR}&quot;" valueType="string"/>
<option id="gnu.c.compiler.option.include.paths.1385687108" name="Include paths (-I)" superClass="gnu.c.compiler.option.include.paths" useByScannerDiscovery="false" valueType="includePath">
<listOptionValue builtIn="false" value="&quot;${ProjDirPath}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/lib&quot;"/>
<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/../../../Source&quot;"/>
<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/../../../Source/ARMCM0_S32K11&quot;"/>
</option>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.fpu.abi.1227510703" name="Float ABI" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.fpu.abi" useByScannerDiscovery="true" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.fpu.abi.soft" valueType="enumerated"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.mcpu.1607955435" name="ARM family" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.mcpu" useByScannerDiscovery="true" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.mcpu.cortex-m0plus" valueType="enumerated"/>
<option id="gnu.c.compiler.option.preprocessor.def.symbols.1952269971" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" useByScannerDiscovery="false" valueType="definedSymbols">
<listOptionValue builtIn="false" value="CPU_S32K118"/>
</option>
<option id="gnu.c.compiler.option.dialect.std.821434854" name="Language standard" superClass="gnu.c.compiler.option.dialect.std" useByScannerDiscovery="true" value="gnu.c.compiler.dialect.default" valueType="enumerated"/>
<inputType id="cdt.managedbuild.tool.gnu.c.compiler.input.1553525050" superClass="cdt.managedbuild.tool.gnu.c.compiler.input"/>
</tool>
<tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.1377834751" name="Standard S32DS C++ Compiler" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler">
<option id="gnu.cpp.compiler.option.optimization.level.2146334811" name="Optimization Level" superClass="gnu.cpp.compiler.option.optimization.level" useByScannerDiscovery="false" value="gnu.cpp.compiler.optimization.level.none" valueType="enumerated"/>
<option id="gnu.cpp.compiler.option.debugging.level.1280073826" name="Debug Level" superClass="gnu.cpp.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.cpp.compiler.debugging.level.max" valueType="enumerated"/>
<option id="com.freescale.s32ds.cross.gnu.tool.cpp.compiler.option.optimization.functionsections.289292334" name="Function sections (-ffunction-sections)" superClass="com.freescale.s32ds.cross.gnu.tool.cpp.compiler.option.optimization.functionsections" useByScannerDiscovery="true" value="true" valueType="boolean"/>
<option id="com.freescale.s32ds.cross.gnu.tool.cpp.compiler.option.optimization.datasections.1483866089" name="Data sections (-fdata-sections)" superClass="com.freescale.s32ds.cross.gnu.tool.cpp.compiler.option.optimization.datasections" useByScannerDiscovery="true" value="true" valueType="boolean"/>
<option id="com.freescale.s32ds.cross.gnu.tool.cpp.compiler.option.debugging.format.564859066" name="Debug format" superClass="com.freescale.s32ds.cross.gnu.tool.cpp.compiler.option.debugging.format" useByScannerDiscovery="true"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.sysroot.1022833166" name="Sysroot" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.sysroot" useByScannerDiscovery="false" value="--sysroot=&quot;${S32DS_ARM32_NEWLIB_DIR}&quot;" valueType="string"/>
<option id="gnu.cpp.compiler.option.include.paths.1867782688" name="Include paths (-I)" superClass="gnu.cpp.compiler.option.include.paths" useByScannerDiscovery="false" valueType="includePath">
<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/include&quot;"/>
</option>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.fpu.abi.1637095160" name="Float ABI" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.fpu.abi" useByScannerDiscovery="true" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.fpu.abi.soft" valueType="enumerated"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.mcpu.450473165" name="ARM family" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.mcpu" useByScannerDiscovery="true" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.mcpu.cortex-m0plus" valueType="enumerated"/>
<option id="gnu.cpp.compiler.option.preprocessor.def.345939057" name="Defined symbols (-D)" superClass="gnu.cpp.compiler.option.preprocessor.def" useByScannerDiscovery="false" valueType="definedSymbols">
<listOptionValue builtIn="false" value="CPU_S32K118"/>
</option>
</tool>
<tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.1127172418" name="Standard S32DS C Linker" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker">
<option id="com.freescale.s32ds.cross.gnu.tool.c.linker.option.gcsections.1481381085" name="Remove unused sections (-Xlinker --gc-sections)" superClass="com.freescale.s32ds.cross.gnu.tool.c.linker.option.gcsections" value="true" valueType="boolean"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.libraries.1001728570" name="Libraries support" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.libraries" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.libraries.newlib_nano_noio" valueType="enumerated"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.sysroot.764141660" name="Sysroot" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.sysroot" value="--sysroot=&quot;${S32DS_ARM32_NEWLIB_DIR}&quot;" valueType="string"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.fpu.abi.1903489030" name="Float ABI" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.fpu.abi" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.fpu.abi.soft" valueType="enumerated"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.mcpu.1111081125" name="ARM family" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.mcpu" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.mcpu.cortex-m0plus" valueType="enumerated"/>
<option id="com.freescale.s32ds.cross.gnu.tool.c.linker.option.scriptfile.1071116288" name="Script files (-T)" superClass="com.freescale.s32ds.cross.gnu.tool.c.linker.option.scriptfile" useByScannerDiscovery="false" valueType="stringList">
<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/S32K118_25_flash.ld&quot;"/>
</option>
<inputType id="com.freescale.s32ds.cross.gnu.tool.c.linker.inputType.scriptfile.1402852964" superClass="com.freescale.s32ds.cross.gnu.tool.c.linker.inputType.scriptfile"/>
</tool>
<tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.827368788" name="Standard S32DS C++ Linker" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker">
<option id="com.freescale.s32ds.cross.gnu.tool.cpp.linker.option.gcsections.481977943" name="Remove unused sections (-Xlinker --gc-sections)" superClass="com.freescale.s32ds.cross.gnu.tool.cpp.linker.option.gcsections" value="true" valueType="boolean"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.libraries.898372072" name="Libraries support" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.libraries" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.libraries.newlib_nano_noio" valueType="enumerated"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.sysroot.1699694043" name="Sysroot" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.sysroot" value="--sysroot=&quot;${S32DS_ARM32_NEWLIB_DIR}&quot;" valueType="string"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.fpu.abi.759256562" name="Float ABI" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.fpu.abi" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.fpu.abi.soft" valueType="enumerated"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.mcpu.132691970" name="ARM family" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.mcpu" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.mcpu.cortex-m0plus" valueType="enumerated"/>
<option id="com.freescale.s32ds.cross.gnu.tool.cpp.linker.option.scriptfile.1683922758" name="Script files (-T)" superClass="com.freescale.s32ds.cross.gnu.tool.cpp.linker.option.scriptfile" valueType="stringList">
<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/Project_Settings/Linker_Files/S32K118_25_flash.ld&quot;"/>
</option>
</tool>
<tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.archiver.490793148" name="Standard S32DS Archiver" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.archiver"/>
<tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.2074241287" name="Standard S32DS Assembler" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler">
<option id="com.freescale.s32ds.cross.gnu.tool.assembler.usepreprocessor.726906850" name="Use preprocessor" superClass="com.freescale.s32ds.cross.gnu.tool.assembler.usepreprocessor" value="true" valueType="boolean"/>
<option id="com.freescale.s32ds.cross.gnu.tool.assembler.option.debugging.level.1500501160" name="Debug Level" superClass="com.freescale.s32ds.cross.gnu.tool.assembler.option.debugging.level" value="gnu.c.debugging.level.max" valueType="enumerated"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.libraries.945126113" name="Libraries support" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.libraries" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.libraries.newlib_nano_noio" valueType="enumerated"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.sysroot.1134221508" name="Sysroot" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.sysroot" value="--sysroot=&quot;${S32DS_ARM32_NEWLIB_DIR}&quot;" valueType="string"/>
<option id="gnu.both.asm.option.include.paths.875294595" name="Include paths (-I)" superClass="gnu.both.asm.option.include.paths" useByScannerDiscovery="false"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.fpu.abi.22618522" name="Float ABI" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.fpu.abi" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.fpu.abi.soft" valueType="enumerated"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.mcpu.1020237787" name="ARM family" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.mcpu" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.mcpu.cortex-m0plus" valueType="enumerated"/>
<option id="com.freescale.s32ds.cross.gnu.tool.assembler.option.defs.61779642" name="Defined symbols (-D)" superClass="com.freescale.s32ds.cross.gnu.tool.assembler.option.defs" valueType="definedSymbols">
<listOptionValue builtIn="false" value="START_FROM_FLASH"/>
</option>
<inputType id="cdt.managedbuild.tool.gnu.assembler.input.1287111907" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
<inputType id="com.freescale.s32ds.cross.gnu.tool.assembler.inputType.asmfile.1451377905" superClass="com.freescale.s32ds.cross.gnu.tool.assembler.inputType.asmfile"/>
</tool>
<tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.createflash.1275028893" name="Standard S32DS Create Flash Image" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.createflash"/>
<tool id="com.freescale.s32ds.cross.gnu.tool.createlisting.1659250176" name="Standard S32DS Create Listing" superClass="com.freescale.s32ds.cross.gnu.tool.createlisting">
<option id="com.freescale.s32ds.cross.gnu.option.createlisting.source.1520368181" name="Display source (--source|-S)" superClass="com.freescale.s32ds.cross.gnu.option.createlisting.source" value="true" valueType="boolean"/>
<option id="com.freescale.s32ds.cross.gnu.option.createlisting.allheaders.2009348998" name="Display all headers (--all-headers|-x)" superClass="com.freescale.s32ds.cross.gnu.option.createlisting.allheaders" value="true" valueType="boolean"/>
<option id="com.freescale.s32ds.cross.gnu.option.createlisting.demangle.1413606789" name="Demangle names (--demangle|-C)" superClass="com.freescale.s32ds.cross.gnu.option.createlisting.demangle" value="true" valueType="boolean"/>
<option id="com.freescale.s32ds.cross.gnu.option.createlisting.linenumbers.820482102" name="Display line numbers (--line-numbers|-l)" superClass="com.freescale.s32ds.cross.gnu.option.createlisting.linenumbers" value="true" valueType="boolean"/>
<option id="com.freescale.s32ds.cross.gnu.option.createlisting.wide.1112495897" name="Wide lines (--wide|-w)" superClass="com.freescale.s32ds.cross.gnu.option.createlisting.wide" value="true" valueType="boolean"/>
</tool>
<tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.printsize.1044000140" name="Standard S32DS Print Size" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.printsize">
<option id="com.freescale.s32ds.cross.gnu.option.printsize.format.15544545" name="Size format" superClass="com.freescale.s32ds.cross.gnu.option.printsize.format"/>
</tool>
<tool id="com.freescale.s32ds.cross.gnu.c.preprocessor.246627784" name="Standard S32DS C Preprocessor" superClass="com.freescale.s32ds.cross.gnu.c.preprocessor"/>
<tool id="com.freescale.s32ds.cross.gnu.cpp.preprocessor.1351637021" name="Standard S32DS C++ Preprocessor" superClass="com.freescale.s32ds.cross.gnu.cpp.preprocessor"/>
<tool id="com.freescale.s32ds.cross.gnu.disassembler.1930208815" name="Standard S32DS Disassembler" superClass="com.freescale.s32ds.cross.gnu.disassembler"/>
</toolChain>
</folderInfo>
<sourceEntries>
<entry excluding="Project_Settings" flags="VALUE_WORKSPACE_PATH" kind="sourcePath" name=""/>
</sourceEntries>
</configuration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<project id="Boot.com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.2015036423" name="ARM32 Executable" projectType="com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe"/>
</storageModule>
<storageModule moduleId="scannerConfiguration">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
<scannerConfigBuildInfo instanceId="com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.release.2059606998;com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.release.2059606998.;com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.31149033;cdt.managedbuild.tool.gnu.c.compiler.input.126808481">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
<scannerConfigBuildInfo instanceId="com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.release.ram.1486592527;com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.release.ram.1486592527.;com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.1965338887;cdt.managedbuild.tool.gnu.c.compiler.input.1428969283">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
<scannerConfigBuildInfo instanceId="com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.ram.1790416382;com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.ram.1790416382.;com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.853795767;cdt.managedbuild.tool.gnu.c.compiler.input.183476160">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
<scannerConfigBuildInfo instanceId="com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.1550428572;com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.1550428572.;com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.1117844436;cdt.managedbuild.tool.gnu.c.compiler.input.1553525050">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
<storageModule moduleId="org.eclipse.embsys" parent_project="true" register_architecture="" register_board="--- none ---" register_chip="" register_core="" register_vendor=""/>
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
<storageModule moduleId="refreshScope" versionNumber="2">
<configuration configurationName="Debug">
<resource resourceType="PROJECT" workspacePath="/Boot"/>
</configuration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
</cproject>

59
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/.project Normal file
View File

@ -0,0 +1,59 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>Boot</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
<linkedResources>
<link>
<name>core</name>
<type>2</type>
<locationURI>OPENBLT_CORE</locationURI>
</link>
</linkedResources>
<filteredResources>
<filter>
<id>1585049461138</id>
<name>core</name>
<type>9</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-ARMCM0_S32K11</arguments>
</matcher>
</filter>
<filter>
<id>1585049472883</id>
<name>core/ARMCM0_S32K11</name>
<type>9</type>
<matcher>
<id>org.eclipse.ui.ide.multiFilter</id>
<arguments>1.0-name-matches-false-false-GCC</arguments>
</matcher>
</filter>
</filteredResources>
<variableList>
<variable>
<name>OPENBLT_CORE</name>
<value>$%7BPARENT-3-PROJECT_LOC%7D/Source</value>
</variable>
</variableList>
</projectDescription>

8
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/.settings/com.nxp.s32ds.cle.runtime.component.prefs Normal file
View File

@ -0,0 +1,8 @@
com.nxp.s32ds.cle.runtime.component.registry.archetype.id=application
com.nxp.s32ds.cle.runtime.component.registry.archetype.platform.id=
com.nxp.s32ds.cle.runtime.hardware.registry.core.id=CortexM0P
com.nxp.s32ds.cle.runtime.hardware.registry.device.id=S32K118
com.nxp.s32ds.cle.runtime.hardware.registry.deviceCore.id=S32K118_M0P
com.nxp.s32ds.cle.runtime.hardware.registry.family.id=S32K1
com.nxp.s32ds.cle.runtime.lang.registry.lang.id=c
eclipse.preferences.version=1

2
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/.settings/com.processorexpert.core.ide.newprojectwizard.prefs Normal file
View File

@ -0,0 +1,2 @@
eclipse.preferences.version=1
versionGenerated/versionGenerated=1.8.4.RT7_b1743-0713

14
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/.settings/language.settings.xml Normal file
View File

@ -0,0 +1,14 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project>
<configuration id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.1550428572" name="Debug">
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
<provider class="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" console="false" env-hash="1495519144810931747" id="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT S32DS Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>
</extension>
</configuration>
</project>

3
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/.settings/org.eclipse.cdt.codan.core.prefs Normal file
View File

@ -0,0 +1,3 @@
eclipse.preferences.version=1
inEditor=false
onBuild=false

21
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/.settings/org.eclipse.cdt.core.prefs Normal file
View File

@ -0,0 +1,21 @@
eclipse.preferences.version=1
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.1550428572/PATH/delimiter=;
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.1550428572/PATH/operation=prepend
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.1550428572/PATH/value=
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.1550428572/append=true
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.1550428572/appendContributed=true
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.ram.1790416382/PATH/delimiter=;
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.ram.1790416382/PATH/operation=prepend
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.ram.1790416382/PATH/value=
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.ram.1790416382/append=true
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.ram.1790416382/appendContributed=true
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.release.2059606998/PATH/delimiter=;
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.release.2059606998/PATH/operation=prepend
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.release.2059606998/PATH/value=
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.release.2059606998/append=true
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.release.2059606998/appendContributed=true
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.release.ram.1486592527/PATH/delimiter=;
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.release.ram.1486592527/PATH/operation=prepend
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.release.ram.1486592527/PATH/value=
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.release.ram.1486592527/append=true
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.release.ram.1486592527/appendContributed=true

221
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/Boot_Debug.launch Normal file
View File

@ -0,0 +1,221 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<launchConfiguration type="com.pemicro.debug.gdbjtag.pne.launchConfigurationType">
<stringAttribute key="bad_container_name" value="\Boot\Project_Settings\Debugge"/>
<stringAttribute key="com.nxp.s32ds.ext.cdt.debug.svd.svd_path" value=""/>
<booleanAttribute key="com.nxp.s32ds.ext.cdt.debug.svd.use_default" value="true"/>
<listAttribute key="com.pemicro.debug.gdbjtag.pne.ELVES"/>
<listAttribute key="com.pemicro.debug.gdbjtag.pne.ELVES_OFFSET"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.NUMBER_ELVES" value="0"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.BUSERR" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.CHKERR" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.CORERESET" value="true"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.DEVICE_NAME" value="NXP_S32K1xx_S32K118F256M4"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.GDB_OPTIONS" value=""/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.HARDERR" value="true"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.PE.HARDWARE_INTERFACE" value="6"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.INTERR" value="true"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.LAST_ATTRIBUTE_HEADER" value="com.pemicro.debug.gdbjtag.pne.sda."/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.MMERR" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.NOCPERR" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.STATERR" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.STREAMING_ENABLE_PORT1" value="true"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.STREAMING_SERVER_PORT1" value="10224"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.USE_EXTERNAL_SERVER" value="true"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.algorithmIndex" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.alternativeAlgorithmPath" value=""/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.attachToRunning" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.customTrimFrequency" value="0"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.ALWAYS_ERASE" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.CYCLONE_IP" value=""/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.DO_RESET_DELAY" value="false"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.INTERFACE_PORT" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.INTERFACE_PORT_STRING" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.NETWORK_CARD_IP" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.POWER_DOWN_DELAY" value="250"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.POWER_OFF" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.POWER_UP_DELAY" value="250"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.PROVIDE_POWER" value="true"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.REGULATOR_VOLTAGE" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.RESET_DELAY" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.SHIFT_FREQ" value="5000"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.SPECIFY_IP" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.SPECIFY_NETWORK_CARD" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.STARTUP_USE_SWD" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.ALWAYS_ERASE" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.CYCLONE_IP" value=""/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.DO_RESET_DELAY" value="false"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.INTERFACE_PORT" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.INTERFACE_PORT_STRING" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.NETWORK_CARD_IP" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.POWER_DOWN_DELAY" value="250"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.POWER_OFF" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.POWER_UP_DELAY" value="250"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.PROVIDE_POWER" value="true"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.REGULATOR_VOLTAGE" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.RESET_DELAY" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.SHIFT_FREQ" value="5000"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.SPECIFY_IP" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.SPECIFY_NETWORK_CARD" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.STARTUP_USE_SWD" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.ALWAYS_ERASE" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.CYCLONE_IP" value=""/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.DO_RESET_DELAY" value="false"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.INTERFACE_PORT" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.INTERFACE_PORT_STRING" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.NETWORK_CARD_IP" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.POWER_DOWN_DELAY" value="250"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.POWER_OFF" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.POWER_UP_DELAY" value="250"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.PROVIDE_POWER" value="true"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.REGULATOR_VOLTAGE" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.RESET_DELAY" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.SHIFT_FREQ" value="5000"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.SPECIFY_IP" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.SPECIFY_NETWORK_CARD" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.STARTUP_USE_SWD" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doContinue" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doGdbServerAllocateSemihostingConsole" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doPartitioning" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.enableSemihosting" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.enableSemihostingIoclientGdbClient" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.enableSemihostingIoclientTelnet" value="true"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.eraseCommandParam" value="EM"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.eraseOptionIndex" value="0"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.eraseOptionsenabled" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.executeUnlockCommand" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbClientOtherCommands" value="set mem inaccessible-by-default off&#13;&#10;set tcp auto-retry on&#13;&#10;set tcp connect-timeout 240&#13;&#10;set remotetimeout 60"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbClientOtherOptions" value=""/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerTelnetPortNumber" value="51794"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.gdbmiPortNumber" value="6224"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.jtagPreIrBits" value="0"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.jtagTapNumber" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.macScript" value=""/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.macScriptEnable" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.ALWAYS_ERASE" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.CYCLONE_IP" value=""/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.DO_RESET_DELAY" value="false"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.ml.INTERFACE_PORT" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.INTERFACE_PORT_STRING" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.NETWORK_CARD_IP" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.POWER_DOWN_DELAY" value="250"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.POWER_OFF" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.POWER_UP_DELAY" value="1000"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.PROVIDE_POWER" value="true"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.ml.REGULATOR_VOLTAGE" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.RESET_DELAY" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.SHIFT_FREQ" value="5000"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.SPECIFY_IP" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.SPECIFY_NETWORK_CARD" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.STARTUP_USE_SWD" value="true"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.otherRunCommands" value=""/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.partitionParam" value="0"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemory0" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemory1" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemory2" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryFrom0" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryFrom1" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryFrom2" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryTo0" value="3"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryTo1" value="3"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryTo2" value="3"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.preservePartioning" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.programtrim" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.ALWAYS_ERASE" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.CYCLONE_IP" value=""/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.DO_RESET_DELAY" value="false"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.sda.INTERFACE_PORT" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.INTERFACE_PORT_STRING" value="USB1"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.NETWORK_CARD_IP" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.POWER_DOWN_DELAY" value=""/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.POWER_OFF" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.POWER_UP_DELAY" value=""/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.PROVIDE_POWER" value="true"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.sda.REGULATOR_VOLTAGE" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.RESET_DELAY" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.SHIFT_FREQ" value="5000"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.SPECIFY_IP" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.SPECIFY_NETWORK_CARD" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.STARTUP_USE_SWD" value="true"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.SWO_BAUDRATE_SWITCH_MULTILINK_VALUE" value="-1.000000"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.SWO_BAUDRATE_SWITCH_TARGET_VALUE" value="-1.000000"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.selectedCoreNumber" value="1"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.serverPortNumber" value="7224"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.ALWAYS_ERASE" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.CYCLONE_IP" value=""/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.DO_RESET_DELAY" value="false"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.INTERFACE_PORT" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.INTERFACE_PORT_STRING" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.NETWORK_CARD_IP" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.POWER_DOWN_DELAY" value="250"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.POWER_OFF" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.POWER_UP_DELAY" value="250"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.PROVIDE_POWER" value="true"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.REGULATOR_VOLTAGE" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.RESET_DELAY" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.SHIFT_FREQ" value="5000"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.SPECIFY_IP" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.SPECIFY_NETWORK_CARD" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.STARTUP_USE_SWD" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.ALWAYS_ERASE" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.CYCLONE_IP" value=""/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.DO_RESET_DELAY" value="false"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.INTERFACE_PORT" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.INTERFACE_PORT_STRING" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.NETWORK_CARD_IP" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.POWER_DOWN_DELAY" value="250"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.POWER_OFF" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.POWER_UP_DELAY" value="250"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.PROVIDE_POWER" value="true"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.REGULATOR_VOLTAGE" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.RESET_DELAY" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.SHIFT_FREQ" value="5000"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.SPECIFY_IP" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.SPECIFY_NETWORK_CARD" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.STARTUP_USE_SWD" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.useAlternativeAlgorithm" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.useCustomTrim" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.useDaisyChain" value="false"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU ARM PEMicro Interface"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${S32DS_ARM32_TOOLCHAIN_DIR}/bin/${arm32_cross_prefix}gdb${arm32_cross_suffix}"/>
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/openblt_s32k118.elf"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="Boot"/>
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.1550428572"/>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
<listEntry value="/Boot"/>
</listAttribute>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
<listEntry value="4"/>
</listAttribute>
<stringAttribute key="org.eclipse.debug.core.source_locator_id" value="org.eclipse.cdt.debug.core.sourceLocator"/>
<stringAttribute key="org.eclipse.debug.core.source_locator_memento" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;sourceLookupDirector&gt;&#13;&#10;&lt;sourceContainers duplicates=&quot;false&quot;&gt;&#13;&#10;&lt;container memento=&quot;&amp;lt;?xml version=&amp;quot;1.0&amp;quot; encoding=&amp;quot;UTF-8&amp;quot; standalone=&amp;quot;no&amp;quot;?&amp;gt;&amp;#13;&amp;#10;&amp;lt;mapping backend_enabled=&amp;quot;true&amp;quot; name=&amp;quot;EWL&amp;quot;&amp;gt;&amp;#13;&amp;#10;&amp;lt;mapEntry memento=&amp;quot;&amp;amp;lt;?xml version=&amp;amp;quot;1.0&amp;amp;quot; encoding=&amp;amp;quot;UTF-8&amp;amp;quot; standalone=&amp;amp;quot;no&amp;amp;quot;?&amp;amp;gt;&amp;amp;#13;&amp;amp;#10;&amp;amp;lt;mapEntry backendPath=&amp;amp;quot;arm32_ewl2&amp;amp;quot; localPath=&amp;amp;quot;C:\NXP\S32DS_ARM_v2.2\S32DS\build_tools\gcc_v6.3\arm32_ewl2&amp;amp;quot;/&amp;amp;gt;&amp;amp;#13;&amp;amp;#10;&amp;quot;/&amp;gt;&amp;#13;&amp;#10;&amp;lt;/mapping&amp;gt;&amp;#13;&amp;#10;&quot; typeId=&quot;org.eclipse.cdt.debug.core.containerType.mapping&quot;/&gt;&#13;&#10;&lt;container memento=&quot;&amp;lt;?xml version=&amp;quot;1.0&amp;quot; encoding=&amp;quot;UTF-8&amp;quot; standalone=&amp;quot;no&amp;quot;?&amp;gt;&amp;#13;&amp;#10;&amp;lt;default/&amp;gt;&amp;#13;&amp;#10;&quot; typeId=&quot;org.eclipse.debug.core.containerType.default&quot;/&gt;&#13;&#10;&lt;/sourceContainers&gt;&#13;&#10;&lt;/sourceLookupDirector&gt;&#13;&#10;"/>
<listAttribute key="org.eclipse.debug.ui.favoriteGroups">
<listEntry value="org.eclipse.debug.ui.launchGroup.debug"/>
</listAttribute>
<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#13;&#10;"/>
<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
</launchConfiguration>

BIN
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/Debug/openblt_s32k118.elf Normal file
View File

Binary file not shown.

435
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/Debug/openblt_s32k118.srec Normal file
View File

@ -0,0 +1,435 @@
S01700006F70656E626C745F7333326B3131382E73726563DD
S1130000005800203D0500009905000099050000F6
S113001000000000000000000000000000000000DC
S1130020000000000000000000000000990500002E
S11300300000000000000000990500009905000080
S11300409905000099050000990500009905000034
S11300509905000099050000990500009905000024
S11300609905000099050000990500009905000014
S11300709905000099050000990500009905000004
S113008099050000990500009905000099050000F4
S113009099050000990500009905000099050000E4
S11300A099050000990500009905000099050000D4
S11300B099050000990500009905000099050000C4
S1130400FFFFFFFFFFFFFFFFFFFFFFFFFE7FFFFF79
S1130410054B0648033310B51B1A062B03D9044BAE
S1130420002B00D0984710BD2C0100202C01002087
S1130430000000000648074910B5091A8910CB0FBF
S11304405918491003D0044B002B00D0984710BD15
S11304502C0100202C0100200000000010B5074CE6
S11304602378002B09D1FFF7D3FF054B002B02D0D3
S1130470044800E000BF0123237010BDC0300020F9
S1130480000000005C1D0000094B10B5002B03D0D8
S11304900849094800E000BF08480368002B02D15E
S11304A0FFF7C8FF10BD064B002BF9D09847F7E7BC
S11304B000000000C43000205C1D00002801002062
S11304C000000000164B002B00D1144B9D46402227
S11304D092029A1A924600218B460F461348144AF8
S11304E0121A01F0E5FA0F4B002B00D098470E4B7F
S11304F0002B00D098470020002104000D000D4877
S1130500002802D00C4800E000BF01F0ADFA200042
S1130510290000F033F901F091FAC0460000080008
S1130520005800200000000000000000C03000203F
S1130530D4330020000000000000000072B610490F
S11305400F4A0F4B0E4C0E4D0D4E0D4FB846B9468B
S1130550BA46BB46BC460B490B4A521A013A05DD62
S11305600020042308601944043AFBDA074885464E
S1130570074880470748804762B6FFF7A3FFFEE7B6
S11305800000000000000020005800200058002057
S1130590E118000061190000FEE7C046002243088C
S11305A08B4274D303098B425FD3030A8B4244D337
S11305B0030B8B4228D3030C8B420DD3FF22090279
S11305C012BA030C8B4202D31212090265D0030B38
S11305D08B4219D300E0090AC30B8B4201D3CB032E
S11305E0C01A5241830B8B4201D38B03C01A524170
S11305F0430B8B4201D34B03C01A5241030B8B4272
S113060001D30B03C01A5241C30A8B4201D3CB025C
S1130610C01A5241830A8B4201D38B02C01A524141
S1130620430A8B4201D34B02C01A5241030A8B4244
S113063001D30B02C01A5241CDD2C3098B4201D35C
S1130640CB01C01A524183098B4201D38B01C01ADA
S1130650524143098B4201D34B01C01A5241030951
S11306608B4201D30B01C01A5241C3088B4201D300
S1130670CB00C01A524183088B4201D38B00C01AAD
S1130680524143088B4201D34B00C01A5241411AD4
S113069000D20146524110467047FFE701B50020E1
S11306A000F006F802BDC0460029F7D076E770478F
S11306B07047C04610B5054B1B6900201B0700D5C9
S11306C010BD00F051F80120FAE7C046C0F00F4019
S11306D010B5642000F006F810BD10B500F016F84F
S11306E010BD000080235B00054A1362054A51696E
S11306F01943516191680B439360034B1880704711
S113070000D0044000F10F40DC30002010B500F0B0
S11307106DFE114B1B68984213D3104B1B78002BB2
S113072010D101220D4B1A700D4A516880235B00D1
S11307300B43536000F05AFE0A4B1B881818064BF3
S1130740186010BD0022054B1A70054A9168802379
S11307505B000B439360EDE7E0300020DE300020C7
S113076000F10F40DC300020034A916880235B00D5
S11307700B4393607047C04600F10F4010B5354BF2
S11307800221FF31822252009950CD39043299500E
S11307901900083A80231B0488581842FCD101210F
S11307A080235B002B4AD15011001A0080235B0484
S11307B088581842FCD0274B0222FF32C1218900FD
S11307C05A500139FF395A50234A5A6119000F22ED
S11307D00B691B0E1340032BFAD101F093F81F4B46
S11307E09420400019588022D20511431950083032
S11307F01958114319509A214900585802435A5024
S1130800174BD968802252000A43DA60DA68022161
S11308108A43DA60134B5A6906318A435A619A69EA
S11308208A439A61104B196880229200114319601F
S113083059680A435A600D4B1969A022D20011432A
S1130840196159690A435A6100F01AFE00F026FE44
S1130850FCE7C0460040064001000003005006408B
S113086000C00440C0F00F4000A0044000D0044089
S113087072B6704762B6704770B50D4B1B68002B9B
S113088000DB70BD0A4A13685B005B08136000F06C
S1130890ADFDFA300400064E80256D0333682B420B
S11308A0EFD000F088FE00F0A1FD8442F6D2E8E724
S11308B00040024070B5124B1B68002B1BDB104B31
S11308C019688022D2050A431A60196880225205E9
S11308D00A431A6000F08AFDFA300400084E8025AD
S11308E06D0433682B4205D100F065FE00F07EFDF7
S11308F08442F6D270BDD021024800F07FFDDEE7CD
S113090000400240C41A0000F0B585B0934990221B
S113091088588023DB0503438B50FFF7ADFFFFF7B7
S1130920C9FF8F4B1B68002B15DB8D4A1168802390
S11309301B060B43136000F059FDFA300400884E87
S113094080256D0333682B4205D100F034FE00F09E
S11309504DFD8442F6D2824A536882490B4053606B
S1130960FFF78AFFFFF7A6FF002302AA13700133E3
S11309705370013393700233D3700433137108330B
S11309805371103393712033D371C433764AD358DF
S11309905B055B0F06D1802149000533FF33D1503D
S11309A0043BFF3B02AAD15C7048FFF7F7FD0190BE
S11309B06F4F0026002503E001360437122E20D0A5
S11309C03A785401A41AA400A418A40021000198A0
S11309D0FFF76AFE0029EFD121000198FFF7DEFD41
S11309E085B26B1E9BB2FF2BE6D8B600604B9E19F6
S11309F07178B478F2780CE0F0215E4800F0FEFCE7
S1130A0080E07821FF315B4800F0F8FC00240021ED
S1130A100022534B5868584E304058605E68681E38
S1130A2000063043586058684D1E07212940014391
S1130A3059605868611EC904E025AD03294001438B
S1130A4059605968013A1204E020C00202400A4386
S1130A505A605A68231C042C00D90423DBB2013BDE
S1130A609B05C02109040B4013433D4A536053685E
S1130A7080210B4353600023100000211A00203210
S1130A80920011500133802BF8D100233448002107
S1130A90882292009A18920011500133202BF7D12A
S1130AA02F4B1A687F218A4360390A431A601968F8
S1130AB0802292020A431A601968802252020A4371
S1130AC01A601A682D490A401A602D492D4A995016
S1130AD08021C9048822520099502B49043299502C
S1130AE000229A62013A1A63284A1A621A6828494B
S1130AF00A401A605A6827490A405A601B68002B4A
S1130B0000DA79E7164B1A6823490A401A601A6812
S1130B1022490A401A6000F069FCFA300400104EC1
S1130B2080256D0433682B4205D000F044FD00F0AD
S1130B305DFC8442F6D200F059FCFA300400084E01
S1130B4080252D0533682B4205D000F034FD00F0DC
S1130B504DFC8442F6D205B0F0BDC04600500640BC
S1130B6000400240FFDFFFFF00400640409C0000C1
S1130B70081B0000C41A000078FF0000FFFFFFDF1D
S1130B80FFFFFF5FA408000000009C1906003B0063
S1130B90FFFF7FFFF7EFFFFFFFFFFFBFFFFFFFEF49
S1130BA070B5234A80235B001363D458E400E4083F
S1130BB0D450D4581F4D2C40D450D5588024E4032D
S1130BC02C43D450D4581C4D2C40D450D5580C042C
S1130BD0F026360334402C43D45000290BD0002394
S1130BE00326164DC45C1A007240D2B25455013328
S1130BF0DAB29142F6D80E4B114982225200995032
S1130C00802149005858C022120502435A5000F06E
S1130C10EDFB32300400064E80256D00336B2B4211
S1130C2005D100F0C8FC00F0E1FB8442F6D270BDAF
S1130C3000400240FFFFCFFFFFFFF0FF08410240EA
S1130C400000841F30B5124B1A6B002392051CD58B
S1130C501133FF330E4AD3581B031B0F0B700CD0F8
S1130C60002303250B4C1A006A40D2B2125DC25411
S1130C700133DBB20A789A42F5D8054B8022920000
S1130C801A639A68044B1A600123180030BDC046E9
S1130C900040024018410240E430002010B5FFF744
S1130CA0E7FD10BD10B500F074FA002800D110BDA6
S1130CB0FFF700FD0028FAD000F032FC00F082FBC0
S1130CC000F06BFA054B1840054B064AD050FFF76D
S1130CD0D1FD00F062FA43689847E8E780FFFF1F00
S1130CE0080D000000E000E070B5551EADB2002A0A
S1130CF00AD06D1801350C00461A2378335500F0DC
S1130D005AFC0134AC42F8D170BD000070B5060045
S1130D100A4D002404E00134E4B20C35132C0AD04B
S1130D2000F049FC2B68B342F5D86A6894466344E2
S1130D309E42F0D200E0EC34200070BD501B000055
S1130D40F0B5DE4657464E464546E0B583B080468C
S1130D500068FFF7DBFF00230193FF2807D1019808
S1130D6003B03CBC90469946A246AB46F0BD434610
S1130D701D1D82235B0043449B4601230193053BD5
S1130D8042469B1A9946284C70239A4607E0002352
S1130D90019301E00023019308355D45DFD04B4604
S1130DA05E1943461B689C46664400F004FC2378A5
S1130DB05BB2002B31DA534623700723E371330C03
S1130DC0DBB2A371330ADBB26371F3B223712B7804
S1130DD023726B786372AB78A372EB78E3722B792E
S1130DE023736B796373AB79A373EB79E37300F0CB
S1130DF0C3FF227871231A4212D132782B789A4297
S1130E00C5D1731C30000830AE1B1978F25C9142D6
S1130E10C0D101338342F8D1BEE7002301939EE79A
S1130E20002301939BE7C0460000024070B5040014
S1130E300D00124B98420CD080239B0199420AD09A
S1130E40FFF77EFF03000020002B13D0201E03D1E8
S1130E5010E00B4C00E0094CFF232B420BD123681C
S1130E609D4206D0200020C0802252002900FFF7B6
S1130E703BFF200070BD0020FCE7C046EC310020A1
S1130E80E8300020F0B5C64600B582B005000C007D
S1130E9016001F00FF230A009A439046036801339B
S1130EA00ED02B68984512D041462800FFF7BEFFAC
S1130EB005000020002D0AD102B004BC9046F0BD0C
S1130EC004C0802252004146FFF70EFFE9E70434D4
S1130ED02B68E41A2C1943460133FF33019306E0CF
S1130EE03378237001340136013F002F0DD000F018
S1130EF062FB2B1DE31AFF2BF2D901992800FFF79F
S1130F0095FF051E03D0041DEAE70120D4E7002065
S1130F10D2E7000001235B42024A1360024A1360D5
S1130F207047C046E8300020EC31002070B5040062
S1130F300E0015004A1E124B1B1A9A4201D90020BA
S1130F4070BDFFF7E3FEFF28F9D0601E8019FFF79C
S1130F50DDFEFF28F3D0FF2322009A4380239B0168
S1130F609A4206D033002A0021000648FFF78AFF80
S1130F70E6E733002A0021000348FFF783FFDFE799
S1130F80FFFF0300E8300020EC310020F0B5D64626
S1130F904F464646C0B504000D004A1E3C4B1B1A82
S1130FA09A4205D900201CBC90469946A246F0BD41
S1130FB0FFF7ACFE0600601E4019FFF7A7FE030012
S1130FC00200FF2EEED0FF28ECD0864201D900208B
S1130FD0E9E70020122AE6D87200921992002D49FE
S1130FE091468944721C981BC0B2121853009B1876
S1130FF09B009A468A44284C7023984604E00C23AC
S11310009C46E144CA4536D000F0D5FA4B461D68EB
S11310105B686A1C31D0002B31D06A0531D15A0586
S113102031D1DB0ADBB2002BE9D0013BDEB2F602A0
S113103080231B01EB18F618092700F0BCFA23786B
S11310405BB2002B21DA43462370E7712B0CDBB231
S1131050A3712B0ADBB26371EBB2237100F08CFE37
S1131060227871231A4210D180231B019C466544C7
S1131070AE42E2D1C3E7012095E7002093E70020C8
S113108091E700208FE700208DE700208BE7C04622
S1131090FFFF0300501B00000000024000B583B0B6
S11310A0104B1B68012001331AD00E4A5368916813
S11310B08C466344D1688C46634411698C4663440E
S11310C051698C46634491698C466344D2699B1888
S11310D05B42019301AA042183208001FFF726FFCC
S11310E003B000BDEC31002080239B0118680D4B38
S11310F01B68C0180C4B1B68C0180C4B1B68C0182D
S11311000B4B1B68C0180B4B1B68C0180A4B1B68A1
S1131110C01883239B011B68C01843425841C0B2C6
S11311207047C04604200000082000000C20000086
S113113010200000142000001820000010B50B4BF4
S11311401B68013305D00948FFF7FAFD002800D1D8
S113115010BD074B1B6801200133F9D00448FFF789
S1131160EFFD431E9841C0B2F2E7C046EC310020C7
S1131170E830002080208001704710B5FFF7CAFED8
S113118010BD10B5FFF7D2FE10BD10B5FFF7FEFE7F
S113119010BD10B5FFF7A8FF10BD10B5FFF7EAFFAB
S11311A010BD10B5FFF77AFF002800D110BDFFF77E
S11311B0C5FFFBE770B5094BD86100F017F90A3099
S11311C00400064E80252D0473692B4205D100F0DE
S11311D0F2F900F00BF98442F6D270BD00A006408B
S11311E000B583B000236A46137001335370013392
S11311F093700233D3700433137108335371103373
S113120093712033D371244A6933FF33D15823486F
S11312100140D150D0588421C9050143D1505C33D9
S11312201F4AD3585B055B0F08D11100812292003D
S113123088580133FF3303438B50012382229200E9
S113124017498A58D20724D416486A46D15CFFF756
S1131250A5F9E1210902FFF7A1F907300004C00C48
S1131260E023DB041843104B1861104A5A61002232
S11312709A611A625A62F02292029A629A6A8821E8
S11312800A439A620122DA62C02212039A6103B00D
S113129000BD0748D9E7C04600500640FFFFFFBF26
S11312A00040064080841E0000A0064000C01FC00D
S11312B000127A0070B506000D00402913D82800EA
S11312C0FFF778FFADB2002D0CD03400013DADB274
S11312D00135751900F06FF92078FFF76BFF0134C1
S11312E0AC42F7D170BDC221014800F087F8E6E7AF
S11312F0341C000070B50D00244B1C78002C16D152
S1131300234B5B699B0224D5214BDB69DBB2214A69
S11313101370013B3F2B1CD800F068F81E4B18607B
S113132000221E4B1A700132184B1A7011E0184B30
S11313305B699B021CD519490A78154BDE69154B6C
S11313409C1866700132D2B20A701B780024934252
S113135001D0200070BD92B20E490131FFF7C4FCE8
S113136000220A4B1A700D4B1B782B700134F0E7E6
S113137000F03CF8084B1B686433984204D90022FF
S1131380024B1A700024E4E70024E2E73133002022
S113139000A00640F0320020343300203233002015
S11313A0054B00221A60054959609A6005211960AD
S11313B0034B1A607047C04610E000E07FBB00009A
S11313C0383300200022014B1A60704710E000E01F
S11313D0044B1B68DB0303D5034A13680133136012
S11313E07047C04610E000E03833002010B5FFF726
S11313F0EFFF014B186810BD3833002010B500F022
S1131400DAF8FCE710B500F0CBF8012803D00B4B59
S11314101B78012B00D010BDFFF7E8FF084B1B68B9
S1131420084A12689B18F533FF339842F3D300221D
S1131430024B1A70FFF736FCEDE7C046403300203C
S11314403C3300204433002010B5054B1B78012B9E
S113145000D010BDFFF7CAFF024B1860F9E7C04681
S1131460403300204433002010B50122034B1A708E
S1131470FFF7EAFFFFF7C6FF10BDC0464033002068
S113148010B5FFF70BFC00F092F8FFF789FFFFF7A8
S113149074FE00F00DF8FFF7E7FF10BD10B500F083
S11314A08AF8FFF795FF00F013F8FFF7ABFF10BDC4
S11314B010B500F08FF8FFF727FA044C01232370CE
S11314C0FFF78EFE0023237010BDC046C00000202D
S11314D000B583B06B46D91D0F48FFF7B3FB012855
S11314E008D06B46D91D0C48FFF704FF01280AD029
S11314F003B000BD0122094B1A706B46D979064826
S113150000F086F8EDE70022044B1A706B46D97997
S1131510014800F07DF8EBE748330020C0000020CC
S11315207047000070B505000C000A4B1B78012BB6
S113153006D0084B1B78002B06D000F061F870BD74
S1131540C9B2FFF72DFBF4E7E1B22800FFF7B2FEC2
S1131550F3E7C046C0000020074B1B78022B06D0DF
S1131560032B06D00820012B02D0402000E00020ED
S113157070470020FCE7C046C0000020074B1B78E2
S1131580022B06D0032B06D00820012B02D04020CA
S113159000E0002070470020FCE7C046C0000020A7
S11315A010B500F025F8431E9841C0B210BD10B527
S11315B0FFF78EF810BD10B5FFF78FF810BD0000CF
S11315C0034BFE22DA7018710221BA3A995270471D
S11315D088330020054B00221A709A6443215A5420
S11315E001315A529A705A707047C04688330020AD
S11315F0024B1878431E9841C0B2704788330020CC
S113160000214323014AD1547047C0468833002047
S113161070B504000378FF2B04D0AE4A1278012A77
S113162027D070BDAB4C0023637001252570FF22C9
S1131630E270EF3A22716371FFF78EFFA071FFF73A
S11316409DFFE071FFF79AFF000A20726572A57290
S113165008224423E252FFF790FD43239D4AD35CC2
S1131660012B00D131E144239A4AD15E0029D8DD0F
S113167052E03733DAB2352A00D922E19300964A90
S1131680D3589F464578FFF767FF0138854211DC40
S11316906278904D281DA96CFFF726FBFF23EB70A1
S11316A06378AA6C94466344AB6463780133442240
S11316B0AB52D2E72220FFF783FFCEE74578FFF74E
S11316C04BFF0138854212DC6168824DA96462785F
S11316D0281DFFF709FBFF23EB706378AA6C94467F
S11316E06344AB64637801334422AB52B5E72220F0
S11316F0FFF766FFB1E7774BFF22DA7042689A641E
S11317000121442299524323724AD35C012B00D114
S1131710DBE044236F4AD15E6E4801224323C25466
S113172089B20330FFF7FEFE7BE76A4BFF22DA70D3
S11317309D6C4668002E19D0AE1900242B78E4184D
S1131740E4B20135FFF737FFB542F7D1614A002013
S1131750D471002313725372240E947201331371E3
S11317605071907108214333D152CCE70024EDE746
S1131770584BFF22DA70594A9A6400221A715A713E
S11317809A710721D971002119725972997208311D
S113179044229952B7E70020FFF712FF5DE74D4B53
S11317A0FF22DA7000221A71597859719A71DA712C
S11317B01A72062144329952A5E7464B00221A7048
S11317C05A70FF32DA700121BB3A99529BE7414BC0
S11317D09D6CFFF7C1FE621C411E2800FFF7D1FC7F
S11317E000280DD03B4CFF23E370FFF7B5FE013812
S11317F0A36C9C466044A06401224423E25282E725
S11318003130FFF7DDFE28E74578FFF7A5FE023803
S1131810854211DC2F4BFF22DA700121BB3A995229
S1131820617800290CD1FFF7BCFC002800D014E734
S11318303130FFF7C5FE10E72220FFF7C1FE0CE7A9
S1131840A21C244B986CFFF79CFC002806D0214A6C
S11318506378916C8C4663449364FEE63130FFF701
S1131860AFFEFAE61B4CFF23E3700025257165717A
S1131870FFF772FEA071E571257265720722442399
S1131880E25240E74168134B986CFFF77EFC002856
S113189006D0104BFF22DA700121BB3A995232E78D
S11318A03130FFF78DFED8E6FFF7FCF9094BFF2234
S11318B0DA700121BB3A995225E73120FFF780FE07
S11318C0CBE62020FFF77CFEC7E61020FFF778FE6A
S11318D0C9E6C04688330020781C0000501D000073
S11318E0044B054A5A605A68044A1A60044A9A60CA
S11318F07047C0460020054020C528D9202100009B
S1131900FFFF000010B5124B19691B691B011B0F67
S1131910022B0CD0032B12D0012B07D10D48090345
S1131920090F0131FEF73AFE0B4B186010BD8223FC
S11319309B00074AD358DB07F8D50648EFE7C223D4
S11319409B00034AD3589B07F0D10448E7E7C046FD
S11319500040064000127A00C4000020006CDC0243
S113196030B5274A274B9A4209D02649891A0023C1
S1131970254C1000C25CE25401338B42FAD1234A55
S1131980234B9A4209D02249891A0023214C100082
S1131990C25CE25401339942FAD11F4A1F4B9A4266
S11319A006D0130000211D4A197001339342FBD164
S11319B01B4A1C4B9A4209D01A49891A00231A4C13
S11319C01000C25CE25401339942FAD1174A184B11
S11319D09A4210D01749890809D000230022134CD9
S11319E01348C558E550013204338A42F9D1124BE9
S11319F00E4A1A6030BD104B0D4A1A60FAE7C04611
S1131A00981D0000041E0000C0000020041E0000F9
S1131A101C1E00002C010020C0300020D433002004
S1131A201C1E00001C1E0000C0300020000000200E
S1131A3000000000C000000008ED00E0084B10B5F5
S1131A400400002B02D0002100E000BF054B186801
S1131A50836A002B00D09847200000F031F8C0467C
S1131A6000000000581D000070B500260C4D0D4C00
S1131A70641BA410A64209D1002600F06FF90A4D98
S1131A800A4C641BA410A64205D170BDB300EB58E8
S1131A9098470136EEE7B300EB5898470136F2E772
S1131AA0901D0000901D0000901D0000941D00007A
S1131AB003008218934200D1704719700133F9E78B
S1131AC0FEE70000433A2F576F726B2F736F6674F3
S1131AD0776172652F4F70656E424C545F53333299
S1131AE04B31312F5461726765742F536F75726374
S1131AF0652F41524D434D305F5333324B31312FBB
S1131B0063616E2E630000000803020209030302EE
S1131B100A0303030B0403030C0404030D05040369
S1131B200E0504040F060404100605041107050439
S1131B301207050513080505140806051508070509
S1131B4016080706170808061808080719080808D9
S1131B50002000000008000004000000002800002D
S1131B60000800000500000000300000000800002C
S1131B700600000000380000000800000700000014
S1131B8000400000000800000800000000480000B9
S1131B9000080000090000000050000000080000D8
S1131BA00A00000000580000000800000B000000BC
S1131BB000600000000800000C0000000068000045
S1131BC0000800000D000000007000000008000084
S1131BD00E00000000780000000800000F00000064
S1131BE000800000008000001000000000000100E0
S1131BF0008000001100000000800100008000004F
S1131C001200000000000200008000001300000029
S1131C1000800200008000001400000000000300A7
S1131C200080000015000000008003000080000018
S1131C3016000000433A2F576F726B2F736F667450
S1131C40776172652F4F70656E424C545F53333227
S1131C504B31312F5461726765742F536F75726302
S1131C60652F41524D434D305F5333324B31312F49
S1131C7072733233322E6300CE170000C218000094
S1131C80C2180000BA180000C2180000C2180000F0
S1131C90A818000008180000841800006418000048
S1131CA0C2180000C2180000C2180000C2180000C8
S1131CB0C2180000C2180000C2180000C2180000B8
S1131CC0C2180000C2180000C2180000C2180000A8
S1131CD0C2180000C2180000C2180000C218000098
S1131CE0C2180000C2180000C2180000C218000088
S1131CF0C2180000C2180000C2180000C218000078
S1131D00C2180000C2180000C2180000C218000067
S1131D10C2180000C2180000C2180000C218000057
S1131D202A170000BC16000084160000F6160000F6
S1131D30C2180000C2180000C2180000701700008A
S1131D40C2180000961700009E170000BA17000082
S1131D504F70656E424C5400C8000020F8B5C04670
S1131D60F8BC08BC9E467047F8B5C046F8BC08BC31
S1131D709E4670470000000001B40248844601BC3E
S10B1D80604700BF2D010020A3
S10B1D883CE7FF7F01000000AD
S1071D9089040000BE
S1071D945D040000E6
S1131D9804000000006CDC020000000000000000E9
S1131DA80000000000000000000000000000000027
S1131DB80000000000000000000000000000000017
S1131DC80000000000000000000000000000000007
S1131DD800000000000000000000000000000000F7
S1131DE800000000000000000000000000000000E7
S10F1DF8000000000000000000000000DB
S1131E04044A137880210B43137013785BB2002BBC
S10B1E14FBDA704700000240F4
S903053DBA

278
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/S32K118_25_flash.ld Normal file
View File

@ -0,0 +1,278 @@
/*
** ###################################################################
** Processor: S32K118 with 25 KB SRAM
** Compiler: GNU C Compiler
**
** Abstract:
** Linker file for the GNU C Compiler
**
** Copyright 2018 NXP
** All rights reserved.
**
** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
** THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** ###################################################################
*/
/* Entry Point */
ENTRY(Reset_Handler)
/*
To use "new" operator with EWL in C++ project the following symbol shall be defined
*/
/*EXTERN(_ZN10__cxxabiv119__terminate_handlerE)*/
HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x00000200;
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x00000200;
/* If symbol __flash_vector_table__=1 is defined at link time
* the interrupt vector will not be copied to RAM.
* Warning: Using the interrupt vector from Flash will not allow
* INT_SYS_InstallHandler because the section is Read Only.
*/
M_VECTOR_RAM_SIZE = DEFINED(__flash_vector_table__) ? 0x0 : 0x00C0;
/* Specify the memory areas */
MEMORY
{
/* Flash */
m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x000000C0
m_flash_config (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000010
m_text (RX) : ORIGIN = 0x00000410, LENGTH = 0x00001BF0
/* SRAM_L */
/* SRAM_U */
m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x000030C0
m_data_2 (RW) : ORIGIN = 0x200030C0, LENGTH = 0x00002740
}
/* Define output sections */
SECTIONS
{
/* The startup code goes first into internal flash */
.interrupts :
{
__VECTOR_TABLE = .;
__interrupts_start__ = .;
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
__interrupts_end__ = .;
. = ALIGN(4);
} > m_interrupts
.flash_config :
{
. = ALIGN(4);
KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */
. = ALIGN(4);
} > m_flash_config
/* The program code and other data goes into internal flash */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
} > m_text
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > m_text
.ARM :
{
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} > m_text
.ctors :
{
__CTOR_LIST__ = .;
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
} > m_text
.dtors :
{
__DTOR_LIST__ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__DTOR_END__ = .;
} > m_text
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} > m_text
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} > m_text
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} > m_text
__etext = .; /* Define a global symbol at end of code. */
__DATA_ROM = .; /* Symbol is used by startup for data initialization. */
.interrupts_ram :
{
. = ALIGN(4);
__VECTOR_RAM__ = .;
__RAM_START = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start. */
*(.m_interrupts_ram) /* This is a user defined section. */
. += M_VECTOR_RAM_SIZE;
. = ALIGN(4);
__interrupts_ram_end__ = .; /* Define a global symbol at data end. */
} > m_data
__VECTOR_RAM = DEFINED(__flash_vector_table__) ? ORIGIN(m_interrupts) : __VECTOR_RAM__ ;
__RAM_VECTOR_TABLE_SIZE = DEFINED(__flash_vector_table__) ? 0x0 : (__interrupts_ram_end__ - __interrupts_ram_start__) ;
.data : AT(__DATA_ROM)
{
. = ALIGN(4);
__DATA_RAM = .;
__data_start__ = .; /* Create a global symbol at data start. */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
KEEP(*(.jcr*))
. = ALIGN(4);
__data_end__ = .; /* Define a global symbol at data end. */
} > m_data
__DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
__CODE_ROM = __DATA_END; /* Symbol is used by code initialization. */
.code : AT(__CODE_ROM)
{
. = ALIGN(4);
__CODE_RAM = .;
__code_start__ = .; /* Create a global symbol at code start. */
__code_ram_start__ = .;
*(.code_ram) /* Custom section for storing code in RAM */
. = ALIGN(4);
__code_end__ = .; /* Define a global symbol at code end. */
__code_ram_end__ = .;
} > m_data
__CODE_END = __CODE_ROM + (__code_end__ - __code_start__);
__CUSTOM_ROM = __CODE_END;
/* Custom Section Block that can be used to place data at absolute address. */
/* Use __attribute__((section (".customSection"))) to place data here. */
.customSectionBlock ORIGIN(m_data_2) : AT(__CUSTOM_ROM)
{
__customSection_start__ = .;
KEEP(*(.customSection)) /* Keep section even if not referenced. */
__customSection_end__ = .;
} > m_data_2
__CUSTOM_END = __CUSTOM_ROM + (__customSection_end__ - __customSection_start__);
/* Uninitialized data section. */
.bss :
{
/* This is used by the startup in order to initialize the .bss section. */
. = ALIGN(4);
__BSS_START = .;
__bss_start__ = .;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
__BSS_END = .;
} > m_data_2
.heap :
{
. = ALIGN(8);
__end__ = .;
__heap_start__ = .;
PROVIDE(end = .);
PROVIDE(_end = .);
PROVIDE(__end = .);
__HeapBase = .;
. += HEAP_SIZE;
__HeapLimit = .;
__heap_limit = .;
__heap_end__ = .;
} > m_data_2
/* Initializes stack on the end of block */
__StackTop = ORIGIN(m_data_2) + LENGTH(m_data_2);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
__RAM_END = __StackTop;
.stack __StackLimit :
{
. = ALIGN(8);
__stack_start__ = .;
. += STACK_SIZE;
__stack_end__ = .;
} > m_data_2
/* Labels required by EWL */
__START_BSS = __BSS_START;
__END_BSS = __BSS_END;
__SP_INIT = __StackTop;
.ARM.attributes 0 : { *(.ARM.attributes) }
ASSERT(__StackLimit >= __HeapLimit, "region m_data_2 overflowed with stack and heap")
}

176
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/blt_conf.h Normal file
View File

@ -0,0 +1,176 @@
/************************************************************************************//**
* \file Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/blt_conf.h
* \brief Bootloader configuration header file.
* \ingroup Boot_ARMCM0_S32K14_S32K118EVB_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef BLT_CONF_H
#define BLT_CONF_H
/****************************************************************************************
* C P U D R I V E R C O N F I G U R A T I O N
****************************************************************************************/
/* To properly initialize the baudrate clocks of the communication interface, typically
* the speed of the crystal oscillator and/or the speed at which the system runs is
* needed. Set these through configurables BOOT_CPU_XTAL_SPEED_KHZ and
* BOOT_CPU_SYSTEM_SPEED_KHZ, respectively. To enable data exchange with the host that is
* not dependent on the targets architecture, the byte ordering needs to be known.
* Setting BOOT_CPU_BYTE_ORDER_MOTOROLA to 1 selects big endian mode and 0 selects
* little endian mode.
*
* Set BOOT_CPU_USER_PROGRAM_START_HOOK to 1 if you would like a hook function to be
* called the moment the user program is about to be started. This could be used to
* de-initialize application specific parts, for example to stop blinking an LED, etc.
*/
/** \brief Frequency of the external crystal oscillator. */
#define BOOT_CPU_XTAL_SPEED_KHZ (40000)
/** \brief Desired system speed. */
#define BOOT_CPU_SYSTEM_SPEED_KHZ (48000)
/** \brief Motorola or Intel style byte ordering. */
#define BOOT_CPU_BYTE_ORDER_MOTOROLA (0)
/** \brief Enable/disable hook function call right before user program start. */
#define BOOT_CPU_USER_PROGRAM_START_HOOK (1)
/****************************************************************************************
* C O M M U N I C A T I O N I N T E R F A C E C O N F I G U R A T I O N
****************************************************************************************/
/* The UART communication interface is selected by setting the BOOT_COM_UART_ENABLE
* configurable to 1. Configurable BOOT_COM_UART_BAUDRATE selects the communication speed
* in bits/second. The maximum amount of data bytes in a message for data transmission
* and reception is set through BOOT_COM_UART_TX_MAX_DATA and BOOT_COM_UART_RX_MAX_DATA,
* respectively. It is common for a microcontroller to have more than 1 UART interface
* on board. The zero-based BOOT_COM_UART_CHANNEL_INDEX selects the UART interface.
*
*/
/** \brief Enable/disable UART transport layer. */
#define BOOT_COM_RS232_ENABLE (1)
/** \brief Configure the desired communication speed. */
#define BOOT_COM_RS232_BAUDRATE (57600)
/** \brief Configure number of bytes in the target->host data packet. */
#define BOOT_COM_RS232_TX_MAX_DATA (64)
/** \brief Configure number of bytes in the host->target data packet. */
#define BOOT_COM_RS232_RX_MAX_DATA (64)
/** \brief Select the desired UART peripheral as a zero based index. */
#define BOOT_COM_RS232_CHANNEL_INDEX (0)
/* The CAN communication interface is selected by setting the BOOT_COM_CAN_ENABLE
* configurable to 1. Configurable BOOT_COM_CAN_BAUDRATE selects the communication speed
* in bits/second. Two CAN messages are reserved for communication with the host. The
* message identifier for sending data from the target to the host is configured with
* BOOT_COM_CAN_TXMSG_ID. The one for receiving data from the host is configured with
* BOOT_COM_CAN_RXMSG_ID. Note that an extended 29-bit CAN identifier is configured by
* OR-ing with mask 0x80000000. The maximum amount of data bytes in a message for data
* transmission and reception is set through BOOT_COM_CAN_TX_MAX_DATA and
* BOOT_COM_CAN_RX_MAX_DATA, respectively. It is common for a microcontroller to have more
* than 1 CAN controller on board. The zero-based BOOT_COM_CAN_CHANNEL_INDEX selects the
* CAN controller channel.
*
*/
/** \brief Enable/disable CAN transport layer. */
#define BOOT_COM_CAN_ENABLE (1)
/** \brief Configure the desired CAN baudrate. */
#define BOOT_COM_CAN_BAUDRATE (500000)
/** \brief Configure CAN message ID target->host. */
#define BOOT_COM_CAN_TX_MSG_ID (0x7E1 /*| 0x80000000*/)
/** \brief Configure number of bytes in the target->host CAN message. */
#define BOOT_COM_CAN_TX_MAX_DATA (8)
/** \brief Configure CAN message ID host->target. */
#define BOOT_COM_CAN_RX_MSG_ID (0x667 /*| 0x80000000*/)
/** \brief Configure number of bytes in the host->target CAN message. */
#define BOOT_COM_CAN_RX_MAX_DATA (8)
/** \brief Select the desired CAN peripheral as a zero based index. */
#define BOOT_COM_CAN_CHANNEL_INDEX (0)
/****************************************************************************************
* B A C K D O O R E N T R Y C O N F I G U R A T I O N
****************************************************************************************/
/* It is possible to implement an application specific method to force the bootloader to
* stay active after a reset. Such a backdoor entry into the bootloader is desired in
* situations where the user program does not run properly and therefore cannot
* reactivate the bootloader. By enabling these hook functions, the application can
* implement the backdoor, which overrides the default backdoor entry that is programmed
* into the bootloader. When desired for security purposes, these hook functions can
* also be implemented in a way that disables the backdoor entry altogether.
*/
/** \brief Enable/disable the backdoor override hook functions. */
#define BOOT_BACKDOOR_HOOKS_ENABLE (0)
/****************************************************************************************
* N O N - V O L A T I L E M E M O R Y D R I V E R C O N F I G U R A T I O N
****************************************************************************************/
/* The NVM driver typically supports erase and program operations of the internal memory
* present on the microcontroller. Through these hook functions the NVM driver can be
* extended to support additional memory types such as external flash memory and serial
* eeproms. The size of the internal memory in kilobytes is specified with configurable
* BOOT_NVM_SIZE_KB. If desired the internal checksum writing and verification method can
* be overridden with a application specific method by enabling configuration switch
* BOOT_NVM_CHECKSUM_HOOKS_ENABLE.
*/
/** \brief Enable/disable the NVM hook function for supporting additional memory devices. */
#define BOOT_NVM_HOOKS_ENABLE (0)
/** \brief Configure the size of the default memory device (typically flash EEPROM). */
#define BOOT_NVM_SIZE_KB (256)
/** \brief Enable/disable hooks functions to override the user program checksum handling. */
#define BOOT_NVM_CHECKSUM_HOOKS_ENABLE (0)
/****************************************************************************************
* W A T C H D O G D R I V E R C O N F I G U R A T I O N
****************************************************************************************/
/* The COP driver cannot be configured internally in the bootloader, because its use
* and configuration is application specific. The bootloader does need to service the
* watchdog in case it is used. When the application requires the use of a watchdog,
* set BOOT_COP_HOOKS_ENABLE to be able to initialize and service the watchdog through
* hook functions.
*/
/** \brief Enable/disable the hook functions for controlling the watchdog. */
#define BOOT_COP_HOOKS_ENABLE (1)
/****************************************************************************************
* S E E D / K E Y S E C U R I T Y C O N F I G U R A T I O N
****************************************************************************************/
/* A security mechanism can be enabled in the bootloader's XCP module by setting configu-
* rable BOOT_XCP_SEED_KEY_ENABLE to 1. Before any memory erase or programming
* operations can be performed, access to this resource need to be unlocked.
* In the Microboot settings on tab "XCP Protection" you need to specify a DLL that
* implements the unlocking algorithm. The demo programs are configured for the (simple)
* algorithm in "libseednkey.dll". The source code for this DLL is available so it can be
* customized to your needs.
* During the unlock sequence, Microboot requests a seed from the bootloader, which is in
* the format of a byte array. Using this seed the unlock algorithm in the DLL computes
* a key, which is also a byte array, and sends this back to the bootloader. The
* bootloader then verifies this key to determine if programming and erase operations are
* permitted.
* After enabling this feature the hook functions XcpGetSeedHook() and XcpVerifyKeyHook()
* are called by the bootloader to obtain the seed and to verify the key, respectively.
*/
#define BOOT_XCP_SEED_KEY_ENABLE (0)
#endif /* BLT_CONF_H */
/*********************************** end of blt_conf.h *********************************/

7
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/boot.dox Normal file
View File

@ -0,0 +1,7 @@
/**
\defgroup Boot_ARMCM0_S32K14_S32K118EVB_GCC Bootloader
\brief Bootloader.
\ingroup ARMCM0_S32K14_S32K118EVB_GCC
*/

307
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/hooks.c Normal file
View File

@ -0,0 +1,307 @@
/************************************************************************************//**
* \file Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/hooks.c
* \brief Bootloader callback source file.
* \ingroup Boot_ARMCM0_S32K14_S32K118EVB_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
#include "led.h" /* LED driver header */
#include "device_registers.h" /* device registers */
/****************************************************************************************
* B A C K D O O R E N T R Y H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_BACKDOOR_HOOKS_ENABLE > 0)
/************************************************************************************//**
** \brief Initializes the backdoor entry option.
** \return none.
**
****************************************************************************************/
void BackDoorInitHook(void)
{
} /*** end of BackDoorInitHook ***/
/************************************************************************************//**
** \brief Checks if a backdoor entry is requested.
** \return BLT_TRUE if the backdoor entry is requested, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool BackDoorEntryHook(void)
{
/* default implementation always activates the bootloader after a reset */
return BLT_TRUE;
} /*** end of BackDoorEntryHook ***/
#endif /* BOOT_BACKDOOR_HOOKS_ENABLE > 0 */
/****************************************************************************************
* C P U D R I V E R H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0)
/************************************************************************************//**
** \brief Callback that gets called when the bootloader is about to exit and
** hand over control to the user program. This is the last moment that
** some final checking can be performed and if necessary prevent the
** bootloader from activiting the user program.
** \return BLT_TRUE if it is okay to start the user program, BLT_FALSE to keep
** keep the bootloader active.
**
****************************************************************************************/
blt_bool CpuUserProgramStartHook(void)
{
/* additional and optional backdoor entry through the pushbutton (SW2) on the board. to
* force the bootloader to stay active after reset, keep it pressed during reset.
*/
if ((PTD->PDIR & GPIO_PDIR_PDI(1 << 3U)) != 0U)
{
/* pushbutton pressed, so do not start the user program and keep the
* bootloader active instead.
*/
return BLT_FALSE;
}
/* clean up the LED driver */
LedBlinkExit();
/* okay to start the user program */
return BLT_TRUE;
} /*** end of CpuUserProgramStartHook ***/
#endif /* BOOT_CPU_USER_PROGRAM_START_HOOK > 0 */
/****************************************************************************************
* W A T C H D O G D R I V E R H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_COP_HOOKS_ENABLE > 0)
/************************************************************************************//**
** \brief Callback that gets called at the end of the internal COP driver
** initialization routine. It can be used to configure and enable the
** watchdog.
** \return none.
**
****************************************************************************************/
void CopInitHook(void)
{
/* this function is called upon initialization. might as well use it to initialize
* the LED driver. It is kind of a visual watchdog anyways.
*/
LedBlinkInit(100);
} /*** end of CopInitHook ***/
/************************************************************************************//**
** \brief Callback that gets called at the end of the internal COP driver
** service routine. This gets called upon initialization and during
** potential long lasting loops and routine. It can be used to service
** the watchdog to prevent a watchdog reset.
** \return none.
**
****************************************************************************************/
void CopServiceHook(void)
{
/* run the LED blink task. this is a better place to do it than in the main() program
* loop. certain operations such as flash erase can take a long time, which would cause
* a blink interval to be skipped. this function is also called during such operations,
* so no blink intervals will be skipped when calling the LED blink task here.
*/
LedBlinkTask();
} /*** end of CopServiceHook ***/
#endif /* BOOT_COP_HOOKS_ENABLE > 0 */
/****************************************************************************************
* N O N - V O L A T I L E M E M O R Y D R I V E R H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_NVM_HOOKS_ENABLE > 0)
/************************************************************************************//**
** \brief Callback that gets called at the start of the internal NVM driver
** initialization routine.
** \return none.
**
****************************************************************************************/
void NvmInitHook(void)
{
} /*** end of NvmInitHook ***/
/************************************************************************************//**
** \brief Callback that gets called at the start of a firmware update to reinitialize
** the NVM driver.
** \return none.
**
****************************************************************************************/
void NvmReinitHook(void)
{
} /*** end of NvmReinitHook ***/
/************************************************************************************//**
** \brief Callback that gets called at the start of the NVM driver write
** routine. It allows additional memory to be operated on. If the address
** is not within the range of the additional memory, then
** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the data hasn't
** been written yet.
** \param addr Start address.
** \param len Length in bytes.
** \param data Pointer to the data buffer.
** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is
** not within the supported memory range, or BLT_NVM_ERROR is the write
** operation failed.
**
****************************************************************************************/
blt_int8u NvmWriteHook(blt_addr addr, blt_int32u len, blt_int8u *data)
{
return BLT_NVM_NOT_IN_RANGE;
} /*** end of NvmWriteHook ***/
/************************************************************************************//**
** \brief Callback that gets called at the start of the NVM driver erase
** routine. It allows additional memory to be operated on. If the address
** is not within the range of the additional memory, then
** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the memory
** hasn't been erased yet.
** \param addr Start address.
** \param len Length in bytes.
** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is
** not within the supported memory range, or BLT_NVM_ERROR is the erase
** operation failed.
**
****************************************************************************************/
blt_int8u NvmEraseHook(blt_addr addr, blt_int32u len)
{
return BLT_NVM_NOT_IN_RANGE;
} /*** end of NvmEraseHook ***/
/************************************************************************************//**
** \brief Callback that gets called at the end of the NVM programming session.
** \return BLT_TRUE is successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool NvmDoneHook(void)
{
return BLT_TRUE;
} /*** end of NvmDoneHook ***/
#endif /* BOOT_NVM_HOOKS_ENABLE > 0 */
#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0)
/************************************************************************************//**
** \brief Verifies the checksum, which indicates that a valid user program is
** present and can be started.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool NvmVerifyChecksumHook(void)
{
return BLT_TRUE;
} /*** end of NvmVerifyChecksum ***/
/************************************************************************************//**
** \brief Writes a checksum of the user program to non-volatile memory. This is
** performed once the entire user program has been programmed. Through
** the checksum, the bootloader can check if a valid user programming is
** present and can be started.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool NvmWriteChecksumHook(void)
{
return BLT_TRUE;
}
#endif /* BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0 */
/****************************************************************************************
* S E E D / K E Y S E C U R I T Y H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_XCP_SEED_KEY_ENABLE > 0)
/************************************************************************************//**
** \brief Provides a seed to the XCP master that will be used for the key
** generation when the master attempts to unlock the specified resource.
** Called by the GET_SEED command.
** \param resource Resource that the seed if requested for (XCP_RES_XXX).
** \param seed Pointer to byte buffer wher the seed will be stored.
** \return Length of the seed in bytes.
**
****************************************************************************************/
blt_int8u XcpGetSeedHook(blt_int8u resource, blt_int8u *seed)
{
/* request seed for unlocking ProGraMming resource */
if ((resource & XCP_RES_PGM) != 0)
{
seed[0] = 0x55;
}
/* return seed length */
return 1;
} /*** end of XcpGetSeedHook ***/
/************************************************************************************//**
** \brief Called by the UNLOCK command and checks if the key to unlock the
** specified resource was correct. If so, then the resource protection
** will be removed.
** \param resource resource to unlock (XCP_RES_XXX).
** \param key pointer to the byte buffer holding the key.
** \param len length of the key in bytes.
** \return 1 if the key was correct, 0 otherwise.
**
****************************************************************************************/
blt_int8u XcpVerifyKeyHook(blt_int8u resource, blt_int8u *key, blt_int8u len)
{
/* suppress compiler warning for unused parameter */
len = len;
/* the example key algorithm in "libseednkey.dll" works as follows:
* - PGM will be unlocked if key = seed - 1
*/
/* check key for unlocking ProGraMming resource */
if ((resource == XCP_RES_PGM) && (key[0] == (0x55-1)))
{
/* correct key received for unlocking PGM resource */
return 1;
}
/* still here so key incorrect */
return 0;
} /*** end of XcpVerifyKeyHook ***/
#endif /* BOOT_XCP_SEED_KEY_ENABLE > 0 */
/*********************************** end of hooks.c ************************************/

108
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/led.c Normal file
View File

@ -0,0 +1,108 @@
/************************************************************************************//**
* \file Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/led.c
* \brief LED driver source file.
* \ingroup Boot_ARMCM0_S32K14_S32K118EVB_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
#include "led.h" /* module header */
#include "device_registers.h" /* device registers */
/****************************************************************************************
* Local data declarations
****************************************************************************************/
/** \brief Holds the desired LED blink interval time. */
static blt_int16u ledBlinkIntervalMs;
/************************************************************************************//**
** \brief Initializes the LED blink driver.
** \param interval_ms Specifies the desired LED blink interval time in milliseconds.
** \return none.
**
****************************************************************************************/
void LedBlinkInit(blt_int16u interval_ms)
{
/* LED GPIO pin configuration. PE8 = GPIO, MUX = ALT1. */
PORTE->PCR[8] = PORT_PCR_MUX(1);
/* Configure Port E pin 8 GPIO as digital output. */
PTE->PDDR |= GPIO_PDDR_PDD(1 << 8U);
/* Turn the LED off on Port E pin 8. */
PTE->PCOR |= GPIO_PSOR_PTSO(1 << 8U);
/* store the interval time between LED toggles */
ledBlinkIntervalMs = interval_ms;
} /*** end of LedBlinkInit ***/
/************************************************************************************//**
** \brief Task function for blinking the LED as a fixed timer interval.
** \return none.
**
****************************************************************************************/
void LedBlinkTask(void)
{
static blt_bool ledOn = BLT_FALSE;
static blt_int32u nextBlinkEvent = 0;
/* check for blink event */
if (TimerGet() >= nextBlinkEvent)
{
/* toggle the LED state */
if (ledOn == BLT_FALSE)
{
ledOn = BLT_TRUE;
/* Turn the LED on. */
PTE->PSOR |= GPIO_PSOR_PTSO(1 << 8U);
}
else
{
ledOn = BLT_FALSE;
/* Turn the LED off. */
PTE->PCOR |= GPIO_PSOR_PTSO(1 << 8U);
}
/* schedule the next blink event */
nextBlinkEvent = TimerGet() + ledBlinkIntervalMs;
}
} /*** end of LedBlinkTask ***/
/************************************************************************************//**
** \brief Cleans up the LED blink driver. This is intended to be used upon program
** exit.
** \return none.
**
****************************************************************************************/
void LedBlinkExit(void)
{
/* Turn the LED off. */
PTE->PCOR |= GPIO_PSOR_PTSO(1 << 8U);
} /*** end of LedBlinkExit ***/
/*********************************** end of led.c **************************************/

40
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/led.h Normal file
View File

@ -0,0 +1,40 @@
/************************************************************************************//**
* \file Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/led.h
* \brief LED driver header file.
* \ingroup Boot_ARMCM0_S32K14_S32K118EVB_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef LED_H
#define LED_H
/****************************************************************************************
* Function prototypes
****************************************************************************************/
void LedBlinkInit(blt_int16u interval_ms);
void LedBlinkTask(void);
void LedBlinkExit(void);
#endif /* LED_H */
/*********************************** end of led.h **************************************/

10438
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/lib/S32K118.h Normal file
View File

File diff suppressed because it is too large Load Diff

1302
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/lib/S32K118_features.h Normal file
View File

File diff suppressed because it is too large Load Diff

84
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/lib/devassert.h Normal file
View File

@ -0,0 +1,84 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef DEVASSERT_H
#define DEVASSERT_H
#include <stdbool.h>
/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 2.5, global macro not referenced.
* The macro is defined to be used by drivers to validate input parameters and can be disabled.
*
* @section [global]
* Violates MISRA 2012 Advisory Directive 4.9, Function-like macro defined.
* The macros are used to validate input parameters to driver functions.
*
*/
/**
\page Error_detection_and_reporting Error detection and reporting
S32 SDK drivers can use a mechanism to validate data coming from upper software layers (application code) by performing
a number of checks on input parameters' range or other invariants that can be statically checked (not dependent on
runtime conditions). A failed validation is indicative of a software bug in application code, therefore it is important
to use this mechanism during development.
The validation is performed by using DEV_ASSERT macro.
A default implementation of this macro is provided in this file. However, application developers can provide their own
implementation in a custom file. This requires defining the CUSTOM_DEVASSERT symbol with the specific file name in the
project configuration (for example: -DCUSTOM_DEVASSERT="custom_devassert.h")
The default implementation accommodates two behaviors, based on DEV_ERROR_DETECT symbol:
- When DEV_ERROR_DETECT symbol is defined in the project configuration (for example: -DDEV_ERROR_DETECT), the validation
performed by the DEV_ASSERT macro is enabled, and a failed validation triggers a software breakpoint and further execution is
prevented (application spins in an infinite loop)
This configuration is recommended for development environments, as it prevents further execution and allows investigating
potential problems from the point of error detection.
- When DEV_ERROR_DETECT symbol is not defined, the DEV_ASSERT macro is implemented as no-op, therefore disabling all validations.
This configuration can be used to eliminate the overhead of development-time checks.
It is the application developer's responsibility to decide the error detection strategy for production code: one can opt to
disable development-time checking altogether (by not defining DEV_ERROR_DETECT symbol), or one can opt to keep the checks
in place and implement a recovery mechanism in case of a failed validation, by defining CUSTOM_DEVASSERT to point
to the file containing the custom implementation.
*/
#if defined (CUSTOM_DEVASSERT)
/* If the CUSTOM_DEVASSERT symbol is defined, then add the custom implementation */
#include CUSTOM_DEVASSERT
#elif defined (DEV_ERROR_DETECT)
/* Implement default assert macro */
static inline void DevAssert(volatile bool x)
{
if(x) { } else { BKPT_ASM; for(;;) {} }
}
#define DEV_ASSERT(x) DevAssert(x)
#else
/* Assert macro does nothing */
#define DEV_ASSERT(x) ((void)0)
#endif
#endif /* DEVASSERT_H */
/*******************************************************************************
* EOF
******************************************************************************/

67
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/lib/device_registers.h Normal file
View File

@ -0,0 +1,67 @@
/*
** ###################################################################
** Abstract:
** Common include file for CMSIS register access layer headers.
**
** Copyright (c) 2015 Freescale Semiconductor, Inc.
** Copyright 2016-2017 NXP
** All rights reserved.
**
** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
** THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.nxp.com
** mail: support@nxp.com
** ###################################################################
*/
#ifndef DEVICE_REGISTERS_H
#define DEVICE_REGISTERS_H
/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 2.5, global macro not referenced.
* The macro defines the device currently in use and may be used by components for specific checks.
*
*/
/*
* Include the cpu specific register header files.
*
* The CPU macro should be declared in the project or makefile.
*/
#if defined(CPU_S32K118)
#define S32K11x_SERIES
/* Specific core definitions */
#include "s32_core_cm0.h"
/* Register definitions */
#include "S32K118.h"
/* CPU specific feature definitions */
#include "S32K118_features.h"
#else
#error "No valid CPU defined!"
#endif
#include "devassert.h"
#endif /* DEVICE_REGISTERS_H */
/*******************************************************************************
* EOF
******************************************************************************/

198
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/lib/s32_core_cm0.h Normal file
View File

@ -0,0 +1,198 @@
/*
* Copyright (c) 2015-2016 Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/*!
* @file s32_core_cm0.h
*
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Directive 4.9, Function-like macro
* Function-like macros are used instead of inline functions in order to ensure
* that the performance will not be decreased if the functions will not be
* inlined by the compiler.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 2.5, Global macro not referenced.
* The macros defined are used only on some of the drivers, so this might be reported
* when the analysis is made only on one driver.
*/
/*
* Tool Chains:
* GNUC flag is defined also by ARM compiler - it shows the current major version of the compatible GCC version
* __GNUC__ : GNU Compiler Collection
* __ghs__ : Green Hills ARM Compiler
* __ICCARM__ : IAR ARM Compiler
* __DCC__ : Wind River Diab Compiler
* __ARMCC_VERSION : ARM Compiler
*/
#if !defined (CORE_CM0_H)
#define CORE_CM0_H
#ifdef __cplusplus
extern "C" {
#endif
/** \brief BKPT_ASM
*
* Macro to be used to trigger an debug interrupt
*/
#if defined ( __DCC__ )
#define BKPT_ASM __asm ("BKPT 0\n\t")
#else
#define BKPT_ASM __asm ("BKPT #0\n\t")
#endif
/** \brief Enable interrupts
*/
#if defined (__GNUC__)
#define ENABLE_INTERRUPTS() __asm volatile ("cpsie i" : : : "memory");
#elif defined ( __DCC__ )
#define ENABLE_INTERRUPTS() __asm (".short 0xb662");
#else
#define ENABLE_INTERRUPTS() __asm("cpsie i")
#endif
/** \brief Disable interrupts
*/
#if defined (__GNUC__)
#define DISABLE_INTERRUPTS() __asm volatile ("cpsid i" : : : "memory");
#elif defined ( __DCC__ )
#define DISABLE_INTERRUPTS() __asm (".short 0xb672");
#else
#define DISABLE_INTERRUPTS() __asm("cpsid i")
#endif
/** \brief Enter low-power standby state
* WFI (Wait For Interrupt) makes the processor suspend execution (Clock is stopped) until an IRQ interrupts.
*/
#if defined (__GNUC__)
#define STANDBY() __asm volatile ("wfi")
#elif defined ( __DCC__ )
#define STANDBY() __asm (".short 0xbf30");
#else
#define STANDBY() __asm ("wfi")
#endif
/** \brief No-op
*/
#define NOP() __asm volatile ("nop")
/** \brief Reverse byte order in a word.
* ARM Documentation Cortex-M0 Devices Generic User Guide
* Accordingly to 3.5.7. REV, REV16, and REVSH
* Restriction "This function requires low registers R0-R7 register"
*/
#if defined (__GNUC__) || defined (__ICCARM__) || defined (__ARMCC_VERSION)
#define REV_BYTES_32(a, b) __asm volatile ("rev %0, %1" : "=l" (b) : "l" (a))
#elif defined (__ghs__)
#define REV_BYTES_32(a, b) __asm volatile ("rev %0, %1" : "=r" (b) : "r" (a))
#else
#define REV_BYTES_32(a, b) (b = ((a & 0xFF000000U) >> 24U) | ((a & 0xFF0000U) >> 8U) \
| ((a & 0xFF00U) << 8U) | ((a & 0xFFU) << 24U))
#endif
/** \brief Reverse byte order in each halfword independently.
* ARM Documentation Cortex-M0 Devices Generic User Guide
* Accordingly to 3.5.7. REV, REV16, and REVSH
* Restriction "This function requires low registers R0-R7 register"
*/
#if defined (__GNUC__) || defined (__ICCARM__) || defined (__ARMCC_VERSION)
#define REV_BYTES_16(a, b) __asm volatile ("rev16 %0, %1" : "=l" (b) : "l" (a))
#elif defined (__ghs__)
#define REV_BYTES_16(a, b) __asm volatile ("rev16 %0, %1" : "=r" (b) : "r" (a))
#else
#define REV_BYTES_16(a, b) (b = ((a & 0xFF000000U) >> 8U) | ((a & 0xFF0000U) << 8U) \
| ((a & 0xFF00U) >> 8U) | ((a & 0xFFU) << 8U))
#endif
/** \brief Places a function in RAM.
*/
#if defined ( __GNUC__ ) || defined (__ARMCC_VERSION)
#define START_FUNCTION_DECLARATION_RAMSECTION
#define END_FUNCTION_DECLARATION_RAMSECTION __attribute__((section (".code_ram")));
#elif defined ( __ghs__ )
#define START_FUNCTION_DECLARATION_RAMSECTION _Pragma("ghs callmode=far")
#define END_FUNCTION_DECLARATION_RAMSECTION __attribute__((section (".code_ram")));\
_Pragma("ghs callmode=default")
#elif defined ( __ICCARM__ )
#define START_FUNCTION_DECLARATION_RAMSECTION __ramfunc
#define END_FUNCTION_DECLARATION_RAMSECTION ;
#elif defined ( __DCC__ )
#define START_FUNCTION_DECLARATION_RAMSECTION _Pragma("section CODE \".code_ram\" \"\" far-absolute") \
_Pragma("use_section CODE")
#define END_FUNCTION_DECLARATION_RAMSECTION ; \
_Pragma("section CODE \".text\"")
#else
/* Keep compatibility with software analysis tools */
#define START_FUNCTION_DECLARATION_RAMSECTION
#define END_FUNCTION_DECLARATION_RAMSECTION ;
#endif
/* For GCC, IAR, GHS, Diab and ARMC there is no need to specify the section when
defining a function, it is enough to specify it at the declaration. This
also enables compatibility with software analysis tools. */
#define START_FUNCTION_DEFINITION_RAMSECTION
#define END_FUNCTION_DEFINITION_RAMSECTION
#if defined (__ICCARM__)
#define DISABLE_CHECK_RAMSECTION_FUNCTION_CALL _Pragma("diag_suppress=Ta022")
#define ENABLE_CHECK_RAMSECTION_FUNCTION_CALL _Pragma("diag_default=Ta022")
#else
#define DISABLE_CHECK_RAMSECTION_FUNCTION_CALL
#define ENABLE_CHECK_RAMSECTION_FUNCTION_CALL
#endif
/** \brief Get Core ID
*
* GET_CORE_ID returns the processor identification number for cm0
*/
#define GET_CORE_ID() 0U
/** \brief Data alignment.
*/
#if defined ( __GNUC__ ) || defined ( __ghs__ ) || defined ( __DCC__ ) || defined (__ARMCC_VERSION)
#define ALIGNED(x) __attribute__((aligned(x)))
#elif defined ( __ICCARM__ )
#define stringify(s) tostring(s)
#define tostring(s) #s
#define ALIGNED(x) _Pragma(stringify(data_alignment=x))
#else
/* Keep compatibility with software analysis tools */
#define ALIGNED(x)
#endif
/** \brief Endianness.
*/
#define CORE_LITTLE_ENDIAN
#ifdef __cplusplus
}
#endif
#endif /* CORE_CM0_H */
/*******************************************************************************
* EOF
******************************************************************************/

176
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/lib/system_S32K118.c Normal file
View File

@ -0,0 +1,176 @@
/*
* Copyright 2017-2018 NXP
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block
* scope if its identifier only appears in a single function.
* An object with static storage duration declared at block scope cannot be
* accessed directly from outside the block.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed
* between a pointer to object and an integer type.
* The cast is required to initialize a pointer with an unsigned int define,
* representing an address.
*
* @section [global]
* Violates MISRA 2012 Required Rule 11.6, A cast shall not be performed
* between pointer to void and an arithmetic type.
* The cast is required to initialize a pointer with an unsigned int define,
* representing an address.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 8.7, External could be made static.
* Function is defined for usage by application code.
*
*/
#include "device_registers.h"
#include "system_S32K118.h"
#include "stdbool.h"
/* ----------------------------------------------------------------------------
-- Core clock
---------------------------------------------------------------------------- */
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
/*FUNCTION**********************************************************************
*
* Function Name : SystemInit
* Description : This function disables the watchdog, enables FPU
* and the power mode protection if the corresponding feature macro
* is enabled. SystemInit is called from startup_device file.
*
* Implements : SystemInit_Activity
*END**************************************************************************/
void SystemInit(void)
{
/**************************************************************************/
/* WDOG DISABLE*/
/**************************************************************************/
#if (DISABLE_WDOG)
/* Write of the WDOG unlock key to CNT register, must be done in order to allow any modifications*/
WDOG->CNT = (uint32_t ) FEATURE_WDOG_UNLOCK_VALUE;
/* The dummy read is used in order to make sure that the WDOG registers will be configured only
* after the write of the unlock value was completed. */
(void)WDOG->CNT;
/* Initial write of WDOG configuration register:
* enables support for 32-bit refresh/unlock command write words,
* clock select from LPO, update enable, watchdog disabled */
WDOG->CS = (uint32_t ) ( (1UL << WDOG_CS_CMD32EN_SHIFT) |
(FEATURE_WDOG_CLK_FROM_LPO << WDOG_CS_CLK_SHIFT) |
(0U << WDOG_CS_EN_SHIFT) |
(1U << WDOG_CS_UPDATE_SHIFT) );
/* Configure timeout */
WDOG->TOVAL = (uint32_t )0xFFFF;
#endif /* (DISABLE_WDOG) */
}
/*FUNCTION**********************************************************************
*
* Function Name : SystemCoreClockUpdate
* Description : This function must be called whenever the core clock is changed
* during program execution. It evaluates the clock register settings and calculates
* the current core clock.
*
* Implements : SystemCoreClockUpdate_Activity
*END**************************************************************************/
void SystemCoreClockUpdate(void)
{
uint32_t SCGOUTClock = 0U; /* Variable to store output clock frequency of the SCG module */
uint32_t regValue; /* Temporary variable */
uint32_t divider;
bool validSystemClockSource = true;
divider = ((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1U;
switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT)
{
case 0x1:
/* System OSC */
SCGOUTClock = CPU_XTAL_CLK_HZ;
break;
case 0x2:
/* Slow IRC */
regValue = (SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT;
if (regValue != 0UL)
{
SCGOUTClock = FEATURE_SCG_SIRC_HIGH_RANGE_FREQ;
}
else
{
validSystemClockSource = false;
}
break;
case 0x3:
/* Fast IRC */
regValue = (SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT;
if (regValue == 0x0UL)
{
SCGOUTClock = FEATURE_SCG_FIRC_FREQ0;
}
else
{
validSystemClockSource = false;
}
break;
default:
validSystemClockSource = false;
break;
}
if (validSystemClockSource == true)
{
SystemCoreClock = (SCGOUTClock / divider);
}
}
/*FUNCTION**********************************************************************
*
* Function Name : SystemSoftwareReset
* Description : This function is used to initiate a system reset
*
* Implements : SystemSoftwareReset_Activity
*END**************************************************************************/
void SystemSoftwareReset(void)
{
uint32_t regValue;
/* Read Application Interrupt and Reset Control Register */
regValue = S32_SCB->AIRCR;
/* Clear register key */
regValue &= ~( S32_SCB_AIRCR_VECTKEY_MASK);
/* Configure System reset request bit and Register Key */
regValue |= S32_SCB_AIRCR_VECTKEY(FEATURE_SCB_VECTKEY);
regValue |= S32_SCB_AIRCR_SYSRESETREQ(0x1u);
/* Write computed register value */
S32_SCB->AIRCR = regValue;
}
/*******************************************************************************
* EOF
******************************************************************************/

105
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/lib/system_S32K118.h Normal file
View File

@ -0,0 +1,105 @@
/*
* Copyright 2017-2018 NXP
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
/*! @addtogroup soc_support_S32K118*/
/*! @{*/
/*!
* @file system_S32K118.h
* @brief Device specific configuration file for S32K118
*/
#ifndef SYSTEM_S32K118_H_
#define SYSTEM_S32K118_H_ /**< Symbol preventing repeated inclusion */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/******************************************************************************
* CPU Settings.
*****************************************************************************/
/* Watchdog disable */
#ifndef DISABLE_WDOG
#define DISABLE_WDOG 1
#endif
/* Value of the external crystal or oscillator clock frequency in Hz */
#ifndef CPU_XTAL_CLK_HZ
#define CPU_XTAL_CLK_HZ 8000000u
#endif
/* Value of the fast internal oscillator clock frequency in Hz */
#ifndef CPU_INT_FAST_CLK_HZ
#define CPU_INT_FAST_CLK_HZ 48000000u
#endif
/* Default System clock value */
#ifndef DEFAULT_SYSTEM_CLOCK
#define DEFAULT_SYSTEM_CLOCK 48000000u
#endif
/**
* @brief System clock frequency (core clock)
*
* The system clock frequency supplied to the SysTick timer and the processor
* core clock. This variable can be used by the user application to setup the
* SysTick timer or configure other parameters. It may also be used by debugger to
* query the frequency of the debug timer or configure the trace clock speed
* SystemCoreClock is initialized with a correct predefined value.
*/
extern uint32_t SystemCoreClock;
/**
* @brief Setup the SoC.
*
* This function disables the watchdog.
* if the corresponding feature macro is enabled.
* SystemInit is called from startup_device file.
*/
void SystemInit(void);
/**
* @brief Updates the SystemCoreClock variable.
*
* It must be called whenever the core clock is changed during program
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
* the current core clock.
* This function must be called when user does not want to use clock manager component.
* If clock manager is used, the CLOCK_SYS_GetFreq function must be used with CORE_CLOCK
* parameter.
*
*/
void SystemCoreClockUpdate(void);
/**
* @brief Initiates a system reset.
*
* This function is used to initiate a system reset
*/
void SystemSoftwareReset(void);
#ifdef __cplusplus
}
#endif
/*! @}*/
#endif /* #if !defined(SYSTEM_S32K118_H_) */

189
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/main.c Normal file
View File

@ -0,0 +1,189 @@
/************************************************************************************//**
* \file Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/main.c
* \brief Bootloader application source file.
* \ingroup Boot_ARMCM0_S32K14_S32K118EVB_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
#include "device_registers.h" /* device registers */
#include "system_S32K118.h" /* device sconfiguration */
/****************************************************************************************
* Function prototypes
****************************************************************************************/
static void Init(void);
static void SystemClockConfig(void);
/************************************************************************************//**
** \brief This is the entry point for the bootloader application and is called
** by the reset interrupt vector after the C-startup routines executed.
** \return Program return code.
**
****************************************************************************************/
int main(void)
{
/* Initialize the microcontroller. */
Init();
/* Initialize the bootloader. */
BootInit();
/* Start the infinite program loop. */
while (1)
{
/* Run the bootloader task. */
BootTask();
}
/* Program should never get here. */
return 0;
} /*** end of main ***/
/************************************************************************************//**
** \brief Initializes the microcontroller.
** \return none.
**
****************************************************************************************/
static void Init(void)
{
/* Configure the system clock. */
SystemClockConfig();
/* Enable the peripheral clock for the ports that are used. */
PCC->PCCn[PCC_PORTB_INDEX] |= PCC_PCCn_CGC_MASK;
PCC->PCCn[PCC_PORTD_INDEX] |= PCC_PCCn_CGC_MASK;
PCC->PCCn[PCC_PORTE_INDEX] |= PCC_PCCn_CGC_MASK;
/* Configure SW2 (PD3) GPIO pin for (optional) backdoor entry input. */
/* Input GPIO pin configuration. PD3 = GPIO, MUX = ALT1. */
PORTD->PCR[3] |= PORT_PCR_MUX(1);
/* Disable pull device, as SW2 already has a pull down resistor on the board. */
PORTD->PCR[3] &= ~PORT_PCR_PE(1);
/* Configure and enable Port D pin 3 GPIO as digital input */
PTD->PDDR &= ~GPIO_PDDR_PDD(1 << 3U);
PTD->PIDR &= ~GPIO_PIDR_PID(1 << 3U);
#if (BOOT_COM_RS232_ENABLE > 0)
/* UART RX GPIO pin configuration. PB0 = UART0 RX, MUX = ALT2. */
PORTB->PCR[0] |= PORT_PCR_MUX(2);
/* UART TX GPIO pin configuration. PB1 = UART0 TX, MUX = ALT2. */
PORTB->PCR[1] |= PORT_PCR_MUX(2);
#endif
#if (BOOT_COM_CAN_ENABLE > 0)
/* CAN RX GPIO pin configuration. PE4 = CAN0 RX, MUX = ALT5. */
PORTE->PCR[4] |= PORT_PCR_MUX(5);
/* CAN TX GPIO pin configuration. PE5 = CAN0 TX, MUX = ALT5. */
PORTE->PCR[5] |= PORT_PCR_MUX(5);
#endif
} /*** end of Init ***/
/************************************************************************************//**
** \brief System Clock Configuration. This code was derived from a S32 Design Studio
** example program. It enables the SOCS (40 MHz external crystal), FIRC (48
** MHz internal) and SIRC (8 MHz internal). The FIRC is used as a source for
** the system clock and configures the normal RUN mode for the following clock
** settings:
** - CORE_CLK = 48 MHz
** - SYS_CLK = 48 MHz
** - BUS_CLK = 48 MHz
** - FLASH_CLK = 24 MHz
** - SOSCDIV1_CLK = 40 MHz
** - SOSCDIV2_CLK = 40 MHz
** - FIRCDIV1_CLK = 48 MHz
** - FIRCDIV2_CLK = 48 MHz
** - SIRCDIV1_CLK = 8 MHz
** - SIRCDIV2_CLK = 8 MHz
** \return none.
**
****************************************************************************************/
static void SystemClockConfig(void)
{
/* --------- SOSC Initialization (40 MHz) ------------------------------------------ */
/* SOSCDIV1 & SOSCDIV2 =1: divide by 1. */
SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV1(1) | SCG_SOSCDIV_SOSCDIV2(1);
/* Range=3: High freq (SOSC betw 8MHz - 40MHz).
* HGO=0: Config xtal osc for low power.
* EREFS=1: Input is external XTAL.
*/
SCG->SOSCCFG = SCG_SOSCCFG_RANGE(3) | SCG_SOSCCFG_EREFS_MASK;
/* Ensure SOSCCSR unlocked. */
while (SCG->SOSCCSR & SCG_SOSCCSR_LK_MASK)
{
;
}
/* LK=0: SOSCCSR can be written.
* SOSCCMRE=0: OSC CLK monitor IRQ if enabled.
* SOSCCM=0: OSC CLK monitor disabled.
* SOSCERCLKEN=0: Sys OSC 3V ERCLK output clk disabled.
* SOSCLPEN=0: Sys OSC disabled in VLP modes.
* SOSCSTEN=0: Sys OSC disabled in Stop modes.
* SOSCEN=1: Enable oscillator.
*/
SCG->SOSCCSR = SCG_SOSCCSR_SOSCEN_MASK;
/* Wait for system OSC clock to become valid. */
while (!(SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK))
{
;
}
/* --------- FIRC Initialization --------------------------------------------------- */
/* Fast IRC is enabled and trimmed to 48 MHz in reset (default). Enable FIRCDIV2_CLK
* and FIRCDIV1_CLK, divide by 1 = 48 MHz.
*/
SCG->FIRCDIV = SCG_FIRCDIV_FIRCDIV1(1) | SCG_FIRCDIV_FIRCDIV2(1);
/* --------- SIRC Initialization --------------------------------------------------- */
/* Slow IRC is enabled with high range (8 MHz) in reset. Enable SIRCDIV2_CLK and
* SIRCDIV1_CLK, divide by 1 = 8MHz asynchronous clock source.
*/
SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV1(1) | SCG_SIRCDIV_SIRCDIV2(1);
/* --------- Change to normal RUN mode with 48MHz FIRC ----------------------------- */
/* Select FIRC as clock source.
* DIVCORE=0, div. by 1: Core clock = 48 MHz.
* DIVBUS=0, div. by 1: bus clock = 48 MHz.
* DIVSLOW=1, div. by 2: SCG slow, flash clock= 24 MHz
*/
SCG->RCCR = SCG_RCCR_SCS(3) | SCG_RCCR_DIVCORE(0) | SCG_RCCR_DIVBUS(0) |
SCG_RCCR_DIVSLOW(1);
/* Wait until system clock source is FIRC. */
while (((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT ) != 3U)
{
;
}
/* Evaluate the clock register settings and calculates the current core clock. This
* function must be called when the clock manager component is not used.
*/
SystemCoreClockUpdate();
} /*** end of SystemClockConfig ***/
/*********************************** end of main.c *************************************/

248
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/startup/startup.c Normal file
View File

@ -0,0 +1,248 @@
/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* Copyright 2016-2018 NXP
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block
* scope if its identifier only appears in a single function.
* All variables with this problem are defined in the linker files.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 8.11, When an array with external linkage
* is declared, its size should be explicitly specified.
* The size of the arrays can not be explicitly determined.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed
* between a pointer to object and an integer type.
* The cast is required to initialize a pointer with an unsigned int define,
* representing an address.
*
* @section [global]
* Violates MISRA 2012 Required Rule 11.6, A cast shall not be performed
* between pointer to void and an arithmetic type.
* The cast is required to initialize a pointer with an unsigned int define,
* representing an address.
*
* @section [global]
* Violates MISRA 2012 Required Rule 2.1, A project shall not contain unreachable
* code.
* The condition compares two address defined in linker files that can be different.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 8.7, External could be made static.
* Function is defined for usage by application code.
*
* @section [global]
* Violates MISRA 2012 Mandatory Rule 17.3, Symbol 'MFSPR' undeclared, assumed
* to return int.
* This is an e200 Power Architecture Assembly instruction used to retrieve
* the core number.
*
*/
#include "startup.h"
#include <stdint.h>
/*******************************************************************************
* Static Variables
******************************************************************************/
static volatile uint32_t * const s_vectors[NUMBER_OF_CORES] = FEATURE_INTERRUPT_INT_VECTORS;
/*******************************************************************************
* Code
******************************************************************************/
/*FUNCTION**********************************************************************
*
* Function Name : init_data_bss
* Description : Make necessary initializations for RAM.
* - Copy the vector table from ROM to RAM.
* - Copy initialized data from ROM to RAM.
* - Copy code that should reside in RAM from ROM
* - Clear the zero-initialized data section.
*
* Tool Chains:
* __GNUC__ : GNU Compiler Collection
* __ghs__ : Green Hills ARM Compiler
* __ICCARM__ : IAR ARM Compiler
* __DCC__ : Wind River Diab Compiler
* __ARMCC_VERSION : ARMC Compiler
*
* Implements : init_data_bss_Activity
*END**************************************************************************/
void init_data_bss(void)
{
uint32_t n;
uint8_t coreId;
/* For ARMC we are using the library method of initializing DATA, Custom Section and
* Code RAM sections so the below variables are not needed */
#if !defined(__ARMCC_VERSION)
/* Declare pointers for various data sections. These pointers
* are initialized using values pulled in from the linker file */
uint8_t * data_ram;
uint8_t * code_ram;
uint8_t * bss_start;
uint8_t * custom_ram;
const uint8_t * data_rom, * data_rom_end;
const uint8_t * code_rom, * code_rom_end;
const uint8_t * bss_end;
const uint8_t * custom_rom, * custom_rom_end;
#endif
/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
#if defined(__ARMCC_VERSION)
extern uint32_t __RAM_VECTOR_TABLE_SIZE;
extern uint32_t __VECTOR_ROM;
extern uint32_t __VECTOR_RAM;
#else
extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
extern uint32_t __VECTOR_TABLE[];
extern uint32_t __VECTOR_RAM[];
#endif
/* Get section information from linker files */
#if defined(__ICCARM__)
/* Data */
data_ram = __section_begin(".data");
data_rom = __section_begin(".data_init");
data_rom_end = __section_end(".data_init");
/* CODE RAM */
#pragma section = "__CODE_ROM"
#pragma section = "__CODE_RAM"
code_ram = __section_begin("__CODE_RAM");
code_rom = __section_begin("__CODE_ROM");
code_rom_end = __section_end("__CODE_ROM");
/* BSS */
bss_start = __section_begin(".bss");
bss_end = __section_end(".bss");
custom_ram = __section_begin(".customSection");
custom_rom = __section_begin(".customSection_init");
custom_rom_end = __section_end(".customSection_init");
#elif defined (__ARMCC_VERSION)
/* VECTOR TABLE*/
uint8_t * vector_table_size = (uint8_t *)__RAM_VECTOR_TABLE_SIZE;
uint32_t * vector_rom = (uint32_t *)__VECTOR_ROM;
uint32_t * vector_ram = (uint32_t *)__VECTOR_RAM;
#else
extern uint32_t __DATA_ROM[];
extern uint32_t __DATA_RAM[];
extern uint32_t __DATA_END[];
extern uint32_t __CODE_RAM[];
extern uint32_t __CODE_ROM[];
extern uint32_t __CODE_END[];
extern uint32_t __BSS_START[];
extern uint32_t __BSS_END[];
extern uint32_t __CUSTOM_ROM[];
extern uint32_t __CUSTOM_END[];
/* Data */
data_ram = (uint8_t *)__DATA_RAM;
data_rom = (uint8_t *)__DATA_ROM;
data_rom_end = (uint8_t *)__DATA_END;
/* CODE RAM */
code_ram = (uint8_t *)__CODE_RAM;
code_rom = (uint8_t *)__CODE_ROM;
code_rom_end = (uint8_t *)__CODE_END;
/* BSS */
bss_start = (uint8_t *)__BSS_START;
bss_end = (uint8_t *)__BSS_END;
/* Custom section */
custom_ram = CUSTOMSECTION_SECTION_START;
custom_rom = (uint8_t *)__CUSTOM_ROM;
custom_rom_end = (uint8_t *)__CUSTOM_END;
#endif
#if !defined(__ARMCC_VERSION)
/* Copy initialized data from ROM to RAM */
while (data_rom_end != data_rom)
{
*data_ram = *data_rom;
data_ram++;
data_rom++;
}
/* Copy functions from ROM to RAM */
while (code_rom_end != code_rom)
{
*code_ram = *code_rom;
code_ram++;
code_rom++;
}
/* Clear the zero-initialized data section */
while(bss_end != bss_start)
{
*bss_start = 0;
bss_start++;
}
/* Copy customsection rom to ram */
while(custom_rom_end != custom_rom)
{
*custom_ram = *custom_rom;
custom_rom++;
custom_ram++;
}
#endif
coreId = (uint8_t)GET_CORE_ID();
#if defined (__ARMCC_VERSION)
/* Copy the vector table from ROM to RAM */
/* Workaround */
for (n = 0; n < (((uint32_t)(vector_table_size))/sizeof(uint32_t)); n++)
{
vector_ram[n] = vector_rom[n];
}
/* Point the VTOR to the position of vector table */
*s_vectors[coreId] = (uint32_t) __VECTOR_RAM;
#else
/* Check if VECTOR_TABLE copy is needed */
if (__VECTOR_RAM != __VECTOR_TABLE)
{
/* Copy the vector table from ROM to RAM */
for (n = 0; n < (((uint32_t)__RAM_VECTOR_TABLE_SIZE)/sizeof(uint32_t)); n++)
{
__VECTOR_RAM[n] = __VECTOR_TABLE[n];
}
/* Point the VTOR to the position of vector table */
*s_vectors[coreId] = (uint32_t)__VECTOR_RAM;
}
else
{
/* Point the VTOR to the position of vector table */
*s_vectors[coreId] = (uint32_t)__VECTOR_TABLE;
}
#endif
}
/*******************************************************************************
* EOF
******************************************************************************/

133
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/startup/startup.h Normal file
View File

@ -0,0 +1,133 @@
/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* Copyright 2016-2019 NXP
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef STARTUP_H
#define STARTUP_H
#include <stdint.h>
#include "device_registers.h"
/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 2.5, Local macro not referenced.
* The defined macro is used as include guard.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block
* scope if its identifier only appears in a single function.
* All variables with this problem are defined in the linker files.
*
*/
/*******************************************************************************
* API
******************************************************************************/
/*!
* @brief define symbols that specific start and end addres of some basic sections.
*/
#if (defined(S32K14x_SERIES) || defined(S32K11x_SERIES) || defined(S32V234_SERIES) || defined(MPC574x_SERIES) || defined(S32R_SERIES) || defined(S32MTV_SERIES) || defined(SJA1110_SERIES)) || defined (S32K144W_M4_SERIES)
#if (defined(__ICCARM__))
#define INTERRUPTS_SECTION_START __section_begin(".intvec")
#define INTERRUPTS_SECTION_END __section_end(".intvec")
#define BSS_SECTION_START __section_begin(".bss")
#define BSS_SECTION_END __section_end(".bss")
#define DATA_SECTION_START __section_begin(".data")
#define DATA_SECTION_END __section_end(".data")
#define CUSTOMSECTION_SECTION_START __section_begin(".customSection")
#define CUSTOMSECTION_SECTION_END __section_end(".customSection")
#define CODE_RAM_SECTION_START __section_begin("__CODE_RAM")
#define CODE_RAM_SECTION_END __section_end("__CODE_RAM")
#define DATA_INIT_SECTION_START __section_begin(".data_init")
#define DATA_INIT_SECTION_END __section_end(".data_init")
#define CODE_ROM_SECTION_START __section_begin("__CODE_ROM")
#define CODE_ROM_SECTION_END __section_end("__CODE_ROM")
#elif (defined(__ARMCC_VERSION))
#define INTERRUPTS_SECTION_START (uint8_t *)__VECTOR_ROM_START
#define INTERRUPTS_SECTION_END (uint8_t *)__VECTOR_ROM_END
#define BSS_SECTION_START (uint8_t *)__BSS_START
#define BSS_SECTION_END (uint8_t *)__BSS_END
#define DATA_SECTION_START (uint8_t *)__DATA_RAM_START
#define DATA_SECTION_END (uint8_t *)__DATA_RAM_END
#define CUSTOMSECTION_SECTION_START (uint8_t *)__CUSTOM_SECTION_START
#define CUSTOMSECTION_SECTION_END (uint8_t *)__CUSTOM_SECTION_END
#define CODE_RAM_SECTION_START (uint8_t *)__CODE_RAM_START
#define CODE_RAM_SECTION_END (uint8_t *)__CODE_RAM_END
extern uint32_t __VECTOR_ROM_START;
extern uint32_t __VECTOR_ROM_END;
extern uint32_t __BSS_START;
extern uint32_t __BSS_END;
extern uint32_t __DATA_RAM_START;
extern uint32_t __DATA_RAM_END;
extern uint32_t __CUSTOM_SECTION_START;
extern uint32_t __CUSTOM_SECTION_END;
extern uint32_t __CODE_RAM_START;
extern uint32_t __CODE_RAM_END;
#else
#define INTERRUPTS_SECTION_START (uint8_t *)&__interrupts_start__
#define INTERRUPTS_SECTION_END (uint8_t *)&__interrupts_end__
#define BSS_SECTION_START (uint8_t *)&__bss_start__
#define BSS_SECTION_END (uint8_t *)&__bss_end__
#define DATA_SECTION_START (uint8_t *)&__data_start__
#define DATA_SECTION_END (uint8_t *)&__data_end__
#define CUSTOMSECTION_SECTION_START (uint8_t *)&__customSection_start__
#define CUSTOMSECTION_SECTION_END (uint8_t *)&__customSection_end__
#define CODE_RAM_SECTION_START (uint8_t *)&__code_ram_start__
#define CODE_RAM_SECTION_END (uint8_t *)&__code_ram_end__
extern uint32_t __interrupts_start__;
extern uint32_t __interrupts_end__;
extern uint32_t __bss_start__;
extern uint32_t __bss_end__;
extern uint32_t __data_start__;
extern uint32_t __data_end__;
extern uint32_t __customSection_start__;
extern uint32_t __customSection_end__;
extern uint32_t __code_ram_start__;
extern uint32_t __code_ram_end__;
#endif
#endif
#if (defined(__ICCARM__))
#pragma section = ".data"
#pragma section = ".data_init"
#pragma section = ".bss"
#pragma section = ".intvec"
#pragma section = ".customSection"
#pragma section = ".customSection_init"
#pragma section = "__CODE_RAM"
#pragma section = "__CODE_ROM"
#endif
/*!
* @brief Make necessary initializations for RAM.
*
* - Copy initialized data from ROM to RAM.
* - Clear the zero-initialized data section.
* - Copy the vector table from ROM to RAM. This could be an option.
*/
void init_data_bss(void);
#endif /* STARTUP_H*/
/*******************************************************************************
* EOF
******************************************************************************/

227
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/startup/startup_S32K118.S Normal file
View File

@ -0,0 +1,227 @@
/* ---------------------------------------------------------------------------------------*/
/* @file: startup_S32K118.s */
/* @purpose: GNU Compiler Collection Startup File */
/* S32K118 */
/* @version: 1.0 */
/* @date: 2018-1-22 */
/* @build: b170107 */
/* ---------------------------------------------------------------------------------------*/
/* */
/* Copyright 2018 NXP */
/* All rights reserved. */
/* */
/* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES */
/* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. */
/* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, */
/* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR */
/* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) */
/* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, */
/* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING */
/* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF */
/* THE POSSIBILITY OF SUCH DAMAGE. */
/*****************************************************************************/
/* Version: GNU Compiler Collection */
/*****************************************************************************/
.syntax unified
.arch armv6-m
.section .isr_vector, "a"
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* Non Maskable Interrupt */
.long HardFault_Handler /* Cortex-M0 SV Hard Fault Interrupt */
.long 0
.long 0
.long 0
.long 0
.long 0
.long 0
.long 0
.long SVC_Handler /* Cortex-M0 SV Call Interrupt */
.long 0
.long 0
.long PendSV_Handler /* Cortex-M0 Pend SV Interrupt */
.long SysTick_Handler /* Cortex-M0 System Tick Interrupt */
.long DMA0_IRQHandler /* DMA channel 0 transfer complete */
.long DMA1_IRQHandler /* DMA channel 1 transfer complete */
.long DMA2_IRQHandler /* DMA channel 2 transfer complete */
.long DMA3_IRQHandler /* DMA channel 3 transfer complete */
.long DMA_Error_IRQHandler /* DMA error interrupt channels 0-3 */
.long ERM_fault_IRQHandler /* ERM single and double bit error correction */
.long RTC_IRQHandler /* RTC alarm interrupt */
.long RTC_Seconds_IRQHandler /* RTC seconds interrupt */
.long LPTMR0_IRQHandler /* LPTIMER interrupt request */
.long PORT_IRQHandler /* Port A, B, C, D and E pin detect interrupt */
.long CAN0_ORed_Err_Wakeup_IRQHandler /* OR’ed [Bus Off OR Bus Off Done OR Transmit Warning OR Receive Warning], Interrupt indicating that errors were detected on the CAN bus, Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode */
.long CAN0_ORed_0_31_MB_IRQHandler /* OR’ed Message buffer (0-15, 16-31) */
.long FTM0_Ch0_7_IRQHandler /* FTM0 Channel 0 to 7 interrupt */
.long FTM0_Fault_IRQHandler /* FTM0 Fault interrupt */
.long FTM0_Ovf_Reload_IRQHandler /* FTM0 Counter overflow and Reload interrupt */
.long FTM1_Ch0_7_IRQHandler /* FTM1 Channel 0 to 7 interrupt */
.long FTM1_Fault_IRQHandler /* FTM1 Fault interrupt */
.long FTM1_Ovf_Reload_IRQHandler /* FTM1 Counter overflow and Reload interrupt */
.long FTFC_IRQHandler /* FTFC Command complete, Read collision and Double bit fault detect */
.long PDB0_IRQHandler /* PDB0 interrupt */
.long LPIT0_IRQHandler /* LPIT interrupt */
.long SCG_CMU_LVD_LVWSCG_IRQHandler /* PMC Low voltage detect interrupt, SCG bus interrupt request and CMU loss of range interrupt */
.long WDOG_IRQHandler /* WDOG interrupt request out before wdg reset out */
.long RCM_IRQHandler /* RCM Asynchronous Interrupt */
.long LPI2C0_Master_Slave_IRQHandler /* LPI2C0 Master Interrupt and Slave Interrupt */
.long FLEXIO_IRQHandler /* FlexIO Interrupt */
.long LPSPI0_IRQHandler /* LPSPI0 Interrupt */
.long LPSPI1_IRQHandler /* LPSPI1 Interrupt */
.long ADC0_IRQHandler /* ADC0 interrupt request. */
.long CMP0_IRQHandler /* CMP0 interrupt request */
.long LPUART1_RxTx_IRQHandler /* LPUART1 Transmit / Receive Interrupt */
.long LPUART0_RxTx_IRQHandler /* LPUART0 Transmit / Receive Interrupt */
.size __isr_vector, . - __isr_vector
/* Flash Configuration */
.section .FlashConfig, "a"
.long 0xFFFFFFFF /* 8 bytes backdoor comparison key */
.long 0xFFFFFFFF /* */
.long 0xFFFFFFFF /* 4 bytes program flash protection bytes */
.long 0xFFFF7FFE /* FDPROT:FEPROT:FOPT:FSEC(0xFE = unsecured) */
.text
.thumb
/* Reset Handler */
.thumb_func
.align 2
.globl Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
cpsid i /* Mask interrupts */
/* Init the rest of the registers */
ldr r1,=0
ldr r2,=0
ldr r3,=0
ldr r4,=0
ldr r5,=0
ldr r6,=0
ldr r7,=0
mov r8,r7
mov r9,r7
mov r10,r7
mov r11,r7
mov r12,r7
#ifdef START_FROM_FLASH
/* Init ECC RAM */
ldr r1, =__RAM_START
ldr r2, =__RAM_END
subs r2, r1
subs r2, #1
ble .LC5
movs r0, 0
movs r3, #4
.LC4:
str r0, [r1]
add r1, r1, r3
subs r2, 4
bge .LC4
.LC5:
#endif
/* Initialize the stack pointer */
ldr r0,=__StackTop
mov r13,r0
#ifndef __NO_SYSTEM_INIT
/* Call the system init routine */
ldr r0,=SystemInit
blx r0
#endif
/* Init .data and .bss sections */
ldr r0,=init_data_bss
blx r0
cpsie i /* Unmask interrupts */
#ifndef __START
#ifdef __EWL__
#define __START __thumb_startup
#else
#define __START _start
#endif
#endif
bl __START
JumpToSelf:
b JumpToSelf
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak DefaultISR
.type DefaultISR, %function
DefaultISR:
b DefaultISR
.size DefaultISR, . - DefaultISR
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, DefaultISR
.endm
/* Exception Handlers */
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler SVC_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler DMA0_IRQHandler
def_irq_handler DMA1_IRQHandler
def_irq_handler DMA2_IRQHandler
def_irq_handler DMA3_IRQHandler
def_irq_handler DMA_Error_IRQHandler
def_irq_handler ERM_fault_IRQHandler
def_irq_handler RTC_IRQHandler
def_irq_handler RTC_Seconds_IRQHandler
def_irq_handler LPTMR0_IRQHandler
def_irq_handler PORT_IRQHandler
def_irq_handler CAN0_ORed_Err_Wakeup_IRQHandler
def_irq_handler CAN0_ORed_0_31_MB_IRQHandler
def_irq_handler FTM0_Ch0_7_IRQHandler
def_irq_handler FTM0_Fault_IRQHandler
def_irq_handler FTM0_Ovf_Reload_IRQHandler
def_irq_handler FTM1_Ch0_7_IRQHandler
def_irq_handler FTM1_Fault_IRQHandler
def_irq_handler FTM1_Ovf_Reload_IRQHandler
def_irq_handler FTFC_IRQHandler
def_irq_handler PDB0_IRQHandler
def_irq_handler LPIT0_IRQHandler
def_irq_handler SCG_CMU_LVD_LVWSCG_IRQHandler
def_irq_handler WDOG_IRQHandler
def_irq_handler RCM_IRQHandler
def_irq_handler LPI2C0_Master_Slave_IRQHandler
def_irq_handler FLEXIO_IRQHandler
def_irq_handler LPSPI0_IRQHandler
def_irq_handler LPSPI1_IRQHandler
def_irq_handler ADC0_IRQHandler
def_irq_handler CMP0_IRQHandler
def_irq_handler LPUART1_RxTx_IRQHandler
def_irq_handler LPUART0_RxTx_IRQHandler
.end

151
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/.cproject Normal file
View File

@ -0,0 +1,151 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.1790979322">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.1790979322" moduleId="org.eclipse.cdt.core.settings" name="Debug">
<externalSettings/>
<extensions>
<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="com.freescale.s32ds.cdt.core.errorParsers.S32DSGNULinkerErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactExtension="elf" artifactName="demoprog_s32k118" buildArtefactType="com.nxp.s32ds.cle.arm.mbs.arm32.bare.buildArtefact.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=com.nxp.s32ds.cle.arm.mbs.arm32.bare.buildArtefact.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" description="" id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.1790979322" name="Debug" parent="com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug">
<folderInfo id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.1790979322." name="/" resourcePath="">
<toolChain id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.toolchain.debug.853553229" name="ARM Bare-Metal 32-bit Target Binary Toolchain" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.toolchain.debug">
<option defaultValue="true" id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.addtools.printsize.1198921672" name="Print size" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.addtools.printsize" valueType="boolean"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.libraries.1563254957" name="Libraries support" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.libraries" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.libraries.newlib_nano_noio" valueType="enumerated"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.fpu.abi.2014712464" name="Float ABI" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.fpu.abi" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.fpu.abi.soft" valueType="enumerated"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.mcpu.789373242" name="ARM family" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.mcpu" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.mcpu.cortex-m0plus" valueType="enumerated"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.fpu.unit.1690809584" name="FPU Type" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.target.fpu.unit"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.addtools.createflash.516336742" name="Create flash image" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.option.addtools.createflash" value="true" valueType="boolean"/>
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="cdt.managedbuild.targetPlatform.gnu.cross.1926394370" isAbstract="false" osList="all" superClass="cdt.managedbuild.targetPlatform.gnu.cross"/>
<builder buildPath="${workspace_loc:/Prog}/Debug_FLASH" id="com.freescale.s32ds.cross.gnu.builder.1847987425" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="FSL Make Builder" superClass="com.freescale.s32ds.cross.gnu.builder"/>
<tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.1515912810" name="Standard S32DS C Compiler" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler">
<option defaultValue="gnu.c.optimization.level.none" id="gnu.c.compiler.option.optimization.level.1455786821" name="Optimization Level" superClass="gnu.c.compiler.option.optimization.level" useByScannerDiscovery="false" value="gnu.c.optimization.level.optimize" valueType="enumerated"/>
<option id="gnu.c.compiler.option.debugging.level.1709968537" name="Debug Level" superClass="gnu.c.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.c.debugging.level.max" valueType="enumerated"/>
<option id="com.freescale.s32ds.cross.gnu.tool.c.compiler.option.optimization.functionsections.1598922797" name="Function sections (-ffunction-sections)" superClass="com.freescale.s32ds.cross.gnu.tool.c.compiler.option.optimization.functionsections" useByScannerDiscovery="true" value="true" valueType="boolean"/>
<option id="com.freescale.s32ds.cross.gnu.tool.c.compiler.option.optimization.datasections.126920980" name="Data sections (-fdata-sections)" superClass="com.freescale.s32ds.cross.gnu.tool.c.compiler.option.optimization.datasections" useByScannerDiscovery="true" value="true" valueType="boolean"/>
<option id="com.freescale.s32ds.cross.gnu.tool.c.compiler.option.debugging.format.1646106944" name="Debug format" superClass="com.freescale.s32ds.cross.gnu.tool.c.compiler.option.debugging.format" useByScannerDiscovery="true"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.libraries.1470967861" name="Libraries support" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.libraries" useByScannerDiscovery="false" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.libraries.newlib_nano_noio" valueType="enumerated"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.sysroot.719044715" name="Sysroot" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.sysroot" useByScannerDiscovery="false" value="--sysroot=&quot;${S32DS_ARM32_NEWLIB_DIR}&quot;" valueType="string"/>
<option id="gnu.c.compiler.option.include.paths.1639099346" name="Include paths (-I)" superClass="gnu.c.compiler.option.include.paths" useByScannerDiscovery="false" valueType="includePath">
<listOptionValue builtIn="false" value="&quot;${ProjDirPath}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/lib&quot;"/>
</option>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.fpu.abi.1978266662" name="Float ABI" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.fpu.abi" useByScannerDiscovery="true" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.fpu.abi.soft" valueType="enumerated"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.mcpu.1621521473" name="ARM family" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.mcpu" useByScannerDiscovery="true" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.option.target.mcpu.cortex-m0plus" valueType="enumerated"/>
<option id="gnu.c.compiler.option.preprocessor.def.symbols.1718931904" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" useByScannerDiscovery="false" valueType="definedSymbols">
<listOptionValue builtIn="false" value="CPU_S32K118"/>
</option>
<option id="gnu.c.compiler.option.dialect.std.968525961" name="Language standard" superClass="gnu.c.compiler.option.dialect.std" useByScannerDiscovery="true" value="gnu.c.compiler.dialect.default" valueType="enumerated"/>
<inputType id="cdt.managedbuild.tool.gnu.c.compiler.input.1385460980" superClass="cdt.managedbuild.tool.gnu.c.compiler.input"/>
</tool>
<tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.1157175604" name="Standard S32DS C++ Compiler" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler">
<option id="gnu.cpp.compiler.option.optimization.level.1631000509" name="Optimization Level" superClass="gnu.cpp.compiler.option.optimization.level" useByScannerDiscovery="false" value="gnu.cpp.compiler.optimization.level.none" valueType="enumerated"/>
<option id="gnu.cpp.compiler.option.debugging.level.1236566075" name="Debug Level" superClass="gnu.cpp.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.cpp.compiler.debugging.level.max" valueType="enumerated"/>
<option id="com.freescale.s32ds.cross.gnu.tool.cpp.compiler.option.optimization.functionsections.1272020322" name="Function sections (-ffunction-sections)" superClass="com.freescale.s32ds.cross.gnu.tool.cpp.compiler.option.optimization.functionsections" useByScannerDiscovery="true" value="true" valueType="boolean"/>
<option id="com.freescale.s32ds.cross.gnu.tool.cpp.compiler.option.optimization.datasections.1599180276" name="Data sections (-fdata-sections)" superClass="com.freescale.s32ds.cross.gnu.tool.cpp.compiler.option.optimization.datasections" useByScannerDiscovery="true" value="true" valueType="boolean"/>
<option id="com.freescale.s32ds.cross.gnu.tool.cpp.compiler.option.debugging.format.27302084" name="Debug format" superClass="com.freescale.s32ds.cross.gnu.tool.cpp.compiler.option.debugging.format" useByScannerDiscovery="true"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.sysroot.2131116479" name="Sysroot" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.sysroot" useByScannerDiscovery="false" value="--sysroot=&quot;${S32DS_ARM32_NEWLIB_DIR}&quot;" valueType="string"/>
<option id="gnu.cpp.compiler.option.include.paths.1833351253" name="Include paths (-I)" superClass="gnu.cpp.compiler.option.include.paths" useByScannerDiscovery="false" valueType="includePath">
<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/include&quot;"/>
</option>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.fpu.abi.1841077811" name="Float ABI" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.fpu.abi" useByScannerDiscovery="true" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.fpu.abi.soft" valueType="enumerated"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.mcpu.1603820521" name="ARM family" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.mcpu" useByScannerDiscovery="true" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.compiler.option.target.mcpu.cortex-m0plus" valueType="enumerated"/>
<option id="gnu.cpp.compiler.option.preprocessor.def.1108447598" name="Defined symbols (-D)" superClass="gnu.cpp.compiler.option.preprocessor.def" useByScannerDiscovery="false" valueType="definedSymbols">
<listOptionValue builtIn="false" value="CPU_S32K118"/>
</option>
</tool>
<tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.756601295" name="Standard S32DS C Linker" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker">
<option id="com.freescale.s32ds.cross.gnu.tool.c.linker.option.gcsections.955862378" name="Remove unused sections (-Xlinker --gc-sections)" superClass="com.freescale.s32ds.cross.gnu.tool.c.linker.option.gcsections" value="true" valueType="boolean"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.libraries.1494570485" name="Libraries support" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.libraries" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.libraries.newlib_nano_noio" valueType="enumerated"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.sysroot.1048856664" name="Sysroot" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.sysroot" value="--sysroot=&quot;${S32DS_ARM32_NEWLIB_DIR}&quot;" valueType="string"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.fpu.abi.839014107" name="Float ABI" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.fpu.abi" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.fpu.abi.soft" valueType="enumerated"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.mcpu.1859143379" name="ARM family" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.mcpu" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.linker.option.target.mcpu.cortex-m0plus" valueType="enumerated"/>
<option id="com.freescale.s32ds.cross.gnu.tool.c.linker.option.scriptfile.1138791579" name="Script files (-T)" superClass="com.freescale.s32ds.cross.gnu.tool.c.linker.option.scriptfile" useByScannerDiscovery="false" valueType="stringList">
<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/S32K118_25_flash.ld&quot;"/>
</option>
<inputType id="com.freescale.s32ds.cross.gnu.tool.c.linker.inputType.scriptfile.364679834" superClass="com.freescale.s32ds.cross.gnu.tool.c.linker.inputType.scriptfile"/>
</tool>
<tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.651467496" name="Standard S32DS C++ Linker" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker">
<option id="com.freescale.s32ds.cross.gnu.tool.cpp.linker.option.gcsections.554106804" name="Remove unused sections (-Xlinker --gc-sections)" superClass="com.freescale.s32ds.cross.gnu.tool.cpp.linker.option.gcsections" value="true" valueType="boolean"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.libraries.1726629560" name="Libraries support" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.libraries" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.libraries.newlib_nano_noio" valueType="enumerated"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.sysroot.1085864978" name="Sysroot" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.sysroot" value="--sysroot=&quot;${S32DS_ARM32_NEWLIB_DIR}&quot;" valueType="string"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.fpu.abi.662116187" name="Float ABI" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.fpu.abi" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.fpu.abi.soft" valueType="enumerated"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.mcpu.1587968838" name="ARM family" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.mcpu" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.cpp.linker.option.target.mcpu.cortex-m0plus" valueType="enumerated"/>
<option id="com.freescale.s32ds.cross.gnu.tool.cpp.linker.option.scriptfile.641757288" name="Script files (-T)" superClass="com.freescale.s32ds.cross.gnu.tool.cpp.linker.option.scriptfile" valueType="stringList">
<listOptionValue builtIn="false" value="&quot;${ProjDirPath}/Project_Settings/Linker_Files/S32K118_25_flash.ld&quot;"/>
</option>
</tool>
<tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.archiver.1485848924" name="Standard S32DS Archiver" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.archiver"/>
<tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.697880452" name="Standard S32DS Assembler" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler">
<option id="com.freescale.s32ds.cross.gnu.tool.assembler.usepreprocessor.1191775841" name="Use preprocessor" superClass="com.freescale.s32ds.cross.gnu.tool.assembler.usepreprocessor" value="true" valueType="boolean"/>
<option id="com.freescale.s32ds.cross.gnu.tool.assembler.option.debugging.level.400665451" name="Debug Level" superClass="com.freescale.s32ds.cross.gnu.tool.assembler.option.debugging.level" value="gnu.c.debugging.level.max" valueType="enumerated"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.libraries.438121810" name="Libraries support" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.libraries" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.libraries.newlib_nano_noio" valueType="enumerated"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.sysroot.1746556726" name="Sysroot" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.sysroot" value="--sysroot=&quot;${S32DS_ARM32_NEWLIB_DIR}&quot;" valueType="string"/>
<option id="gnu.both.asm.option.include.paths.2085769346" name="Include paths (-I)" superClass="gnu.both.asm.option.include.paths" useByScannerDiscovery="false"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.fpu.abi.259737196" name="Float ABI" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.fpu.abi" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.fpu.abi.soft" valueType="enumerated"/>
<option id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.mcpu.2056411974" name="ARM family" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.mcpu" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.assembler.option.target.mcpu.cortex-m0plus" valueType="enumerated"/>
<option id="com.freescale.s32ds.cross.gnu.tool.assembler.option.defs.1295943463" name="Defined symbols (-D)" superClass="com.freescale.s32ds.cross.gnu.tool.assembler.option.defs" valueType="definedSymbols">
<listOptionValue builtIn="false" value="START_FROM_FLASH"/>
</option>
<inputType id="cdt.managedbuild.tool.gnu.assembler.input.846888159" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
<inputType id="com.freescale.s32ds.cross.gnu.tool.assembler.inputType.asmfile.1566494432" superClass="com.freescale.s32ds.cross.gnu.tool.assembler.inputType.asmfile"/>
</tool>
<tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.createflash.1272754177" name="Standard S32DS Create Flash Image" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.createflash"/>
<tool id="com.freescale.s32ds.cross.gnu.tool.createlisting.1890754460" name="Standard S32DS Create Listing" superClass="com.freescale.s32ds.cross.gnu.tool.createlisting">
<option id="com.freescale.s32ds.cross.gnu.option.createlisting.source.270010890" name="Display source (--source|-S)" superClass="com.freescale.s32ds.cross.gnu.option.createlisting.source" value="true" valueType="boolean"/>
<option id="com.freescale.s32ds.cross.gnu.option.createlisting.allheaders.547464589" name="Display all headers (--all-headers|-x)" superClass="com.freescale.s32ds.cross.gnu.option.createlisting.allheaders" value="true" valueType="boolean"/>
<option id="com.freescale.s32ds.cross.gnu.option.createlisting.demangle.255176246" name="Demangle names (--demangle|-C)" superClass="com.freescale.s32ds.cross.gnu.option.createlisting.demangle" value="true" valueType="boolean"/>
<option id="com.freescale.s32ds.cross.gnu.option.createlisting.linenumbers.1722862074" name="Display line numbers (--line-numbers|-l)" superClass="com.freescale.s32ds.cross.gnu.option.createlisting.linenumbers" value="true" valueType="boolean"/>
<option id="com.freescale.s32ds.cross.gnu.option.createlisting.wide.1247876828" name="Wide lines (--wide|-w)" superClass="com.freescale.s32ds.cross.gnu.option.createlisting.wide" value="true" valueType="boolean"/>
</tool>
<tool id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.printsize.1666393696" name="Standard S32DS Print Size" superClass="com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.printsize">
<option id="com.freescale.s32ds.cross.gnu.option.printsize.format.2120164826" name="Size format" superClass="com.freescale.s32ds.cross.gnu.option.printsize.format"/>
</tool>
<tool id="com.freescale.s32ds.cross.gnu.c.preprocessor.9648124" name="Standard S32DS C Preprocessor" superClass="com.freescale.s32ds.cross.gnu.c.preprocessor"/>
<tool id="com.freescale.s32ds.cross.gnu.cpp.preprocessor.1069203551" name="Standard S32DS C++ Preprocessor" superClass="com.freescale.s32ds.cross.gnu.cpp.preprocessor"/>
<tool id="com.freescale.s32ds.cross.gnu.disassembler.811303159" name="Standard S32DS Disassembler" superClass="com.freescale.s32ds.cross.gnu.disassembler"/>
</toolChain>
</folderInfo>
<fileInfo id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.1790979322.Project_Settings/Debugger" name="Debugger" rcbsApplicability="disable" resourcePath="Project_Settings/Debugger" toolsToInvoke=""/>
<sourceEntries>
<entry excluding="Project_Settings" flags="VALUE_WORKSPACE_PATH" kind="sourcePath" name=""/>
</sourceEntries>
</configuration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<project id="Prog.com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.1887796633" name="ARM32 Executable" projectType="com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe"/>
</storageModule>
<storageModule moduleId="scannerConfiguration">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
<scannerConfigBuildInfo instanceId="com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.1790979322;com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.1790979322.;com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.1515912810;cdt.managedbuild.tool.gnu.c.compiler.input.1385460980">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
<scannerConfigBuildInfo instanceId="com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.release.ram.246914351;com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.release.ram.246914351.;com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.199296304;cdt.managedbuild.tool.gnu.c.compiler.input.1026964358">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
<scannerConfigBuildInfo instanceId="com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.release.1876020028;com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.release.1876020028.;com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.1893450840;cdt.managedbuild.tool.gnu.c.compiler.input.1130421182">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
<scannerConfigBuildInfo instanceId="com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.ram.839914523;com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.ram.839914523.;com.nxp.s32ds.cle.arm.mbs.arm32.bare.tool.c.compiler.577239036;cdt.managedbuild.tool.gnu.c.compiler.input.533102289">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
<storageModule moduleId="org.eclipse.embsys" parent_project="true" register_architecture="" register_board="--- none ---" register_chip="" register_core="" register_vendor=""/>
<storageModule moduleId="refreshScope" versionNumber="2">
<configuration configurationName="Debug">
<resource resourceType="PROJECT" workspacePath="/Prog"/>
</configuration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
</cproject>

26
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/.project Normal file
View File

@ -0,0 +1,26 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>Prog</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
</projectDescription>

8
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/.settings/com.nxp.s32ds.cle.runtime.component.prefs Normal file
View File

@ -0,0 +1,8 @@
com.nxp.s32ds.cle.runtime.component.registry.archetype.id=application
com.nxp.s32ds.cle.runtime.component.registry.archetype.platform.id=
com.nxp.s32ds.cle.runtime.hardware.registry.core.id=CortexM0P
com.nxp.s32ds.cle.runtime.hardware.registry.device.id=S32K118
com.nxp.s32ds.cle.runtime.hardware.registry.deviceCore.id=S32K118_M0P
com.nxp.s32ds.cle.runtime.hardware.registry.family.id=S32K1
com.nxp.s32ds.cle.runtime.lang.registry.lang.id=c
eclipse.preferences.version=1

2
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/.settings/com.processorexpert.core.ide.newprojectwizard.prefs Normal file
View File

@ -0,0 +1,2 @@
eclipse.preferences.version=1
versionGenerated/versionGenerated=1.8.4.RT7_b1743-0713

14
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/.settings/language.settings.xml Normal file
View File

@ -0,0 +1,14 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project>
<configuration id="com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.1790979322" name="Debug">
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
<provider class="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" console="false" env-hash="1495519144810931747" id="com.freescale.s32ds.cross.gnu.CrossGCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT S32DS Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>
</extension>
</configuration>
</project>

3
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/.settings/org.eclipse.cdt.codan.core.prefs Normal file
View File

@ -0,0 +1,3 @@
eclipse.preferences.version=1
inEditor=false
onBuild=false

21
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/.settings/org.eclipse.cdt.core.prefs Normal file
View File

@ -0,0 +1,21 @@
eclipse.preferences.version=1
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.1790979322/PATH/delimiter=;
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.1790979322/PATH/operation=prepend
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.1790979322/PATH/value=
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.1790979322/append=true
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.1790979322/appendContributed=true
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.ram.839914523/PATH/delimiter=;
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.ram.839914523/PATH/operation=prepend
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.ram.839914523/PATH/value=
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.ram.839914523/append=true
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.ram.839914523/appendContributed=true
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.release.1876020028/PATH/delimiter=;
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.release.1876020028/PATH/operation=prepend
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.release.1876020028/PATH/value=
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.release.1876020028/append=true
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.release.1876020028/appendContributed=true
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.release.ram.246914351/PATH/delimiter=;
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.release.ram.246914351/PATH/operation=prepend
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.release.ram.246914351/PATH/value=
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.release.ram.246914351/append=true
environment/project/com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.release.ram.246914351/appendContributed=true

BIN
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/Debug/demoprog_s32k118.elf Normal file
View File

Binary file not shown.

206
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/Debug/demoprog_s32k118.srec Normal file
View File

@ -0,0 +1,206 @@
S018000064656D6F70726F675F7333326B3131382E7372656373
S1132000005800203D250000992500009925000076
S113201000000000000000000000000000000000BC
S113202000000000000000000000000099250000EE
S1132030000000000000000099250000D92C0000D9
S11320409925000099250000992500009925000094
S11320509925000099250000992500009925000084
S11320609925000099250000992500009925000074
S11320709925000099250000992500009925000064
S11320809925000099250000992500009925000054
S11320909925000099250000992500009925000044
S11320A09925000099250000992500009925000034
S11320B09925000099250000992500009925000024
S10720C0EE11AA551A
S1132400FFFFFFFFFFFFFFFFFFFFFFFFFE7FFFFF59
S1132410054B0648033310B51B1A062B03D9044B8E
S1132420002B00D0984710BD28010020280100206F
S1132430000000000648074910B5091A8910CB0F9F
S11324405918491003D0044B002B00D0984710BDF5
S113245028010020280100200000000010B5074CCE
S11324602378002B09D1FFF7D3FF054B002B02D0B3
S1132470044800E000BF0123237010BDC0300020D9
S113248000000000382F0000094B10B5002B03D0CA
S11324900849094800E000BF08480368002B02D13E
S11324A0FFF7C8FF10BD064B002BF9D09847F7E79C
S11324B000000000C4300020382F00002401002058
S11324C000000000164B002B00D1144B9D46402207
S11324D092029A1A924600218B460F461348144AD8
S11324E0121A00F0F9FC0F4B002B00D098470E4B4A
S11324F0002B00D098470020002104000D000D4857
S1132500002802D00C4800E000BF00F0C1FC20000D
S1132510290000F05DFB00F0A5FCC04600000800A7
S1132520005800200000000000000000C03000201F
S113253034310020000000000000000072B6104991
S11325400F4A0F4B0E4C0E4D0D4E0D4FB846B9466B
S1132550BA46BB46BC460B490B4A521A013A05DD42
S11325600020042308601944043AFBDA074885462E
S1132570074880470748804762B6FFF7A3FFFEE796
S11325800000000000000020005800200058002037
S1132590E92C0000892D0000FEE7C0460022430814
S11325A08B4274D303098B425FD3030A8B4244D317
S11325B0030B8B4228D3030C8B420DD3FF22090259
S11325C012BA030C8B4202D31212090265D0030B18
S11325D08B4219D300E0090AC30B8B4201D3CB030E
S11325E0C01A5241830B8B4201D38B03C01A524150
S11325F0430B8B4201D34B03C01A5241030B8B4252
S113260001D30B03C01A5241C30A8B4201D3CB023C
S1132610C01A5241830A8B4201D38B02C01A524121
S1132620430A8B4201D34B02C01A5241030A8B4224
S113263001D30B02C01A5241CDD2C3098B4201D33C
S1132640CB01C01A524183098B4201D38B01C01ABA
S1132650524143098B4201D34B01C01A5241030931
S11326608B4201D30B01C01A5241C3088B4201D3E0
S1132670CB00C01A524183088B4201D38B00C01A8D
S1132680524143088B4201D34B00C01A5241411AB4
S113269000D20146524110467047FFE701B50020C1
S11326A000F006F802BDC0460029F7D076E770476F
S11326B07047C04670B50C4B1B68002B00DB70BD27
S11326C0094A13685B005B08136000F0FFFAFA30F4
S11326D00400054E80256D0333682B42EFD000F0D3
S11326E0F5FA8442F8D2EAE70040024070B50D4B97
S11326F019688022D2050A431A601968802252059B
S11327000A431A6000F0E2FAFA300400054E80250C
S11327106D0433682B4203D100F0D8FA8442F8D216
S113272070BDC04600400240F0B585B0002302AA47
S1132730137001335370013393700233D370043335
S1132740137108335371103393712033D371AA4A30
S11327506933FF33D158A9480140D150D05884215E
S1132760C9050143D1505C33A54AD3585B055B0FBF
S113277005D18021490081239B00D150012382226D
S113278092009F498A58D20776D49E4802AAD15C07
S1132790FFF704FFE1210902FFF700FFC31D1B043B
S11327A0DB0CE022D2041A43974B1A61974A5A6110
S11327B000229A611A625A62F02292029A629A6A1A
S11327C088210A439A620122DA62C02212039A61C2
S11327D08949902288588023DB0503438B50FFF7F7
S11327E069FFFFF783FF8A4B1B68002B13DB884AC2
S11327F0116880231B060B43136000F067FAFA305C
S11328000400834E80256D0333682B4203D100F00E
S11328105DFA8442F8D27E4A53687E490B40536085
S1132820FFF748FFFFF762FF002302AA137001338A
S11328305370013393700233D3700433137108332C
S11328405371103393712033D371C4336C4AD3580A
S11328505B055B0F06D1802149000533FF33D1505E
S1132860043BFF3B02AAD15C6B48FFF797FE019043
S11328706A4F0026002505E0694887E701360437DA
S1132880122E1BD03A785401A41AA400A418A40050
S113289021000198FFF708FF0029EFD121000198DA
S11328A0FFF77CFE85B26B1E9BB2FF2BE6D8B60009
S11328B05A4B9E197778B078F17802E00021002015
S11328C00027534A5468574B1C40546054686B1E8D
S11328D01B062343536056687D1E07232B40334356
S11328E053605468431EDB04E025AD032B402343AF
S11328F0536054684B1E1B04E021C9020B40234360
S113290053605268031C042800D90423DBB2013B42
S11329109B05C02109040B4013433D4A536053688F
S113292080210B4353600023100000211A00203241
S1132930920011500133802BF8D100233448002138
S1132940882292009A18920011500133202BF7D15B
S11329502F4B1A687F218A4360390A431A60196829
S1132960802292020A431A601968802252020A43A2
S11329701A601A682C490A401A602C492C4A99504A
S11329808021C9048822520099502A49043299505E
S113299000229A62013A1A63274A1A621A6827497E
S11329A00A401A605A6826490A405A601A6813494C
S11329B00A401A601A6823490A401A6000F086F92E
S11329C0FA300400124E80256D0433682B4203D084
S11329D000F07CF98442F8D200F078F9FA3004006F
S11329E00B4E80252D0533682B4203D000F06EF981
S11329F08442F8D205B0F0BD00500640FFFFFFBF8F
S1132A000040064080841E0000A0064000C01FC095
S1132A1000400240FFDFFFFF409C0000EC2E00005E
S1132A2000127A0078FF0000FFFFFFDFFFFFFF5F67
S1132A30A408000000009C1906003B00FFFF7FFF74
S1132A40F7EFFFFFFFFFFFEF30B583B03A4B1B7882
S1132A50002B3AD1394B5B699B0207D5374BDB69B5
S1132A60DBB2374A1370013B3F2B23D9354B1B6B29
S1132A709B051DD588235B00324AD1580903090FF1
S1132A8052D00023032430481A006240D2B2125CB0
S1132A906D465A550133DAB29142F5D8294B80225A
S1132AA092001A639A68294B1A602B78FF2B2BD05B
S1132AB003B030BD00F00AF9254B186001221E4B0B
S1132AC01A700022234B1A70D0E71C4B5B699B02DF
S1132AD01FD520490B78194AD469194AD018447073
S1132AE00133DBB20B7012789A42BFD10022124B31
S1132AF01A70134B5B78FF2BB8D1114B9B78002BCA
S1132B00B4D100F031F9B1E70229D1D100F02CF9A8
S1132B10CEE700F0DBF80E4B1B6864339842A5D96E
S1132B200022054B1A70A1E7064B802292001A631B
S1132B309A68064B1A60BBE72131002000A00640CA
S1132B40E03000200040024018410240DC30002008
S1132B50243100202231002080235B00044A1362C8
S1132B60044A51691943516191680B43936070475A
S1132B7000D0044000F10F4010B500F0A7F8114B4D
S1132B801B68C31AF422FF3293420FD90E4B1B78F1
S1132B90002B0CD1F33AFF3A0B4B1A700B4A5168D5
S1132BA080235B000B435360064B186010BD00226A
S1132BB0054B1A70054A916880235B000B439360B0
S1132BC0F2E7C0462C3100202831002000F10F40EC
S1132BD010B52D4B0221FF31822252009950CD397C
S1132BE0043299501900083A80231B04885818426B
S1132BF0FCD1012180235B00234AD15011001A002B
S1132C0080235B0488581842FCD01F4B0222FF32F9
S1132C10C12189005A500139FF395A501B4A5A615F
S1132C2019000F220B691B0E1340032BFAD100F07D
S1132C306DF8174B9420400019588022D205114397
S1132C4019509A214900585802435A50114B196897
S1132C50802292001143196059680A435A600E4B4E
S1132C601969A022D2001143196159690A435A61B2
S1132C7000F014F8FFF770FF62B6FFF755FDFFF799
S1132C807BFFFFF7E1FEFAE7004006400100000386
S1132C900050064000A0044000D0044010B5084B8A
S1132CA01868FA218900FFF779FC0138054B586050
S1132CB000229A6007211960034B1A6010BDC046B8
S1132CC0C000002010E000E030310020014B186803
S1132CD07047C04630310020024A13680133136044
S1132CE07047C04630310020044B054A5A605A6888
S1132CF0044A1A60044A9A607047C046002005409E
S1132D0020C528D920210000FFFF000010B5124B78
S1132D1019691B691B011B0F022B0CD0032B12D04A
S1132D20012B07D10D480903090F0131FFF736FCC8
S1132D300B4B186010BD82239B00074AD358DB0756
S1132D40F8D50648EFE7C2239B00034AD3589B07F4
S1132D50F0D10448E7E7C0460040064000127A007C
S1132D60C0000020006CDC020448054943581B04E1
S1132D701B0C044A134343507047C04600E000E074
S1132D800C0D00000400FA0530B5274A274B9A427F
S1132D9009D02649891A0023254C1000C25CE2544C
S1132DA001338B42FAD1234A234B9A4209D0224958
S1132DB0891A0023214C1000C25CE2540133994269
S1132DC0FAD11F4A1F4B9A4206D0130000211D4A14
S1132DD0197001339342FBD11B4A1C4B9A4209D010
S1132DE01A49891A00231A4C1000C25CE2540133B8
S1132DF09942FAD1174A184B9A4210D017498908B8
S1132E0009D000230022134C1348C558E550013261
S1132E1004338A42F9D1124B0E4A1A6030BD104B6A
S1132E200D4A1A60FAE7C046602F0000C82F000060
S1132E30C0000020C82F0000C82F00002801002077
S1132E40C030002034310020C82F0000C82F0000FB
S1132E50C03000200000002000200000C00000005E
S1132E6008ED00E0084B10B50400002B02D000214F
S1132E7000E000BF054B1868836A002B00D0984718
S1132E80200000F031F8C04600000000342F00009C
S1132E9070B500260C4D0D4C641BA410A64209D13C
S1132EA0002600F049F80A4D0A4C641BA410A642FF
S1132EB005D170BDB300EB5898470136EEE7B30077
S1132EC0EB5898470136F2E7582F0000582F0000BE
S1132ED0582F00005C2F000003008218934200D199
S1132EE0704719700133F9E7FEE700000803020296
S1132EF0090303020A0303030B0403030C0404037E
S1132F000D0504030E0504040F060404100605044D
S1132F10110705041207050513080505140806051D
S1132F2015080705160807061708080618080807ED
S1132F3019080808C4000020F8B5C046F8BC08BC4D
S1132F409E467047F8B5C046F8BC08BC9E4670471C
S10B2F5074F5FF7F010000008D
S1072F5889240000C4
S1072F5C5D240000EC
S1132F60006CDC0200000000000000000000000013
S1132F70000000000000000000000000000000004D
S1132F80000000000000000000000000000000003D
S1132F90000000000000000000000000000000002D
S1132FA0000000000000000000000000000000001D
S1132FB0000000000000000000000000000000000D
S10B2FC0000000000000000005
S903253D9A

221
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/Prog_Debug.launch Normal file
View File

@ -0,0 +1,221 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<launchConfiguration type="com.pemicro.debug.gdbjtag.pne.launchConfigurationType">
<stringAttribute key="bad_container_name" value="\Prog\P"/>
<stringAttribute key="com.nxp.s32ds.ext.cdt.debug.svd.svd_path" value=""/>
<booleanAttribute key="com.nxp.s32ds.ext.cdt.debug.svd.use_default" value="true"/>
<listAttribute key="com.pemicro.debug.gdbjtag.pne.ELVES"/>
<listAttribute key="com.pemicro.debug.gdbjtag.pne.ELVES_OFFSET"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.NUMBER_ELVES" value="0"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.BUSERR" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.CHKERR" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.CORERESET" value="true"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.DEVICE_NAME" value="NXP_S32K1xx_S32K118F256M4"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.GDB_OPTIONS" value=""/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.HARDERR" value="true"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.PE.HARDWARE_INTERFACE" value="6"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.INTERR" value="true"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.LAST_ATTRIBUTE_HEADER" value="com.pemicro.debug.gdbjtag.pne.sda."/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.MMERR" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.NOCPERR" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.STATERR" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.STREAMING_ENABLE_PORT1" value="true"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.PE.STREAMING_SERVER_PORT1" value="10224"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.PE.USE_EXTERNAL_SERVER" value="true"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.algorithmIndex" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.alternativeAlgorithmPath" value=""/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.attachToRunning" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.customTrimFrequency" value="0"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.ALWAYS_ERASE" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.CYCLONE_IP" value=""/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.DO_RESET_DELAY" value="false"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.INTERFACE_PORT" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.INTERFACE_PORT_STRING" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.NETWORK_CARD_IP" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.POWER_DOWN_DELAY" value="250"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.POWER_OFF" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.POWER_UP_DELAY" value="250"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.PROVIDE_POWER" value="true"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.REGULATOR_VOLTAGE" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.RESET_DELAY" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.SHIFT_FREQ" value="5000"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.SPECIFY_IP" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.SPECIFY_NETWORK_CARD" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_eth.STARTUP_USE_SWD" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.ALWAYS_ERASE" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.CYCLONE_IP" value=""/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.DO_RESET_DELAY" value="false"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.INTERFACE_PORT" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.INTERFACE_PORT_STRING" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.NETWORK_CARD_IP" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.POWER_DOWN_DELAY" value="250"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.POWER_OFF" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.POWER_UP_DELAY" value="250"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.PROVIDE_POWER" value="true"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.REGULATOR_VOLTAGE" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.RESET_DELAY" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.SHIFT_FREQ" value="5000"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.SPECIFY_IP" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.SPECIFY_NETWORK_CARD" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_ser.STARTUP_USE_SWD" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.ALWAYS_ERASE" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.CYCLONE_IP" value=""/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.DO_RESET_DELAY" value="false"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.INTERFACE_PORT" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.INTERFACE_PORT_STRING" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.NETWORK_CARD_IP" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.POWER_DOWN_DELAY" value="250"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.POWER_OFF" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.POWER_UP_DELAY" value="250"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.PROVIDE_POWER" value="true"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.REGULATOR_VOLTAGE" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.RESET_DELAY" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.SHIFT_FREQ" value="5000"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.SPECIFY_IP" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.SPECIFY_NETWORK_CARD" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.cyc_usb.STARTUP_USE_SWD" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doContinue" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doGdbServerAllocateSemihostingConsole" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.doPartitioning" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.enableSemihosting" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.enableSemihostingIoclientGdbClient" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.enableSemihostingIoclientTelnet" value="true"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.eraseCommandParam" value="EM"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.eraseOptionIndex" value="0"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.eraseOptionsenabled" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.executeUnlockCommand" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbClientOtherCommands" value="set mem inaccessible-by-default off&#13;&#10;set tcp auto-retry on&#13;&#10;set tcp connect-timeout 240&#13;&#10;set remotetimeout 60"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.gdbClientOtherOptions" value=""/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.gdbServerTelnetPortNumber" value="51794"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.gdbmiPortNumber" value="6224"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.jtagPreIrBits" value="0"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.jtagTapNumber" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.macScript" value=""/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.macScriptEnable" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.ALWAYS_ERASE" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.CYCLONE_IP" value=""/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.DO_RESET_DELAY" value="false"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.ml.INTERFACE_PORT" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.INTERFACE_PORT_STRING" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.NETWORK_CARD_IP" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.POWER_DOWN_DELAY" value="250"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.POWER_OFF" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.POWER_UP_DELAY" value="1000"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.PROVIDE_POWER" value="true"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.ml.REGULATOR_VOLTAGE" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.RESET_DELAY" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.ml.SHIFT_FREQ" value="5000"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.SPECIFY_IP" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.SPECIFY_NETWORK_CARD" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.ml.STARTUP_USE_SWD" value="true"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.otherRunCommands" value=""/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.partitionParam" value="0"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemory0" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemory1" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemory2" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryFrom0" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryFrom1" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryFrom2" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryTo0" value="3"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryTo1" value="3"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.preserveMemoryTo2" value="3"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.preservePartioning" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.programtrim" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.ALWAYS_ERASE" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.CYCLONE_IP" value=""/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.DO_RESET_DELAY" value="false"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.sda.INTERFACE_PORT" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.INTERFACE_PORT_STRING" value="USB1"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.NETWORK_CARD_IP" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.POWER_DOWN_DELAY" value=""/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.POWER_OFF" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.POWER_UP_DELAY" value=""/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.PROVIDE_POWER" value="true"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.sda.REGULATOR_VOLTAGE" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.RESET_DELAY" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.SHIFT_FREQ" value="5000"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.SPECIFY_IP" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.SPECIFY_NETWORK_CARD" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.sda.STARTUP_USE_SWD" value="true"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.SWO_BAUDRATE_SWITCH_MULTILINK_VALUE" value="-1.000000"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.sda.SWO_BAUDRATE_SWITCH_TARGET_VALUE" value="-1.000000"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.selectedCoreNumber" value="1"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.serverPortNumber" value="7224"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.ALWAYS_ERASE" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.CYCLONE_IP" value=""/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.DO_RESET_DELAY" value="false"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.INTERFACE_PORT" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.INTERFACE_PORT_STRING" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.NETWORK_CARD_IP" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.POWER_DOWN_DELAY" value="250"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.POWER_OFF" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.POWER_UP_DELAY" value="250"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.PROVIDE_POWER" value="true"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.REGULATOR_VOLTAGE" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.RESET_DELAY" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.SHIFT_FREQ" value="5000"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.SPECIFY_IP" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.SPECIFY_NETWORK_CARD" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_eth.STARTUP_USE_SWD" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.ALWAYS_ERASE" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.CYCLONE_IP" value=""/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.DO_RESET_DELAY" value="false"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.INTERFACE_PORT" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.INTERFACE_PORT_STRING" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.NETWORK_CARD_IP" value=""/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.POWER_DOWN_DELAY" value="250"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.POWER_OFF" value="false"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.POWER_UP_DELAY" value="250"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.PROVIDE_POWER" value="true"/>
<intAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.REGULATOR_VOLTAGE" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.RESET_DELAY" value="0"/>
<stringAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.SHIFT_FREQ" value="5000"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.SPECIFY_IP" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.SPECIFY_NETWORK_CARD" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.trc_usb.STARTUP_USE_SWD" value="true"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.useAlternativeAlgorithm" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.useCustomTrim" value="false"/>
<booleanAttribute key="com.pemicro.debug.gdbjtag.pne.useDaisyChain" value="false"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU ARM PEMicro Interface"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard (Windows)"/>
<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${S32DS_ARM32_TOOLCHAIN_DIR}/bin/${arm32_cross_prefix}gdb${arm32_cross_suffix}"/>
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/demoprog_s32k118.elf"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="Prog"/>
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="com.nxp.s32ds.cle.arm.mbs.arm32.bare.exe.debug.1790979322"/>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
<listEntry value="/Prog"/>
</listAttribute>
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
<listEntry value="4"/>
</listAttribute>
<stringAttribute key="org.eclipse.debug.core.source_locator_id" value="org.eclipse.cdt.debug.core.sourceLocator"/>
<stringAttribute key="org.eclipse.debug.core.source_locator_memento" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;sourceLookupDirector&gt;&#13;&#10;&lt;sourceContainers duplicates=&quot;false&quot;&gt;&#13;&#10;&lt;container memento=&quot;&amp;lt;?xml version=&amp;quot;1.0&amp;quot; encoding=&amp;quot;UTF-8&amp;quot; standalone=&amp;quot;no&amp;quot;?&amp;gt;&amp;#13;&amp;#10;&amp;lt;mapping backend_enabled=&amp;quot;true&amp;quot; name=&amp;quot;EWL&amp;quot;&amp;gt;&amp;#13;&amp;#10;&amp;lt;mapEntry memento=&amp;quot;&amp;amp;lt;?xml version=&amp;amp;quot;1.0&amp;amp;quot; encoding=&amp;amp;quot;UTF-8&amp;amp;quot; standalone=&amp;amp;quot;no&amp;amp;quot;?&amp;amp;gt;&amp;amp;#13;&amp;amp;#10;&amp;amp;lt;mapEntry backendPath=&amp;amp;quot;arm32_ewl2&amp;amp;quot; localPath=&amp;amp;quot;C:\NXP\S32DS_ARM_v2.2\S32DS\build_tools\gcc_v6.3\arm32_ewl2&amp;amp;quot;/&amp;amp;gt;&amp;amp;#13;&amp;amp;#10;&amp;quot;/&amp;gt;&amp;#13;&amp;#10;&amp;lt;/mapping&amp;gt;&amp;#13;&amp;#10;&quot; typeId=&quot;org.eclipse.cdt.debug.core.containerType.mapping&quot;/&gt;&#13;&#10;&lt;container memento=&quot;&amp;lt;?xml version=&amp;quot;1.0&amp;quot; encoding=&amp;quot;UTF-8&amp;quot; standalone=&amp;quot;no&amp;quot;?&amp;gt;&amp;#13;&amp;#10;&amp;lt;default/&amp;gt;&amp;#13;&amp;#10;&quot; typeId=&quot;org.eclipse.debug.core.containerType.default&quot;/&gt;&#13;&#10;&lt;/sourceContainers&gt;&#13;&#10;&lt;/sourceLookupDirector&gt;&#13;&#10;"/>
<listAttribute key="org.eclipse.debug.ui.favoriteGroups">
<listEntry value="org.eclipse.debug.ui.launchGroup.debug"/>
</listAttribute>
<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#13;&#10;"/>
<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
</launchConfiguration>

278
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/S32K118_25_flash.ld Normal file
View File

@ -0,0 +1,278 @@
/*
** ###################################################################
** Processor: S32K118 with 25 KB SRAM
** Compiler: GNU C Compiler
**
** Abstract:
** Linker file for the GNU C Compiler
**
** Copyright 2018 NXP
** All rights reserved.
**
** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
** THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** ###################################################################
*/
/* Entry Point */
ENTRY(Reset_Handler)
/*
To use "new" operator with EWL in C++ project the following symbol shall be defined
*/
/*EXTERN(_ZN10__cxxabiv119__terminate_handlerE)*/
HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x00000200;
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x00000200;
/* If symbol __flash_vector_table__=1 is defined at link time
* the interrupt vector will not be copied to RAM.
* Warning: Using the interrupt vector from Flash will not allow
* INT_SYS_InstallHandler because the section is Read Only.
*/
M_VECTOR_RAM_SIZE = DEFINED(__flash_vector_table__) ? 0x0 : 0x00C0;
/* Specify the memory areas */
MEMORY
{
/* Flash */
m_interrupts (RX) : ORIGIN = 0x00002000, LENGTH = 0x000000C4
m_flash_config (RX) : ORIGIN = 0x00002400, LENGTH = 0x00000010
m_text (RX) : ORIGIN = 0x00002410, LENGTH = 0x0003FBF0 - 0x2000
/* SRAM_L */
/* SRAM_U */
m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x000030C0
m_data_2 (RW) : ORIGIN = 0x200030C0, LENGTH = 0x00002740
}
/* Define output sections */
SECTIONS
{
/* The startup code goes first into internal flash */
.interrupts :
{
__VECTOR_TABLE = .;
__interrupts_start__ = .;
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
__interrupts_end__ = .;
. = ALIGN(4);
} > m_interrupts
.flash_config :
{
. = ALIGN(4);
KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */
. = ALIGN(4);
} > m_flash_config
/* The program code and other data goes into internal flash */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
} > m_text
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > m_text
.ARM :
{
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} > m_text
.ctors :
{
__CTOR_LIST__ = .;
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
} > m_text
.dtors :
{
__DTOR_LIST__ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__DTOR_END__ = .;
} > m_text
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} > m_text
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} > m_text
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} > m_text
__etext = .; /* Define a global symbol at end of code. */
__DATA_ROM = .; /* Symbol is used by startup for data initialization. */
.interrupts_ram :
{
. = ALIGN(4);
__VECTOR_RAM__ = .;
__RAM_START = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start. */
*(.m_interrupts_ram) /* This is a user defined section. */
. += M_VECTOR_RAM_SIZE;
. = ALIGN(4);
__interrupts_ram_end__ = .; /* Define a global symbol at data end. */
} > m_data
__VECTOR_RAM = DEFINED(__flash_vector_table__) ? ORIGIN(m_interrupts) : __VECTOR_RAM__ ;
__RAM_VECTOR_TABLE_SIZE = DEFINED(__flash_vector_table__) ? 0x0 : (__interrupts_ram_end__ - __interrupts_ram_start__) ;
.data : AT(__DATA_ROM)
{
. = ALIGN(4);
__DATA_RAM = .;
__data_start__ = .; /* Create a global symbol at data start. */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
KEEP(*(.jcr*))
. = ALIGN(4);
__data_end__ = .; /* Define a global symbol at data end. */
} > m_data
__DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
__CODE_ROM = __DATA_END; /* Symbol is used by code initialization. */
.code : AT(__CODE_ROM)
{
. = ALIGN(4);
__CODE_RAM = .;
__code_start__ = .; /* Create a global symbol at code start. */
__code_ram_start__ = .;
*(.code_ram) /* Custom section for storing code in RAM */
. = ALIGN(4);
__code_end__ = .; /* Define a global symbol at code end. */
__code_ram_end__ = .;
} > m_data
__CODE_END = __CODE_ROM + (__code_end__ - __code_start__);
__CUSTOM_ROM = __CODE_END;
/* Custom Section Block that can be used to place data at absolute address. */
/* Use __attribute__((section (".customSection"))) to place data here. */
.customSectionBlock ORIGIN(m_data_2) : AT(__CUSTOM_ROM)
{
__customSection_start__ = .;
KEEP(*(.customSection)) /* Keep section even if not referenced. */
__customSection_end__ = .;
} > m_data_2
__CUSTOM_END = __CUSTOM_ROM + (__customSection_end__ - __customSection_start__);
/* Uninitialized data section. */
.bss :
{
/* This is used by the startup in order to initialize the .bss section. */
. = ALIGN(4);
__BSS_START = .;
__bss_start__ = .;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
__BSS_END = .;
} > m_data_2
.heap :
{
. = ALIGN(8);
__end__ = .;
__heap_start__ = .;
PROVIDE(end = .);
PROVIDE(_end = .);
PROVIDE(__end = .);
__HeapBase = .;
. += HEAP_SIZE;
__HeapLimit = .;
__heap_limit = .;
__heap_end__ = .;
} > m_data_2
/* Initializes stack on the end of block */
__StackTop = ORIGIN(m_data_2) + LENGTH(m_data_2);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
__RAM_END = __StackTop;
.stack __StackLimit :
{
. = ALIGN(8);
__stack_start__ = .;
. += STACK_SIZE;
__stack_end__ = .;
} > m_data_2
/* Labels required by EWL */
__START_BSS = __BSS_START;
__END_BSS = __BSS_END;
__SP_INIT = __StackTop;
.ARM.attributes 0 : { *(.ARM.attributes) }
ASSERT(__StackLimit >= __HeapLimit, "region m_data_2 overflowed with stack and heap")
}

772
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/boot.c Normal file
View File

@ -0,0 +1,772 @@
/************************************************************************************//**
* \file Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/boot.c
* \brief Demo program bootloader interface source file.
* \ingroup Prog_ARMCM0_S32K14_S32K118EVB_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "header.h" /* generic header */
/****************************************************************************************
* Function prototypes
****************************************************************************************/
#if (BOOT_COM_RS232_ENABLE > 0)
static void BootComRs232Init(void);
static void BootComRs232CheckActivationRequest(void);
#endif
#if (BOOT_COM_CAN_ENABLE > 0)
static void BootComCanInit(void);
static void BootComCanCheckActivationRequest(void);
#endif
/************************************************************************************//**
** \brief Initializes the communication interface.
** \return none.
**
****************************************************************************************/
void BootComInit(void)
{
#if (BOOT_COM_RS232_ENABLE > 0)
BootComRs232Init();
#endif
#if (BOOT_COM_CAN_ENABLE > 0)
BootComCanInit();
#endif
} /*** end of BootComInit ***/
/************************************************************************************//**
** \brief Receives the CONNECT request from the host, which indicates that the
** bootloader should be activated and, if so, activates it.
** \return none.
**
****************************************************************************************/
void BootComCheckActivationRequest(void)
{
#if (BOOT_COM_RS232_ENABLE > 0)
BootComRs232CheckActivationRequest();
#endif
#if (BOOT_COM_CAN_ENABLE > 0)
BootComCanCheckActivationRequest();
#endif
} /*** end of BootComCheckActivationRequest ***/
/************************************************************************************//**
** \brief Bootloader activation function.
** \return none.
**
****************************************************************************************/
void BootActivate(void)
{
/* Activate the bootloader by performing a software reset. */
SystemSoftwareReset();
} /*** end of BootActivate ***/
#if (BOOT_COM_RS232_ENABLE > 0)
/****************************************************************************************
* U N I V E R S A L A S Y N C H R O N O U S R X T X I N T E R F A C E
****************************************************************************************/
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/** \brief Timeout time for the reception of a CTO packet. The timer is started upon
* reception of the first packet byte.
*/
#define RS232_CTO_RX_PACKET_TIMEOUT_MS (100u)
/** \brief Set the peripheral LPUART base pointer. */
#define LPUARTx (LPUART0)
/** \brief Set the PCC index offset for LPUART. */
#define PCC_LPUARTx_INDEX (PCC_LPUART0_INDEX)
/****************************************************************************************
* Function prototypes
****************************************************************************************/
static unsigned char Rs232ReceiveByte(unsigned char *data);
/************************************************************************************//**
** \brief Initializes the UART communication interface.
** \return none.
**
****************************************************************************************/
static void BootComRs232Init(void)
{
unsigned long sourceClockFreqHz;
unsigned long div2RegValue;
unsigned short baudrateSbr0_12;
unsigned char const div2DividerLookup[] =
{
0U, /* 0b000. Output disabled. */
1U, /* 0b001. Divide by 1. */
2U, /* 0b010. Divide by 2. */
4U, /* 0b011. Divide by 4. */
8U, /* 0b100. Divide by 8. */
16U, /* 0b101. Divide by 16. */
32U, /* 0b110. Divide by 32. */
64U, /* 0b111. Divide by 64. */
};
/* Make sure the UART peripheral clock is disabled before configuring its source
* clock.
*/
PCC->PCCn[PCC_LPUARTx_INDEX] &= ~PCC_PCCn_CGC_MASK;
/* Select option 2 as the UART peripheral source clock and enable the clock. Option 2
* is the SIRCDIV2_CLK, which is available on all peripherals and configurations.
*/
PCC->PCCn[PCC_LPUARTx_INDEX] |= PCC_PCCn_PCS(2) | PCC_PCCn_CGC_MASK;
/* Obtain the DIV2 divider value of the SIRC_CLK. */
div2RegValue = (SCG->SIRCDIV & SCG_SIRCDIV_SIRCDIV2_MASK) >> SCG_SIRCDIV_SIRCDIV2_SHIFT;
/* Check if the DIV2 register value for SIRC is 0. In this case SIRCDIV2_CLK is
* currently disabled.
*/
if (div2RegValue == 0U)
{
/* Configure the DIV2 for a default divide by 1 to make sure the SIRCDIV2_CLK is
* actually enabled.
*/
div2RegValue = 1U;
SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV2(div2RegValue);
}
/* Determine the SIRC clock frequency. If SIRC high range is enabled, it is 8 MHz. If
* SIRC low range is enabled, it is 2 MHz.
*/
sourceClockFreqHz = 8000000U;
if ((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) == SCG_SIRCCFG_RANGE(0))
{
sourceClockFreqHz = 2000000U;
}
/* Now process the configured DIV2 divider factor to get the actual frequency of the
* UART peripheral source clock.
*/
sourceClockFreqHz /= div2DividerLookup[div2RegValue];
/* Configure the baudrate from BOOT_COM_RS232_BAUDRATE, taking into account that an
* oversampling of 8 will be configured. Default 8,n,1 format is used. Integer
* rounding is used to get the best value for baudrateSbr0_12. Actual baudrate equals
* sourceClockFreqHz / 8 / baudrateSbr0_12.
*/
baudrateSbr0_12 = (((sourceClockFreqHz / BOOT_COM_RS232_BAUDRATE) + (8U - 1U)) / 8U) &
LPUART_BAUD_SBR_MASK;
/* OSR=7: Over sampling ratio = 7+1=8.
* SBNS=0: One stop bit.
* BOTHEDGE=0: receiver samples only on rising edge.
* M10=0: Rx and Tx use 7 to 9 bit data characters.
* RESYNCDIS=0: Resync during rec'd data word supported.
* LBKDIE, RXEDGIE=0: interrupts disable.
* TDMAE, RDMAE, TDMAE=0: DMA requests disabled.
* MAEN1, MAEN2, MATCFG=0: Match disabled.
*/
LPUARTx->BAUD = LPUART_BAUD_SBR(baudrateSbr0_12) | LPUART_BAUD_OSR(7);
/* Clear the error/interrupt flags */
LPUARTx->STAT = FEATURE_LPUART_STAT_REG_FLAGS_MASK;
/* Reset all features/interrupts by default */
LPUARTx->CTRL = 0x00000000;
/* Reset match addresses */
LPUARTx->MATCH = 0x00000000;
#if FEATURE_LPUART_HAS_MODEM_SUPPORT
/* Reset IrDA modem features */
LPUARTx->MODIR = 0x00000000;
#endif
#if FEATURE_LPUART_FIFO_SIZE > 0U
/* Reset FIFO feature */
LPUARTx->FIFO = FEATURE_LPUART_FIFO_RESET_MASK;
/* Enable the transmit and receive FIFOs. */
LPUARTx->FIFO |= LPUART_FIFO_TXFE(1) | LPUART_FIFO_RXFE(1);
/* Set the reception water mark to 0 and the transmitter water mark to 1. */
LPUARTx->WATER = LPUART_WATER_TXWATER(1) | LPUART_WATER_RXWATER(0);
#endif
/* Enable transmitter and receiver, no parity, 8 bit char:
* RE=1: Receiver enabled.
* TE=1: Transmitter enabled.
* PE,PT=0: No hw parity generation or checking.
* M7,M,R8T9,R9T8=0: 8-bit data characters.
* DOZEEN=0: LPUART enabled in Doze mode.
* ORIE,NEIE,FEIE,PEIE,TIE,TCIE,RIE,ILIE,MA1IE,MA2IE=0: no IRQ.
* TxDIR=0: TxD pin is input if in single-wire mode.
* TXINV=0: Transmit data not inverted.
* RWU,WAKE=0: normal operation; rcvr not in standby.
* IDLCFG=0: one idle character.
* ILT=0: Idle char bit count starts after start bit.
* SBK=0: Normal transmitter operation - no break char.
* LOOPS,RSRC=0: no loop back.
*/
LPUARTx->CTRL = LPUART_CTRL_RE_MASK | LPUART_CTRL_TE_MASK;
} /*** end of BootComRs232Init ***/
/************************************************************************************//**
** \brief Receives the CONNECT request from the host, which indicates that the
** bootloader should be activated and, if so, activates it.
** \return none.
**
****************************************************************************************/
static void BootComRs232CheckActivationRequest(void)
{
static unsigned char xcpCtoReqPacket[BOOT_COM_RS232_RX_MAX_DATA+1];
static unsigned char xcpCtoRxLength;
static unsigned char xcpCtoRxInProgress = 0;
static unsigned long xcpCtoRxStartTime = 0;
/* start of cto packet received? */
if (xcpCtoRxInProgress == 0)
{
/* store the message length when received */
if (Rs232ReceiveByte(&xcpCtoReqPacket[0]) == 1)
{
/* check that the length has a valid value. it should not be 0 */
if ( (xcpCtoReqPacket[0] > 0) &&
(xcpCtoReqPacket[0] <= BOOT_COM_RS232_RX_MAX_DATA) )
{
/* store the start time */
xcpCtoRxStartTime = TimerGet();
/* indicate that a cto packet is being received */
xcpCtoRxInProgress = 1;
/* reset packet data count */
xcpCtoRxLength = 0;
}
}
}
else
{
/* store the next packet byte */
if (Rs232ReceiveByte(&xcpCtoReqPacket[xcpCtoRxLength+1]) == 1)
{
/* increment the packet data count */
xcpCtoRxLength++;
/* check to see if the entire packet was received */
if (xcpCtoRxLength == xcpCtoReqPacket[0])
{
/* done with cto packet reception */
xcpCtoRxInProgress = 0;
/* check if this was an XCP CONNECT command */
if ((xcpCtoReqPacket[1] == 0xff) && (xcpCtoReqPacket[2] == 0x00))
{
/* connection request received so start the bootloader */
BootActivate();
}
}
}
else
{
/* check packet reception timeout */
if (TimerGet() > (xcpCtoRxStartTime + RS232_CTO_RX_PACKET_TIMEOUT_MS))
{
/* cancel cto packet reception due to timeout. note that this automatically
* discards the already received packet bytes, allowing the host to retry.
*/
xcpCtoRxInProgress = 0;
}
}
}
} /*** end of BootComRs232CheckActivationRequest ***/
/************************************************************************************//**
** \brief Receives a communication interface byte if one is present.
** \param data Pointer to byte where the data is to be stored.
** \return 1 if a byte was received, 0 otherwise.
**
****************************************************************************************/
static unsigned char Rs232ReceiveByte(unsigned char *data)
{
unsigned char result = 0;
/* Check if a new byte was received by means of the RDRF-bit. */
if (((LPUARTx->STAT & LPUART_STAT_RDRF_MASK) >> LPUART_STAT_RDRF_SHIFT) != 0U)
{
/* Retrieve and store the newly received byte. */
*data = LPUARTx->DATA;
/* Update the result. */
result = 1;
}
/* Give the result back to the caller. */
return result;
} /*** end of Rs232ReceiveByte ***/
#endif /* BOOT_COM_RS232_ENABLE > 0 */
#if (BOOT_COM_CAN_ENABLE > 0)
/****************************************************************************************
* C O N T R O L L E R A R E A N E T W O R K I N T E R F A C E
****************************************************************************************/
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/** \brief Timeout for entering/leaving CAN initialization mode in milliseconds. */
#define CAN_INIT_TIMEOUT_MS (250U)
/** \brief Set the peripheral CAN0 base pointer. */
#define CANx (CAN0)
/** \brief Set the PCC index offset for CAN0. */
#define PCC_FlexCANx_INDEX (PCC_FlexCAN0_INDEX)
/** \brief Set the number of message boxes supported by CAN0. */
#define CANx_MAX_MB_NUM (FEATURE_CAN0_MAX_MB_NUM)
/** \brief The mailbox used for receiving the XCP command message. */
#define CAN_RX_MSGBOX_NUM (9U)
/****************************************************************************************
* Type definitions
****************************************************************************************/
/** \brief Structure type for grouping CAN bus timing related information. */
typedef struct t_can_bus_timing
{
unsigned char timeQuanta; /**< Total number of time quanta */
unsigned char propSeg; /**< CAN propagation segment */
unsigned char phaseSeg1; /**< CAN phase segment 1 */
unsigned char phaseSeg2; /**< CAN phase segment 2 */
} tCanBusTiming;
/****************************************************************************************
* Local constant declarations
****************************************************************************************/
/** \brief CAN bit timing table for dynamically calculating the bittiming settings.
* \details According to the CAN protocol 1 bit-time can be made up of between 8..25
* time quanta (TQ). The total TQ in a bit is SYNC + TSEG1 + TSEG2 with SYNC
* always being 1. The sample point is (SYNC + TSEG1) / (SYNC + TSEG1 + TSEG2)
* * 100%. This array contains possible and valid time quanta configurations
* with a sample point between 68..78%. A visual representation of the TQ in
* a bit is:
* | SYNCSEG | TIME1SEG | TIME2SEG |
* Or with an alternative representation:
* | SYNCSEG | PROPSEG | PHASE1SEG | PHASE2SEG |
* With the alternative representation TIME1SEG = PROPSEG + PHASE1SEG.
*
*/
static const tCanBusTiming canTiming[] =
{
/* Time-Quanta | PROPSEG | PSEG1 | PSEG2 | Sample-Point */
/* ---------------------------------------------------- */
{ 8U, 3U, 2U, 2U }, /*1+3+2+1=8 | 3 | 2 | 2 | 75% */
{ 9U, 3U, 3U, 2U }, /* 9 | 3 | 3 | 2 | 78% */
{ 10U, 3U, 3U, 3U }, /* 10 | 3 | 3 | 3 | 70% */
{ 11U, 4U, 3U, 3U }, /* 11 | 4 | 3 | 3 | 73% */
{ 12U, 4U, 4U, 3U }, /* 12 | 4 | 4 | 3 | 75% */
{ 13U, 5U, 4U, 3U }, /* 13 | 5 | 4 | 3 | 77% */
{ 14U, 5U, 4U, 4U }, /* 14 | 5 | 4 | 4 | 71% */
{ 15U, 6U, 4U, 4U }, /* 15 | 6 | 4 | 4 | 73% */
{ 16U, 6U, 5U, 4U }, /* 16 | 6 | 5 | 4 | 75% */
{ 17U, 7U, 5U, 4U }, /* 17 | 7 | 5 | 4 | 76% */
{ 18U, 7U, 5U, 5U }, /* 18 | 7 | 5 | 5 | 72% */
{ 19U, 8U, 5U, 5U }, /* 19 | 8 | 5 | 5 | 74% */
{ 20U, 8U, 6U, 5U }, /* 20 | 8 | 6 | 5 | 75% */
{ 21U, 8U, 7U, 5U }, /* 21 | 8 | 7 | 5 | 76% */
{ 22U, 8U, 7U, 6U }, /* 22 | 8 | 7 | 6 | 73% */
{ 23U, 8U, 8U, 6U }, /* 23 | 8 | 8 | 6 | 74% */
{ 24U, 8U, 8U, 7U }, /* 24 | 8 | 8 | 7 | 71% */
{ 25U, 8U, 8U, 8U } /* 25 | 8 | 8 | 8 | 68% */
};
/****************************************************************************************
* Local data declarations
****************************************************************************************/
/** \brief Dummy variable to store the CAN controller's free running timer value in.
* This is needed at the end of a CAN message reception to unlock the mailbox
* again. If this variable is declared locally within the function, it generates
* an unwanted compiler warning about assigning a value and not using it.
* For this reason this dummy variabled is declare here as a module global.
*/
static volatile unsigned long dummyTimerVal;
/************************************************************************************//**
** \brief Search algorithm to match the desired baudrate to a possible bus
** timing configuration.
** \param baud The desired baudrate in kbps. Valid values are 10..1000.
** \param prescaler Pointer to where the value for the prescaler will be stored.
** \param busTimingCfg Pointer to where the bus timing values will be stored.
** \return 1 if the CAN bustiming register values were found, 0 otherwise.
**
****************************************************************************************/
static unsigned char CanGetSpeedConfig(unsigned short baud, unsigned short * prescaler,
tCanBusTiming * busTimingCfg)
{
unsigned char cnt;
unsigned long canClockFreqkHz;
unsigned long div2RegValue;
unsigned char const div2DividerLookup[] =
{
0U, /* 0b000. Output disabled. */
1U, /* 0b001. Divide by 1. */
2U, /* 0b010. Divide by 2. */
4U, /* 0b011. Divide by 4. */
8U, /* 0b100. Divide by 8. */
16U, /* 0b101. Divide by 16. */
32U, /* 0b110. Divide by 32. */
64U, /* 0b111. Divide by 64. */
};
/* Obtain the DIV2 divider value of the SOSC_CLK. */
div2RegValue = (SCG->SOSCDIV & SCG_SOSCDIV_SOSCDIV2_MASK) >> SCG_SOSCDIV_SOSCDIV2_SHIFT;
/* Check if the DIV2 register value for SOSC is 0. In this case SOSCDIV2_CLK is
* currently disabled.
*/
if (div2RegValue == 0U)
{
/* Configure the DIV2 for a default divide by 1 to make sure the SOSCDIV2_CLK is
* actually enabled.
*/
div2RegValue = 1U;
SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV2(div2RegValue);
}
/* Determine the SOSC clock frequency. */
canClockFreqkHz = BOOT_CPU_XTAL_SPEED_KHZ;
/* Now process the configured DIV2 divider factor to get the actual frequency of the
* CAN peripheral source clock.
*/
canClockFreqkHz /= div2DividerLookup[div2RegValue];
/* Loop through all possible time quanta configurations to find a match. */
for (cnt=0; cnt < sizeof(canTiming)/sizeof(canTiming[0]); cnt++)
{
if ((canClockFreqkHz % (baud * canTiming[cnt].timeQuanta)) == 0U)
{
/* Compute the prescaler that goes with this TQ configuration. */
*prescaler = canClockFreqkHz/(baud * canTiming[cnt].timeQuanta);
/* Make sure the prescaler is valid. */
if ((*prescaler > 0U) && (*prescaler <= 256U))
{
/* Store the bustiming configuration. */
*busTimingCfg = canTiming[cnt];
/* Found a good bus timing configuration. */
return 1U;
}
}
}
/* Could not find a good bus timing configuration. */
return 0U;
} /*** end of CanGetSpeedConfig ***/
/************************************************************************************//**
** \brief Places the CAN controller in freeze mode. Note that the CAN controller
** can only be placed in freeze mode, if it is actually enabled.
** \return none.
**
****************************************************************************************/
static void CanFreezeModeEnter(void)
{
unsigned long timeout;
/* Request to enter freeze mode. */
CANx->MCR = (CANx->MCR & ~CAN_MCR_FRZ_MASK) | CAN_MCR_FRZ(1U);
CANx->MCR = (CANx->MCR & ~CAN_MCR_HALT_MASK) | CAN_MCR_HALT(1U);
/* Set timeout time for entering freeze mode. */
timeout = TimerGet() + CAN_INIT_TIMEOUT_MS;
/* Wait for freeze mode acknowledgement. */
while (((CANx->MCR & CAN_MCR_FRZACK_MASK)) == 0U)
{
/* Break loop upon timeout. This would indicate a hardware failure. */
if (TimerGet() > timeout)
{
break;
}
}
} /*** end of CanFreezeModeEnter ***/
/************************************************************************************//**
** \brief Leaves the CAN controller's freeze mode. Note that this operation can
** only be done, if it is actually enabled.
** \return none.
**
****************************************************************************************/
static void CanFreezeModeExit(void)
{
unsigned long timeout;
/* Request to leave freeze mode. */
CANx->MCR = (CANx->MCR & ~CAN_MCR_FRZ_MASK) | CAN_MCR_FRZ(0U);
CANx->MCR = (CANx->MCR & ~CAN_MCR_HALT_MASK) | CAN_MCR_HALT(0U);
/* Set timeout time for leaving freeze mode. */
timeout = TimerGet() + CAN_INIT_TIMEOUT_MS;
/* Wait for non freeze mode acknowledgement. */
while (((CANx->MCR & CAN_MCR_FRZACK_MASK)) != 0U)
{
/* Break loop upon timeout. This would indicate a hardware failure. */
if (TimerGet() > timeout)
{
break;
}
}
} /*** end of CanFreezeModeExit ***/
/************************************************************************************//**
** \brief Places the CAN controller in disabled mode.
** \return none.
**
****************************************************************************************/
static void CanDisabledModeEnter(void)
{
unsigned long timeout;
/* Only continue if the CAN controller is currently enabled. */
if ((CANx->MCR & CAN_MCR_MDIS_MASK) == 0U)
{
/* Request disabled mode. */
CANx->MCR = (CANx->MCR & ~CAN_MCR_MDIS_MASK) | CAN_MCR_MDIS(1U);
/* Set timeout time for entering disabled mode. */
timeout = TimerGet() + CAN_INIT_TIMEOUT_MS;
/* Wait for disabled mode acknowledgement. */
while (((CANx->MCR & CAN_MCR_LPMACK_MASK)) == 0U)
{
/* Break loop upon timeout. This would indicate a hardware failure. */
if (TimerGet() > timeout)
{
break;
}
}
}
} /*** end of CanDisabledModeEnter ***/
/************************************************************************************//**
** \brief Places the CAN controller in enabled mode.
** \return none.
**
****************************************************************************************/
static void CanDisabledModeExit(void)
{
unsigned long timeout;
/* Only continue if the CAN controller is currently disabled. */
if ((CANx->MCR & CAN_MCR_MDIS_MASK) != 0U)
{
/* Request enabled mode. */
CANx->MCR = (CANx->MCR & ~CAN_MCR_MDIS_MASK) | CAN_MCR_MDIS(0U);
/* Set timeout time for leaving disabled mode. */
timeout = TimerGet() + CAN_INIT_TIMEOUT_MS;
/* Wait for disabled mode acknowledgement. */
while (((CANx->MCR & CAN_MCR_LPMACK_MASK)) != 0U)
{
/* Break loop upon timeout. This would indicate a hardware failure. */
if (TimerGet() > timeout)
{
break;
}
}
}
} /*** end of CanDisabledModeExit ***/
/************************************************************************************//**
** \brief Initializes the CAN communication interface.
** \return none.
**
****************************************************************************************/
static void BootComCanInit(void)
{
unsigned short prescaler = 0;
tCanBusTiming timingCfg = { 0 };
unsigned char rjw;
unsigned short idx;
unsigned long timeout;
unsigned long rxMsgId = BOOT_COM_CAN_RX_MSG_ID;
/* Enable the CAN peripheral clock. */
PCC->PCCn[PCC_FlexCANx_INDEX] |= PCC_PCCn_CGC_MASK;
/* The source clock needs to be configured first. For this the CAN controller must be
* in disabled mode, but that can only be entered after first entering freeze mode,
* which in turn can only be in enabled mode. So first enable the module, then goto
* freeze mode and finally enter disabled mode.
*/
CanDisabledModeExit();
CanFreezeModeEnter();
CanDisabledModeEnter();
/* Configure SOSCDIV2 as the source clock. This assumes that an external oscillator
* is available, which is typically the case to meet the clock tolerance requirements
* of the CAN 2.0B secification.
*/
CANx->CTRL1 &= ~CAN_CTRL1_CLKSRC_MASK;
/* Leave disabled mode. */
CanDisabledModeExit();
/* Make sure freeze mode is active to be able to initialize the CAN controller. */
CanFreezeModeEnter();
/* Obtain bittiming configuration information. */
(void)CanGetSpeedConfig(BOOT_COM_CAN_BAUDRATE/1000, &prescaler, &timingCfg);
/* Reset the current bittiming configuration. */
CANx->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_PROPSEG_MASK |
CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK | CAN_CTRL1_RJW_MASK |
CAN_CTRL1_SMP_MASK);
/* Configure the baudrate prescaler. */
CANx->CTRL1 |= CAN_CTRL1_PRESDIV(prescaler - 1U);
/* Configure the propagation segment. */
CANx->CTRL1 |= CAN_CTRL1_PROPSEG(timingCfg.propSeg - 1U);
/* Configure the phase segments. */
CANx->CTRL1 |= CAN_CTRL1_PSEG1(timingCfg.phaseSeg1 - 1U);
CANx->CTRL1 |= CAN_CTRL1_PSEG2(timingCfg.phaseSeg2 - 1U);
/* The resynchronization jump width (RJW) can be 1 - 4 TQ, yet should never be larger
* than pseg1. Configure the longest possible value for RJW.
*/
rjw = (timingCfg.phaseSeg1 < 4) ? timingCfg.phaseSeg1 : 4;
CANx->CTRL1 |= CAN_CTRL1_RJW(rjw - 1U);
/* All the entries in canTiming[] have a PSEG1 >= 2, so three samples can be used to
* determine the value of the received bit, instead of the default one.
*/
CANx->CTRL1 |= CAN_CTRL1_SMP(1U);
/* Clear the message box RAM. Each message box covers 4 words (1 word = 32-bits. */
for (idx = 0; idx < (CANx_MAX_MB_NUM * 4U); idx++)
{
CANx->RAMn[idx] = 0U;
}
/* Clear the reception mask register for each message box. */
for (idx = 0; idx < CANx_MAX_MB_NUM; idx++)
{
CANx->RXIMR[idx] = 0U;
}
/* Configure the maximum number of message boxes. */
CANx->MCR = (CANx->MCR & ~CAN_MCR_MAXMB_MASK) | CAN_MCR_MAXMB(CANx_MAX_MB_NUM - 1U);
/* Disable the self reception feature. */
CANx->MCR = (CANx->MCR & ~CAN_MCR_SRXDIS_MASK) | CAN_MCR_SRXDIS(1U);
/* Enable individual reception masking. This disables the legacy support for the
* global reception mask and the mailbox 14/15 individual reception mask.
*/
CANx->MCR = (CANx->MCR & ~CAN_MCR_IRMQ_MASK) | CAN_MCR_IRMQ(1U);
/* Disable the reception FIFO. This driver only needs to receive one CAN message
* identifier. It is sufficient to use just one dedicated mailbox for this.
*/
CANx->MCR &= ~CAN_MCR_RFEN_MASK;
/* Configure the mask of the invididual message reception mailbox to check all ID bits
* and also the IDE bit.
*/
CANx->RXIMR[CAN_RX_MSGBOX_NUM] = 0x40000000U | 0x1FFFFFFFU;
/* Configure the reception mailbox to receive just the CAN message configured with
* BOOT_COM_CAN_RX_MSG_ID.
* EDL, BRS, ESI=0: CANFD not used.
* CODE=0b0100: mailbox set to active and empty.
* IDE=0: 11-bit CAN identifier.
* SRR, RTR, TIME STAMP=0: not applicable.
*/
CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 0U] = 0x04000000;
/* Store the message identifier to receive in the mailbox RAM. */
if ((rxMsgId & 0x80000000U) != 0U)
{
/* It is a 29-bit extended CAN identifier. */
rxMsgId &= ~0x80000000U;
/* Set the IDE bit to configure the message for a 29-bit identifier. */
CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 0U] |= CAN_WMBn_CS_IDE_MASK;
/* Store the 29-bit CAN identifier. */
CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 1U] = CAN_WMBn_ID_ID(rxMsgId);
}
else
{
/* Store the 11-bit CAN identifier. */
CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 1U] = CAN_WMBn_ID_ID(rxMsgId << 18U);
}
/* Disable all message box interrupts. */
CANx->IMASK1 = 0U;
/* Clear all mesasge box interrupt flags. */
CANx->IFLAG1 = CAN_IMASK1_BUF31TO0M_MASK;
/* Clear all error interrupt flags */
CANx->ESR1 = CAN_ESR1_ERRINT_MASK | CAN_ESR1_BOFFINT_MASK | CAN_ESR1_RWRNINT_MASK |
CAN_ESR1_TWRNINT_MASK | CAN_ESR1_BOFFDONEINT_MASK |
CAN_ESR1_ERRINT_FAST_MASK | CAN_ESR1_ERROVR_MASK;
/* Switch to normal user mode. */
CANx->MCR &= ~CAN_MCR_SUPV_MASK;
CANx->CTRL1 &= ~(CAN_CTRL1_LOM_MASK | CAN_CTRL1_LPB_MASK);
/* Exit freeze mode. */
CanFreezeModeExit();
/* Set timeout time for entering normal user mode. */
timeout = TimerGet() + CAN_INIT_TIMEOUT_MS;
/* Wait for normal user mode acknowledgement. */
while (((CANx->MCR & CAN_MCR_NOTRDY_MASK)) != 0U)
{
/* Break loop upon timeout. This would indicate a hardware failure. */
if (TimerGet() > timeout)
{
break;
}
}
} /*** end of BootComCanInit ***/
/************************************************************************************//**
** \brief Receives the CONNECT request from the host, which indicates that the
** bootloader should be activated and, if so, activates it.
** \return none.
**
****************************************************************************************/
static void BootComCanCheckActivationRequest(void)
{
unsigned char * pMsgBoxData;
unsigned char byteIdx;
unsigned char rxMsgData[8];
unsigned char rxMsgLen;
/* Check if a message was received in the individual mailbox configured to receive
* the BOOT_COM_CAN_RX_MSG_ID message.
*/
if ((CANx->IFLAG1 & (1U << CAN_RX_MSGBOX_NUM)) != 0U)
{
/* Note that there is no need to verify the identifier of the CAN message because the
* mailbox is configured to only receive the BOOT_COM_CAN_TX_MSG_ID message. Start
* by reading out the DLC of the newly received CAN message.
*/
rxMsgLen = (CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 0U] & CAN_WMBn_CS_DLC_MASK) >> CAN_WMBn_CS_DLC_SHIFT;
/* Read the data bytes of the CAN message from the mailbox RAM. */
pMsgBoxData = (unsigned char *)(&CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 2U]);
for (byteIdx = 0; byteIdx < rxMsgLen; byteIdx++)
{
rxMsgData[byteIdx] = pMsgBoxData[((byteIdx) & ~3U) + (3U - ((byteIdx) & 3U))];
}
/* Clear the mailbox interrupt flag by writing a 1 to the corresponding box. */
CANx->IFLAG1 = (1U << CAN_RX_MSGBOX_NUM);
/* Read the free running timer to unlock the mailbox. */
dummyTimerVal = CANx->TIMER;
/* check if this was an XCP CONNECT command */
if ((rxMsgData[0] == 0xff) && (rxMsgLen == 2))
{
/* connection request received so start the bootloader */
BootActivate();
}
}
} /*** end of BootComCanCheckActivationRequest ***/
#endif /* BOOT_COM_CAN_ENABLE > 0 */
/*********************************** end of boot.c *************************************/

40
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/boot.h Normal file
View File

@ -0,0 +1,40 @@
/************************************************************************************//**
* \file Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/boot.h
* \brief Demo program bootloader interface header file.
* \ingroup Prog_ARMCM0_S32K14_S32K118EVB_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef BOOT_H
#define BOOT_H
/****************************************************************************************
* Function prototypes
****************************************************************************************/
void BootComInit(void);
void BootComCheckActivationRequest(void);
void BootActivate(void);
#endif /* BOOT_H */
/*********************************** end of boot.h *************************************/

42
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/header.h Normal file
View File

@ -0,0 +1,42 @@
/************************************************************************************//**
* \file Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/header.h
* \brief Generic header file.
* \ingroup Prog_ARMCM0_S32K14_S32K118EVB_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef HEADER_H
#define HEADER_H
/****************************************************************************************
* Include files
****************************************************************************************/
#include "../Boot/blt_conf.h" /* bootloader configuration */
#include "boot.h" /* bootloader interface driver */
#include "led.h" /* LED driver */
#include "timer.h" /* Timer driver */
#include "device_registers.h" /* Device registers */
#include "system_S32K118.h" /* Device sconfiguration */
#endif /* HEADER_H */
/*********************************** end of header.h ***********************************/

96
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/led.c Normal file
View File

@ -0,0 +1,96 @@
/************************************************************************************//**
* \file Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/led.c
* \brief LED driver source file.
* \ingroup Prog_ARMCM0_S32K14_S32K118EVB_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "header.h" /* generic header */
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/** \brief Toggle interval time in milliseconds. */
#define LED_TOGGLE_MS (500U)
/************************************************************************************//**
** \brief Initializes the LED.
** \return none.
**
****************************************************************************************/
void LedInit(void)
{
/* LED GPIO pin configuration. PE8 = GPIO, MUX = ALT1. */
PORTE->PCR[8] = PORT_PCR_MUX(1);
/* Configure Port E pin 8 GPIO as digital output. */
PTE->PDDR |= GPIO_PDDR_PDD(1 << 8U);
/* Turn the LED off on Port E pin 8. */
PTE->PCOR |= GPIO_PSOR_PTSO(1 << 8U);
} /*** end of LedInit ***/
/************************************************************************************//**
** \brief Toggles the LED at a fixed time interval.
** \return none.
**
****************************************************************************************/
void LedToggle(void)
{
static unsigned char led_toggle_state = 0;
static unsigned long timer_counter_last = 0;
unsigned long timer_counter_now;
/* Check if toggle interval time passed. */
timer_counter_now = TimerGet();
if ( (timer_counter_now - timer_counter_last) < LED_TOGGLE_MS)
{
/* Not yet time to toggle. */
return;
}
/* Determine toggle action. */
if (led_toggle_state == 0)
{
led_toggle_state = 1;
/* Turn the LED on. */
PTE->PSOR |= GPIO_PSOR_PTSO(1 << 8U);
}
else
{
led_toggle_state = 0;
/* Turn the LED off. */
PTE->PCOR |= GPIO_PSOR_PTSO(1 << 8U);
}
/* Store toggle time to determine next toggle interval. */
timer_counter_last = timer_counter_now;
} /*** end of LedToggle ***/
/*********************************** end of led.c **************************************/

39
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/led.h Normal file
View File

@ -0,0 +1,39 @@
/************************************************************************************//**
* \file Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/led.h
* \brief LED driver header file.
* \ingroup Prog_ARMCM0_S32K14_S32K118EVB_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef LED_H
#define LED_H
/****************************************************************************************
* Function prototypes
****************************************************************************************/
void LedInit(void);
void LedToggle(void);
#endif /* LED_H */
/*********************************** end of led.h **************************************/

10438
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/lib/S32K118.h Normal file
View File

File diff suppressed because it is too large Load Diff

1302
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/lib/S32K118_features.h Normal file
View File

File diff suppressed because it is too large Load Diff

84
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/lib/devassert.h Normal file
View File

@ -0,0 +1,84 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef DEVASSERT_H
#define DEVASSERT_H
#include <stdbool.h>
/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 2.5, global macro not referenced.
* The macro is defined to be used by drivers to validate input parameters and can be disabled.
*
* @section [global]
* Violates MISRA 2012 Advisory Directive 4.9, Function-like macro defined.
* The macros are used to validate input parameters to driver functions.
*
*/
/**
\page Error_detection_and_reporting Error detection and reporting
S32 SDK drivers can use a mechanism to validate data coming from upper software layers (application code) by performing
a number of checks on input parameters' range or other invariants that can be statically checked (not dependent on
runtime conditions). A failed validation is indicative of a software bug in application code, therefore it is important
to use this mechanism during development.
The validation is performed by using DEV_ASSERT macro.
A default implementation of this macro is provided in this file. However, application developers can provide their own
implementation in a custom file. This requires defining the CUSTOM_DEVASSERT symbol with the specific file name in the
project configuration (for example: -DCUSTOM_DEVASSERT="custom_devassert.h")
The default implementation accommodates two behaviors, based on DEV_ERROR_DETECT symbol:
- When DEV_ERROR_DETECT symbol is defined in the project configuration (for example: -DDEV_ERROR_DETECT), the validation
performed by the DEV_ASSERT macro is enabled, and a failed validation triggers a software breakpoint and further execution is
prevented (application spins in an infinite loop)
This configuration is recommended for development environments, as it prevents further execution and allows investigating
potential problems from the point of error detection.
- When DEV_ERROR_DETECT symbol is not defined, the DEV_ASSERT macro is implemented as no-op, therefore disabling all validations.
This configuration can be used to eliminate the overhead of development-time checks.
It is the application developer's responsibility to decide the error detection strategy for production code: one can opt to
disable development-time checking altogether (by not defining DEV_ERROR_DETECT symbol), or one can opt to keep the checks
in place and implement a recovery mechanism in case of a failed validation, by defining CUSTOM_DEVASSERT to point
to the file containing the custom implementation.
*/
#if defined (CUSTOM_DEVASSERT)
/* If the CUSTOM_DEVASSERT symbol is defined, then add the custom implementation */
#include CUSTOM_DEVASSERT
#elif defined (DEV_ERROR_DETECT)
/* Implement default assert macro */
static inline void DevAssert(volatile bool x)
{
if(x) { } else { BKPT_ASM; for(;;) {} }
}
#define DEV_ASSERT(x) DevAssert(x)
#else
/* Assert macro does nothing */
#define DEV_ASSERT(x) ((void)0)
#endif
#endif /* DEVASSERT_H */
/*******************************************************************************
* EOF
******************************************************************************/

67
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/lib/device_registers.h Normal file
View File

@ -0,0 +1,67 @@
/*
** ###################################################################
** Abstract:
** Common include file for CMSIS register access layer headers.
**
** Copyright (c) 2015 Freescale Semiconductor, Inc.
** Copyright 2016-2017 NXP
** All rights reserved.
**
** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
** THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.nxp.com
** mail: support@nxp.com
** ###################################################################
*/
#ifndef DEVICE_REGISTERS_H
#define DEVICE_REGISTERS_H
/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 2.5, global macro not referenced.
* The macro defines the device currently in use and may be used by components for specific checks.
*
*/
/*
* Include the cpu specific register header files.
*
* The CPU macro should be declared in the project or makefile.
*/
#if defined(CPU_S32K118)
#define S32K11x_SERIES
/* Specific core definitions */
#include "s32_core_cm0.h"
/* Register definitions */
#include "S32K118.h"
/* CPU specific feature definitions */
#include "S32K118_features.h"
#else
#error "No valid CPU defined!"
#endif
#include "devassert.h"
#endif /* DEVICE_REGISTERS_H */
/*******************************************************************************
* EOF
******************************************************************************/

198
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/lib/s32_core_cm0.h Normal file
View File

@ -0,0 +1,198 @@
/*
* Copyright (c) 2015-2016 Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/*!
* @file s32_core_cm0.h
*
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Directive 4.9, Function-like macro
* Function-like macros are used instead of inline functions in order to ensure
* that the performance will not be decreased if the functions will not be
* inlined by the compiler.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 2.5, Global macro not referenced.
* The macros defined are used only on some of the drivers, so this might be reported
* when the analysis is made only on one driver.
*/
/*
* Tool Chains:
* GNUC flag is defined also by ARM compiler - it shows the current major version of the compatible GCC version
* __GNUC__ : GNU Compiler Collection
* __ghs__ : Green Hills ARM Compiler
* __ICCARM__ : IAR ARM Compiler
* __DCC__ : Wind River Diab Compiler
* __ARMCC_VERSION : ARM Compiler
*/
#if !defined (CORE_CM0_H)
#define CORE_CM0_H
#ifdef __cplusplus
extern "C" {
#endif
/** \brief BKPT_ASM
*
* Macro to be used to trigger an debug interrupt
*/
#if defined ( __DCC__ )
#define BKPT_ASM __asm ("BKPT 0\n\t")
#else
#define BKPT_ASM __asm ("BKPT #0\n\t")
#endif
/** \brief Enable interrupts
*/
#if defined (__GNUC__)
#define ENABLE_INTERRUPTS() __asm volatile ("cpsie i" : : : "memory");
#elif defined ( __DCC__ )
#define ENABLE_INTERRUPTS() __asm (".short 0xb662");
#else
#define ENABLE_INTERRUPTS() __asm("cpsie i")
#endif
/** \brief Disable interrupts
*/
#if defined (__GNUC__)
#define DISABLE_INTERRUPTS() __asm volatile ("cpsid i" : : : "memory");
#elif defined ( __DCC__ )
#define DISABLE_INTERRUPTS() __asm (".short 0xb672");
#else
#define DISABLE_INTERRUPTS() __asm("cpsid i")
#endif
/** \brief Enter low-power standby state
* WFI (Wait For Interrupt) makes the processor suspend execution (Clock is stopped) until an IRQ interrupts.
*/
#if defined (__GNUC__)
#define STANDBY() __asm volatile ("wfi")
#elif defined ( __DCC__ )
#define STANDBY() __asm (".short 0xbf30");
#else
#define STANDBY() __asm ("wfi")
#endif
/** \brief No-op
*/
#define NOP() __asm volatile ("nop")
/** \brief Reverse byte order in a word.
* ARM Documentation Cortex-M0 Devices Generic User Guide
* Accordingly to 3.5.7. REV, REV16, and REVSH
* Restriction "This function requires low registers R0-R7 register"
*/
#if defined (__GNUC__) || defined (__ICCARM__) || defined (__ARMCC_VERSION)
#define REV_BYTES_32(a, b) __asm volatile ("rev %0, %1" : "=l" (b) : "l" (a))
#elif defined (__ghs__)
#define REV_BYTES_32(a, b) __asm volatile ("rev %0, %1" : "=r" (b) : "r" (a))
#else
#define REV_BYTES_32(a, b) (b = ((a & 0xFF000000U) >> 24U) | ((a & 0xFF0000U) >> 8U) \
| ((a & 0xFF00U) << 8U) | ((a & 0xFFU) << 24U))
#endif
/** \brief Reverse byte order in each halfword independently.
* ARM Documentation Cortex-M0 Devices Generic User Guide
* Accordingly to 3.5.7. REV, REV16, and REVSH
* Restriction "This function requires low registers R0-R7 register"
*/
#if defined (__GNUC__) || defined (__ICCARM__) || defined (__ARMCC_VERSION)
#define REV_BYTES_16(a, b) __asm volatile ("rev16 %0, %1" : "=l" (b) : "l" (a))
#elif defined (__ghs__)
#define REV_BYTES_16(a, b) __asm volatile ("rev16 %0, %1" : "=r" (b) : "r" (a))
#else
#define REV_BYTES_16(a, b) (b = ((a & 0xFF000000U) >> 8U) | ((a & 0xFF0000U) << 8U) \
| ((a & 0xFF00U) >> 8U) | ((a & 0xFFU) << 8U))
#endif
/** \brief Places a function in RAM.
*/
#if defined ( __GNUC__ ) || defined (__ARMCC_VERSION)
#define START_FUNCTION_DECLARATION_RAMSECTION
#define END_FUNCTION_DECLARATION_RAMSECTION __attribute__((section (".code_ram")));
#elif defined ( __ghs__ )
#define START_FUNCTION_DECLARATION_RAMSECTION _Pragma("ghs callmode=far")
#define END_FUNCTION_DECLARATION_RAMSECTION __attribute__((section (".code_ram")));\
_Pragma("ghs callmode=default")
#elif defined ( __ICCARM__ )
#define START_FUNCTION_DECLARATION_RAMSECTION __ramfunc
#define END_FUNCTION_DECLARATION_RAMSECTION ;
#elif defined ( __DCC__ )
#define START_FUNCTION_DECLARATION_RAMSECTION _Pragma("section CODE \".code_ram\" \"\" far-absolute") \
_Pragma("use_section CODE")
#define END_FUNCTION_DECLARATION_RAMSECTION ; \
_Pragma("section CODE \".text\"")
#else
/* Keep compatibility with software analysis tools */
#define START_FUNCTION_DECLARATION_RAMSECTION
#define END_FUNCTION_DECLARATION_RAMSECTION ;
#endif
/* For GCC, IAR, GHS, Diab and ARMC there is no need to specify the section when
defining a function, it is enough to specify it at the declaration. This
also enables compatibility with software analysis tools. */
#define START_FUNCTION_DEFINITION_RAMSECTION
#define END_FUNCTION_DEFINITION_RAMSECTION
#if defined (__ICCARM__)
#define DISABLE_CHECK_RAMSECTION_FUNCTION_CALL _Pragma("diag_suppress=Ta022")
#define ENABLE_CHECK_RAMSECTION_FUNCTION_CALL _Pragma("diag_default=Ta022")
#else
#define DISABLE_CHECK_RAMSECTION_FUNCTION_CALL
#define ENABLE_CHECK_RAMSECTION_FUNCTION_CALL
#endif
/** \brief Get Core ID
*
* GET_CORE_ID returns the processor identification number for cm0
*/
#define GET_CORE_ID() 0U
/** \brief Data alignment.
*/
#if defined ( __GNUC__ ) || defined ( __ghs__ ) || defined ( __DCC__ ) || defined (__ARMCC_VERSION)
#define ALIGNED(x) __attribute__((aligned(x)))
#elif defined ( __ICCARM__ )
#define stringify(s) tostring(s)
#define tostring(s) #s
#define ALIGNED(x) _Pragma(stringify(data_alignment=x))
#else
/* Keep compatibility with software analysis tools */
#define ALIGNED(x)
#endif
/** \brief Endianness.
*/
#define CORE_LITTLE_ENDIAN
#ifdef __cplusplus
}
#endif
#endif /* CORE_CM0_H */
/*******************************************************************************
* EOF
******************************************************************************/

176
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/lib/system_S32K118.c Normal file
View File

@ -0,0 +1,176 @@
/*
* Copyright 2017-2018 NXP
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block
* scope if its identifier only appears in a single function.
* An object with static storage duration declared at block scope cannot be
* accessed directly from outside the block.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed
* between a pointer to object and an integer type.
* The cast is required to initialize a pointer with an unsigned int define,
* representing an address.
*
* @section [global]
* Violates MISRA 2012 Required Rule 11.6, A cast shall not be performed
* between pointer to void and an arithmetic type.
* The cast is required to initialize a pointer with an unsigned int define,
* representing an address.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 8.7, External could be made static.
* Function is defined for usage by application code.
*
*/
#include "device_registers.h"
#include "system_S32K118.h"
#include "stdbool.h"
/* ----------------------------------------------------------------------------
-- Core clock
---------------------------------------------------------------------------- */
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
/*FUNCTION**********************************************************************
*
* Function Name : SystemInit
* Description : This function disables the watchdog, enables FPU
* and the power mode protection if the corresponding feature macro
* is enabled. SystemInit is called from startup_device file.
*
* Implements : SystemInit_Activity
*END**************************************************************************/
void SystemInit(void)
{
/**************************************************************************/
/* WDOG DISABLE*/
/**************************************************************************/
#if (DISABLE_WDOG)
/* Write of the WDOG unlock key to CNT register, must be done in order to allow any modifications*/
WDOG->CNT = (uint32_t ) FEATURE_WDOG_UNLOCK_VALUE;
/* The dummy read is used in order to make sure that the WDOG registers will be configured only
* after the write of the unlock value was completed. */
(void)WDOG->CNT;
/* Initial write of WDOG configuration register:
* enables support for 32-bit refresh/unlock command write words,
* clock select from LPO, update enable, watchdog disabled */
WDOG->CS = (uint32_t ) ( (1UL << WDOG_CS_CMD32EN_SHIFT) |
(FEATURE_WDOG_CLK_FROM_LPO << WDOG_CS_CLK_SHIFT) |
(0U << WDOG_CS_EN_SHIFT) |
(1U << WDOG_CS_UPDATE_SHIFT) );
/* Configure timeout */
WDOG->TOVAL = (uint32_t )0xFFFF;
#endif /* (DISABLE_WDOG) */
}
/*FUNCTION**********************************************************************
*
* Function Name : SystemCoreClockUpdate
* Description : This function must be called whenever the core clock is changed
* during program execution. It evaluates the clock register settings and calculates
* the current core clock.
*
* Implements : SystemCoreClockUpdate_Activity
*END**************************************************************************/
void SystemCoreClockUpdate(void)
{
uint32_t SCGOUTClock = 0U; /* Variable to store output clock frequency of the SCG module */
uint32_t regValue; /* Temporary variable */
uint32_t divider;
bool validSystemClockSource = true;
divider = ((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1U;
switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT)
{
case 0x1:
/* System OSC */
SCGOUTClock = CPU_XTAL_CLK_HZ;
break;
case 0x2:
/* Slow IRC */
regValue = (SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT;
if (regValue != 0UL)
{
SCGOUTClock = FEATURE_SCG_SIRC_HIGH_RANGE_FREQ;
}
else
{
validSystemClockSource = false;
}
break;
case 0x3:
/* Fast IRC */
regValue = (SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT;
if (regValue == 0x0UL)
{
SCGOUTClock = FEATURE_SCG_FIRC_FREQ0;
}
else
{
validSystemClockSource = false;
}
break;
default:
validSystemClockSource = false;
break;
}
if (validSystemClockSource == true)
{
SystemCoreClock = (SCGOUTClock / divider);
}
}
/*FUNCTION**********************************************************************
*
* Function Name : SystemSoftwareReset
* Description : This function is used to initiate a system reset
*
* Implements : SystemSoftwareReset_Activity
*END**************************************************************************/
void SystemSoftwareReset(void)
{
uint32_t regValue;
/* Read Application Interrupt and Reset Control Register */
regValue = S32_SCB->AIRCR;
/* Clear register key */
regValue &= ~( S32_SCB_AIRCR_VECTKEY_MASK);
/* Configure System reset request bit and Register Key */
regValue |= S32_SCB_AIRCR_VECTKEY(FEATURE_SCB_VECTKEY);
regValue |= S32_SCB_AIRCR_SYSRESETREQ(0x1u);
/* Write computed register value */
S32_SCB->AIRCR = regValue;
}
/*******************************************************************************
* EOF
******************************************************************************/

105
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/lib/system_S32K118.h Normal file
View File

@ -0,0 +1,105 @@
/*
* Copyright 2017-2018 NXP
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
/*! @addtogroup soc_support_S32K118*/
/*! @{*/
/*!
* @file system_S32K118.h
* @brief Device specific configuration file for S32K118
*/
#ifndef SYSTEM_S32K118_H_
#define SYSTEM_S32K118_H_ /**< Symbol preventing repeated inclusion */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/******************************************************************************
* CPU Settings.
*****************************************************************************/
/* Watchdog disable */
#ifndef DISABLE_WDOG
#define DISABLE_WDOG 1
#endif
/* Value of the external crystal or oscillator clock frequency in Hz */
#ifndef CPU_XTAL_CLK_HZ
#define CPU_XTAL_CLK_HZ 8000000u
#endif
/* Value of the fast internal oscillator clock frequency in Hz */
#ifndef CPU_INT_FAST_CLK_HZ
#define CPU_INT_FAST_CLK_HZ 48000000u
#endif
/* Default System clock value */
#ifndef DEFAULT_SYSTEM_CLOCK
#define DEFAULT_SYSTEM_CLOCK 48000000u
#endif
/**
* @brief System clock frequency (core clock)
*
* The system clock frequency supplied to the SysTick timer and the processor
* core clock. This variable can be used by the user application to setup the
* SysTick timer or configure other parameters. It may also be used by debugger to
* query the frequency of the debug timer or configure the trace clock speed
* SystemCoreClock is initialized with a correct predefined value.
*/
extern uint32_t SystemCoreClock;
/**
* @brief Setup the SoC.
*
* This function disables the watchdog.
* if the corresponding feature macro is enabled.
* SystemInit is called from startup_device file.
*/
void SystemInit(void);
/**
* @brief Updates the SystemCoreClock variable.
*
* It must be called whenever the core clock is changed during program
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
* the current core clock.
* This function must be called when user does not want to use clock manager component.
* If clock manager is used, the CLOCK_SYS_GetFreq function must be used with CORE_CLOCK
* parameter.
*
*/
void SystemCoreClockUpdate(void);
/**
* @brief Initiates a system reset.
*
* This function is used to initiate a system reset
*/
void SystemSoftwareReset(void);
#ifdef __cplusplus
}
#endif
/*! @}*/
#endif /* #if !defined(SYSTEM_S32K118_H_) */

187
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/main.c Normal file
View File

@ -0,0 +1,187 @@
/************************************************************************************//**
* \file Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/main.c
* \brief Demo program application source file.
* \ingroup Prog_ARMCM0_S32K14_S32K118EVB_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "header.h" /* generic header */
/****************************************************************************************
* Function prototypes
****************************************************************************************/
static void Init(void);
static void SystemClockConfig(void);
/************************************************************************************//**
** \brief This is the entry point for the bootloader application and is called
** by the reset interrupt vector after the C-startup routines executed.
** \return Program return code.
**
****************************************************************************************/
int main(void)
{
/* Initialize the microcontroller. */
Init();
/* Initialize the bootloader interface */
BootComInit();
/* Start the infinite program loop. */
while (1)
{
/* Toggle LED with a fixed frequency. */
LedToggle();
/* Check for bootloader activation request */
BootComCheckActivationRequest();
}
/* Program should never get here. */
return 0;
} /*** end of main ***/
/************************************************************************************//**
** \brief Initializes the microcontroller.
** \return none.
**
****************************************************************************************/
static void Init(void)
{
/* Configure the system clock. */
SystemClockConfig();
/* Enable the peripheral clock for the ports that are used. */
PCC->PCCn[PCC_PORTB_INDEX] |= PCC_PCCn_CGC_MASK;
PCC->PCCn[PCC_PORTE_INDEX] |= PCC_PCCn_CGC_MASK;
#if (BOOT_COM_RS232_ENABLE > 0)
/* UART RX GPIO pin configuration. PB0 = UART0 RX, MUX = ALT2. */
PORTB->PCR[0] |= PORT_PCR_MUX(2);
/* UART TX GPIO pin configuration. PB1 = UART0 TX, MUX = ALT2. */
PORTB->PCR[1] |= PORT_PCR_MUX(2);
#endif
#if (BOOT_COM_CAN_ENABLE > 0)
/* CAN RX GPIO pin configuration. PE4 = CAN0 RX, MUX = ALT5. */
PORTE->PCR[4] |= PORT_PCR_MUX(5);
/* CAN TX GPIO pin configuration. PE5 = CAN0 TX, MUX = ALT5. */
PORTE->PCR[5] |= PORT_PCR_MUX(5);
#endif
/* Initialize the timer driver. */
TimerInit();
/* Initialize the led driver. */
LedInit();
/* Enable the global interrupts. */
ENABLE_INTERRUPTS();
} /*** end of Init ***/
/************************************************************************************//**
** \brief System Clock Configuration. This code was derived from a S32 Design Studio
** example program. It enables the SOCS (40 MHz external crystal), FIRC (48
** MHz internal) and SIRC (8 MHz internal). The FIRC is used as a source for
** the system clock and configures the normal RUN mode for the following clock
** settings:
** - CORE_CLK = 48 MHz
** - SYS_CLK = 48 MHz
** - BUS_CLK = 48 MHz
** - FLASH_CLK = 24 MHz
** - SOSCDIV1_CLK = 40 MHz
** - SOSCDIV2_CLK = 40 MHz
** - FIRCDIV1_CLK = 48 MHz
** - FIRCDIV2_CLK = 48 MHz
** - SIRCDIV1_CLK = 8 MHz
** - SIRCDIV2_CLK = 8 MHz
** \return none.
**
****************************************************************************************/
static void SystemClockConfig(void)
{
/* --------- SOSC Initialization (40 MHz) ------------------------------------------ */
/* SOSCDIV1 & SOSCDIV2 =1: divide by 1. */
SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV1(1) | SCG_SOSCDIV_SOSCDIV2(1);
/* Range=3: High freq (SOSC betw 8MHz - 40MHz).
* HGO=0: Config xtal osc for low power.
* EREFS=1: Input is external XTAL.
*/
SCG->SOSCCFG = SCG_SOSCCFG_RANGE(3) | SCG_SOSCCFG_EREFS_MASK;
/* Ensure SOSCCSR unlocked. */
while (SCG->SOSCCSR & SCG_SOSCCSR_LK_MASK)
{
;
}
/* LK=0: SOSCCSR can be written.
* SOSCCMRE=0: OSC CLK monitor IRQ if enabled.
* SOSCCM=0: OSC CLK monitor disabled.
* SOSCERCLKEN=0: Sys OSC 3V ERCLK output clk disabled.
* SOSCLPEN=0: Sys OSC disabled in VLP modes.
* SOSCSTEN=0: Sys OSC disabled in Stop modes.
* SOSCEN=1: Enable oscillator.
*/
SCG->SOSCCSR = SCG_SOSCCSR_SOSCEN_MASK;
/* Wait for system OSC clock to become valid. */
while (!(SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK))
{
;
}
/* --------- FIRC Initialization --------------------------------------------------- */
/* Fast IRC is enabled and trimmed to 48 MHz in reset (default). Enable FIRCDIV2_CLK
* and FIRCDIV1_CLK, divide by 1 = 48 MHz.
*/
SCG->FIRCDIV = SCG_FIRCDIV_FIRCDIV1(1) | SCG_FIRCDIV_FIRCDIV2(1);
/* --------- SIRC Initialization --------------------------------------------------- */
/* Slow IRC is enabled with high range (8 MHz) in reset. Enable SIRCDIV2_CLK and
* SIRCDIV1_CLK, divide by 1 = 8MHz asynchronous clock source.
*/
SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV1(1) | SCG_SIRCDIV_SIRCDIV2(1);
/* --------- Change to normal RUN mode with 48MHz FIRC ----------------------------- */
/* Select FIRC as clock source.
* DIVCORE=0, div. by 1: Core clock = 48 MHz.
* DIVBUS=0, div. by 1: bus clock = 48 MHz.
* DIVSLOW=1, div. by 2: SCG slow, flash clock= 24 MHz
*/
SCG->RCCR = SCG_RCCR_SCS(3) | SCG_RCCR_DIVCORE(0) | SCG_RCCR_DIVBUS(0) |
SCG_RCCR_DIVSLOW(1);
/* Wait until system clock source is FIRC. */
while (((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT ) != 3U)
{
;
}
/* Evaluate the clock register settings and calculates the current core clock. This
* function must be called when the clock manager component is not used.
*/
SystemCoreClockUpdate();
} /*** end of SystemClockConfig ***/
/*********************************** end of main.c *************************************/

13
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/prog.dox Normal file
View File

@ -0,0 +1,13 @@
/**
\defgroup Prog_ARMCM0_S32K14_S32K118EVB_GCC User Program
\ingroup ARMCM0_S32K14_S32K118EVB_GCC
\brief User Program.
\details The intention of the demo user program is two-fold. (1) To test the
bootloader, you need some sort of firmware to see if you can perform a
firmware update with the bootloader. This program can be used for this
purpose. (2) To make firmware programmable by the bootloader, a few
adjustments to the firmware are required. The demo user program serves as an
example for how these adjustments can be implemented. This demo user program
is a template that can be used as a starting point for creating your own
demo user program.
*/

248
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/startup/startup.c Normal file
View File

@ -0,0 +1,248 @@
/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* Copyright 2016-2018 NXP
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block
* scope if its identifier only appears in a single function.
* All variables with this problem are defined in the linker files.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 8.11, When an array with external linkage
* is declared, its size should be explicitly specified.
* The size of the arrays can not be explicitly determined.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed
* between a pointer to object and an integer type.
* The cast is required to initialize a pointer with an unsigned int define,
* representing an address.
*
* @section [global]
* Violates MISRA 2012 Required Rule 11.6, A cast shall not be performed
* between pointer to void and an arithmetic type.
* The cast is required to initialize a pointer with an unsigned int define,
* representing an address.
*
* @section [global]
* Violates MISRA 2012 Required Rule 2.1, A project shall not contain unreachable
* code.
* The condition compares two address defined in linker files that can be different.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 8.7, External could be made static.
* Function is defined for usage by application code.
*
* @section [global]
* Violates MISRA 2012 Mandatory Rule 17.3, Symbol 'MFSPR' undeclared, assumed
* to return int.
* This is an e200 Power Architecture Assembly instruction used to retrieve
* the core number.
*
*/
#include "startup.h"
#include <stdint.h>
/*******************************************************************************
* Static Variables
******************************************************************************/
static volatile uint32_t * const s_vectors[NUMBER_OF_CORES] = FEATURE_INTERRUPT_INT_VECTORS;
/*******************************************************************************
* Code
******************************************************************************/
/*FUNCTION**********************************************************************
*
* Function Name : init_data_bss
* Description : Make necessary initializations for RAM.
* - Copy the vector table from ROM to RAM.
* - Copy initialized data from ROM to RAM.
* - Copy code that should reside in RAM from ROM
* - Clear the zero-initialized data section.
*
* Tool Chains:
* __GNUC__ : GNU Compiler Collection
* __ghs__ : Green Hills ARM Compiler
* __ICCARM__ : IAR ARM Compiler
* __DCC__ : Wind River Diab Compiler
* __ARMCC_VERSION : ARMC Compiler
*
* Implements : init_data_bss_Activity
*END**************************************************************************/
void init_data_bss(void)
{
uint32_t n;
uint8_t coreId;
/* For ARMC we are using the library method of initializing DATA, Custom Section and
* Code RAM sections so the below variables are not needed */
#if !defined(__ARMCC_VERSION)
/* Declare pointers for various data sections. These pointers
* are initialized using values pulled in from the linker file */
uint8_t * data_ram;
uint8_t * code_ram;
uint8_t * bss_start;
uint8_t * custom_ram;
const uint8_t * data_rom, * data_rom_end;
const uint8_t * code_rom, * code_rom_end;
const uint8_t * bss_end;
const uint8_t * custom_rom, * custom_rom_end;
#endif
/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
#if defined(__ARMCC_VERSION)
extern uint32_t __RAM_VECTOR_TABLE_SIZE;
extern uint32_t __VECTOR_ROM;
extern uint32_t __VECTOR_RAM;
#else
extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
extern uint32_t __VECTOR_TABLE[];
extern uint32_t __VECTOR_RAM[];
#endif
/* Get section information from linker files */
#if defined(__ICCARM__)
/* Data */
data_ram = __section_begin(".data");
data_rom = __section_begin(".data_init");
data_rom_end = __section_end(".data_init");
/* CODE RAM */
#pragma section = "__CODE_ROM"
#pragma section = "__CODE_RAM"
code_ram = __section_begin("__CODE_RAM");
code_rom = __section_begin("__CODE_ROM");
code_rom_end = __section_end("__CODE_ROM");
/* BSS */
bss_start = __section_begin(".bss");
bss_end = __section_end(".bss");
custom_ram = __section_begin(".customSection");
custom_rom = __section_begin(".customSection_init");
custom_rom_end = __section_end(".customSection_init");
#elif defined (__ARMCC_VERSION)
/* VECTOR TABLE*/
uint8_t * vector_table_size = (uint8_t *)__RAM_VECTOR_TABLE_SIZE;
uint32_t * vector_rom = (uint32_t *)__VECTOR_ROM;
uint32_t * vector_ram = (uint32_t *)__VECTOR_RAM;
#else
extern uint32_t __DATA_ROM[];
extern uint32_t __DATA_RAM[];
extern uint32_t __DATA_END[];
extern uint32_t __CODE_RAM[];
extern uint32_t __CODE_ROM[];
extern uint32_t __CODE_END[];
extern uint32_t __BSS_START[];
extern uint32_t __BSS_END[];
extern uint32_t __CUSTOM_ROM[];
extern uint32_t __CUSTOM_END[];
/* Data */
data_ram = (uint8_t *)__DATA_RAM;
data_rom = (uint8_t *)__DATA_ROM;
data_rom_end = (uint8_t *)__DATA_END;
/* CODE RAM */
code_ram = (uint8_t *)__CODE_RAM;
code_rom = (uint8_t *)__CODE_ROM;
code_rom_end = (uint8_t *)__CODE_END;
/* BSS */
bss_start = (uint8_t *)__BSS_START;
bss_end = (uint8_t *)__BSS_END;
/* Custom section */
custom_ram = CUSTOMSECTION_SECTION_START;
custom_rom = (uint8_t *)__CUSTOM_ROM;
custom_rom_end = (uint8_t *)__CUSTOM_END;
#endif
#if !defined(__ARMCC_VERSION)
/* Copy initialized data from ROM to RAM */
while (data_rom_end != data_rom)
{
*data_ram = *data_rom;
data_ram++;
data_rom++;
}
/* Copy functions from ROM to RAM */
while (code_rom_end != code_rom)
{
*code_ram = *code_rom;
code_ram++;
code_rom++;
}
/* Clear the zero-initialized data section */
while(bss_end != bss_start)
{
*bss_start = 0;
bss_start++;
}
/* Copy customsection rom to ram */
while(custom_rom_end != custom_rom)
{
*custom_ram = *custom_rom;
custom_rom++;
custom_ram++;
}
#endif
coreId = (uint8_t)GET_CORE_ID();
#if defined (__ARMCC_VERSION)
/* Copy the vector table from ROM to RAM */
/* Workaround */
for (n = 0; n < (((uint32_t)(vector_table_size))/sizeof(uint32_t)); n++)
{
vector_ram[n] = vector_rom[n];
}
/* Point the VTOR to the position of vector table */
*s_vectors[coreId] = (uint32_t) __VECTOR_RAM;
#else
/* Check if VECTOR_TABLE copy is needed */
if (__VECTOR_RAM != __VECTOR_TABLE)
{
/* Copy the vector table from ROM to RAM */
for (n = 0; n < (((uint32_t)__RAM_VECTOR_TABLE_SIZE)/sizeof(uint32_t)); n++)
{
__VECTOR_RAM[n] = __VECTOR_TABLE[n];
}
/* Point the VTOR to the position of vector table */
*s_vectors[coreId] = (uint32_t)__VECTOR_RAM;
}
else
{
/* Point the VTOR to the position of vector table */
*s_vectors[coreId] = (uint32_t)__VECTOR_TABLE;
}
#endif
}
/*******************************************************************************
* EOF
******************************************************************************/

133
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/startup/startup.h Normal file
View File

@ -0,0 +1,133 @@
/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* Copyright 2016-2019 NXP
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef STARTUP_H
#define STARTUP_H
#include <stdint.h>
#include "device_registers.h"
/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 2.5, Local macro not referenced.
* The defined macro is used as include guard.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block
* scope if its identifier only appears in a single function.
* All variables with this problem are defined in the linker files.
*
*/
/*******************************************************************************
* API
******************************************************************************/
/*!
* @brief define symbols that specific start and end addres of some basic sections.
*/
#if (defined(S32K14x_SERIES) || defined(S32K11x_SERIES) || defined(S32V234_SERIES) || defined(MPC574x_SERIES) || defined(S32R_SERIES) || defined(S32MTV_SERIES) || defined(SJA1110_SERIES)) || defined (S32K144W_M4_SERIES)
#if (defined(__ICCARM__))
#define INTERRUPTS_SECTION_START __section_begin(".intvec")
#define INTERRUPTS_SECTION_END __section_end(".intvec")
#define BSS_SECTION_START __section_begin(".bss")
#define BSS_SECTION_END __section_end(".bss")
#define DATA_SECTION_START __section_begin(".data")
#define DATA_SECTION_END __section_end(".data")
#define CUSTOMSECTION_SECTION_START __section_begin(".customSection")
#define CUSTOMSECTION_SECTION_END __section_end(".customSection")
#define CODE_RAM_SECTION_START __section_begin("__CODE_RAM")
#define CODE_RAM_SECTION_END __section_end("__CODE_RAM")
#define DATA_INIT_SECTION_START __section_begin(".data_init")
#define DATA_INIT_SECTION_END __section_end(".data_init")
#define CODE_ROM_SECTION_START __section_begin("__CODE_ROM")
#define CODE_ROM_SECTION_END __section_end("__CODE_ROM")
#elif (defined(__ARMCC_VERSION))
#define INTERRUPTS_SECTION_START (uint8_t *)__VECTOR_ROM_START
#define INTERRUPTS_SECTION_END (uint8_t *)__VECTOR_ROM_END
#define BSS_SECTION_START (uint8_t *)__BSS_START
#define BSS_SECTION_END (uint8_t *)__BSS_END
#define DATA_SECTION_START (uint8_t *)__DATA_RAM_START
#define DATA_SECTION_END (uint8_t *)__DATA_RAM_END
#define CUSTOMSECTION_SECTION_START (uint8_t *)__CUSTOM_SECTION_START
#define CUSTOMSECTION_SECTION_END (uint8_t *)__CUSTOM_SECTION_END
#define CODE_RAM_SECTION_START (uint8_t *)__CODE_RAM_START
#define CODE_RAM_SECTION_END (uint8_t *)__CODE_RAM_END
extern uint32_t __VECTOR_ROM_START;
extern uint32_t __VECTOR_ROM_END;
extern uint32_t __BSS_START;
extern uint32_t __BSS_END;
extern uint32_t __DATA_RAM_START;
extern uint32_t __DATA_RAM_END;
extern uint32_t __CUSTOM_SECTION_START;
extern uint32_t __CUSTOM_SECTION_END;
extern uint32_t __CODE_RAM_START;
extern uint32_t __CODE_RAM_END;
#else
#define INTERRUPTS_SECTION_START (uint8_t *)&__interrupts_start__
#define INTERRUPTS_SECTION_END (uint8_t *)&__interrupts_end__
#define BSS_SECTION_START (uint8_t *)&__bss_start__
#define BSS_SECTION_END (uint8_t *)&__bss_end__
#define DATA_SECTION_START (uint8_t *)&__data_start__
#define DATA_SECTION_END (uint8_t *)&__data_end__
#define CUSTOMSECTION_SECTION_START (uint8_t *)&__customSection_start__
#define CUSTOMSECTION_SECTION_END (uint8_t *)&__customSection_end__
#define CODE_RAM_SECTION_START (uint8_t *)&__code_ram_start__
#define CODE_RAM_SECTION_END (uint8_t *)&__code_ram_end__
extern uint32_t __interrupts_start__;
extern uint32_t __interrupts_end__;
extern uint32_t __bss_start__;
extern uint32_t __bss_end__;
extern uint32_t __data_start__;
extern uint32_t __data_end__;
extern uint32_t __customSection_start__;
extern uint32_t __customSection_end__;
extern uint32_t __code_ram_start__;
extern uint32_t __code_ram_end__;
#endif
#endif
#if (defined(__ICCARM__))
#pragma section = ".data"
#pragma section = ".data_init"
#pragma section = ".bss"
#pragma section = ".intvec"
#pragma section = ".customSection"
#pragma section = ".customSection_init"
#pragma section = "__CODE_RAM"
#pragma section = "__CODE_ROM"
#endif
/*!
* @brief Make necessary initializations for RAM.
*
* - Copy initialized data from ROM to RAM.
* - Clear the zero-initialized data section.
* - Copy the vector table from ROM to RAM. This could be an option.
*/
void init_data_bss(void);
#endif /* STARTUP_H*/
/*******************************************************************************
* EOF
******************************************************************************/

228
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/startup/startup_S32K118.S Normal file
View File

@ -0,0 +1,228 @@
/* ---------------------------------------------------------------------------------------*/
/* @file: startup_S32K118.s */
/* @purpose: GNU Compiler Collection Startup File */
/* S32K118 */
/* @version: 1.0 */
/* @date: 2018-1-22 */
/* @build: b170107 */
/* ---------------------------------------------------------------------------------------*/
/* */
/* Copyright 2018 NXP */
/* All rights reserved. */
/* */
/* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES */
/* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. */
/* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, */
/* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR */
/* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) */
/* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, */
/* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING */
/* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF */
/* THE POSSIBILITY OF SUCH DAMAGE. */
/*****************************************************************************/
/* Version: GNU Compiler Collection */
/*****************************************************************************/
.syntax unified
.arch armv6-m
.section .isr_vector, "a"
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* Non Maskable Interrupt */
.long HardFault_Handler /* Cortex-M0 SV Hard Fault Interrupt */
.long 0
.long 0
.long 0
.long 0
.long 0
.long 0
.long 0
.long SVC_Handler /* Cortex-M0 SV Call Interrupt */
.long 0
.long 0
.long PendSV_Handler /* Cortex-M0 Pend SV Interrupt */
.long SysTick_Handler /* Cortex-M0 System Tick Interrupt */
.long DMA0_IRQHandler /* DMA channel 0 transfer complete */
.long DMA1_IRQHandler /* DMA channel 1 transfer complete */
.long DMA2_IRQHandler /* DMA channel 2 transfer complete */
.long DMA3_IRQHandler /* DMA channel 3 transfer complete */
.long DMA_Error_IRQHandler /* DMA error interrupt channels 0-3 */
.long ERM_fault_IRQHandler /* ERM single and double bit error correction */
.long RTC_IRQHandler /* RTC alarm interrupt */
.long RTC_Seconds_IRQHandler /* RTC seconds interrupt */
.long LPTMR0_IRQHandler /* LPTIMER interrupt request */
.long PORT_IRQHandler /* Port A, B, C, D and E pin detect interrupt */
.long CAN0_ORed_Err_Wakeup_IRQHandler /* OR’ed [Bus Off OR Bus Off Done OR Transmit Warning OR Receive Warning], Interrupt indicating that errors were detected on the CAN bus, Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode */
.long CAN0_ORed_0_31_MB_IRQHandler /* OR’ed Message buffer (0-15, 16-31) */
.long FTM0_Ch0_7_IRQHandler /* FTM0 Channel 0 to 7 interrupt */
.long FTM0_Fault_IRQHandler /* FTM0 Fault interrupt */
.long FTM0_Ovf_Reload_IRQHandler /* FTM0 Counter overflow and Reload interrupt */
.long FTM1_Ch0_7_IRQHandler /* FTM1 Channel 0 to 7 interrupt */
.long FTM1_Fault_IRQHandler /* FTM1 Fault interrupt */
.long FTM1_Ovf_Reload_IRQHandler /* FTM1 Counter overflow and Reload interrupt */
.long FTFC_IRQHandler /* FTFC Command complete, Read collision and Double bit fault detect */
.long PDB0_IRQHandler /* PDB0 interrupt */
.long LPIT0_IRQHandler /* LPIT interrupt */
.long SCG_CMU_LVD_LVWSCG_IRQHandler /* PMC Low voltage detect interrupt, SCG bus interrupt request and CMU loss of range interrupt */
.long WDOG_IRQHandler /* WDOG interrupt request out before wdg reset out */
.long RCM_IRQHandler /* RCM Asynchronous Interrupt */
.long LPI2C0_Master_Slave_IRQHandler /* LPI2C0 Master Interrupt and Slave Interrupt */
.long FLEXIO_IRQHandler /* FlexIO Interrupt */
.long LPSPI0_IRQHandler /* LPSPI0 Interrupt */
.long LPSPI1_IRQHandler /* LPSPI1 Interrupt */
.long ADC0_IRQHandler /* ADC0 interrupt request. */
.long CMP0_IRQHandler /* CMP0 interrupt request */
.long LPUART1_RxTx_IRQHandler /* LPUART1 Transmit / Receive Interrupt */
.long LPUART0_RxTx_IRQHandler /* LPUART0 Transmit / Receive Interrupt */
.long 0x55AA11EE /* Reserved for OpenBLT checksum */
.size __isr_vector, . - __isr_vector
/* Flash Configuration */
.section .FlashConfig, "a"
.long 0xFFFFFFFF /* 8 bytes backdoor comparison key */
.long 0xFFFFFFFF /* */
.long 0xFFFFFFFF /* 4 bytes program flash protection bytes */
.long 0xFFFF7FFE /* FDPROT:FEPROT:FOPT:FSEC(0xFE = unsecured) */
.text
.thumb
/* Reset Handler */
.thumb_func
.align 2
.globl Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
cpsid i /* Mask interrupts */
/* Init the rest of the registers */
ldr r1,=0
ldr r2,=0
ldr r3,=0
ldr r4,=0
ldr r5,=0
ldr r6,=0
ldr r7,=0
mov r8,r7
mov r9,r7
mov r10,r7
mov r11,r7
mov r12,r7
#ifdef START_FROM_FLASH
/* Init ECC RAM */
ldr r1, =__RAM_START
ldr r2, =__RAM_END
subs r2, r1
subs r2, #1
ble .LC5
movs r0, 0
movs r3, #4
.LC4:
str r0, [r1]
add r1, r1, r3
subs r2, 4
bge .LC4
.LC5:
#endif
/* Initialize the stack pointer */
ldr r0,=__StackTop
mov r13,r0
#ifndef __NO_SYSTEM_INIT
/* Call the system init routine */
ldr r0,=SystemInit
blx r0
#endif
/* Init .data and .bss sections */
ldr r0,=init_data_bss
blx r0
cpsie i /* Unmask interrupts */
#ifndef __START
#ifdef __EWL__
#define __START __thumb_startup
#else
#define __START _start
#endif
#endif
bl __START
JumpToSelf:
b JumpToSelf
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak DefaultISR
.type DefaultISR, %function
DefaultISR:
b DefaultISR
.size DefaultISR, . - DefaultISR
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, DefaultISR
.endm
/* Exception Handlers */
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler SVC_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler DMA0_IRQHandler
def_irq_handler DMA1_IRQHandler
def_irq_handler DMA2_IRQHandler
def_irq_handler DMA3_IRQHandler
def_irq_handler DMA_Error_IRQHandler
def_irq_handler ERM_fault_IRQHandler
def_irq_handler RTC_IRQHandler
def_irq_handler RTC_Seconds_IRQHandler
def_irq_handler LPTMR0_IRQHandler
def_irq_handler PORT_IRQHandler
def_irq_handler CAN0_ORed_Err_Wakeup_IRQHandler
def_irq_handler CAN0_ORed_0_31_MB_IRQHandler
def_irq_handler FTM0_Ch0_7_IRQHandler
def_irq_handler FTM0_Fault_IRQHandler
def_irq_handler FTM0_Ovf_Reload_IRQHandler
def_irq_handler FTM1_Ch0_7_IRQHandler
def_irq_handler FTM1_Fault_IRQHandler
def_irq_handler FTM1_Ovf_Reload_IRQHandler
def_irq_handler FTFC_IRQHandler
def_irq_handler PDB0_IRQHandler
def_irq_handler LPIT0_IRQHandler
def_irq_handler SCG_CMU_LVD_LVWSCG_IRQHandler
def_irq_handler WDOG_IRQHandler
def_irq_handler RCM_IRQHandler
def_irq_handler LPI2C0_Master_Slave_IRQHandler
def_irq_handler FLEXIO_IRQHandler
def_irq_handler LPSPI0_IRQHandler
def_irq_handler LPSPI1_IRQHandler
def_irq_handler ADC0_IRQHandler
def_irq_handler CMP0_IRQHandler
def_irq_handler LPUART1_RxTx_IRQHandler
def_irq_handler LPUART0_RxTx_IRQHandler
.end

88
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/timer.c Normal file
View File

@ -0,0 +1,88 @@
/************************************************************************************//**
* \file Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/timer.c
* \brief Timer driver source file.
* \ingroup Prog_ARMCM0_S32K14_S32K118EVB_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "header.h" /* generic header */
/****************************************************************************************
* Local data declarations
****************************************************************************************/
/** \brief Local variable for storing the number of milliseconds that have elapsed since
* startup.
*/
static unsigned long millisecond_counter;
/************************************************************************************//**
** \brief Initializes the timer.
** \return none.
**
****************************************************************************************/
void TimerInit(void)
{
/* Configure the systick frequency as a 1 ms event generator. */
S32_SysTick->RVR = (SystemCoreClock / 1000U) - 1U;
/* Reset the current counter value. */
S32_SysTick->CVR = 0U;
/* Select core clock as source and enable the timer. */
S32_SysTick->CSR = S32_SysTick_CSR_ENABLE_MASK |
S32_SysTick_CSR_TICKINT_MASK |
S32_SysTick_CSR_CLKSOURCE_MASK;
/* Reset the millisecond counter value. */
millisecond_counter = 0U;
} /*** end of TimerInit ***/
/************************************************************************************//**
** \brief Obtains the counter value of the millisecond timer.
** \return Current value of the millisecond timer.
**
****************************************************************************************/
unsigned long TimerGet(void)
{
/* Read and return the tick counter value. */
return millisecond_counter;
} /*** end of TimerGet ***/
/************************************************************************************//**
** \brief Interrupt service routine of the timer.
** \return none.
**
****************************************************************************************/
void SysTick_Handler(void)
{
/* Increment the millisecond counter. */
millisecond_counter++;
} /*** end of SysTick_Handler ***/
/*********************************** end of timer.c ************************************/

38
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/timer.h Normal file
View File

@ -0,0 +1,38 @@
/************************************************************************************//**
* \file Demo/ARMCM0_S32K14_S32K118EVB_GCC/Prog/timer.h
* \brief Timer driver header file.
* \ingroup Prog_ARMCM0_S32K14_S32K118EVB_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef TIMER_H
#define TIMER_H
/****************************************************************************************
* Function prototypes
****************************************************************************************/
void TimerInit(void);
unsigned long TimerGet(void);
#endif /* TIMER_H */
/*********************************** end of timer.h ************************************/

8
Target/Demo/ARMCM0_S32K14_S32K118EVB_GCC/demo.dox Normal file
View File

@ -0,0 +1,8 @@
/**
\defgroup ARMCM0_S32K14_S32K118EVB_GCC Demo for S32K118EVB/GCC
\ingroup Demos
\brief Preconfigured programs for the NXP S32K118EVB board and the S32 Design Studio
development environment, which is based on the ARM GCC toolchain.
*/

125
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/S32K118_25_flash.icf Normal file
View File

@ -0,0 +1,125 @@
/*
** ###################################################################
** Processor: S32K118 with 25 KB SRAM
** Compiler: IAR ANSI C/C++ Compiler for ARM
**
** Abstract:
** Linker file for the IAR ANSI C/C++ Compiler for ARM
**
** Copyright 2018 NXP
** All rights reserved.
**
** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
** THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** ###################################################################
*/
/* If symbol __flash_vector_table__=1 is defined at link time
* the interrupt vector will not be copied to RAM.
* Warning: Using the interrupt vector from FLASH will not allow
* INT_SYS_InstallHandler because the section is Read Only.
*/
define symbol __ram_vector_table_size__ = isdefinedsymbol(__flash_vector_table__) ? 0 : 0x000000C0;
define symbol __ram_vector_table_offset__ = isdefinedsymbol(__flash_vector_table__) ? 0 : 0x000000BF;
/* Flash */
define symbol m_interrupts_start = 0x00000000;
define symbol m_interrupts_end = 0x000000BF;
define symbol m_flash_config_start = 0x00000400;
define symbol m_flash_config_end = 0x0000040F;
define symbol m_text_start = 0x00000410;
define symbol m_text_end = 0x00001FFF;
/* SRAM_L */
define symbol m_custom_start = 0x1FFFFC00;
define symbol m_custom_end = 0x1FFFFFFF;
/* SRAM_U */
define symbol m_interrupts_ram_start = 0x20000000;
define symbol m_interrupts_ram_end = 0x20000000 + __ram_vector_table_offset__;
define symbol m_data_start = m_interrupts_ram_start + __ram_vector_table_size__;
define symbol m_data_end = 0x200030BF;
define symbol m_data_2_start = 0x200030C0;
define symbol m_data_2_end = 0x200057FF;
/* Sizes */
if (isdefinedsymbol(__stack_size__)) {
define symbol __size_cstack__ = __stack_size__;
} else {
define symbol __size_cstack__ = 0x00000200;
}
if (isdefinedsymbol(__heap_size__)) {
define symbol __size_heap__ = __heap_size__;
} else {
define symbol __size_heap__ = 0x00000200;
}
define exported symbol __VECTOR_TABLE = m_interrupts_start;
define exported symbol __VECTOR_RAM = isdefinedsymbol(__flash_vector_table__) ? m_interrupts_start : m_interrupts_ram_start;
define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__;
define exported symbol __RAM_START = m_interrupts_ram_start;
define exported symbol __RAM_END = m_data_2_end;
define memory mem with size = 4G;
define region m_flash_config_region = mem:[from m_flash_config_start to m_flash_config_end];
define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
| mem:[from m_text_start to m_text_end];
define region DATA_region = mem:[from m_data_start to m_data_end];
define region DATA_region_2 = mem:[from m_data_2_start to m_data_2_end-__size_cstack__];
define region CSTACK_region = mem:[from m_data_2_end-__size_cstack__+1 to m_data_2_end];
define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end];
define region CUSTOM_region = mem:[from m_custom_start to m_custom_end];
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block RW { readwrite };
define block ZI { zi };
/* Custom Section Block that can be used to place data at absolute address. */
/* Use __attribute__((section (".customSection"))) to place data here. */
/* Use this section only when MTB (Micro Trace Buffer) is not used, because MTB uses the same RAM area, as described in S32K Reference Manual. */
define block customSectionBlock { section .customSection };
define block __CODE_ROM { section .textrw_init };
define block __CODE_RAM { section .textrw };
initialize manually { section .textrw };
initialize manually { section .bss };
initialize manually { section .customSection };
initialize manually { section .data };
initialize manually { section __DLIB_PERTHREAD };
do not initialize { section .noinit, section .bss, section .data, section __DLIB_PERTHREAD, section .customSection };
place at address mem: m_interrupts_start { readonly section .intvec };
place in m_flash_config_region { section FlashConfig };
place in TEXT_region { readonly };
place in TEXT_region { block __CODE_ROM };
place in DATA_region { block RW };
place in DATA_region { block __CODE_RAM };
place in CUSTOM_region { first block customSectionBlock };
place in DATA_region_2 { block ZI };
place in DATA_region_2 { last block HEAP };
place in CSTACK_region { block CSTACK };
place in m_interrupts_ram_region { section m_interrupts_ram };

BIN
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/bin/openblt_s32k118.out Normal file
View File

Binary file not shown.

443
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/bin/openblt_s32k118.srec Normal file
View File

@ -0,0 +1,443 @@
S01700006F70656E626C745F7333326B3131382E73726563DD
S113000000580020091D0000030B0000030B000032
S113001000000000000000000000000000000000DC
S1130020000000000000000000000000030B0000BE
S11300300000000000000000030B0000030B0000A0
S1130040030B0000030B0000030B0000030B000074
S1130050030B0000030B0000030B0000030B000064
S1130060030B0000030B0000030B0000030B000054
S1130070030B0000030B0000030B0000030B000044
S1130080030B0000030B0000030B0000030B000034
S1130090030B0000030B0000030B0000030B000024
S11300A0030B0000030B0000030B0000030B000014
S11300B0030B0000030B0000030B0000030B000004
S1130400FFFFFFFFFFFFFFFFFFFFFFFFFE7FFFFF79
S113041008B4024B9C4608BC6047C046C10000209B
S11304200020C04399490860994908607047F2B5B3
S1130430070014000125974ED8203058DC2171584C
S11304404018401EC01B0099491E884200D2002556
S11304502800C0B201280CD1380000F063FAFF284C
S113046006D000983818401E00F05CFAFF2800D12E
S113047000252800C0B2012814D1380A802149007F
S1130480484322003168884206D1009B39008048E5
S113049000F002F9050005E0009B39007B4800F0FC
S11304A0FBF805002800C0B2F2BDF8B504000F0047
S11304B001267849D8228A58DC23C9585118491E84
S11304C0091B7A1E914200D200263100C9B20129CB
S11304D010D1200000F026FA0500E019401E00F0BB
S11304E021FA2900C9B2FF2903D00100C9B2FF29AA
S11304F000D100263100C9B2012906D10100C9B2D8
S11305002800C0B200F091F906003000C0B2F2BD7C
S113051080B50120002100915D490A680023DB4376
S11305209A422CD00200D2B2012A28D100984A68FB
S11305308018009000988A68801800900098CA6813
S11305408018009000980A698018009000984A6901
S11305508018009000988A69801800900098C969F2
S1130560401800900098C14300910098401C0090EE
S11305706A46042147480068C030FFF758FFC0B2FC
S113058002BD10B5012000210B00424A1468246802
S11305901B191468241D24681B1914680834246862
S11305A01B1914680C3424681B191468103424684B
S11305B01B191468143424681B191468183424682B
S11305C01B191268C03212689A18002A00D0080059
S11305D0C0B210BD38B501240025ED432C48016894
S11305E0A94204D000F0A6F8002800D1002420007D
S11305F0C0B2012808D125480168A94204D000F0FE
S113060099F8002800D100242000C0B232BD21484E
S11306100068704710B50124CAB2002A00D0002433
S11306202200D2B2012A08D102688A4205D00160B0
S113063080225200001D00F0DBF92000C0B210BD82
S1130640F8B504000E00002738001148844202D196
S11306500E4C25000EE00F490A68964203D10400AF
S11306600E68250006E02500200000F063F800284D
S113067000D13D00002D06D031002000FFF7CAFF55
S1130680002800D13D002800F2BD00000C310020FC
S1130690103200204C1B0000FEB504000E001700B1
S11306A00125300A80214900484300902068002138
S11306B0C943884206D100992000FFF7ABFF002808
S11306C000D100252800C0B201280BD12068009970
S11306D0884207D000992000FFF7B2FF0400002CE5
S11306E000D100252800C0B2012820D12068301A8A
S11306F02018061D00F091F980204000211D711A78
S1130700814208D3009909182000FFF799FF0400DB
S1130710002C0BD0261D38783070761C7F1C029874
S1130720401E029002980028E4D100E00025280031
S1130730C0B2FEBDF1B582B001240820694608703C
S11307400298006800F0EEF8FF2800D10024200091
S1130750C0B2012864D10020019012E0491C0A00B3
S11307606B461B78D2B29A4208D20A00D2B2AA5C73
S11307700B00DBB2F35C9A42F0D004000198401CF9
S11307800190802040006946097800F060F90199E1
S1130790814245D20298006801996A461278514311
S11307A04518029801996A46127851434018061D6B
S11307B000F033F96E4F3878000630D57020387069
S11307C007206C4908702800000C6B490870280A3F
S11307D06A49087028006A490870307869490870C5
S11307E0707869490870B07868490870F078684989
S11307F00870307967490870707967490870B07972
S113080066490870F07966490870FFF701FE387888
S113081071210140002906D1002001009FE7002436
S11308202000C0B2FEBD0024FAE7F2B582B0012474
S11308306946097A0200D2B2914200D20024210012
S1130840C9B2012904D16946097A132900D30024C5
S11308502100C9B2012962D1070000E07F1C68466B
S1130860007A3900C9B2884259D300F0D6F84D480D
S11308703900C9B20C225143415801913900C9B21F
S11308800C2251434018406801990022D2439142FE
S11308900FD000280DD001994905490D00290AD12E
S11308A04105490D002908D1C00A69460870002590
S11308B01BE0002433E0002431E000242FE0702109
S11308C0317009212B4A11700100090C2A4A117058
S11308D0010A2A4A11702A490870FFF799FD3078F5
S11308E071210140002915D16D1C28006946097841
S11308F0C0B288420FD200F090F801982900C9B222
S11309008022120151434018194E31780906D6D479
S1130910002400E000242000C0B200289ED1200062
S1130920C0B2FEBD70B50400FF25002600E0761CB1
S11309303000C0B2132818D200F06FF81948310003
S1130940C9B20C22514341588C42F0D33100C9B290
S11309500C22514341583200D2B20C235A4380181E
S1130960406808188442E2D235002800C0B270BD45
S11309700000024007000240060002400500024059
S11309800400024008000240090002400A0002403C
S11309900B0002400C0002400D0002400E00024019
S11309A00F0002404C1B000080B500F0ABF801BD05
S11309B080B500F0B7F8002814D000F0C5F800287E
S11309C010D000F005F900F064F900F0AFF8064922
S11309D001400648016000F097F800F0A7F8001DF8
S11309E00068804701BD000080FFFF1F08ED00E0A4
S11309F070B514000D00060005E0287830706D1CF9
S1130A00761C00F00AF82000441E80B20028F4D1BD
S1130A1070BD80B500F0A6F801BD80B500F0A7F860
S1130A2001BDF446002804D4494200F013F84042C2
S1130A3060474042002905D45FD000F00BF84042E3
S1130A4049426047494200F005F84942604703467D
S1130A500B43E6D40022030A8B420BD203098B42D8
S1130A6019D243088B422ED2411A00D20146524178
S1130A7010467047FF2209023FD012068B4205D36D
S1130A80121209028B4201D31212090203098B428A
S1130A9019D300E0090AC3098B4201D3CB01C01A60
S1130AA0524183098B4201D38B01C01A524143093D
S1130AB08B4201D34B01C01A524103098B4201D32B
S1130AC00B01C01A5241C3088B4201D3CB00C01A98
S1130AD0524183088B4201D38B00C01A5241430810
S1130AE08B4201D34B00C01A5241884200D3401AB2
S1130AF05241CFD201461046704708B500F0E8F8DD
S1130B0008BDFEE762B6704762B6704780B5FFF76E
S1130B1087FC01BD80B5FFF78AFC02BD80B5FFF7F5
S1130B20C4FC02BD80B5FFF72CFD02BD80B5FFF704
S1130B306EFD02BD80B5FFF7EBFC002801D100205B
S1130B4001E0FFF747FD02BD80B5054800680007D6
S1130B5001D5002002E000F0EFF8012002BD000002
S1130B60D0F00F4080B5642000F0B4F801BD80B52A
S1130B7000F0BFF801BD000010B500F0F3F800F07C
S1130B80A1FB354C0120207000F04CFD00202070AA
S1130B9010BD1CB5314C6946200000F0E5FC01286D
S1130BA007D101202C49087068460178200000F024
S1130BB0F5F86946200000F0AAFD012807D10020BD
S1130BC02549087068460178200000F0E7F813BD55
S1130BD0704770B506000C001F4D2878012804D119
S1130BE02100C9B2300000F045FC2878002804D167
S1130BF02100C9B2300000F069FD00F0CBF870BDEF
S1130C0000B515480078002805D0022807D004D381
S1130C10032806D007E0402006E0082004E0002076
S1130C2002E0002000E0402080B200BD00B50A4888
S1130C300078002805D0022807D004D3032806D062
S1130C4007E0402006E0082004E0002002E0002045
S1130C5000E0402080B200BDDC000020CC30002049
S1130C6010B5002400F08DF8002800D001242000E5
S1130C70C0B210BD80B500F00CF8104810490860EF
S1130C8000201049086005210F4A11600F490860CF
S1130C9001BD00200C490860704700B50A4800688F
S1130CA0C00303D509480168491C016000BD80B533
S1130CB0FFF7F3FF0548006802BD00007FBB00009A
S1130CC014E000E018E000E010E000E060330020F1
S1130CD070470000802149001B4A11601B4A1368B9
S1130CE00B4313601A4A13681943116019490880A9
S1130CF0704710B5FFF7DBFF174C216888421AD301
S1130D0016480178002908D10121017014480168AE
S1130D10802252000A43026007E0002101700C485F
S1130D200168802252000A430260FFF7C0FF0949AC
S1130D3009884018206010BD0548016880225200CF
S1130D400A4302607047000020D0044014F10F40B1
S1130D5008F10F40B033002014330020B3330020D7
S1130D6004F10F400020B74902000A7088640200B1
S1130D704323CA5402004423CA5202008A704870B2
S1130D80704700B5AF480078002801D1002000E08A
S1130D90012000BD0020BB490870704710B50178E0
S1130DA0FF2916D100F08AF8A64C4320205C0128C4
S1130DB002D1102000F07AF84420205E012807DBDD
S1130DC00120432160544420215EE01C00F052F8CD
S1130DD010BD9C49097801294BD10178C92932D029
S1130DE0CC293FD0CF293AD0D0292FD0D12933D004
S1130DF0D2292ED0F32917D0F4290FD0F5290AD0FF
S1130E00F6290ED0FA2912D0FC2913D0FD2914D0CA
S1130E10FE2915D029E000F0B0F8C5E700F0CCF8C1
S1130E20C2E700F0A1F8BFE700F0E9F8BCE700F082
S1130E308AF8B9E700F082F8B6E700F071F8B3E792
S1130E4000F062F8B0E700F0FFF8ADE700F01CF93D
S1130E50AAE700F0E5F8A7E700F044F9A4E700F0FA
S1130E6053F9A1E700F05EF99EE7202000F01EF898
S1130E709AE7ADE780B589B2FFF7ABFE01BDF8B5DF
S1130E8004000D001700002604E020783618641CC6
S1130E90FFF7C3FD2800451E0028F6D1F6B23E60D8
S1130EA00120F2BD00206749487070476549FE2261
S1130EB0CA700871022044228852704738B5FFF77F
S1130EC0F1FF604C01252570FF20E0700020211DFA
S1130ED008702279102313430B70611D0870607928
S1130EE00870FFF78DFEA071FFF7A0FEE071FFF719
S1130EF09DFE80B2000A20726572A572082044210A
S1130F006052FFF703FE31BD10B54E4C0020207037
S1130F10FFF7C8FFFF20E07001204421605210BD9C
S1130F204848FF21C17000210171427842718171EA
S1130F30C1710172062144228152704780B500209C
S1130F40FFF7B4FF01BD3F48FF21C17073498164BD
S1130F5000210171417181710721C01C4160C01ED3
S1130F6008214422815270473649FF22CA704068E2
S1130F708864012044228852704738B50500FFF781
S1130F803FFE80B2401E6978884203DA2220FFF7D0
S1130F908DFF10E06A782B4C201D92B2A16CFFF7F4
S1130FA027FDFF20E070A06C69784018A064687881
S1130FB0401C4421605231BD70B50500FFF720FE8E
S1130FC080B2401E6978884203DA2220FFF76EFF60
S1130FD014E01C4C26004836686830606A78201D8E
S1130FE092B2A16CFFF704FDFF20E070A06C697859
S1130FF0401830606878401C4421605270BD10B5C0
S1131000104CFF21E170E21D4168A06CFFF737FF2F
S1131010207100206071A07108204421605210BD2D
S113102038B5084CFF20E070002525716571FFF785
S1131030E7FDA071E57125726572072044216052B5
S113104031BD00006433002038B50500FFF7D8FD3A
S1131050334C6A1C80B2411EA06CFFF75BFD002874
S113106003D13120FFF722FF0BE0FF20E070FFF7F0
S1131070C7FDA16C80B2401E0818A0640120442161
S1131080605231BDA733002038B50500FFF7B8FD25
S113109080B2801E6978884203DA2220FFF706FFB7
S11310A01FE01F4CFF20E07001204421605268784B
S11310B0002807D1FFF73EFD002802D13120FFF7B9
S11310C0F5FE0EE0AA1C6978A06CFFF723FD00284A
S11310D003D13120FFF7EAFE03E0A06C69784018E1
S11310E0A06431BD10B50E4C4168A06CFFF716FD2D
S11310F0002803D13120FFF7D9FE04E0FF20E0707F
S113110001204421605210BD80B5FFF751FC044812
S1131110FF21C17001214422815201BDB01E000093
S11311206433002080B53120FFF7C0FE01BD00000C
S1131130FEB507000D00140068465F490CC90CC0D9
S1131140083908385D480168090A4907490F002928
S113115005D101210A02E023DB0013400360584853
S11311606A46515CFFF776FC0190002668460780CA
S113117000E0761C3000C0B212282BD2B94F01987F
S113118069460A883100C9B204235943795C514342
S1131190FFF760FC0029ECD1019869460A88310008
S11311A0C9B204235943795C5143FFF753FC2880A7
S11311B028880028DDD02888FF21891C8842D8D2BD
S11311C02000F6B204214E43B919042200F050FB6A
S11311D0012000E00020FEBD38B5A34C20680028A3
S11311E003D5D021A14800F050FB20688021C90517
S11311F00143216020688021490501432160FFF7F4
S113120056FD0500FA352068C00105D4FFF705FC3A
S1131210FFF74DFD8542F6D231BD38B5924C2068BA
S1131220002803D5F021914800F02FFB2068904955
S1131230014021602068C74901402160FFF737FD64
S11312400500FA352068C00105D5FFF7E6FBFFF776
S11312502EFD8542F6D231BD38B5834C2068002876
S113126011D420688021090601432160FFF71FFD86
S11312700500FA352068C00205D4FFF7CEFBFFF75E
S113128016FD8542F6D231BD38B5774C206800286A
S113129010D52068400040082060FFF708FD0500D5
S11312A0FA352068C00205D5FFF7B7FBFFF7FFFC4E
S11312B08542F6D231BD0000A01E00000441064064
S11312C0409C0000FEB500273800694608800422CF
S11312D0002101A800F0DDFA9F4DA048016880229A
S11312E0D2050A430260FFF7CFFFFFF775FFFFF750
S11312F0B3FF9B4C20689B4901402160FFF7C4FF6A
S1131300FFF76AFF01AA6946FA204000FFF710FFC1
S1131310002804D1FF217831544800F0B6FA20683F
S1131320A94901402160206869460988491E0906C7
S11313300143216001A821684278521E5207520FCE
S11313400A43226021688278521ED204E0239B0360
S113135013400B4323602168C278521E1204E02319
S1131360DB0213400B4323608178042901DA80787F
S113137000E004202168C0B2401E8005C02212048F
S113138002400A4322602068802101432160380022
S113139006E08E49020092B204235343CF50401C0E
S11313A0010089B28029F4D3380006E0884902009C
S11313B092B204235343CF50401C010089B2202928
S11313C0F4D3294E30687F2188431F2101433160C3
S11313D030688021890201433160306880214902EC
S11313E00143316030687B49014031607A487B4970
S11313F008607B488021C9040160002D0BD5690079
S11314004908026880239B0313430360C800C00893
S11314107449086004E0A804C000C0087149086069
S1131420714807600020C0437049086070487149E2
S11314300860306870490140316020686F4901409C
S11314402160FFF7EAFEFFF732FC0400FA3430684B
S1131450000105D5FFF7E1FAFFF729FC8442F6D233
S1131460F7BD0000601D000000400240A81D000000
S1131470FFFFFFBFFEB506000A00002529006048F3
S1131480002802D54000400801216B461A708024D0
S11314906400564A14605B4A1368DB00DB0813607F
S11314A01368594F1F40176013688027FF031F43B9
S11314B017601368554F1F4017601768BC466B468A
S11314C01B781F04F0231B033B4067463B43136018
S11314D04F4B019611E02E00F6B20327BE43F61CD3
S11314E02F00FFB2BF07BF0FF71BBC46019F2E00A2
S11314F0F6B2BE5D6746DE556D1C2E006F463F7822
S1131500F6B2BE42E7D3C9B2002905D18004C000B7
S1131510C0084049086008E0116880239B030B431E
S11315201360C000C0083B4908601068C021090569
S113153001431160FFF7BBFB050032352B480068FF
S11315402040002805D1FFF768FAFFF7B0FB854279
S1131550F4D2F7BDFFFFFFEF67060000905006408E
S113156004400240FFDFFFFFF0B50A00002319002A
S11315708024A4001D4D2E682640002E21D0184939
S11315800968090C0907090F117023490EE01E00B0
S1131590F6B20327BE43F61C1F00FFB2BF07BF0FFE
S11315A0F61B8E5D1F00FFB2C6555B1C1E0017782C
S11315B0F6B2BE42EBD32C601848006818490860A4
S11315C001210800C0B2F0BD78FF00008040024055
S11315D080480240FFFFFFDFFFFFFF5FA448024097
S11315E01041024014410240284002403040024071
S11315F006003B0020400240FFFF7FFFF7EFFFFFA4
S1131600E107000000410240FFFFCFFFFFFFF0FFB2
S1131610084102400441024018410240084002408F
S1131620C83000201CB568466F490CC90CC0083985
S113163008386E4801686E4A0A40026001688422D4
S1131640D2050A4302606B480168090A4907490F39
S1131650002907D1012102680B02E024E4001C40A8
S11316601443046064480124644A12682240002A36
S113167000D163486A46515CFFF7ECF9E1210902A5
S1131680FFF7E8F9C01DC008C004C00C80B2C00454
S1131690C00CE021C90401435A4801605A485B491F
S11316A008605B48002101605A4A11605A4A11607F
S11316B05A49F02292020A600A68882313430B6095
S11316C057490C60C0210903016013BD70B50400C3
S11316D00D002800C0B2412803DBC221514800F0AC
S11316E0D4F82800C0B200F069F8002607E0FFF73C
S11316F094F9300080B2205C00F060F8761C300071
S11317002900C9B280B289B28842F0D370BDF8B55D
S113171007000E0044480078002816D1434C2000EE
S113172000F03CF8012837D12078002834D0207804
S1131730412831DAFFF7BBFA3D49086000203D49F2
S1131740087001203849087026E03A4C374D20785B
S11317502818401C00F022F8012813D12078401CDE
S1131760207020782978884216D13800227892B2E5
S1131770691CFFF73DF900202B4908702078307070
S113178001200AE0FFF793FA29490968643181428C
S113179002D20020244908700020F2BD00B50021C7
S11317A001221A4B1B685B0D1340002B03D0224906
S11317B00968017011000800C0B200BD10B5C0B2C4
S11317C01D490860FFF773FA04000A340F480068E3
S11317D001000902C90F002905D1FFF71EF9FFF71F
S11317E066FA8442F2D210BDA81E0000A851064039
S11317F0FFFFFFBF0442064000127A000842064081
S113180080841E0010A0064000C01FC014A0064023
S113181018A0064020A0064024A0064028A00640A8
S11318202CA00640EC1D0000B53300201833002026
S11318305C330020B43300201CA0064070B4103A7E
S113184003D378C9103A78C0FBD2530701D318C91F
S113185018C001D508C908C0D20704D30B88038077
S1131860891C801C002A01D50B78037070BC70475A
S11318708B0701D18307E1D0124205D00B78491CB4
S11318800370401C521EF9D1704780B5FFF7C5F8AC
S1131890FCE710B50400080011000200200000F06D
S11318A003F8200010BD00001206130A1A43130C9B
S11318B01A4300BF094205D0830705D00270401CBB
S11318C0491EF9D1704700001300103906D330B413
S11318D01400150010393CC0FCD230BC490700D3B9
S11318E00CC000D504C0890002D30280801C0029EA
S11318F000D502707047000080B500F005F800F0D4
S113190083F800F08FF8FCE780B500F037F880200A
S1131910C0052B490A6802430A602A490A6802433F
S11319200A6029490A68104308602848016880222F
S113193052000A43026001680222914301600820B8
S1131940C04323490A6802400A6022490A681040D9
S113195008608020800020490A6802430A601F4909
S11319600A6810430860A020C0001D490A680243A9
S11319700A601C490A681043086001BD80B5FF2055
S1131980801C194908603421184A116018490A68F2
S11319901202FBD401220A600A68D201FCD515495F
S11319A0086015490860154815490860154800681D
S11319B0000E0007000F0328F8D100F048F801BD1D
S11319C02851064030510640345106400CC00440B2
S11319D0D4F00F40D8F00F4000A0044004A004400D
S11319E010D0044014D0044004410640084106408D
S11319F0004106400443064004420640010000033F
S1131A00144006401040064080B5FEF7CDFFFFF7B6
S1131A1000F8FFF72FF9FFF779F8FFF7ADF800F0BA
S1131A2061F801BD80B5FEF7F8FFFFF736F9FFF75F
S1131A30B0F800F060F801BD1E481F49016000685D
S1131A401E481F4908601F481F490860704770B549
S1131A500022100001252B000F241C4E3168090CB4
S1131A602140491C3668360E3440012C04D018D36A
S1131A70032C0CD002D314E0154813E0154C246851
S1131A802540002D01D0124800E013000AE0124C5A
S1131A902468A407A40F002C01D1104800E013000F
S1131AA000E01300DBB2002B03D0FEF7D3FF0C4998
S1131AB0086070BD0420054020C528D920210000FD
S1131AC000200540FFFF00000820054010400640AC
S1131AD000127A000842064008430640006CDC020B
S1131AE0D800002080B501201549087000F01DF8C9
S1131AF000F001F801BD10B5FFF7B2F8012813D0CA
S1131B000F4C207801280FD1FFF7D1F80D4909684F
S1131B100D4A12688918FA2252008918884203D3A0
S1131B2000202070FEF744FF10BD80B50448007803
S1131B30012803D1FFF7BBF80349086001BD000089
S1131B40B2330020C4300020C03000200020000048
S1131B500008000004000000002800000008000045
S1131B60050000000030000000080000060000002E
S1131B7000380000000800000700000000400000DA
S1131B8000080000080000000048000000080000F1
S1131B900900000000500000000800000A000000D6
S1131BA000580000000800000B0000000060000066
S1131BB0000800000C00000000680000000800009D
S1131BC00D00000000700000000800000E0000007E
S1131BD000780000000800000F00000000800000F2
S1131BE000800000100000000000010000800000E0
S1131BF011000000008001000080000012000000BD
S1131C0000000200008000001300000000800200B9
S1131C1000800000140000000000030000800000A9
S1131C201500000000800300008000001600000082
S1131C30FFB526482649274A0392274A274B284CB2
S1131C400294284C284D0195284D294E294F009780
S1131C5003E00F780770401C491C039F8F42F8D1A2
S1131C600298984207D018781070521C5B1CF7E752
S1131C7000202070641C0198A042F9D10098B04261
S1131C8004D030782870761C6D1CF7E70023180008
S1131C9019491A4A8A4212D006E004245C430C59BA
S1131CA004255D4354515B1C154CA408A342F4D392
S1131CB01449C0B2042358430858026005E0114A8D
S1131CC0C0B20423584310580160FFBDD80000205F
S1131CD0B81E0000C01E0000C00000207C1E0000D2
S1131CE0941E0000C0300020B63300200000000025
S1131CF000000000000000000000000000000020C0
S1131D00C0000000C01E000072B6002100220023A3
S1131D100024002500260027B846B946BA46BB462B
S1131D20BC460A490A4A521A013A05DD0020042336
S1131D3008601944043AFBDA064885460648804799
S1131D400648804762B6FFF7D7FDFEE70000002093
S1131D50FF57002000580020391A0000311C0000F1
S1131D6008030202090303020A0303030B04030327
S1131D700C0404030D0504030E0504040F060404F7
S1131D8010060504110705041207050513080505C7
S1131D901408060515080705160807061708080697
S1131DA01808080719080808433A5C576F726B5CF7
S1131DB0736F6674776172655C4F70656E424C54E4
S1131DC05F5333324B31315C5461726765745C53D9
S1131DD06F757263655C41524D434D305F533332CE
S1131DE04B31315C63616E2E63000000433A5C57F3
S1131DF06F726B5C736F6674776172655C4F70654C
S1131E006E424C545F5333324B31315C54617267D0
S1131E1065745C536F757263655C41524D434D301C
S1131E205F5333324B31315C72733233322E630081
S1131E3000F00DF8002801D000BF00BF00BF00BFB4
S1131E40002000BF00BFFFF757FD00F002F801209B
S1131E50704780B500F002F801BD0000074638461F
S1131E6000F002F8FBE7000080B500BF00BF024AA3
S1131E7011001820ABBEFBE72600020000B580204D
S1131E8003490A7802430A700A780242FCD000BD72
S1131E900000024000BF00BF00BF00BFFFF7C8FF43
S1131EA00001020408102040000102040810204030
S1131EB04F70656E424C5400006CDC02040000005C
S1071EC008ED00E045
S9031E9549

176
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/blt_conf.h Normal file
View File

@ -0,0 +1,176 @@
/************************************************************************************//**
* \file Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/blt_conf.h
* \brief Bootloader configuration header file.
* \ingroup Boot_ARMCM0_S32K14_S32K118EVB_IAR
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef BLT_CONF_H
#define BLT_CONF_H
/****************************************************************************************
* C P U D R I V E R C O N F I G U R A T I O N
****************************************************************************************/
/* To properly initialize the baudrate clocks of the communication interface, typically
* the speed of the crystal oscillator and/or the speed at which the system runs is
* needed. Set these through configurables BOOT_CPU_XTAL_SPEED_KHZ and
* BOOT_CPU_SYSTEM_SPEED_KHZ, respectively. To enable data exchange with the host that is
* not dependent on the targets architecture, the byte ordering needs to be known.
* Setting BOOT_CPU_BYTE_ORDER_MOTOROLA to 1 selects big endian mode and 0 selects
* little endian mode.
*
* Set BOOT_CPU_USER_PROGRAM_START_HOOK to 1 if you would like a hook function to be
* called the moment the user program is about to be started. This could be used to
* de-initialize application specific parts, for example to stop blinking an LED, etc.
*/
/** \brief Frequency of the external crystal oscillator. */
#define BOOT_CPU_XTAL_SPEED_KHZ (40000)
/** \brief Desired system speed. */
#define BOOT_CPU_SYSTEM_SPEED_KHZ (48000)
/** \brief Motorola or Intel style byte ordering. */
#define BOOT_CPU_BYTE_ORDER_MOTOROLA (0)
/** \brief Enable/disable hook function call right before user program start. */
#define BOOT_CPU_USER_PROGRAM_START_HOOK (1)
/****************************************************************************************
* C O M M U N I C A T I O N I N T E R F A C E C O N F I G U R A T I O N
****************************************************************************************/
/* The UART communication interface is selected by setting the BOOT_COM_UART_ENABLE
* configurable to 1. Configurable BOOT_COM_UART_BAUDRATE selects the communication speed
* in bits/second. The maximum amount of data bytes in a message for data transmission
* and reception is set through BOOT_COM_UART_TX_MAX_DATA and BOOT_COM_UART_RX_MAX_DATA,
* respectively. It is common for a microcontroller to have more than 1 UART interface
* on board. The zero-based BOOT_COM_UART_CHANNEL_INDEX selects the UART interface.
*
*/
/** \brief Enable/disable UART transport layer. */
#define BOOT_COM_RS232_ENABLE (1)
/** \brief Configure the desired communication speed. */
#define BOOT_COM_RS232_BAUDRATE (57600)
/** \brief Configure number of bytes in the target->host data packet. */
#define BOOT_COM_RS232_TX_MAX_DATA (64)
/** \brief Configure number of bytes in the host->target data packet. */
#define BOOT_COM_RS232_RX_MAX_DATA (64)
/** \brief Select the desired UART peripheral as a zero based index. */
#define BOOT_COM_RS232_CHANNEL_INDEX (0)
/* The CAN communication interface is selected by setting the BOOT_COM_CAN_ENABLE
* configurable to 1. Configurable BOOT_COM_CAN_BAUDRATE selects the communication speed
* in bits/second. Two CAN messages are reserved for communication with the host. The
* message identifier for sending data from the target to the host is configured with
* BOOT_COM_CAN_TXMSG_ID. The one for receiving data from the host is configured with
* BOOT_COM_CAN_RXMSG_ID. Note that an extended 29-bit CAN identifier is configured by
* OR-ing with mask 0x80000000. The maximum amount of data bytes in a message for data
* transmission and reception is set through BOOT_COM_CAN_TX_MAX_DATA and
* BOOT_COM_CAN_RX_MAX_DATA, respectively. It is common for a microcontroller to have more
* than 1 CAN controller on board. The zero-based BOOT_COM_CAN_CHANNEL_INDEX selects the
* CAN controller channel.
*
*/
/** \brief Enable/disable CAN transport layer. */
#define BOOT_COM_CAN_ENABLE (1)
/** \brief Configure the desired CAN baudrate. */
#define BOOT_COM_CAN_BAUDRATE (500000)
/** \brief Configure CAN message ID target->host. */
#define BOOT_COM_CAN_TX_MSG_ID (0x7E1 /*| 0x80000000*/)
/** \brief Configure number of bytes in the target->host CAN message. */
#define BOOT_COM_CAN_TX_MAX_DATA (8)
/** \brief Configure CAN message ID host->target. */
#define BOOT_COM_CAN_RX_MSG_ID (0x667 /*| 0x80000000*/)
/** \brief Configure number of bytes in the host->target CAN message. */
#define BOOT_COM_CAN_RX_MAX_DATA (8)
/** \brief Select the desired CAN peripheral as a zero based index. */
#define BOOT_COM_CAN_CHANNEL_INDEX (0)
/****************************************************************************************
* B A C K D O O R E N T R Y C O N F I G U R A T I O N
****************************************************************************************/
/* It is possible to implement an application specific method to force the bootloader to
* stay active after a reset. Such a backdoor entry into the bootloader is desired in
* situations where the user program does not run properly and therefore cannot
* reactivate the bootloader. By enabling these hook functions, the application can
* implement the backdoor, which overrides the default backdoor entry that is programmed
* into the bootloader. When desired for security purposes, these hook functions can
* also be implemented in a way that disables the backdoor entry altogether.
*/
/** \brief Enable/disable the backdoor override hook functions. */
#define BOOT_BACKDOOR_HOOKS_ENABLE (0)
/****************************************************************************************
* N O N - V O L A T I L E M E M O R Y D R I V E R C O N F I G U R A T I O N
****************************************************************************************/
/* The NVM driver typically supports erase and program operations of the internal memory
* present on the microcontroller. Through these hook functions the NVM driver can be
* extended to support additional memory types such as external flash memory and serial
* eeproms. The size of the internal memory in kilobytes is specified with configurable
* BOOT_NVM_SIZE_KB. If desired the internal checksum writing and verification method can
* be overridden with a application specific method by enabling configuration switch
* BOOT_NVM_CHECKSUM_HOOKS_ENABLE.
*/
/** \brief Enable/disable the NVM hook function for supporting additional memory devices. */
#define BOOT_NVM_HOOKS_ENABLE (0)
/** \brief Configure the size of the default memory device (typically flash EEPROM). */
#define BOOT_NVM_SIZE_KB (256)
/** \brief Enable/disable hooks functions to override the user program checksum handling. */
#define BOOT_NVM_CHECKSUM_HOOKS_ENABLE (0)
/****************************************************************************************
* W A T C H D O G D R I V E R C O N F I G U R A T I O N
****************************************************************************************/
/* The COP driver cannot be configured internally in the bootloader, because its use
* and configuration is application specific. The bootloader does need to service the
* watchdog in case it is used. When the application requires the use of a watchdog,
* set BOOT_COP_HOOKS_ENABLE to be able to initialize and service the watchdog through
* hook functions.
*/
/** \brief Enable/disable the hook functions for controlling the watchdog. */
#define BOOT_COP_HOOKS_ENABLE (1)
/****************************************************************************************
* S E E D / K E Y S E C U R I T Y C O N F I G U R A T I O N
****************************************************************************************/
/* A security mechanism can be enabled in the bootloader's XCP module by setting configu-
* rable BOOT_XCP_SEED_KEY_ENABLE to 1. Before any memory erase or programming
* operations can be performed, access to this resource need to be unlocked.
* In the Microboot settings on tab "XCP Protection" you need to specify a DLL that
* implements the unlocking algorithm. The demo programs are configured for the (simple)
* algorithm in "libseednkey.dll". The source code for this DLL is available so it can be
* customized to your needs.
* During the unlock sequence, Microboot requests a seed from the bootloader, which is in
* the format of a byte array. Using this seed the unlock algorithm in the DLL computes
* a key, which is also a byte array, and sends this back to the bootloader. The
* bootloader then verifies this key to determine if programming and erase operations are
* permitted.
* After enabling this feature the hook functions XcpGetSeedHook() and XcpVerifyKeyHook()
* are called by the bootloader to obtain the seed and to verify the key, respectively.
*/
#define BOOT_XCP_SEED_KEY_ENABLE (0)
#endif /* BLT_CONF_H */
/*********************************** end of blt_conf.h *********************************/

7
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/boot.dox Normal file
View File

@ -0,0 +1,7 @@
/**
\defgroup Boot_ARMCM0_S32K14_S32K118EVB_IAR Bootloader
\brief Bootloader.
\ingroup ARMCM0_S32K14_S32K118EVB_IAR
*/

307
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/hooks.c Normal file
View File

@ -0,0 +1,307 @@
/************************************************************************************//**
* \file Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/hooks.c
* \brief Bootloader callback source file.
* \ingroup Boot_ARMCM0_S32K14_S32K118EVB_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
#include "led.h" /* LED driver header */
#include "device_registers.h" /* device registers */
/****************************************************************************************
* B A C K D O O R E N T R Y H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_BACKDOOR_HOOKS_ENABLE > 0)
/************************************************************************************//**
** \brief Initializes the backdoor entry option.
** \return none.
**
****************************************************************************************/
void BackDoorInitHook(void)
{
} /*** end of BackDoorInitHook ***/
/************************************************************************************//**
** \brief Checks if a backdoor entry is requested.
** \return BLT_TRUE if the backdoor entry is requested, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool BackDoorEntryHook(void)
{
/* default implementation always activates the bootloader after a reset */
return BLT_TRUE;
} /*** end of BackDoorEntryHook ***/
#endif /* BOOT_BACKDOOR_HOOKS_ENABLE > 0 */
/****************************************************************************************
* C P U D R I V E R H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0)
/************************************************************************************//**
** \brief Callback that gets called when the bootloader is about to exit and
** hand over control to the user program. This is the last moment that
** some final checking can be performed and if necessary prevent the
** bootloader from activiting the user program.
** \return BLT_TRUE if it is okay to start the user program, BLT_FALSE to keep
** keep the bootloader active.
**
****************************************************************************************/
blt_bool CpuUserProgramStartHook(void)
{
/* additional and optional backdoor entry through the pushbutton (SW2) on the board. to
* force the bootloader to stay active after reset, keep it pressed during reset.
*/
if ((PTD->PDIR & GPIO_PDIR_PDI(1 << 3U)) != 0U)
{
/* pushbutton pressed, so do not start the user program and keep the
* bootloader active instead.
*/
return BLT_FALSE;
}
/* clean up the LED driver */
LedBlinkExit();
/* okay to start the user program */
return BLT_TRUE;
} /*** end of CpuUserProgramStartHook ***/
#endif /* BOOT_CPU_USER_PROGRAM_START_HOOK > 0 */
/****************************************************************************************
* W A T C H D O G D R I V E R H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_COP_HOOKS_ENABLE > 0)
/************************************************************************************//**
** \brief Callback that gets called at the end of the internal COP driver
** initialization routine. It can be used to configure and enable the
** watchdog.
** \return none.
**
****************************************************************************************/
void CopInitHook(void)
{
/* this function is called upon initialization. might as well use it to initialize
* the LED driver. It is kind of a visual watchdog anyways.
*/
LedBlinkInit(100);
} /*** end of CopInitHook ***/
/************************************************************************************//**
** \brief Callback that gets called at the end of the internal COP driver
** service routine. This gets called upon initialization and during
** potential long lasting loops and routine. It can be used to service
** the watchdog to prevent a watchdog reset.
** \return none.
**
****************************************************************************************/
void CopServiceHook(void)
{
/* run the LED blink task. this is a better place to do it than in the main() program
* loop. certain operations such as flash erase can take a long time, which would cause
* a blink interval to be skipped. this function is also called during such operations,
* so no blink intervals will be skipped when calling the LED blink task here.
*/
LedBlinkTask();
} /*** end of CopServiceHook ***/
#endif /* BOOT_COP_HOOKS_ENABLE > 0 */
/****************************************************************************************
* N O N - V O L A T I L E M E M O R Y D R I V E R H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_NVM_HOOKS_ENABLE > 0)
/************************************************************************************//**
** \brief Callback that gets called at the start of the internal NVM driver
** initialization routine.
** \return none.
**
****************************************************************************************/
void NvmInitHook(void)
{
} /*** end of NvmInitHook ***/
/************************************************************************************//**
** \brief Callback that gets called at the start of a firmware update to reinitialize
** the NVM driver.
** \return none.
**
****************************************************************************************/
void NvmReinitHook(void)
{
} /*** end of NvmReinitHook ***/
/************************************************************************************//**
** \brief Callback that gets called at the start of the NVM driver write
** routine. It allows additional memory to be operated on. If the address
** is not within the range of the additional memory, then
** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the data hasn't
** been written yet.
** \param addr Start address.
** \param len Length in bytes.
** \param data Pointer to the data buffer.
** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is
** not within the supported memory range, or BLT_NVM_ERROR is the write
** operation failed.
**
****************************************************************************************/
blt_int8u NvmWriteHook(blt_addr addr, blt_int32u len, blt_int8u *data)
{
return BLT_NVM_NOT_IN_RANGE;
} /*** end of NvmWriteHook ***/
/************************************************************************************//**
** \brief Callback that gets called at the start of the NVM driver erase
** routine. It allows additional memory to be operated on. If the address
** is not within the range of the additional memory, then
** BLT_NVM_NOT_IN_RANGE must be returned to indicate that the memory
** hasn't been erased yet.
** \param addr Start address.
** \param len Length in bytes.
** \return BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is
** not within the supported memory range, or BLT_NVM_ERROR is the erase
** operation failed.
**
****************************************************************************************/
blt_int8u NvmEraseHook(blt_addr addr, blt_int32u len)
{
return BLT_NVM_NOT_IN_RANGE;
} /*** end of NvmEraseHook ***/
/************************************************************************************//**
** \brief Callback that gets called at the end of the NVM programming session.
** \return BLT_TRUE is successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool NvmDoneHook(void)
{
return BLT_TRUE;
} /*** end of NvmDoneHook ***/
#endif /* BOOT_NVM_HOOKS_ENABLE > 0 */
#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0)
/************************************************************************************//**
** \brief Verifies the checksum, which indicates that a valid user program is
** present and can be started.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool NvmVerifyChecksumHook(void)
{
return BLT_TRUE;
} /*** end of NvmVerifyChecksum ***/
/************************************************************************************//**
** \brief Writes a checksum of the user program to non-volatile memory. This is
** performed once the entire user program has been programmed. Through
** the checksum, the bootloader can check if a valid user programming is
** present and can be started.
** \return BLT_TRUE if successful, BLT_FALSE otherwise.
**
****************************************************************************************/
blt_bool NvmWriteChecksumHook(void)
{
return BLT_TRUE;
}
#endif /* BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0 */
/****************************************************************************************
* S E E D / K E Y S E C U R I T Y H O O K F U N C T I O N S
****************************************************************************************/
#if (BOOT_XCP_SEED_KEY_ENABLE > 0)
/************************************************************************************//**
** \brief Provides a seed to the XCP master that will be used for the key
** generation when the master attempts to unlock the specified resource.
** Called by the GET_SEED command.
** \param resource Resource that the seed if requested for (XCP_RES_XXX).
** \param seed Pointer to byte buffer wher the seed will be stored.
** \return Length of the seed in bytes.
**
****************************************************************************************/
blt_int8u XcpGetSeedHook(blt_int8u resource, blt_int8u *seed)
{
/* request seed for unlocking ProGraMming resource */
if ((resource & XCP_RES_PGM) != 0)
{
seed[0] = 0x55;
}
/* return seed length */
return 1;
} /*** end of XcpGetSeedHook ***/
/************************************************************************************//**
** \brief Called by the UNLOCK command and checks if the key to unlock the
** specified resource was correct. If so, then the resource protection
** will be removed.
** \param resource resource to unlock (XCP_RES_XXX).
** \param key pointer to the byte buffer holding the key.
** \param len length of the key in bytes.
** \return 1 if the key was correct, 0 otherwise.
**
****************************************************************************************/
blt_int8u XcpVerifyKeyHook(blt_int8u resource, blt_int8u *key, blt_int8u len)
{
/* suppress compiler warning for unused parameter */
len = len;
/* the example key algorithm in "libseednkey.dll" works as follows:
* - PGM will be unlocked if key = seed - 1
*/
/* check key for unlocking ProGraMming resource */
if ((resource == XCP_RES_PGM) && (key[0] == (0x55-1)))
{
/* correct key received for unlocking PGM resource */
return 1;
}
/* still here so key incorrect */
return 0;
} /*** end of XcpVerifyKeyHook ***/
#endif /* BOOT_XCP_SEED_KEY_ENABLE > 0 */
/*********************************** end of hooks.c ************************************/

716
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/ide/s32k118.dep Normal file
View File

@ -0,0 +1,716 @@
<?xml version="1.0" encoding="UTF-8"?>
<project>
<fileVersion>4</fileVersion>
<fileChecksum>688922450</fileChecksum>
<configuration>
<name>Debug</name>
<outputs>
<file>$PROJ_DIR$\..\lib\startup.c</file>
<file>$PROJ_DIR$\..\main.c</file>
<file>$PROJ_DIR$\..\timer.h</file>
<file>$PROJ_DIR$\..\obj\s32k118.pbd</file>
<file>$PROJ_DIR$\..\boot.c</file>
<file>$PROJ_DIR$\..\obj\timer.xcl</file>
<file>$PROJ_DIR$\..\lib\S32K118_features.h</file>
<file>$PROJ_DIR$\..\lib\startup.h</file>
<file>$PROJ_DIR$\..\startup_S32K118.s</file>
<file>$PROJ_DIR$\..\obj\system_S32K118.xcl</file>
<file>$PROJ_DIR$\..\bin\demoprog_s32k118.out</file>
<file>$PROJ_DIR$\..\led.h</file>
<file>$PROJ_DIR$\..\obj\system_S32K118.__cstat.et</file>
<file>$PROJ_DIR$\..\obj\boot.o</file>
<file>$PROJ_DIR$\..\obj\led.o</file>
<file>$PROJ_DIR$\..\timer.c</file>
<file>$PROJ_DIR$\..\obj\timer.o</file>
<file>$PROJ_DIR$\..\obj\timer.__cstat.et</file>
<file>$PROJ_DIR$\..\obj\led.xcl</file>
<file>$TOOLKIT_DIR$\inc\c\yvals.h</file>
<file>$PROJ_DIR$\..\obj\boot.xcl</file>
<file>$PROJ_DIR$\..\obj\main.o</file>
<file>$PROJ_DIR$\..\lib\system_S32K118.c</file>
<file>$PROJ_DIR$\..\lib\system_S32K118.h</file>
<file>$PROJ_DIR$\..\obj\main.xcl</file>
<file>$PROJ_DIR$\..\header.h</file>
<file>$PROJ_DIR$\..\led.c</file>
<file>$PROJ_DIR$\..\obj\startup.xcl</file>
<file>$PROJ_DIR$\..\obj\startup_S32K118.o</file>
<file>$PROJ_DIR$\..\obj\startup.__cstat.et</file>
<file>$PROJ_DIR$\..\boot.h</file>
<file>$PROJ_DIR$\..\obj\system_S32K118.o</file>
<file>$PROJ_DIR$\..\lib\devassert.h</file>
<file>$PROJ_DIR$\..\lib\device_registers.h</file>
<file>$PROJ_DIR$\..\lib\s32_core_cm0.h</file>
<file>$PROJ_DIR$\..\lib\S32K118.h</file>
<file>$TOOLKIT_DIR$\inc\c\DLib_Defaults.h</file>
<file>$PROJ_DIR$\..\obj\boot.__cstat.et</file>
<file>$TOOLKIT_DIR$\lib\m6M_tl.a</file>
<file>$TOOLKIT_DIR$\inc\c\stdint.h</file>
<file>$TOOLKIT_DIR$\lib\rt6M_tl.a</file>
<file>$PROJ_DIR$\..\S32K118_25_flash.icf</file>
<file>$PROJ_DIR$\..\obj\demoprog_s32k118.map</file>
<file>$TOOLKIT_DIR$\lib\shb_l.a</file>
<file>$TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h</file>
<file>$TOOLKIT_DIR$\inc\c\ycheck.h</file>
<file>$PROJ_DIR$\..\obj\main.__cstat.et</file>
<file>$PROJ_DIR$\..\obj\led.__cstat.et</file>
<file>$PROJ_DIR$\..\bin\demoprog_s32k118.srec</file>
<file>$TOOLKIT_DIR$\inc\c\stdbool.h</file>
<file>$TOOLKIT_DIR$\inc\c\DLib_Product.h</file>
<file>$TOOLKIT_DIR$\lib\dl6M_tln.a</file>
<file>$PROJ_DIR$\..\obj\startup.o</file>
<file>$PROJ_DIR$\..\blt_conf.h</file>
<file>$PROJ_DIR$\..\obj\cpu_comp.__cstat.et</file>
<file>$PROJ_DIR$\..\obj\cpu.__cstat.et</file>
<file>$PROJ_DIR$\..\obj\flash.__cstat.et</file>
<file>$PROJ_DIR$\..\obj\assert.__cstat.et</file>
<file>$PROJ_DIR$\..\obj\can.__cstat.et</file>
<file>$PROJ_DIR$\..\obj\cop.__cstat.et</file>
<file>$PROJ_DIR$\..\obj\net.__cstat.et</file>
<file>$PROJ_DIR$\..\obj\nvm.__cstat.et</file>
<file>$PROJ_DIR$\..\obj\rs232.__cstat.et</file>
<file>$PROJ_DIR$\..\obj\backdoor.__cstat.et</file>
<file>$PROJ_DIR$\..\obj\hooks.__cstat.et</file>
<file>$PROJ_DIR$\..\obj\com.__cstat.et</file>
<file>$PROJ_DIR$\..\obj\file.__cstat.et</file>
<file>$PROJ_DIR$\..\obj\xcp.__cstat.et</file>
<file>$PROJ_DIR$\..\..\..\..\Source\com.c</file>
<file>$PROJ_DIR$\..\..\..\..\Source\ARMCM0_S32K11\nvm.c</file>
<file>$PROJ_DIR$\..\..\..\..\Source\boot.c</file>
<file>$PROJ_DIR$\..\..\..\..\Source\boot.h</file>
<file>$PROJ_DIR$\..\..\..\..\Source\com.h</file>
<file>$PROJ_DIR$\..\..\..\..\Source\file.c</file>
<file>$PROJ_DIR$\..\..\..\..\Source\ARMCM0_S32K11\flash.h</file>
<file>$PROJ_DIR$\..\..\..\..\Source\assert.c</file>
<file>$PROJ_DIR$\..\obj\cpu_comp.xcl</file>
<file>$PROJ_DIR$\..\..\..\..\Source\file.h</file>
<file>$PROJ_DIR$\..\..\..\..\Source\net.c</file>
<file>$PROJ_DIR$\..\..\..\..\Source\net.h</file>
<file>$PROJ_DIR$\..\..\..\..\Source\ARMCM0_S32K11\rs232.c</file>
<file>$PROJ_DIR$\..\..\..\..\Source\ARMCM0_S32K11\types.h</file>
<file>$PROJ_DIR$\..\obj\cpu_comp.o</file>
<file>$PROJ_DIR$\..\..\..\..\Source\can.h</file>
<file>$PROJ_DIR$\..\..\..\..\Source\ARMCM0_S32K11\timer.c</file>
<file>$PROJ_DIR$\..\..\..\..\Source\cop.h</file>
<file>$PROJ_DIR$\..\..\..\..\Source\nvm.h</file>
<file>$PROJ_DIR$\..\..\..\..\Source\ARMCM0_S32K11\cpu.c</file>
<file>$PROJ_DIR$\..\..\..\..\Source\assert.h</file>
<file>$PROJ_DIR$\..\..\..\..\Source\backdoor.c</file>
<file>$PROJ_DIR$\..\..\..\..\Source\backdoor.h</file>
<file>$PROJ_DIR$\..\..\..\..\Source\cpu.h</file>
<file>$PROJ_DIR$\..\..\..\..\Source\cop.c</file>
<file>$PROJ_DIR$\..\..\..\..\Source\ARMCM0_S32K11\can.c</file>
<file>$PROJ_DIR$\..\..\..\..\Source\ARMCM0_S32K11\flash.c</file>
<file>$PROJ_DIR$\..\..\..\..\Source\plausibility.h</file>
<file>$PROJ_DIR$\..\bin\openblt_s32k118.srec</file>
<file>$PROJ_DIR$\..\obj\flash.o</file>
<file>$PROJ_DIR$\..\obj\flash.xcl</file>
<file>$PROJ_DIR$\..\obj\nvm.xcl</file>
<file>$PROJ_DIR$\..\obj\rs232.xcl</file>
<file>$PROJ_DIR$\..\obj\nvm.o</file>
<file>$PROJ_DIR$\..\obj\can.o</file>
<file>$PROJ_DIR$\..\bin\openblt_s32k118.out</file>
<file>$PROJ_DIR$\..\obj\cpu.o</file>
<file>$PROJ_DIR$\..\obj\rs232.o</file>
<file>$PROJ_DIR$\..\obj\can.xcl</file>
<file>$PROJ_DIR$\..\obj\cpu.xcl</file>
<file>$PROJ_DIR$\..\..\..\..\Source\usb.h</file>
<file>$PROJ_DIR$\..\..\..\..\Source\rs232.h</file>
<file>$PROJ_DIR$\..\..\..\..\Source\xcp.c</file>
<file>$PROJ_DIR$\..\hooks.c</file>
<file>$PROJ_DIR$\..\..\..\..\Source\xcp.h</file>
<file>$PROJ_DIR$\..\..\..\..\Source\timer.h</file>
<file>$PROJ_DIR$\..\obj\assert.o</file>
<file>$PROJ_DIR$\..\obj\com.xcl</file>
<file>$PROJ_DIR$\..\obj\net.xcl</file>
<file>$PROJ_DIR$\..\obj\xcp.o</file>
<file>$PROJ_DIR$\..\obj\backdoor.xcl</file>
<file>$PROJ_DIR$\..\obj\backdoor.o</file>
<file>$PROJ_DIR$\..\obj\assert.xcl</file>
<file>$PROJ_DIR$\..\..\..\..\Source\ARMCM0_S32K11\IAR\cpu_comp.c</file>
<file>$PROJ_DIR$\..\obj\com.o</file>
<file>$PROJ_DIR$\..\obj\file.o</file>
<file>$PROJ_DIR$\..\obj\file.xcl</file>
<file>$PROJ_DIR$\..\obj\net.o</file>
<file>$PROJ_DIR$\..\obj\xcp.xcl</file>
<file>$PROJ_DIR$\..\obj\cop.xcl</file>
<file>$PROJ_DIR$\..\obj\cop.o</file>
<file>$PROJ_DIR$\..\obj\hooks.o</file>
<file>$PROJ_DIR$\..\obj\hooks.xcl</file>
<file>$TOOLKIT_DIR$\inc\c\string.h</file>
<file>$PROJ_DIR$\..\obj\openblt_s32k118.map</file>
<file>$TOOLKIT_DIR$\inc\c\ysizet.h</file>
<file>$TOOLKIT_DIR$\inc\c\ctype.h</file>
<file>$TOOLKIT_DIR$\inc\c\DLib_Product_string.h</file>
</outputs>
<file>
<name>[ROOT_NODE]</name>
<outputs>
<tool>
<name>ILINK</name>
<file> 103 132</file>
</tool>
</outputs>
</file>
<file>
<name>$PROJ_DIR$\..\lib\startup.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 52</file>
</tool>
<tool>
<name>__cstat</name>
<file> 29</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 27</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 7 39 45 19 36 44 50 33 34 35 6 32 49</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\main.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 21</file>
</tool>
<tool>
<name>__cstat</name>
<file> 46</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 24</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 71 81 88 53 95 91 85 86 113 90 77 72 112 33 34 35 39 45 19 36 44 50 6 32 49 23</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\boot.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 13</file>
</tool>
<tool>
<name>__cstat</name>
<file> 37</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 20</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 25 53 30 11 2 33 34 35 39 45 19 36 44 50 6 32 49 23</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\startup_S32K118.s</name>
<outputs>
<tool>
<name>AARM</name>
<file> 28</file>
</tool>
</outputs>
</file>
<file>
<name>$PROJ_DIR$\..\bin\demoprog_s32k118.out</name>
<outputs>
<tool>
<name>OBJCOPY</name>
<file> 48</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ILINK</name>
<file> 41 13 14 21 52 28 31 16 43 40 38 51</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\timer.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 16</file>
</tool>
<tool>
<name>__cstat</name>
<file> 17</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 5</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 25 53 30 11 2 33 34 35 39 45 19 36 44 50 6 32 49 23</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\lib\system_S32K118.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 31</file>
</tool>
<tool>
<name>__cstat</name>
<file> 12</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 9</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 33 34 35 39 45 19 36 44 50 6 32 49 23</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\led.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 14</file>
</tool>
<tool>
<name>__cstat</name>
<file> 47</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 18</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 71 81 88 53 95 91 85 86 113 90 77 72 112 11 33 34 35 39 45 19 36 44 50 6 32 49</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\Source\com.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 122</file>
</tool>
<tool>
<name>__cstat</name>
<file> 65</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 115</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 71 81 88 53 95 91 85 86 113 90 77 72 112 83 109</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\Source\ARMCM0_S32K11\nvm.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 101</file>
</tool>
<tool>
<name>__cstat</name>
<file> 61</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 99</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 71 81 88 53 95 91 85 86 113 90 77 72 112 74</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\Source\boot.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 13</file>
</tool>
<tool>
<name>__cstat</name>
<file> 37</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 20</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 71 81 88 53 95 91 85 86 113 90 77 72 112</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\Source\file.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 123</file>
</tool>
<tool>
<name>__cstat</name>
<file> 66</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 124</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 71 81 88 53 95 91 85 86 113 90 77 72 112 131 45 19 36 44 50 133 135 134</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\Source\assert.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 114</file>
</tool>
<tool>
<name>__cstat</name>
<file> 57</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 120</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 71 81 88 53 95 91 85 86 113 90 77 72 112</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\Source\net.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 125</file>
</tool>
<tool>
<name>__cstat</name>
<file> 60</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 116</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 71 81 88 53 95 91 85 86 113 90 77 72 112</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\Source\ARMCM0_S32K11\rs232.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 105</file>
</tool>
<tool>
<name>__cstat</name>
<file> 62</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 100</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 71 81 88 53 95 91 85 86 113 90 77 72 112 33 34 35 39 45 19 36 44 50 6 32 49</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\Source\ARMCM0_S32K11\timer.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 16</file>
</tool>
<tool>
<name>__cstat</name>
<file> 17</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 5</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 71 81 88 53 95 91 85 86 113 90 77 72 112 33 34 35 39 45 19 36 44 50 6 32 49</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\Source\ARMCM0_S32K11\cpu.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 104</file>
</tool>
<tool>
<name>__cstat</name>
<file> 55</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 107</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 71 81 88 53 95 91 85 86 113 90 77 72 112 33 34 35 39 45 19 36 44 50 6 32 49</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\Source\backdoor.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 119</file>
</tool>
<tool>
<name>__cstat</name>
<file> 63</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 118</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 71 81 88 53 95 91 85 86 113 90 77 72 112</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\Source\cop.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 128</file>
</tool>
<tool>
<name>__cstat</name>
<file> 59</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 127</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 71 81 88 53 95 91 85 86 113 90 77 72 112</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\Source\ARMCM0_S32K11\can.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 102</file>
</tool>
<tool>
<name>__cstat</name>
<file> 58</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 106</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 71 81 88 53 95 91 85 86 113 90 77 72 112 33 34 35 39 45 19 36 44 50 6 32 49</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\Source\ARMCM0_S32K11\flash.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 97</file>
</tool>
<tool>
<name>__cstat</name>
<file> 56</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 98</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 71 81 88 53 95 91 85 86 113 90 77 72 112 33 34 35 39 45 19 36 44 50 6 32 49</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\bin\openblt_s32k118.out</name>
<outputs>
<tool>
<name>OBJCOPY</name>
<file> 96</file>
</tool>
<tool>
<name>ILINK</name>
<file> 132</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ILINK</name>
<file> 41 114 119 13 102 122 128 104 82 123 97 129 14 21 125 101 105 52 28 31 16 117 43 40 38 51</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\Source\xcp.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 117</file>
</tool>
<tool>
<name>__cstat</name>
<file> 67</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 126</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 71 81 88 53 95 91 85 86 113 90 77 72 112</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\hooks.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 129</file>
</tool>
<tool>
<name>__cstat</name>
<file> 64</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 130</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 71 81 88 53 95 91 85 86 113 90 77 72 112 11 33 34 35 39 45 19 36 44 50 6 32 49</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\..\Source\ARMCM0_S32K11\IAR\cpu_comp.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 82</file>
</tool>
<tool>
<name>__cstat</name>
<file> 54</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 76</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 71 81 88 53 95 91 85 86 113 90 77 72 112</file>
</tool>
</inputs>
</file>
<forcedrebuild>
<name>$PROJ_DIR$\..\bin\demoprog_s32k118.out</name>
<tool>OBJCOPY</tool>
</forcedrebuild>
</configuration>
<configuration>
<name>Release</name>
<outputs />
<forcedrebuild>
<name>[MULTI_TOOL]</name>
<tool>ILINK</tool>
</forcedrebuild>
</configuration>
</project>

2966
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/ide/s32k118.ewd Normal file
View File

File diff suppressed because it is too large Load Diff

2266
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/ide/s32k118.ewp Normal file
View File

File diff suppressed because it is too large Load Diff

2528
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/ide/s32k118.ewt Normal file
View File

File diff suppressed because it is too large Load Diff

7
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/ide/s32k118.eww Normal file
View File

@ -0,0 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<workspace>
<project>
<path>$WS_DIR$\s32k118.ewp</path>
</project>
<batchBuild />
</workspace>

108
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/led.c Normal file
View File

@ -0,0 +1,108 @@
/************************************************************************************//**
* \file Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/led.c
* \brief LED driver source file.
* \ingroup Boot_ARMCM0_S32K14_S32K118EVB_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
#include "led.h" /* module header */
#include "device_registers.h" /* device registers */
/****************************************************************************************
* Local data declarations
****************************************************************************************/
/** \brief Holds the desired LED blink interval time. */
static blt_int16u ledBlinkIntervalMs;
/************************************************************************************//**
** \brief Initializes the LED blink driver.
** \param interval_ms Specifies the desired LED blink interval time in milliseconds.
** \return none.
**
****************************************************************************************/
void LedBlinkInit(blt_int16u interval_ms)
{
/* LED GPIO pin configuration. PE8 = GPIO, MUX = ALT1. */
PORTE->PCR[8] = PORT_PCR_MUX(1);
/* Configure Port E pin 8 GPIO as digital output. */
PTE->PDDR |= GPIO_PDDR_PDD(1 << 8U);
/* Turn the LED off on Port E pin 8. */
PTE->PCOR |= GPIO_PSOR_PTSO(1 << 8U);
/* store the interval time between LED toggles */
ledBlinkIntervalMs = interval_ms;
} /*** end of LedBlinkInit ***/
/************************************************************************************//**
** \brief Task function for blinking the LED as a fixed timer interval.
** \return none.
**
****************************************************************************************/
void LedBlinkTask(void)
{
static blt_bool ledOn = BLT_FALSE;
static blt_int32u nextBlinkEvent = 0;
/* check for blink event */
if (TimerGet() >= nextBlinkEvent)
{
/* toggle the LED state */
if (ledOn == BLT_FALSE)
{
ledOn = BLT_TRUE;
/* Turn the LED on. */
PTE->PSOR |= GPIO_PSOR_PTSO(1 << 8U);
}
else
{
ledOn = BLT_FALSE;
/* Turn the LED off. */
PTE->PCOR |= GPIO_PSOR_PTSO(1 << 8U);
}
/* schedule the next blink event */
nextBlinkEvent = TimerGet() + ledBlinkIntervalMs;
}
} /*** end of LedBlinkTask ***/
/************************************************************************************//**
** \brief Cleans up the LED blink driver. This is intended to be used upon program
** exit.
** \return none.
**
****************************************************************************************/
void LedBlinkExit(void)
{
/* Turn the LED off. */
PTE->PCOR |= GPIO_PSOR_PTSO(1 << 8U);
} /*** end of LedBlinkExit ***/
/*********************************** end of led.c **************************************/

40
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/led.h Normal file
View File

@ -0,0 +1,40 @@
/************************************************************************************//**
* \file Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/led.h
* \brief LED driver header file.
* \ingroup Boot_ARMCM0_S32K14_S32K118EVB_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef LED_H
#define LED_H
/****************************************************************************************
* Function prototypes
****************************************************************************************/
void LedBlinkInit(blt_int16u interval_ms);
void LedBlinkTask(void);
void LedBlinkExit(void);
#endif /* LED_H */
/*********************************** end of led.h **************************************/

10438
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/lib/S32K118.h Normal file
View File

File diff suppressed because it is too large Load Diff

1302
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/lib/S32K118_features.h Normal file
View File

File diff suppressed because it is too large Load Diff

84
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/lib/devassert.h Normal file
View File

@ -0,0 +1,84 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef DEVASSERT_H
#define DEVASSERT_H
#include <stdbool.h>
/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 2.5, global macro not referenced.
* The macro is defined to be used by drivers to validate input parameters and can be disabled.
*
* @section [global]
* Violates MISRA 2012 Advisory Directive 4.9, Function-like macro defined.
* The macros are used to validate input parameters to driver functions.
*
*/
/**
\page Error_detection_and_reporting Error detection and reporting
S32 SDK drivers can use a mechanism to validate data coming from upper software layers (application code) by performing
a number of checks on input parameters' range or other invariants that can be statically checked (not dependent on
runtime conditions). A failed validation is indicative of a software bug in application code, therefore it is important
to use this mechanism during development.
The validation is performed by using DEV_ASSERT macro.
A default implementation of this macro is provided in this file. However, application developers can provide their own
implementation in a custom file. This requires defining the CUSTOM_DEVASSERT symbol with the specific file name in the
project configuration (for example: -DCUSTOM_DEVASSERT="custom_devassert.h")
The default implementation accommodates two behaviors, based on DEV_ERROR_DETECT symbol:
- When DEV_ERROR_DETECT symbol is defined in the project configuration (for example: -DDEV_ERROR_DETECT), the validation
performed by the DEV_ASSERT macro is enabled, and a failed validation triggers a software breakpoint and further execution is
prevented (application spins in an infinite loop)
This configuration is recommended for development environments, as it prevents further execution and allows investigating
potential problems from the point of error detection.
- When DEV_ERROR_DETECT symbol is not defined, the DEV_ASSERT macro is implemented as no-op, therefore disabling all validations.
This configuration can be used to eliminate the overhead of development-time checks.
It is the application developer's responsibility to decide the error detection strategy for production code: one can opt to
disable development-time checking altogether (by not defining DEV_ERROR_DETECT symbol), or one can opt to keep the checks
in place and implement a recovery mechanism in case of a failed validation, by defining CUSTOM_DEVASSERT to point
to the file containing the custom implementation.
*/
#if defined (CUSTOM_DEVASSERT)
/* If the CUSTOM_DEVASSERT symbol is defined, then add the custom implementation */
#include CUSTOM_DEVASSERT
#elif defined (DEV_ERROR_DETECT)
/* Implement default assert macro */
static inline void DevAssert(volatile bool x)
{
if(x) { } else { BKPT_ASM; for(;;) {} }
}
#define DEV_ASSERT(x) DevAssert(x)
#else
/* Assert macro does nothing */
#define DEV_ASSERT(x) ((void)0)
#endif
#endif /* DEVASSERT_H */
/*******************************************************************************
* EOF
******************************************************************************/

67
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/lib/device_registers.h Normal file
View File

@ -0,0 +1,67 @@
/*
** ###################################################################
** Abstract:
** Common include file for CMSIS register access layer headers.
**
** Copyright (c) 2015 Freescale Semiconductor, Inc.
** Copyright 2016-2017 NXP
** All rights reserved.
**
** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
** THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.nxp.com
** mail: support@nxp.com
** ###################################################################
*/
#ifndef DEVICE_REGISTERS_H
#define DEVICE_REGISTERS_H
/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 2.5, global macro not referenced.
* The macro defines the device currently in use and may be used by components for specific checks.
*
*/
/*
* Include the cpu specific register header files.
*
* The CPU macro should be declared in the project or makefile.
*/
#if defined(CPU_S32K118)
#define S32K11x_SERIES
/* Specific core definitions */
#include "s32_core_cm0.h"
/* Register definitions */
#include "S32K118.h"
/* CPU specific feature definitions */
#include "S32K118_features.h"
#else
#error "No valid CPU defined!"
#endif
#include "devassert.h"
#endif /* DEVICE_REGISTERS_H */
/*******************************************************************************
* EOF
******************************************************************************/

198
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/lib/s32_core_cm0.h Normal file
View File

@ -0,0 +1,198 @@
/*
* Copyright (c) 2015-2016 Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/*!
* @file s32_core_cm0.h
*
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Directive 4.9, Function-like macro
* Function-like macros are used instead of inline functions in order to ensure
* that the performance will not be decreased if the functions will not be
* inlined by the compiler.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 2.5, Global macro not referenced.
* The macros defined are used only on some of the drivers, so this might be reported
* when the analysis is made only on one driver.
*/
/*
* Tool Chains:
* GNUC flag is defined also by ARM compiler - it shows the current major version of the compatible GCC version
* __GNUC__ : GNU Compiler Collection
* __ghs__ : Green Hills ARM Compiler
* __ICCARM__ : IAR ARM Compiler
* __DCC__ : Wind River Diab Compiler
* __ARMCC_VERSION : ARM Compiler
*/
#if !defined (CORE_CM0_H)
#define CORE_CM0_H
#ifdef __cplusplus
extern "C" {
#endif
/** \brief BKPT_ASM
*
* Macro to be used to trigger an debug interrupt
*/
#if defined ( __DCC__ )
#define BKPT_ASM __asm ("BKPT 0\n\t")
#else
#define BKPT_ASM __asm ("BKPT #0\n\t")
#endif
/** \brief Enable interrupts
*/
#if defined (__GNUC__)
#define ENABLE_INTERRUPTS() __asm volatile ("cpsie i" : : : "memory");
#elif defined ( __DCC__ )
#define ENABLE_INTERRUPTS() __asm (".short 0xb662");
#else
#define ENABLE_INTERRUPTS() __asm("cpsie i")
#endif
/** \brief Disable interrupts
*/
#if defined (__GNUC__)
#define DISABLE_INTERRUPTS() __asm volatile ("cpsid i" : : : "memory");
#elif defined ( __DCC__ )
#define DISABLE_INTERRUPTS() __asm (".short 0xb672");
#else
#define DISABLE_INTERRUPTS() __asm("cpsid i")
#endif
/** \brief Enter low-power standby state
* WFI (Wait For Interrupt) makes the processor suspend execution (Clock is stopped) until an IRQ interrupts.
*/
#if defined (__GNUC__)
#define STANDBY() __asm volatile ("wfi")
#elif defined ( __DCC__ )
#define STANDBY() __asm (".short 0xbf30");
#else
#define STANDBY() __asm ("wfi")
#endif
/** \brief No-op
*/
#define NOP() __asm volatile ("nop")
/** \brief Reverse byte order in a word.
* ARM Documentation Cortex-M0 Devices Generic User Guide
* Accordingly to 3.5.7. REV, REV16, and REVSH
* Restriction "This function requires low registers R0-R7 register"
*/
#if defined (__GNUC__) || defined (__ICCARM__) || defined (__ARMCC_VERSION)
#define REV_BYTES_32(a, b) __asm volatile ("rev %0, %1" : "=l" (b) : "l" (a))
#elif defined (__ghs__)
#define REV_BYTES_32(a, b) __asm volatile ("rev %0, %1" : "=r" (b) : "r" (a))
#else
#define REV_BYTES_32(a, b) (b = ((a & 0xFF000000U) >> 24U) | ((a & 0xFF0000U) >> 8U) \
| ((a & 0xFF00U) << 8U) | ((a & 0xFFU) << 24U))
#endif
/** \brief Reverse byte order in each halfword independently.
* ARM Documentation Cortex-M0 Devices Generic User Guide
* Accordingly to 3.5.7. REV, REV16, and REVSH
* Restriction "This function requires low registers R0-R7 register"
*/
#if defined (__GNUC__) || defined (__ICCARM__) || defined (__ARMCC_VERSION)
#define REV_BYTES_16(a, b) __asm volatile ("rev16 %0, %1" : "=l" (b) : "l" (a))
#elif defined (__ghs__)
#define REV_BYTES_16(a, b) __asm volatile ("rev16 %0, %1" : "=r" (b) : "r" (a))
#else
#define REV_BYTES_16(a, b) (b = ((a & 0xFF000000U) >> 8U) | ((a & 0xFF0000U) << 8U) \
| ((a & 0xFF00U) >> 8U) | ((a & 0xFFU) << 8U))
#endif
/** \brief Places a function in RAM.
*/
#if defined ( __GNUC__ ) || defined (__ARMCC_VERSION)
#define START_FUNCTION_DECLARATION_RAMSECTION
#define END_FUNCTION_DECLARATION_RAMSECTION __attribute__((section (".code_ram")));
#elif defined ( __ghs__ )
#define START_FUNCTION_DECLARATION_RAMSECTION _Pragma("ghs callmode=far")
#define END_FUNCTION_DECLARATION_RAMSECTION __attribute__((section (".code_ram")));\
_Pragma("ghs callmode=default")
#elif defined ( __ICCARM__ )
#define START_FUNCTION_DECLARATION_RAMSECTION __ramfunc
#define END_FUNCTION_DECLARATION_RAMSECTION ;
#elif defined ( __DCC__ )
#define START_FUNCTION_DECLARATION_RAMSECTION _Pragma("section CODE \".code_ram\" \"\" far-absolute") \
_Pragma("use_section CODE")
#define END_FUNCTION_DECLARATION_RAMSECTION ; \
_Pragma("section CODE \".text\"")
#else
/* Keep compatibility with software analysis tools */
#define START_FUNCTION_DECLARATION_RAMSECTION
#define END_FUNCTION_DECLARATION_RAMSECTION ;
#endif
/* For GCC, IAR, GHS, Diab and ARMC there is no need to specify the section when
defining a function, it is enough to specify it at the declaration. This
also enables compatibility with software analysis tools. */
#define START_FUNCTION_DEFINITION_RAMSECTION
#define END_FUNCTION_DEFINITION_RAMSECTION
#if defined (__ICCARM__)
#define DISABLE_CHECK_RAMSECTION_FUNCTION_CALL _Pragma("diag_suppress=Ta022")
#define ENABLE_CHECK_RAMSECTION_FUNCTION_CALL _Pragma("diag_default=Ta022")
#else
#define DISABLE_CHECK_RAMSECTION_FUNCTION_CALL
#define ENABLE_CHECK_RAMSECTION_FUNCTION_CALL
#endif
/** \brief Get Core ID
*
* GET_CORE_ID returns the processor identification number for cm0
*/
#define GET_CORE_ID() 0U
/** \brief Data alignment.
*/
#if defined ( __GNUC__ ) || defined ( __ghs__ ) || defined ( __DCC__ ) || defined (__ARMCC_VERSION)
#define ALIGNED(x) __attribute__((aligned(x)))
#elif defined ( __ICCARM__ )
#define stringify(s) tostring(s)
#define tostring(s) #s
#define ALIGNED(x) _Pragma(stringify(data_alignment=x))
#else
/* Keep compatibility with software analysis tools */
#define ALIGNED(x)
#endif
/** \brief Endianness.
*/
#define CORE_LITTLE_ENDIAN
#ifdef __cplusplus
}
#endif
#endif /* CORE_CM0_H */
/*******************************************************************************
* EOF
******************************************************************************/

248
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/lib/startup.c Normal file
View File

@ -0,0 +1,248 @@
/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* Copyright 2016-2018 NXP
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block
* scope if its identifier only appears in a single function.
* All variables with this problem are defined in the linker files.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 8.11, When an array with external linkage
* is declared, its size should be explicitly specified.
* The size of the arrays can not be explicitly determined.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed
* between a pointer to object and an integer type.
* The cast is required to initialize a pointer with an unsigned int define,
* representing an address.
*
* @section [global]
* Violates MISRA 2012 Required Rule 11.6, A cast shall not be performed
* between pointer to void and an arithmetic type.
* The cast is required to initialize a pointer with an unsigned int define,
* representing an address.
*
* @section [global]
* Violates MISRA 2012 Required Rule 2.1, A project shall not contain unreachable
* code.
* The condition compares two address defined in linker files that can be different.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 8.7, External could be made static.
* Function is defined for usage by application code.
*
* @section [global]
* Violates MISRA 2012 Mandatory Rule 17.3, Symbol 'MFSPR' undeclared, assumed
* to return int.
* This is an e200 Power Architecture Assembly instruction used to retrieve
* the core number.
*
*/
#include "startup.h"
#include <stdint.h>
/*******************************************************************************
* Static Variables
******************************************************************************/
static volatile uint32_t * const s_vectors[NUMBER_OF_CORES] = FEATURE_INTERRUPT_INT_VECTORS;
/*******************************************************************************
* Code
******************************************************************************/
/*FUNCTION**********************************************************************
*
* Function Name : init_data_bss
* Description : Make necessary initializations for RAM.
* - Copy the vector table from ROM to RAM.
* - Copy initialized data from ROM to RAM.
* - Copy code that should reside in RAM from ROM
* - Clear the zero-initialized data section.
*
* Tool Chains:
* __GNUC__ : GNU Compiler Collection
* __ghs__ : Green Hills ARM Compiler
* __ICCARM__ : IAR ARM Compiler
* __DCC__ : Wind River Diab Compiler
* __ARMCC_VERSION : ARMC Compiler
*
* Implements : init_data_bss_Activity
*END**************************************************************************/
void init_data_bss(void)
{
uint32_t n;
uint8_t coreId;
/* For ARMC we are using the library method of initializing DATA, Custom Section and
* Code RAM sections so the below variables are not needed */
#if !defined(__ARMCC_VERSION)
/* Declare pointers for various data sections. These pointers
* are initialized using values pulled in from the linker file */
uint8_t * data_ram;
uint8_t * code_ram;
uint8_t * bss_start;
uint8_t * custom_ram;
const uint8_t * data_rom, * data_rom_end;
const uint8_t * code_rom, * code_rom_end;
const uint8_t * bss_end;
const uint8_t * custom_rom, * custom_rom_end;
#endif
/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
#if defined(__ARMCC_VERSION)
extern uint32_t __RAM_VECTOR_TABLE_SIZE;
extern uint32_t __VECTOR_ROM;
extern uint32_t __VECTOR_RAM;
#else
extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
extern uint32_t __VECTOR_TABLE[];
extern uint32_t __VECTOR_RAM[];
#endif
/* Get section information from linker files */
#if defined(__ICCARM__)
/* Data */
data_ram = __section_begin(".data");
data_rom = __section_begin(".data_init");
data_rom_end = __section_end(".data_init");
/* CODE RAM */
#pragma section = "__CODE_ROM"
#pragma section = "__CODE_RAM"
code_ram = __section_begin("__CODE_RAM");
code_rom = __section_begin("__CODE_ROM");
code_rom_end = __section_end("__CODE_ROM");
/* BSS */
bss_start = __section_begin(".bss");
bss_end = __section_end(".bss");
custom_ram = __section_begin(".customSection");
custom_rom = __section_begin(".customSection_init");
custom_rom_end = __section_end(".customSection_init");
#elif defined (__ARMCC_VERSION)
/* VECTOR TABLE*/
uint8_t * vector_table_size = (uint8_t *)__RAM_VECTOR_TABLE_SIZE;
uint32_t * vector_rom = (uint32_t *)__VECTOR_ROM;
uint32_t * vector_ram = (uint32_t *)__VECTOR_RAM;
#else
extern uint32_t __DATA_ROM[];
extern uint32_t __DATA_RAM[];
extern uint32_t __DATA_END[];
extern uint32_t __CODE_RAM[];
extern uint32_t __CODE_ROM[];
extern uint32_t __CODE_END[];
extern uint32_t __BSS_START[];
extern uint32_t __BSS_END[];
extern uint32_t __CUSTOM_ROM[];
extern uint32_t __CUSTOM_END[];
/* Data */
data_ram = (uint8_t *)__DATA_RAM;
data_rom = (uint8_t *)__DATA_ROM;
data_rom_end = (uint8_t *)__DATA_END;
/* CODE RAM */
code_ram = (uint8_t *)__CODE_RAM;
code_rom = (uint8_t *)__CODE_ROM;
code_rom_end = (uint8_t *)__CODE_END;
/* BSS */
bss_start = (uint8_t *)__BSS_START;
bss_end = (uint8_t *)__BSS_END;
/* Custom section */
custom_ram = CUSTOMSECTION_SECTION_START;
custom_rom = (uint8_t *)__CUSTOM_ROM;
custom_rom_end = (uint8_t *)__CUSTOM_END;
#endif
#if !defined(__ARMCC_VERSION)
/* Copy initialized data from ROM to RAM */
while (data_rom_end != data_rom)
{
*data_ram = *data_rom;
data_ram++;
data_rom++;
}
/* Copy functions from ROM to RAM */
while (code_rom_end != code_rom)
{
*code_ram = *code_rom;
code_ram++;
code_rom++;
}
/* Clear the zero-initialized data section */
while(bss_end != bss_start)
{
*bss_start = 0;
bss_start++;
}
/* Copy customsection rom to ram */
while(custom_rom_end != custom_rom)
{
*custom_ram = *custom_rom;
custom_rom++;
custom_ram++;
}
#endif
coreId = (uint8_t)GET_CORE_ID();
#if defined (__ARMCC_VERSION)
/* Copy the vector table from ROM to RAM */
/* Workaround */
for (n = 0; n < (((uint32_t)(vector_table_size))/sizeof(uint32_t)); n++)
{
vector_ram[n] = vector_rom[n];
}
/* Point the VTOR to the position of vector table */
*s_vectors[coreId] = (uint32_t) __VECTOR_RAM;
#else
/* Check if VECTOR_TABLE copy is needed */
if (__VECTOR_RAM != __VECTOR_TABLE)
{
/* Copy the vector table from ROM to RAM */
for (n = 0; n < (((uint32_t)__RAM_VECTOR_TABLE_SIZE)/sizeof(uint32_t)); n++)
{
__VECTOR_RAM[n] = __VECTOR_TABLE[n];
}
/* Point the VTOR to the position of vector table */
*s_vectors[coreId] = (uint32_t)__VECTOR_RAM;
}
else
{
/* Point the VTOR to the position of vector table */
*s_vectors[coreId] = (uint32_t)__VECTOR_TABLE;
}
#endif
}
/*******************************************************************************
* EOF
******************************************************************************/

133
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/lib/startup.h Normal file
View File

@ -0,0 +1,133 @@
/*
* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
* Copyright 2016-2019 NXP
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef STARTUP_H
#define STARTUP_H
#include <stdint.h>
#include "device_registers.h"
/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 2.5, Local macro not referenced.
* The defined macro is used as include guard.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block
* scope if its identifier only appears in a single function.
* All variables with this problem are defined in the linker files.
*
*/
/*******************************************************************************
* API
******************************************************************************/
/*!
* @brief define symbols that specific start and end addres of some basic sections.
*/
#if (defined(S32K14x_SERIES) || defined(S32K11x_SERIES) || defined(S32V234_SERIES) || defined(MPC574x_SERIES) || defined(S32R_SERIES) || defined(S32MTV_SERIES) || defined(SJA1110_SERIES)) || defined (S32K144W_M4_SERIES)
#if (defined(__ICCARM__))
#define INTERRUPTS_SECTION_START __section_begin(".intvec")
#define INTERRUPTS_SECTION_END __section_end(".intvec")
#define BSS_SECTION_START __section_begin(".bss")
#define BSS_SECTION_END __section_end(".bss")
#define DATA_SECTION_START __section_begin(".data")
#define DATA_SECTION_END __section_end(".data")
#define CUSTOMSECTION_SECTION_START __section_begin(".customSection")
#define CUSTOMSECTION_SECTION_END __section_end(".customSection")
#define CODE_RAM_SECTION_START __section_begin("__CODE_RAM")
#define CODE_RAM_SECTION_END __section_end("__CODE_RAM")
#define DATA_INIT_SECTION_START __section_begin(".data_init")
#define DATA_INIT_SECTION_END __section_end(".data_init")
#define CODE_ROM_SECTION_START __section_begin("__CODE_ROM")
#define CODE_ROM_SECTION_END __section_end("__CODE_ROM")
#elif (defined(__ARMCC_VERSION))
#define INTERRUPTS_SECTION_START (uint8_t *)__VECTOR_ROM_START
#define INTERRUPTS_SECTION_END (uint8_t *)__VECTOR_ROM_END
#define BSS_SECTION_START (uint8_t *)__BSS_START
#define BSS_SECTION_END (uint8_t *)__BSS_END
#define DATA_SECTION_START (uint8_t *)__DATA_RAM_START
#define DATA_SECTION_END (uint8_t *)__DATA_RAM_END
#define CUSTOMSECTION_SECTION_START (uint8_t *)__CUSTOM_SECTION_START
#define CUSTOMSECTION_SECTION_END (uint8_t *)__CUSTOM_SECTION_END
#define CODE_RAM_SECTION_START (uint8_t *)__CODE_RAM_START
#define CODE_RAM_SECTION_END (uint8_t *)__CODE_RAM_END
extern uint32_t __VECTOR_ROM_START;
extern uint32_t __VECTOR_ROM_END;
extern uint32_t __BSS_START;
extern uint32_t __BSS_END;
extern uint32_t __DATA_RAM_START;
extern uint32_t __DATA_RAM_END;
extern uint32_t __CUSTOM_SECTION_START;
extern uint32_t __CUSTOM_SECTION_END;
extern uint32_t __CODE_RAM_START;
extern uint32_t __CODE_RAM_END;
#else
#define INTERRUPTS_SECTION_START (uint8_t *)&__interrupts_start__
#define INTERRUPTS_SECTION_END (uint8_t *)&__interrupts_end__
#define BSS_SECTION_START (uint8_t *)&__bss_start__
#define BSS_SECTION_END (uint8_t *)&__bss_end__
#define DATA_SECTION_START (uint8_t *)&__data_start__
#define DATA_SECTION_END (uint8_t *)&__data_end__
#define CUSTOMSECTION_SECTION_START (uint8_t *)&__customSection_start__
#define CUSTOMSECTION_SECTION_END (uint8_t *)&__customSection_end__
#define CODE_RAM_SECTION_START (uint8_t *)&__code_ram_start__
#define CODE_RAM_SECTION_END (uint8_t *)&__code_ram_end__
extern uint32_t __interrupts_start__;
extern uint32_t __interrupts_end__;
extern uint32_t __bss_start__;
extern uint32_t __bss_end__;
extern uint32_t __data_start__;
extern uint32_t __data_end__;
extern uint32_t __customSection_start__;
extern uint32_t __customSection_end__;
extern uint32_t __code_ram_start__;
extern uint32_t __code_ram_end__;
#endif
#endif
#if (defined(__ICCARM__))
#pragma section = ".data"
#pragma section = ".data_init"
#pragma section = ".bss"
#pragma section = ".intvec"
#pragma section = ".customSection"
#pragma section = ".customSection_init"
#pragma section = "__CODE_RAM"
#pragma section = "__CODE_ROM"
#endif
/*!
* @brief Make necessary initializations for RAM.
*
* - Copy initialized data from ROM to RAM.
* - Clear the zero-initialized data section.
* - Copy the vector table from ROM to RAM. This could be an option.
*/
void init_data_bss(void);
#endif /* STARTUP_H*/
/*******************************************************************************
* EOF
******************************************************************************/

176
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/lib/system_S32K118.c Normal file
View File

@ -0,0 +1,176 @@
/*
* Copyright 2017-2018 NXP
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 8.9, An object should be defined at block
* scope if its identifier only appears in a single function.
* An object with static storage duration declared at block scope cannot be
* accessed directly from outside the block.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 11.4, A conversion should not be performed
* between a pointer to object and an integer type.
* The cast is required to initialize a pointer with an unsigned int define,
* representing an address.
*
* @section [global]
* Violates MISRA 2012 Required Rule 11.6, A cast shall not be performed
* between pointer to void and an arithmetic type.
* The cast is required to initialize a pointer with an unsigned int define,
* representing an address.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 8.7, External could be made static.
* Function is defined for usage by application code.
*
*/
#include "device_registers.h"
#include "system_S32K118.h"
#include "stdbool.h"
/* ----------------------------------------------------------------------------
-- Core clock
---------------------------------------------------------------------------- */
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
/*FUNCTION**********************************************************************
*
* Function Name : SystemInit
* Description : This function disables the watchdog, enables FPU
* and the power mode protection if the corresponding feature macro
* is enabled. SystemInit is called from startup_device file.
*
* Implements : SystemInit_Activity
*END**************************************************************************/
void SystemInit(void)
{
/**************************************************************************/
/* WDOG DISABLE*/
/**************************************************************************/
#if (DISABLE_WDOG)
/* Write of the WDOG unlock key to CNT register, must be done in order to allow any modifications*/
WDOG->CNT = (uint32_t ) FEATURE_WDOG_UNLOCK_VALUE;
/* The dummy read is used in order to make sure that the WDOG registers will be configured only
* after the write of the unlock value was completed. */
(void)WDOG->CNT;
/* Initial write of WDOG configuration register:
* enables support for 32-bit refresh/unlock command write words,
* clock select from LPO, update enable, watchdog disabled */
WDOG->CS = (uint32_t ) ( (1UL << WDOG_CS_CMD32EN_SHIFT) |
(FEATURE_WDOG_CLK_FROM_LPO << WDOG_CS_CLK_SHIFT) |
(0U << WDOG_CS_EN_SHIFT) |
(1U << WDOG_CS_UPDATE_SHIFT) );
/* Configure timeout */
WDOG->TOVAL = (uint32_t )0xFFFF;
#endif /* (DISABLE_WDOG) */
}
/*FUNCTION**********************************************************************
*
* Function Name : SystemCoreClockUpdate
* Description : This function must be called whenever the core clock is changed
* during program execution. It evaluates the clock register settings and calculates
* the current core clock.
*
* Implements : SystemCoreClockUpdate_Activity
*END**************************************************************************/
void SystemCoreClockUpdate(void)
{
uint32_t SCGOUTClock = 0U; /* Variable to store output clock frequency of the SCG module */
uint32_t regValue; /* Temporary variable */
uint32_t divider;
bool validSystemClockSource = true;
divider = ((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1U;
switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT)
{
case 0x1:
/* System OSC */
SCGOUTClock = CPU_XTAL_CLK_HZ;
break;
case 0x2:
/* Slow IRC */
regValue = (SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT;
if (regValue != 0UL)
{
SCGOUTClock = FEATURE_SCG_SIRC_HIGH_RANGE_FREQ;
}
else
{
validSystemClockSource = false;
}
break;
case 0x3:
/* Fast IRC */
regValue = (SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT;
if (regValue == 0x0UL)
{
SCGOUTClock = FEATURE_SCG_FIRC_FREQ0;
}
else
{
validSystemClockSource = false;
}
break;
default:
validSystemClockSource = false;
break;
}
if (validSystemClockSource == true)
{
SystemCoreClock = (SCGOUTClock / divider);
}
}
/*FUNCTION**********************************************************************
*
* Function Name : SystemSoftwareReset
* Description : This function is used to initiate a system reset
*
* Implements : SystemSoftwareReset_Activity
*END**************************************************************************/
void SystemSoftwareReset(void)
{
uint32_t regValue;
/* Read Application Interrupt and Reset Control Register */
regValue = S32_SCB->AIRCR;
/* Clear register key */
regValue &= ~( S32_SCB_AIRCR_VECTKEY_MASK);
/* Configure System reset request bit and Register Key */
regValue |= S32_SCB_AIRCR_VECTKEY(FEATURE_SCB_VECTKEY);
regValue |= S32_SCB_AIRCR_SYSRESETREQ(0x1u);
/* Write computed register value */
S32_SCB->AIRCR = regValue;
}
/*******************************************************************************
* EOF
******************************************************************************/

105
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/lib/system_S32K118.h Normal file
View File

@ -0,0 +1,105 @@
/*
* Copyright 2017-2018 NXP
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
/*! @addtogroup soc_support_S32K118*/
/*! @{*/
/*!
* @file system_S32K118.h
* @brief Device specific configuration file for S32K118
*/
#ifndef SYSTEM_S32K118_H_
#define SYSTEM_S32K118_H_ /**< Symbol preventing repeated inclusion */
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/******************************************************************************
* CPU Settings.
*****************************************************************************/
/* Watchdog disable */
#ifndef DISABLE_WDOG
#define DISABLE_WDOG 1
#endif
/* Value of the external crystal or oscillator clock frequency in Hz */
#ifndef CPU_XTAL_CLK_HZ
#define CPU_XTAL_CLK_HZ 8000000u
#endif
/* Value of the fast internal oscillator clock frequency in Hz */
#ifndef CPU_INT_FAST_CLK_HZ
#define CPU_INT_FAST_CLK_HZ 48000000u
#endif
/* Default System clock value */
#ifndef DEFAULT_SYSTEM_CLOCK
#define DEFAULT_SYSTEM_CLOCK 48000000u
#endif
/**
* @brief System clock frequency (core clock)
*
* The system clock frequency supplied to the SysTick timer and the processor
* core clock. This variable can be used by the user application to setup the
* SysTick timer or configure other parameters. It may also be used by debugger to
* query the frequency of the debug timer or configure the trace clock speed
* SystemCoreClock is initialized with a correct predefined value.
*/
extern uint32_t SystemCoreClock;
/**
* @brief Setup the SoC.
*
* This function disables the watchdog.
* if the corresponding feature macro is enabled.
* SystemInit is called from startup_device file.
*/
void SystemInit(void);
/**
* @brief Updates the SystemCoreClock variable.
*
* It must be called whenever the core clock is changed during program
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
* the current core clock.
* This function must be called when user does not want to use clock manager component.
* If clock manager is used, the CLOCK_SYS_GetFreq function must be used with CORE_CLOCK
* parameter.
*
*/
void SystemCoreClockUpdate(void);
/**
* @brief Initiates a system reset.
*
* This function is used to initiate a system reset
*/
void SystemSoftwareReset(void);
#ifdef __cplusplus
}
#endif
/*! @}*/
#endif /* #if !defined(SYSTEM_S32K118_H_) */

186
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/main.c Normal file
View File

@ -0,0 +1,186 @@
/************************************************************************************//**
* \file Demo/ARMCM0_S32K14_S32K118EVB_GCC/Boot/main.c
* \brief Bootloader application source file.
* \ingroup Boot_ARMCM0_S32K14_S32K118EVB_GCC
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "boot.h" /* bootloader generic header */
#include "device_registers.h" /* device registers */
#include "system_S32K118.h" /* device sconfiguration */
/****************************************************************************************
* Function prototypes
****************************************************************************************/
static void Init(void);
static void SystemClockConfig(void);
/************************************************************************************//**
** \brief This is the entry point for the bootloader application and is called
** by the reset interrupt vector after the C-startup routines executed.
** \return none.
**
****************************************************************************************/
void main(void)
{
/* Initialize the microcontroller. */
Init();
/* Initialize the bootloader. */
BootInit();
/* Start the infinite program loop. */
while (1)
{
/* Run the bootloader task. */
BootTask();
}
} /*** end of main ***/
/************************************************************************************//**
** \brief Initializes the microcontroller.
** \return none.
**
****************************************************************************************/
static void Init(void)
{
/* Configure the system clock. */
SystemClockConfig();
/* Enable the peripheral clock for the ports that are used. */
PCC->PCCn[PCC_PORTB_INDEX] |= PCC_PCCn_CGC_MASK;
PCC->PCCn[PCC_PORTD_INDEX] |= PCC_PCCn_CGC_MASK;
PCC->PCCn[PCC_PORTE_INDEX] |= PCC_PCCn_CGC_MASK;
/* Configure SW2 (PD3) GPIO pin for (optional) backdoor entry input. */
/* Input GPIO pin configuration. PD3 = GPIO, MUX = ALT1. */
PORTD->PCR[3] |= PORT_PCR_MUX(1);
/* Disable pull device, as SW2 already has a pull down resistor on the board. */
PORTD->PCR[3] &= ~PORT_PCR_PE(1);
/* Configure and enable Port D pin 3 GPIO as digital input */
PTD->PDDR &= ~GPIO_PDDR_PDD(1 << 3U);
PTD->PIDR &= ~GPIO_PIDR_PID(1 << 3U);
#if (BOOT_COM_RS232_ENABLE > 0)
/* UART RX GPIO pin configuration. PB0 = UART0 RX, MUX = ALT2. */
PORTB->PCR[0] |= PORT_PCR_MUX(2);
/* UART TX GPIO pin configuration. PB1 = UART0 TX, MUX = ALT2. */
PORTB->PCR[1] |= PORT_PCR_MUX(2);
#endif
#if (BOOT_COM_CAN_ENABLE > 0)
/* CAN RX GPIO pin configuration. PE4 = CAN0 RX, MUX = ALT5. */
PORTE->PCR[4] |= PORT_PCR_MUX(5);
/* CAN TX GPIO pin configuration. PE5 = CAN0 TX, MUX = ALT5. */
PORTE->PCR[5] |= PORT_PCR_MUX(5);
#endif
} /*** end of Init ***/
/************************************************************************************//**
** \brief System Clock Configuration. This code was derived from a S32 Design Studio
** example program. It enables the SOCS (40 MHz external crystal), FIRC (48
** MHz internal) and SIRC (8 MHz internal). The FIRC is used as a source for
** the system clock and configures the normal RUN mode for the following clock
** settings:
** - CORE_CLK = 48 MHz
** - SYS_CLK = 48 MHz
** - BUS_CLK = 48 MHz
** - FLASH_CLK = 24 MHz
** - SOSCDIV1_CLK = 40 MHz
** - SOSCDIV2_CLK = 40 MHz
** - FIRCDIV1_CLK = 48 MHz
** - FIRCDIV2_CLK = 48 MHz
** - SIRCDIV1_CLK = 8 MHz
** - SIRCDIV2_CLK = 8 MHz
** \return none.
**
****************************************************************************************/
static void SystemClockConfig(void)
{
/* --------- SOSC Initialization (40 MHz) ------------------------------------------ */
/* SOSCDIV1 & SOSCDIV2 =1: divide by 1. */
SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV1(1) | SCG_SOSCDIV_SOSCDIV2(1);
/* Range=3: High freq (SOSC betw 8MHz - 40MHz).
* HGO=0: Config xtal osc for low power.
* EREFS=1: Input is external XTAL.
*/
SCG->SOSCCFG = SCG_SOSCCFG_RANGE(3) | SCG_SOSCCFG_EREFS_MASK;
/* Ensure SOSCCSR unlocked. */
while (SCG->SOSCCSR & SCG_SOSCCSR_LK_MASK)
{
;
}
/* LK=0: SOSCCSR can be written.
* SOSCCMRE=0: OSC CLK monitor IRQ if enabled.
* SOSCCM=0: OSC CLK monitor disabled.
* SOSCERCLKEN=0: Sys OSC 3V ERCLK output clk disabled.
* SOSCLPEN=0: Sys OSC disabled in VLP modes.
* SOSCSTEN=0: Sys OSC disabled in Stop modes.
* SOSCEN=1: Enable oscillator.
*/
SCG->SOSCCSR = SCG_SOSCCSR_SOSCEN_MASK;
/* Wait for system OSC clock to become valid. */
while (!(SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK))
{
;
}
/* --------- FIRC Initialization --------------------------------------------------- */
/* Fast IRC is enabled and trimmed to 48 MHz in reset (default). Enable FIRCDIV2_CLK
* and FIRCDIV1_CLK, divide by 1 = 48 MHz.
*/
SCG->FIRCDIV = SCG_FIRCDIV_FIRCDIV1(1) | SCG_FIRCDIV_FIRCDIV2(1);
/* --------- SIRC Initialization --------------------------------------------------- */
/* Slow IRC is enabled with high range (8 MHz) in reset. Enable SIRCDIV2_CLK and
* SIRCDIV1_CLK, divide by 1 = 8MHz asynchronous clock source.
*/
SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV1(1) | SCG_SIRCDIV_SIRCDIV2(1);
/* --------- Change to normal RUN mode with 48MHz FIRC ----------------------------- */
/* Select FIRC as clock source.
* DIVCORE=0, div. by 1: Core clock = 48 MHz.
* DIVBUS=0, div. by 1: bus clock = 48 MHz.
* DIVSLOW=1, div. by 2: SCG slow, flash clock= 24 MHz
*/
SCG->RCCR = SCG_RCCR_SCS(3) | SCG_RCCR_DIVCORE(0) | SCG_RCCR_DIVBUS(0) |
SCG_RCCR_DIVSLOW(1);
/* Wait until system clock source is FIRC. */
while (((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT ) != 3U)
{
;
}
/* Evaluate the clock register settings and calculates the current core clock. This
* function must be called when the clock manager component is not used.
*/
SystemCoreClockUpdate();
} /*** end of SystemClockConfig ***/
/*********************************** end of main.c *************************************/

287
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Boot/startup_S32K118.s Normal file
View File

@ -0,0 +1,287 @@
; ---------------------------------------------------------------------------------------
; @file: startup_S32K118.s
; @purpose: IAR Startup File
; S32K118
; @version: 1.0
; @date: 2018-1-22
; @build: b170107
; ---------------------------------------------------------------------------------------
;
; Copyright 2018 NXP
; All rights reserved.
;
; THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
; OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
; IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
; INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
; HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
; STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
; IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
; THE POSSIBILITY OF SUCH DAMAGE.
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:ROOT(2)
EXTERN main
EXTERN SystemInit
EXTERN init_data_bss
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; Non Maskable Interrupt
DCD HardFault_Handler ; Cortex-M0 SV Hard Fault Interrupt
DCD 0
DCD 0
DCD 0
__vector_table_0x1c
DCD 0
DCD 0
DCD 0
DCD 0
DCD SVC_Handler ; Cortex-M0 SV Call Interrupt
DCD 0
DCD 0
DCD PendSV_Handler ; Cortex-M0 Pend SV Interrupt
DCD SysTick_Handler ; Cortex-M0 System Tick Interrupt
DCD DMA0_IRQHandler ; DMA channel 0 transfer complete
DCD DMA1_IRQHandler ; DMA channel 1 transfer complete
DCD DMA2_IRQHandler ; DMA channel 2 transfer complete
DCD DMA3_IRQHandler ; DMA channel 3 transfer complete
DCD DMA_Error_IRQHandler ; DMA error interrupt channels 0-3
DCD ERM_fault_IRQHandler ; ERM single and double bit error correction
DCD RTC_IRQHandler ; RTC alarm interrupt
DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
DCD LPTMR0_IRQHandler ; LPTIMER interrupt request
DCD PORT_IRQHandler ; Port A, B, C, D and E pin detect interrupt
DCD CAN0_ORed_Err_Wakeup_IRQHandler ; OR’ed [Bus Off OR Bus Off Done OR Transmit Warning OR Receive Warning], Interrupt indicating that errors were detected on the CAN bus, Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode
DCD CAN0_ORed_0_31_MB_IRQHandler ; OR’ed Message buffer (0-15, 16-31)
DCD FTM0_Ch0_7_IRQHandler ; FTM0 Channel 0 to 7 interrupt
DCD FTM0_Fault_IRQHandler ; FTM0 Fault interrupt
DCD FTM0_Ovf_Reload_IRQHandler ; FTM0 Counter overflow and Reload interrupt
DCD FTM1_Ch0_7_IRQHandler ; FTM1 Channel 0 to 7 interrupt
DCD FTM1_Fault_IRQHandler ; FTM1 Fault interrupt
DCD FTM1_Ovf_Reload_IRQHandler ; FTM1 Counter overflow and Reload interrupt
DCD FTFC_IRQHandler ; FTFC Command complete, Read collision and Double bit fault detect
DCD PDB0_IRQHandler ; PDB0 interrupt
DCD LPIT0_IRQHandler ; LPIT interrupt
DCD SCG_CMU_LVD_LVWSCG_IRQHandler ; PMC Low voltage detect interrupt, SCG bus interrupt request and CMU loss of range interrupt
DCD WDOG_IRQHandler ; WDOG interrupt request out before wdg reset out
DCD RCM_IRQHandler ; RCM Asynchronous Interrupt
DCD LPI2C0_Master_Slave_IRQHandler ; LPI2C0 Master Interrupt and Slave Interrupt
DCD FLEXIO_IRQHandler ; FlexIO Interrupt
DCD LPSPI0_IRQHandler ; LPSPI0 Interrupt
DCD LPSPI1_IRQHandler ; LPSPI1 Interrupt
DCD ADC0_IRQHandler ; ADC0 interrupt request.
DCD CMP0_IRQHandler ; CMP0 interrupt request
DCD LPUART1_RxTx_IRQHandler ; LPUART1 Transmit / Receive Interrupt
DCD LPUART0_RxTx_IRQHandler ; LPUART0 Transmit / Receive Interrupt
__Vectors_End
SECTION FlashConfig:CODE
__FlashConfig
DCD 0xFFFFFFFF ; 8 bytes backdoor comparison key
DCD 0xFFFFFFFF ;
DCD 0xFFFFFFFF ; 4 bytes program flash protection bytes
DCD 0xFFFF7FFE ; FDPROT:FEPROT:FOPT:FSEC(0xFE = unsecured)
__FlashConfig_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
CPSID I ; Mask interrupts
;; Init the rest of the registers
LDR R1,=0
LDR R2,=0
LDR R3,=0
LDR R4,=0
LDR R5,=0
LDR R6,=0
LDR R7,=0
MOV R8,R7
MOV R9,R7
MOV R10,R7
MOV R11,R7
MOV R12,R7
#ifdef START_FROM_FLASH
IMPORT __RAM_START, __RAM_END
;; INIT ECC RAM
LDR R1, =__RAM_START
LDR R2, =__RAM_END
SUBS R2, R2, R1
SUBS R2, #1
BLE .LC5
MOVS R0, #0
MOVS R3, #4
.LC4:
STR R0, [R1]
ADD R1, R1, R3
SUBS R2, #4
BGE .LC4
.LC5:
#endif
;; Initialize the stack pointer
LDR R0, =sfe(CSTACK)
MOV R13,R0
#ifndef __NO_SYSTEM_INIT
;; Call the CMSIS system init routine
LDR R0, =SystemInit
BLX R0
#endif
;; Init .data and .bss sections
LDR R0, =init_data_bss
BLX R0
CPSIE I ; Unmask interrupts
BL main
JumpToSelf
B JumpToSelf
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B .
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B .
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B .
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B .
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B .
PUBWEAK DMA0_IRQHandler
PUBWEAK DMA1_IRQHandler
PUBWEAK DMA2_IRQHandler
PUBWEAK DMA3_IRQHandler
PUBWEAK DMA_Error_IRQHandler
PUBWEAK ERM_fault_IRQHandler
PUBWEAK RTC_IRQHandler
PUBWEAK RTC_Seconds_IRQHandler
PUBWEAK LPTMR0_IRQHandler
PUBWEAK PORT_IRQHandler
PUBWEAK CAN0_ORed_Err_Wakeup_IRQHandler
PUBWEAK CAN0_ORed_0_31_MB_IRQHandler
PUBWEAK FTM0_Ch0_7_IRQHandler
PUBWEAK FTM0_Fault_IRQHandler
PUBWEAK FTM0_Ovf_Reload_IRQHandler
PUBWEAK FTM1_Ch0_7_IRQHandler
PUBWEAK FTM1_Fault_IRQHandler
PUBWEAK FTM1_Ovf_Reload_IRQHandler
PUBWEAK FTFC_IRQHandler
PUBWEAK PDB0_IRQHandler
PUBWEAK LPIT0_IRQHandler
PUBWEAK SCG_CMU_LVD_LVWSCG_IRQHandler
PUBWEAK WDOG_IRQHandler
PUBWEAK RCM_IRQHandler
PUBWEAK LPI2C0_Master_Slave_IRQHandler
PUBWEAK FLEXIO_IRQHandler
PUBWEAK LPSPI0_IRQHandler
PUBWEAK LPSPI1_IRQHandler
PUBWEAK ADC0_IRQHandler
PUBWEAK CMP0_IRQHandler
PUBWEAK LPUART1_RxTx_IRQHandler
PUBWEAK LPUART0_RxTx_IRQHandler
PUBWEAK DefaultISR
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
HardFault_Handler
SVC_Handler
PendSV_Handler
SysTick_Handler
DMA0_IRQHandler
DMA1_IRQHandler
DMA2_IRQHandler
DMA3_IRQHandler
DMA_Error_IRQHandler
ERM_fault_IRQHandler
RTC_IRQHandler
RTC_Seconds_IRQHandler
LPTMR0_IRQHandler
PORT_IRQHandler
CAN0_ORed_Err_Wakeup_IRQHandler
CAN0_ORed_0_31_MB_IRQHandler
FTM0_Ch0_7_IRQHandler
FTM0_Fault_IRQHandler
FTM0_Ovf_Reload_IRQHandler
FTM1_Ch0_7_IRQHandler
FTM1_Fault_IRQHandler
FTM1_Ovf_Reload_IRQHandler
FTFC_IRQHandler
PDB0_IRQHandler
LPIT0_IRQHandler
SCG_CMU_LVD_LVWSCG_IRQHandler
WDOG_IRQHandler
RCM_IRQHandler
LPI2C0_Master_Slave_IRQHandler
FLEXIO_IRQHandler
LPSPI0_IRQHandler
LPSPI1_IRQHandler
ADC0_IRQHandler
CMP0_IRQHandler
LPUART1_RxTx_IRQHandler
LPUART0_RxTx_IRQHandler
DefaultISR
B DefaultISR
END

125
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/S32K118_25_flash.icf Normal file
View File

@ -0,0 +1,125 @@
/*
** ###################################################################
** Processor: S32K118 with 25 KB SRAM
** Compiler: IAR ANSI C/C++ Compiler for ARM
**
** Abstract:
** Linker file for the IAR ANSI C/C++ Compiler for ARM
**
** Copyright 2018 NXP
** All rights reserved.
**
** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
** THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** ###################################################################
*/
/* If symbol __flash_vector_table__=1 is defined at link time
* the interrupt vector will not be copied to RAM.
* Warning: Using the interrupt vector from FLASH will not allow
* INT_SYS_InstallHandler because the section is Read Only.
*/
define symbol __ram_vector_table_size__ = isdefinedsymbol(__flash_vector_table__) ? 0 : 0x000000C0;
define symbol __ram_vector_table_offset__ = isdefinedsymbol(__flash_vector_table__) ? 0 : 0x000000BF;
/* Flash */
define symbol m_interrupts_start = 0x00002000;
define symbol m_interrupts_end = 0x000020C3;
define symbol m_flash_config_start = 0x00002400;
define symbol m_flash_config_end = 0x0000240F;
define symbol m_text_start = 0x00002410;
define symbol m_text_end = 0x0003FFFF;
/* SRAM_L */
define symbol m_custom_start = 0x1FFFFC00;
define symbol m_custom_end = 0x1FFFFFFF;
/* SRAM_U */
define symbol m_interrupts_ram_start = 0x20000000;
define symbol m_interrupts_ram_end = 0x20000000 + __ram_vector_table_offset__;
define symbol m_data_start = m_interrupts_ram_start + __ram_vector_table_size__;
define symbol m_data_end = 0x200030BF;
define symbol m_data_2_start = 0x200030C0;
define symbol m_data_2_end = 0x200057FF;
/* Sizes */
if (isdefinedsymbol(__stack_size__)) {
define symbol __size_cstack__ = __stack_size__;
} else {
define symbol __size_cstack__ = 0x00000200;
}
if (isdefinedsymbol(__heap_size__)) {
define symbol __size_heap__ = __heap_size__;
} else {
define symbol __size_heap__ = 0x00000200;
}
define exported symbol __VECTOR_TABLE = m_interrupts_start;
define exported symbol __VECTOR_RAM = isdefinedsymbol(__flash_vector_table__) ? m_interrupts_start : m_interrupts_ram_start;
define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__;
define exported symbol __RAM_START = m_interrupts_ram_start;
define exported symbol __RAM_END = m_data_2_end;
define memory mem with size = 4G;
define region m_flash_config_region = mem:[from m_flash_config_start to m_flash_config_end];
define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
| mem:[from m_text_start to m_text_end];
define region DATA_region = mem:[from m_data_start to m_data_end];
define region DATA_region_2 = mem:[from m_data_2_start to m_data_2_end-__size_cstack__];
define region CSTACK_region = mem:[from m_data_2_end-__size_cstack__+1 to m_data_2_end];
define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end];
define region CUSTOM_region = mem:[from m_custom_start to m_custom_end];
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block RW { readwrite };
define block ZI { zi };
/* Custom Section Block that can be used to place data at absolute address. */
/* Use __attribute__((section (".customSection"))) to place data here. */
/* Use this section only when MTB (Micro Trace Buffer) is not used, because MTB uses the same RAM area, as described in S32K Reference Manual. */
define block customSectionBlock { section .customSection };
define block __CODE_ROM { section .textrw_init };
define block __CODE_RAM { section .textrw };
initialize manually { section .textrw };
initialize manually { section .bss };
initialize manually { section .customSection };
initialize manually { section .data };
initialize manually { section __DLIB_PERTHREAD };
do not initialize { section .noinit, section .bss, section .data, section __DLIB_PERTHREAD, section .customSection };
place at address mem: m_interrupts_start { readonly section .intvec };
place in m_flash_config_region { section FlashConfig };
place in TEXT_region { readonly };
place in TEXT_region { block __CODE_ROM };
place in DATA_region { block RW };
place in DATA_region { block __CODE_RAM };
place in CUSTOM_region { first block customSectionBlock };
place in DATA_region_2 { block ZI };
place in DATA_region_2 { last block HEAP };
place in CSTACK_region { block CSTACK };
place in m_interrupts_ram_region { section m_interrupts_ram };

BIN
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/bin/demoprog_s32k118.out Normal file
View File

Binary file not shown.

195
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/bin/demoprog_s32k118.srec Normal file
View File

@ -0,0 +1,195 @@
S018000064656D6F70726F675F7333326B3131382E7372656373
S1132000005800202D2E0000FB2A0000FB2A0000AF
S113201000000000000000000000000000000000BC
S1132020000000000000000000000000FB2A000087
S11320300000000000000000FB2A0000292B000023
S1132040FB2A0000FB2A0000FB2A0000FB2A0000F8
S1132050FB2A0000FB2A0000FB2A0000FB2A0000E8
S1132060FB2A0000FB2A0000FB2A0000FB2A0000D8
S1132070FB2A0000FB2A0000FB2A0000FB2A0000C8
S1132080FB2A0000FB2A0000FB2A0000FB2A0000B8
S1132090FB2A0000FB2A0000FB2A0000FB2A0000A8
S11320A0FB2A0000FB2A0000FB2A0000FB2A000098
S11320B0FB2A0000FB2A0000FB2A0000FB2A000088
S10720C0EE11AA551A
S1132400FFFFFFFFFFFFFFFFFFFFFFFFFE7FFFFF59
S113241080B500F00DF800F087F901BD80B500F03B
S113242059F800F04BFA01BD80B500F0E9FA01BD9E
S11324301CB568469B490CC90CC0083908389A4831
S11324400168A54A0A40026001688422D2050A4351
S11324500260A2480168090A4907490F002905D109
S113246001210A02E023DB00134003609C4801249D
S11324709C4A12682240002A00D19B486A46515C5B
S113248000F0E4FAE121090200F0E0FAC01DC008FE
S1132490C004C00C80B2C004C00CE021C9040143D4
S11324A09248016092489349086093480021016072
S11324B0924A1160924A11609249F02292020A6093
S11324C00A68882313430B608F490C60C0210903F9
S11324D0016013BD70B58D4C2078002815D18C4D4A
S11324E0280000F037F8012833D12878002830D0AC
S11324F0287841282DDA00F014FB86490860012071
S1132500207000208449087023E0834D804E287891
S11325103018401C00F01EF8012811D12878401C06
S1132520287028783178884213D100202070707880
S1132530FF280ED1B07800280BD1FFF775FF08E013
S113254000F0EFFA734909686431814201D2002036
S1132550207070BD00B500210122664B1B685B0D25
S11325601340002B03D0D3490968017011000800FF
S1132570C0B200BDFEB507000D00140068466749EF
S11325800CC90CC00839083865480168090A4907AC
S1132590490F002905D101210A02E023DB00134081
S11325A0036060486A46515C00F050FA01900026CE
S11325B06846078000E0761C3000C0B212282BD297
S11325C0BD4F019869460A883100C9B204235943B2
S11325D0795C514300F03AFA0029ECD1019869463C
S11325E00A883100C9B204235943795C514300F08D
S11325F02DFA288028880028DDD02888FF21891C0E
S11326008842D8D22000F6B204214E43B9190422DC
S113261000F0B4FA012000E00020FEBD38B5C24C41
S113262020688021C9050143216020688021490573
S11326300143216000F075FA0500FA352068C001F5
S113264003D400F06EFA8542F8D231BD38B5B64CE9
S113265020682149014021602068B449014021607B
S113266000F05FFA0500FA352068C00103D500F0D8
S113267058FA8542F8D231BD38B5AB4C20680028F1
S11326800FD42068802109060143216000F049FA33
S11326900500FA352068C00203D400F042FA8542EE
S11326A0F8D231BD242F0000A851064038B59E4C05
S11326B0206800280ED5206840004008206000F003
S11326C030FA0500FA352068C00203D500F029FA73
S11326D08542F8D231BD0000FFFFFFBF044206402F
S11326E000127A000842064080841E0010A00640B2
S11326F000C01FC014A0064018A0064020A0064039
S113270024A0064028A006402CA006401531002035
S1132710C030002004310020143100202C2F000090
S113272004410640409C0000FEB50027380069467D
S113273008800422002101A800F02DFA7C4D7D4878
S113274001688022D2050A430260FFF7AFFFFFF75A
S113275065FFFFF791FF784C2068784901402160BC
S1132760FFF7A4FFFFF75AFF01AA6946FA204000C9
S1132770FFF700FF20687249014021602068694624
S11327800988491E09060143216001A8216842788D
S1132790521E5207520F0A43226021688278521E49
S11327A0D204E0239B0313400B4323602168C278C7
S11327B0521E1204E023DB0213400B432360817892
S11327C0042901DA807800E004202168C0B2401EA8
S11327D08005C022120402400A432260206880213E
S11327E001432160380006E05649020092B20423F6
S11327F05343CF50401C010089B28029F4D33800E0
S113280006E05149020092B204235343CF50401CC6
S1132810010089B22029F4D3434E30687F218843D4
S11328201F210143316030688021890201433160F6
S113283030688021490201433160306843490140D6
S1132840316043484349086043488021C90401601A
S1132850002D0BD569004908026880239B031343AC
S11328600360C800C0083D49086004E0A804C00033
S1132870C0083A4908603A4807600020C043394913
S11328800860394839490860306839490140316085
S11328902068384901402160FFF7D8FE00F041F973
S11328A00400FA343068000103D500F03AF9844298
S11328B0F8D2F7BD1CA00640842E0000FEB580208F
S11328C0800028490A680240002A2BD0224A126854
S11328D0120C1207120F284B00240FE02500EDB252
S11328E00326B543ED1C2600F6B2B607B60FAD1BA2
S11328F05D5D6E462700FFB2F555641C2500160089
S1132900EDB2F6B2B542E9D308601C4800681C4930
S1132910086068460078FF2804D1D2B2022A01D1A7
S1132920FFF782FDF7BD000000400240FFFFFFEF0C
S1132930670600009050064004400240FFDFFFFF9E
S113294078FF00008040024080480240FFFFFFDF24
S1132950FFFFFF5FA44802401041024014410240BF
S1132960284002403040024006003B002040024024
S1132970FFFF7FFFF7EFFFFF1841024008400240CE
S11329800831002023482449016000682348244971
S11329900860244824490860704770B5002210007C
S11329A001252B000F24214E3168090C2140491CBC
S11329B03668360E3440012C04D018D3032C0CD0C6
S11329C002D314E01A4813E01A4C24682540002D61
S11329D001D0174800E013000AE0174C2468A4074C
S11329E0A40F002C01D1154800E0130000E01300EF
S11329F0DBB2002B03D000F029F81149086070BD48
S1132A00104A106880B21049014304200843106042
S1132A10704700000420054020C528D9202100006B
S1132A2000200540FFFF000008200540104006403C
S1132A3000127A000842064008430640006CDC029B
S1132A40C00000200CED00E00000FA050022030A9B
S1132A508B420BD203098B4219D243088B422ED2EC
S1132A60411A00D20146524110467047FF22090222
S1132A703FD012068B4205D3121209028B4201D3B6
S1132A801212090203098B4219D300E0090AC3098F
S1132A908B4201D3CB01C01A524183098B4201D32B
S1132AA08B01C01A524143098B4201D34B01C01A16
S1132AB0524103098B4201D30B01C01A5241C3088E
S1132AC08B4201D3CB00C01A524183088B4201D3FD
S1132AD08B00C01A524143088B4201D34B00C01AE9
S1132AE05241884200D3401A5241CFD20146104687
S1132AF0704708B500F05AF808BDFEE700B50D4868
S1132B000068FA218900FFF7A1FF401E0A49086006
S1132B1000200A4908600721094A11600949086030
S1132B2000BD08480068704706480168491C0160F8
S1132B3070470000C000002014E000E018E000E04E
S1132B4010E000E01031002070B4103A03D378C9CB
S1132B50103A78C0FBD2530701D318C918C001D565
S1132B6008C908C0D20704D30B880380891C801CC1
S1132B70002A01D50B78037070BC70478B0701D114
S1132B808307E1D0124205D00B78491C0370401C26
S1132B90521EF9D1704710B504000800110002005C
S1132BA0200000F005F8200010BD00007047000070
S1132BB01206130A1A43130C1A4300BF094205D024
S1132BC0830705D00270401C491EF9D170470000EC
S1132BD01300103906D330B41400150010393CC06A
S1132BE0FCD230BC490700D30CC000D504C0890016
S1132BF002D30280801C002900D5027070470000B7
S1132C0080B500F007F8FFF703FC00F076F8FFF753
S1132C1005FCFAE780B500F024F88020C0052249BD
S1132C200A6802430A6021490A6810430860802048
S1132C3080001F490A6802430A601E490A6810435B
S1132C400860A020C0001C490A6802430A601B49AE
S1132C500A6810430860FFF751FF00F041F862B6BC
S1132C6001BD80B5FF20801C154908603421154A38
S1132C70116015490A681202FBD401220A600A682D
S1132C80D201FCD511490860114908601148124964
S1132C90086012480068000E0007000F0328F8D1EE
S1132CA0FFF77BFE01BD0000285106403451064069
S1132CB000A0044004A0044010D0044014D00440F8
S1132CC004410640084106400041064004430640D2
S1132CD00442064001000003144006401040064030
S1132CE0802040001549086015490A6802430A60BB
S1132CF014490A6810430860704710B5FFF711FFC4
S1132D0011490A68821AFA235B009A4215D30F4AC2
S1132D101378002B08D1012313700D4A1368802403
S1132D2064001C43146007E000231370054A136811
S1132D30802464001C431460086010BD20D004404B
S1132D4014F10F4008F10F400C310020163100201F
S1132D5004F10F40FFB526482649274A0392274A23
S1132D60274B284C0294284C284D0195284D294E78
S1132D70294F009703E00F780770401C491C039FFC
S1132D808F42F8D10298984207D018781070521CDC
S1132D905B1CF7E700202070641C0198A042F9D165
S1132DA00098B04204D030782870761C6D1CF7E788
S1132DB00023180019491A4A8A4212D006E0042452
S1132DC05C430C5904255D4354515B1C154CA40809
S1132DD0A342F4D31449C0B20423584308580260F0
S1132DE005E0114AC0B20423584310580160FFBDE6
S1132DF0C0000020382F00003C2F0000C400002039
S1132E003C2F00003C2F0000C03000201731002070
S1132E10000000000000000000000000002000008E
S1132E2000000020C0000000342F000072B6002112
S1132E30002200230024002500260027B846B946B6
S1132E40BA46BB46BC460A490A4A521A013A05DD4B
S1132E500020042308601944043AFBDA0648854636
S1132E60064880470648804762B6FFF7C9FEFEE77A
S1132E7000000020FF570020005800208529000092
S1132E80552D000008030202090303020A03030389
S1132E900B0403030C0404030D0504030E050404CE
S1132EA00F0604041006050411070504120705059E
S1132EB0130805051408060515080705160807066E
S1132EC017080806180808071908080800F00DF87C
S1132ED0002801D000BF00BF00BF00BF002000BF1A
S1132EE000BFFFF78DFE00F002F80120704780B5A7
S1132EF000F002F801BD00000746384600F002F871
S1132F00FBE7000080B500BF00BF024A1100182093
S1132F10ABBEFBE72600020000BF00BF00BF00BF3E
S1132F20FFF7D4FF0001020408102040000102044E
S10F2F300810204008ED00E0006CDC02FA
S9032F19B4

772
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/boot.c Normal file
View File

@ -0,0 +1,772 @@
/************************************************************************************//**
* \file Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/boot.c
* \brief Demo program bootloader interface source file.
* \ingroup Prog_ARMCM0_S32K14_S32K118EVB_IAR
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "header.h" /* generic header */
/****************************************************************************************
* Function prototypes
****************************************************************************************/
#if (BOOT_COM_RS232_ENABLE > 0)
static void BootComRs232Init(void);
static void BootComRs232CheckActivationRequest(void);
#endif
#if (BOOT_COM_CAN_ENABLE > 0)
static void BootComCanInit(void);
static void BootComCanCheckActivationRequest(void);
#endif
/************************************************************************************//**
** \brief Initializes the communication interface.
** \return none.
**
****************************************************************************************/
void BootComInit(void)
{
#if (BOOT_COM_RS232_ENABLE > 0)
BootComRs232Init();
#endif
#if (BOOT_COM_CAN_ENABLE > 0)
BootComCanInit();
#endif
} /*** end of BootComInit ***/
/************************************************************************************//**
** \brief Receives the CONNECT request from the host, which indicates that the
** bootloader should be activated and, if so, activates it.
** \return none.
**
****************************************************************************************/
void BootComCheckActivationRequest(void)
{
#if (BOOT_COM_RS232_ENABLE > 0)
BootComRs232CheckActivationRequest();
#endif
#if (BOOT_COM_CAN_ENABLE > 0)
BootComCanCheckActivationRequest();
#endif
} /*** end of BootComCheckActivationRequest ***/
/************************************************************************************//**
** \brief Bootloader activation function.
** \return none.
**
****************************************************************************************/
void BootActivate(void)
{
/* Activate the bootloader by performing a software reset. */
SystemSoftwareReset();
} /*** end of BootActivate ***/
#if (BOOT_COM_RS232_ENABLE > 0)
/****************************************************************************************
* U N I V E R S A L A S Y N C H R O N O U S R X T X I N T E R F A C E
****************************************************************************************/
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/** \brief Timeout time for the reception of a CTO packet. The timer is started upon
* reception of the first packet byte.
*/
#define RS232_CTO_RX_PACKET_TIMEOUT_MS (100u)
/** \brief Set the peripheral LPUART base pointer. */
#define LPUARTx (LPUART0)
/** \brief Set the PCC index offset for LPUART. */
#define PCC_LPUARTx_INDEX (PCC_LPUART0_INDEX)
/****************************************************************************************
* Function prototypes
****************************************************************************************/
static unsigned char Rs232ReceiveByte(unsigned char *data);
/************************************************************************************//**
** \brief Initializes the UART communication interface.
** \return none.
**
****************************************************************************************/
static void BootComRs232Init(void)
{
unsigned long sourceClockFreqHz;
unsigned long div2RegValue;
unsigned short baudrateSbr0_12;
unsigned char const div2DividerLookup[] =
{
0U, /* 0b000. Output disabled. */
1U, /* 0b001. Divide by 1. */
2U, /* 0b010. Divide by 2. */
4U, /* 0b011. Divide by 4. */
8U, /* 0b100. Divide by 8. */
16U, /* 0b101. Divide by 16. */
32U, /* 0b110. Divide by 32. */
64U, /* 0b111. Divide by 64. */
};
/* Make sure the UART peripheral clock is disabled before configuring its source
* clock.
*/
PCC->PCCn[PCC_LPUARTx_INDEX] &= ~PCC_PCCn_CGC_MASK;
/* Select option 2 as the UART peripheral source clock and enable the clock. Option 2
* is the SIRCDIV2_CLK, which is available on all peripherals and configurations.
*/
PCC->PCCn[PCC_LPUARTx_INDEX] |= PCC_PCCn_PCS(2) | PCC_PCCn_CGC_MASK;
/* Obtain the DIV2 divider value of the SIRC_CLK. */
div2RegValue = (SCG->SIRCDIV & SCG_SIRCDIV_SIRCDIV2_MASK) >> SCG_SIRCDIV_SIRCDIV2_SHIFT;
/* Check if the DIV2 register value for SIRC is 0. In this case SIRCDIV2_CLK is
* currently disabled.
*/
if (div2RegValue == 0U)
{
/* Configure the DIV2 for a default divide by 1 to make sure the SIRCDIV2_CLK is
* actually enabled.
*/
div2RegValue = 1U;
SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV2(div2RegValue);
}
/* Determine the SIRC clock frequency. If SIRC high range is enabled, it is 8 MHz. If
* SIRC low range is enabled, it is 2 MHz.
*/
sourceClockFreqHz = 8000000U;
if ((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) == SCG_SIRCCFG_RANGE(0))
{
sourceClockFreqHz = 2000000U;
}
/* Now process the configured DIV2 divider factor to get the actual frequency of the
* UART peripheral source clock.
*/
sourceClockFreqHz /= div2DividerLookup[div2RegValue];
/* Configure the baudrate from BOOT_COM_RS232_BAUDRATE, taking into account that an
* oversampling of 8 will be configured. Default 8,n,1 format is used. Integer
* rounding is used to get the best value for baudrateSbr0_12. Actual baudrate equals
* sourceClockFreqHz / 8 / baudrateSbr0_12.
*/
baudrateSbr0_12 = (((sourceClockFreqHz / BOOT_COM_RS232_BAUDRATE) + (8U - 1U)) / 8U) &
LPUART_BAUD_SBR_MASK;
/* OSR=7: Over sampling ratio = 7+1=8.
* SBNS=0: One stop bit.
* BOTHEDGE=0: receiver samples only on rising edge.
* M10=0: Rx and Tx use 7 to 9 bit data characters.
* RESYNCDIS=0: Resync during rec'd data word supported.
* LBKDIE, RXEDGIE=0: interrupts disable.
* TDMAE, RDMAE, TDMAE=0: DMA requests disabled.
* MAEN1, MAEN2, MATCFG=0: Match disabled.
*/
LPUARTx->BAUD = LPUART_BAUD_SBR(baudrateSbr0_12) | LPUART_BAUD_OSR(7);
/* Clear the error/interrupt flags */
LPUARTx->STAT = FEATURE_LPUART_STAT_REG_FLAGS_MASK;
/* Reset all features/interrupts by default */
LPUARTx->CTRL = 0x00000000;
/* Reset match addresses */
LPUARTx->MATCH = 0x00000000;
#if FEATURE_LPUART_HAS_MODEM_SUPPORT
/* Reset IrDA modem features */
LPUARTx->MODIR = 0x00000000;
#endif
#if FEATURE_LPUART_FIFO_SIZE > 0U
/* Reset FIFO feature */
LPUARTx->FIFO = FEATURE_LPUART_FIFO_RESET_MASK;
/* Enable the transmit and receive FIFOs. */
LPUARTx->FIFO |= LPUART_FIFO_TXFE(1) | LPUART_FIFO_RXFE(1);
/* Set the reception water mark to 0 and the transmitter water mark to 1. */
LPUARTx->WATER = LPUART_WATER_TXWATER(1) | LPUART_WATER_RXWATER(0);
#endif
/* Enable transmitter and receiver, no parity, 8 bit char:
* RE=1: Receiver enabled.
* TE=1: Transmitter enabled.
* PE,PT=0: No hw parity generation or checking.
* M7,M,R8T9,R9T8=0: 8-bit data characters.
* DOZEEN=0: LPUART enabled in Doze mode.
* ORIE,NEIE,FEIE,PEIE,TIE,TCIE,RIE,ILIE,MA1IE,MA2IE=0: no IRQ.
* TxDIR=0: TxD pin is input if in single-wire mode.
* TXINV=0: Transmit data not inverted.
* RWU,WAKE=0: normal operation; rcvr not in standby.
* IDLCFG=0: one idle character.
* ILT=0: Idle char bit count starts after start bit.
* SBK=0: Normal transmitter operation - no break char.
* LOOPS,RSRC=0: no loop back.
*/
LPUARTx->CTRL = LPUART_CTRL_RE_MASK | LPUART_CTRL_TE_MASK;
} /*** end of BootComRs232Init ***/
/************************************************************************************//**
** \brief Receives the CONNECT request from the host, which indicates that the
** bootloader should be activated and, if so, activates it.
** \return none.
**
****************************************************************************************/
static void BootComRs232CheckActivationRequest(void)
{
static unsigned char xcpCtoReqPacket[BOOT_COM_RS232_RX_MAX_DATA+1];
static unsigned char xcpCtoRxLength;
static unsigned char xcpCtoRxInProgress = 0;
static unsigned long xcpCtoRxStartTime = 0;
/* start of cto packet received? */
if (xcpCtoRxInProgress == 0)
{
/* store the message length when received */
if (Rs232ReceiveByte(&xcpCtoReqPacket[0]) == 1)
{
/* check that the length has a valid value. it should not be 0 */
if ( (xcpCtoReqPacket[0] > 0) &&
(xcpCtoReqPacket[0] <= BOOT_COM_RS232_RX_MAX_DATA) )
{
/* store the start time */
xcpCtoRxStartTime = TimerGet();
/* indicate that a cto packet is being received */
xcpCtoRxInProgress = 1;
/* reset packet data count */
xcpCtoRxLength = 0;
}
}
}
else
{
/* store the next packet byte */
if (Rs232ReceiveByte(&xcpCtoReqPacket[xcpCtoRxLength+1]) == 1)
{
/* increment the packet data count */
xcpCtoRxLength++;
/* check to see if the entire packet was received */
if (xcpCtoRxLength == xcpCtoReqPacket[0])
{
/* done with cto packet reception */
xcpCtoRxInProgress = 0;
/* check if this was an XCP CONNECT command */
if ((xcpCtoReqPacket[1] == 0xff) && (xcpCtoReqPacket[2] == 0x00))
{
/* connection request received so start the bootloader */
BootActivate();
}
}
}
else
{
/* check packet reception timeout */
if (TimerGet() > (xcpCtoRxStartTime + RS232_CTO_RX_PACKET_TIMEOUT_MS))
{
/* cancel cto packet reception due to timeout. note that this automatically
* discards the already received packet bytes, allowing the host to retry.
*/
xcpCtoRxInProgress = 0;
}
}
}
} /*** end of BootComRs232CheckActivationRequest ***/
/************************************************************************************//**
** \brief Receives a communication interface byte if one is present.
** \param data Pointer to byte where the data is to be stored.
** \return 1 if a byte was received, 0 otherwise.
**
****************************************************************************************/
static unsigned char Rs232ReceiveByte(unsigned char *data)
{
unsigned char result = 0;
/* Check if a new byte was received by means of the RDRF-bit. */
if (((LPUARTx->STAT & LPUART_STAT_RDRF_MASK) >> LPUART_STAT_RDRF_SHIFT) != 0U)
{
/* Retrieve and store the newly received byte. */
*data = LPUARTx->DATA;
/* Update the result. */
result = 1;
}
/* Give the result back to the caller. */
return result;
} /*** end of Rs232ReceiveByte ***/
#endif /* BOOT_COM_RS232_ENABLE > 0 */
#if (BOOT_COM_CAN_ENABLE > 0)
/****************************************************************************************
* C O N T R O L L E R A R E A N E T W O R K I N T E R F A C E
****************************************************************************************/
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/** \brief Timeout for entering/leaving CAN initialization mode in milliseconds. */
#define CAN_INIT_TIMEOUT_MS (250U)
/** \brief Set the peripheral CAN0 base pointer. */
#define CANx (CAN0)
/** \brief Set the PCC index offset for CAN0. */
#define PCC_FlexCANx_INDEX (PCC_FlexCAN0_INDEX)
/** \brief Set the number of message boxes supported by CAN0. */
#define CANx_MAX_MB_NUM (FEATURE_CAN0_MAX_MB_NUM)
/** \brief The mailbox used for receiving the XCP command message. */
#define CAN_RX_MSGBOX_NUM (9U)
/****************************************************************************************
* Type definitions
****************************************************************************************/
/** \brief Structure type for grouping CAN bus timing related information. */
typedef struct t_can_bus_timing
{
unsigned char timeQuanta; /**< Total number of time quanta */
unsigned char propSeg; /**< CAN propagation segment */
unsigned char phaseSeg1; /**< CAN phase segment 1 */
unsigned char phaseSeg2; /**< CAN phase segment 2 */
} tCanBusTiming;
/****************************************************************************************
* Local constant declarations
****************************************************************************************/
/** \brief CAN bit timing table for dynamically calculating the bittiming settings.
* \details According to the CAN protocol 1 bit-time can be made up of between 8..25
* time quanta (TQ). The total TQ in a bit is SYNC + TSEG1 + TSEG2 with SYNC
* always being 1. The sample point is (SYNC + TSEG1) / (SYNC + TSEG1 + TSEG2)
* * 100%. This array contains possible and valid time quanta configurations
* with a sample point between 68..78%. A visual representation of the TQ in
* a bit is:
* | SYNCSEG | TIME1SEG | TIME2SEG |
* Or with an alternative representation:
* | SYNCSEG | PROPSEG | PHASE1SEG | PHASE2SEG |
* With the alternative representation TIME1SEG = PROPSEG + PHASE1SEG.
*
*/
static const tCanBusTiming canTiming[] =
{
/* Time-Quanta | PROPSEG | PSEG1 | PSEG2 | Sample-Point */
/* ---------------------------------------------------- */
{ 8U, 3U, 2U, 2U }, /*1+3+2+1=8 | 3 | 2 | 2 | 75% */
{ 9U, 3U, 3U, 2U }, /* 9 | 3 | 3 | 2 | 78% */
{ 10U, 3U, 3U, 3U }, /* 10 | 3 | 3 | 3 | 70% */
{ 11U, 4U, 3U, 3U }, /* 11 | 4 | 3 | 3 | 73% */
{ 12U, 4U, 4U, 3U }, /* 12 | 4 | 4 | 3 | 75% */
{ 13U, 5U, 4U, 3U }, /* 13 | 5 | 4 | 3 | 77% */
{ 14U, 5U, 4U, 4U }, /* 14 | 5 | 4 | 4 | 71% */
{ 15U, 6U, 4U, 4U }, /* 15 | 6 | 4 | 4 | 73% */
{ 16U, 6U, 5U, 4U }, /* 16 | 6 | 5 | 4 | 75% */
{ 17U, 7U, 5U, 4U }, /* 17 | 7 | 5 | 4 | 76% */
{ 18U, 7U, 5U, 5U }, /* 18 | 7 | 5 | 5 | 72% */
{ 19U, 8U, 5U, 5U }, /* 19 | 8 | 5 | 5 | 74% */
{ 20U, 8U, 6U, 5U }, /* 20 | 8 | 6 | 5 | 75% */
{ 21U, 8U, 7U, 5U }, /* 21 | 8 | 7 | 5 | 76% */
{ 22U, 8U, 7U, 6U }, /* 22 | 8 | 7 | 6 | 73% */
{ 23U, 8U, 8U, 6U }, /* 23 | 8 | 8 | 6 | 74% */
{ 24U, 8U, 8U, 7U }, /* 24 | 8 | 8 | 7 | 71% */
{ 25U, 8U, 8U, 8U } /* 25 | 8 | 8 | 8 | 68% */
};
/****************************************************************************************
* Local data declarations
****************************************************************************************/
/** \brief Dummy variable to store the CAN controller's free running timer value in.
* This is needed at the end of a CAN message reception to unlock the mailbox
* again. If this variable is declared locally within the function, it generates
* an unwanted compiler warning about assigning a value and not using it.
* For this reason this dummy variabled is declare here as a module global.
*/
static volatile unsigned long dummyTimerVal;
/************************************************************************************//**
** \brief Search algorithm to match the desired baudrate to a possible bus
** timing configuration.
** \param baud The desired baudrate in kbps. Valid values are 10..1000.
** \param prescaler Pointer to where the value for the prescaler will be stored.
** \param busTimingCfg Pointer to where the bus timing values will be stored.
** \return 1 if the CAN bustiming register values were found, 0 otherwise.
**
****************************************************************************************/
static unsigned char CanGetSpeedConfig(unsigned short baud, unsigned short * prescaler,
tCanBusTiming * busTimingCfg)
{
unsigned char cnt;
unsigned long canClockFreqkHz;
unsigned long div2RegValue;
unsigned char const div2DividerLookup[] =
{
0U, /* 0b000. Output disabled. */
1U, /* 0b001. Divide by 1. */
2U, /* 0b010. Divide by 2. */
4U, /* 0b011. Divide by 4. */
8U, /* 0b100. Divide by 8. */
16U, /* 0b101. Divide by 16. */
32U, /* 0b110. Divide by 32. */
64U, /* 0b111. Divide by 64. */
};
/* Obtain the DIV2 divider value of the SOSC_CLK. */
div2RegValue = (SCG->SOSCDIV & SCG_SOSCDIV_SOSCDIV2_MASK) >> SCG_SOSCDIV_SOSCDIV2_SHIFT;
/* Check if the DIV2 register value for SOSC is 0. In this case SOSCDIV2_CLK is
* currently disabled.
*/
if (div2RegValue == 0U)
{
/* Configure the DIV2 for a default divide by 1 to make sure the SOSCDIV2_CLK is
* actually enabled.
*/
div2RegValue = 1U;
SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV2(div2RegValue);
}
/* Determine the SOSC clock frequency. */
canClockFreqkHz = BOOT_CPU_XTAL_SPEED_KHZ;
/* Now process the configured DIV2 divider factor to get the actual frequency of the
* CAN peripheral source clock.
*/
canClockFreqkHz /= div2DividerLookup[div2RegValue];
/* Loop through all possible time quanta configurations to find a match. */
for (cnt=0; cnt < sizeof(canTiming)/sizeof(canTiming[0]); cnt++)
{
if ((canClockFreqkHz % (baud * canTiming[cnt].timeQuanta)) == 0U)
{
/* Compute the prescaler that goes with this TQ configuration. */
*prescaler = canClockFreqkHz/(baud * canTiming[cnt].timeQuanta);
/* Make sure the prescaler is valid. */
if ((*prescaler > 0U) && (*prescaler <= 256U))
{
/* Store the bustiming configuration. */
*busTimingCfg = canTiming[cnt];
/* Found a good bus timing configuration. */
return 1U;
}
}
}
/* Could not find a good bus timing configuration. */
return 0U;
} /*** end of CanGetSpeedConfig ***/
/************************************************************************************//**
** \brief Places the CAN controller in freeze mode. Note that the CAN controller
** can only be placed in freeze mode, if it is actually enabled.
** \return none.
**
****************************************************************************************/
static void CanFreezeModeEnter(void)
{
unsigned long timeout;
/* Request to enter freeze mode. */
CANx->MCR = (CANx->MCR & ~CAN_MCR_FRZ_MASK) | CAN_MCR_FRZ(1U);
CANx->MCR = (CANx->MCR & ~CAN_MCR_HALT_MASK) | CAN_MCR_HALT(1U);
/* Set timeout time for entering freeze mode. */
timeout = TimerGet() + CAN_INIT_TIMEOUT_MS;
/* Wait for freeze mode acknowledgement. */
while (((CANx->MCR & CAN_MCR_FRZACK_MASK)) == 0U)
{
/* Break loop upon timeout. This would indicate a hardware failure. */
if (TimerGet() > timeout)
{
break;
}
}
} /*** end of CanFreezeModeEnter ***/
/************************************************************************************//**
** \brief Leaves the CAN controller's freeze mode. Note that this operation can
** only be done, if it is actually enabled.
** \return none.
**
****************************************************************************************/
static void CanFreezeModeExit(void)
{
unsigned long timeout;
/* Request to leave freeze mode. */
CANx->MCR = (CANx->MCR & ~CAN_MCR_FRZ_MASK) | CAN_MCR_FRZ(0U);
CANx->MCR = (CANx->MCR & ~CAN_MCR_HALT_MASK) | CAN_MCR_HALT(0U);
/* Set timeout time for leaving freeze mode. */
timeout = TimerGet() + CAN_INIT_TIMEOUT_MS;
/* Wait for non freeze mode acknowledgement. */
while (((CANx->MCR & CAN_MCR_FRZACK_MASK)) != 0U)
{
/* Break loop upon timeout. This would indicate a hardware failure. */
if (TimerGet() > timeout)
{
break;
}
}
} /*** end of CanFreezeModeExit ***/
/************************************************************************************//**
** \brief Places the CAN controller in disabled mode.
** \return none.
**
****************************************************************************************/
static void CanDisabledModeEnter(void)
{
unsigned long timeout;
/* Only continue if the CAN controller is currently enabled. */
if ((CANx->MCR & CAN_MCR_MDIS_MASK) == 0U)
{
/* Request disabled mode. */
CANx->MCR = (CANx->MCR & ~CAN_MCR_MDIS_MASK) | CAN_MCR_MDIS(1U);
/* Set timeout time for entering disabled mode. */
timeout = TimerGet() + CAN_INIT_TIMEOUT_MS;
/* Wait for disabled mode acknowledgement. */
while (((CANx->MCR & CAN_MCR_LPMACK_MASK)) == 0U)
{
/* Break loop upon timeout. This would indicate a hardware failure. */
if (TimerGet() > timeout)
{
break;
}
}
}
} /*** end of CanDisabledModeEnter ***/
/************************************************************************************//**
** \brief Places the CAN controller in enabled mode.
** \return none.
**
****************************************************************************************/
static void CanDisabledModeExit(void)
{
unsigned long timeout;
/* Only continue if the CAN controller is currently disabled. */
if ((CANx->MCR & CAN_MCR_MDIS_MASK) != 0U)
{
/* Request enabled mode. */
CANx->MCR = (CANx->MCR & ~CAN_MCR_MDIS_MASK) | CAN_MCR_MDIS(0U);
/* Set timeout time for leaving disabled mode. */
timeout = TimerGet() + CAN_INIT_TIMEOUT_MS;
/* Wait for disabled mode acknowledgement. */
while (((CANx->MCR & CAN_MCR_LPMACK_MASK)) != 0U)
{
/* Break loop upon timeout. This would indicate a hardware failure. */
if (TimerGet() > timeout)
{
break;
}
}
}
} /*** end of CanDisabledModeExit ***/
/************************************************************************************//**
** \brief Initializes the CAN communication interface.
** \return none.
**
****************************************************************************************/
static void BootComCanInit(void)
{
unsigned short prescaler = 0;
tCanBusTiming timingCfg = { 0 };
unsigned char rjw;
unsigned short idx;
unsigned long timeout;
unsigned long rxMsgId = BOOT_COM_CAN_RX_MSG_ID;
/* Enable the CAN peripheral clock. */
PCC->PCCn[PCC_FlexCANx_INDEX] |= PCC_PCCn_CGC_MASK;
/* The source clock needs to be configured first. For this the CAN controller must be
* in disabled mode, but that can only be entered after first entering freeze mode,
* which in turn can only be in enabled mode. So first enable the module, then goto
* freeze mode and finally enter disabled mode.
*/
CanDisabledModeExit();
CanFreezeModeEnter();
CanDisabledModeEnter();
/* Configure SOSCDIV2 as the source clock. This assumes that an external oscillator
* is available, which is typically the case to meet the clock tolerance requirements
* of the CAN 2.0B secification.
*/
CANx->CTRL1 &= ~CAN_CTRL1_CLKSRC_MASK;
/* Leave disabled mode. */
CanDisabledModeExit();
/* Make sure freeze mode is active to be able to initialize the CAN controller. */
CanFreezeModeEnter();
/* Obtain bittiming configuration information. */
(void)CanGetSpeedConfig(BOOT_COM_CAN_BAUDRATE/1000, &prescaler, &timingCfg);
/* Reset the current bittiming configuration. */
CANx->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_PROPSEG_MASK |
CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK | CAN_CTRL1_RJW_MASK |
CAN_CTRL1_SMP_MASK);
/* Configure the baudrate prescaler. */
CANx->CTRL1 |= CAN_CTRL1_PRESDIV(prescaler - 1U);
/* Configure the propagation segment. */
CANx->CTRL1 |= CAN_CTRL1_PROPSEG(timingCfg.propSeg - 1U);
/* Configure the phase segments. */
CANx->CTRL1 |= CAN_CTRL1_PSEG1(timingCfg.phaseSeg1 - 1U);
CANx->CTRL1 |= CAN_CTRL1_PSEG2(timingCfg.phaseSeg2 - 1U);
/* The resynchronization jump width (RJW) can be 1 - 4 TQ, yet should never be larger
* than pseg1. Configure the longest possible value for RJW.
*/
rjw = (timingCfg.phaseSeg1 < 4) ? timingCfg.phaseSeg1 : 4;
CANx->CTRL1 |= CAN_CTRL1_RJW(rjw - 1U);
/* All the entries in canTiming[] have a PSEG1 >= 2, so three samples can be used to
* determine the value of the received bit, instead of the default one.
*/
CANx->CTRL1 |= CAN_CTRL1_SMP(1U);
/* Clear the message box RAM. Each message box covers 4 words (1 word = 32-bits. */
for (idx = 0; idx < (CANx_MAX_MB_NUM * 4U); idx++)
{
CANx->RAMn[idx] = 0U;
}
/* Clear the reception mask register for each message box. */
for (idx = 0; idx < CANx_MAX_MB_NUM; idx++)
{
CANx->RXIMR[idx] = 0U;
}
/* Configure the maximum number of message boxes. */
CANx->MCR = (CANx->MCR & ~CAN_MCR_MAXMB_MASK) | CAN_MCR_MAXMB(CANx_MAX_MB_NUM - 1U);
/* Disable the self reception feature. */
CANx->MCR = (CANx->MCR & ~CAN_MCR_SRXDIS_MASK) | CAN_MCR_SRXDIS(1U);
/* Enable individual reception masking. This disables the legacy support for the
* global reception mask and the mailbox 14/15 individual reception mask.
*/
CANx->MCR = (CANx->MCR & ~CAN_MCR_IRMQ_MASK) | CAN_MCR_IRMQ(1U);
/* Disable the reception FIFO. This driver only needs to receive one CAN message
* identifier. It is sufficient to use just one dedicated mailbox for this.
*/
CANx->MCR &= ~CAN_MCR_RFEN_MASK;
/* Configure the mask of the invididual message reception mailbox to check all ID bits
* and also the IDE bit.
*/
CANx->RXIMR[CAN_RX_MSGBOX_NUM] = 0x40000000U | 0x1FFFFFFFU;
/* Configure the reception mailbox to receive just the CAN message configured with
* BOOT_COM_CAN_RX_MSG_ID.
* EDL, BRS, ESI=0: CANFD not used.
* CODE=0b0100: mailbox set to active and empty.
* IDE=0: 11-bit CAN identifier.
* SRR, RTR, TIME STAMP=0: not applicable.
*/
CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 0U] = 0x04000000;
/* Store the message identifier to receive in the mailbox RAM. */
if ((rxMsgId & 0x80000000U) != 0U)
{
/* It is a 29-bit extended CAN identifier. */
rxMsgId &= ~0x80000000U;
/* Set the IDE bit to configure the message for a 29-bit identifier. */
CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 0U] |= CAN_WMBn_CS_IDE_MASK;
/* Store the 29-bit CAN identifier. */
CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 1U] = CAN_WMBn_ID_ID(rxMsgId);
}
else
{
/* Store the 11-bit CAN identifier. */
CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 1U] = CAN_WMBn_ID_ID(rxMsgId << 18U);
}
/* Disable all message box interrupts. */
CANx->IMASK1 = 0U;
/* Clear all mesasge box interrupt flags. */
CANx->IFLAG1 = CAN_IMASK1_BUF31TO0M_MASK;
/* Clear all error interrupt flags */
CANx->ESR1 = CAN_ESR1_ERRINT_MASK | CAN_ESR1_BOFFINT_MASK | CAN_ESR1_RWRNINT_MASK |
CAN_ESR1_TWRNINT_MASK | CAN_ESR1_BOFFDONEINT_MASK |
CAN_ESR1_ERRINT_FAST_MASK | CAN_ESR1_ERROVR_MASK;
/* Switch to normal user mode. */
CANx->MCR &= ~CAN_MCR_SUPV_MASK;
CANx->CTRL1 &= ~(CAN_CTRL1_LOM_MASK | CAN_CTRL1_LPB_MASK);
/* Exit freeze mode. */
CanFreezeModeExit();
/* Set timeout time for entering normal user mode. */
timeout = TimerGet() + CAN_INIT_TIMEOUT_MS;
/* Wait for normal user mode acknowledgement. */
while (((CANx->MCR & CAN_MCR_NOTRDY_MASK)) != 0U)
{
/* Break loop upon timeout. This would indicate a hardware failure. */
if (TimerGet() > timeout)
{
break;
}
}
} /*** end of BootComCanInit ***/
/************************************************************************************//**
** \brief Receives the CONNECT request from the host, which indicates that the
** bootloader should be activated and, if so, activates it.
** \return none.
**
****************************************************************************************/
static void BootComCanCheckActivationRequest(void)
{
unsigned char * pMsgBoxData;
unsigned char byteIdx;
unsigned char rxMsgData[8];
unsigned char rxMsgLen;
/* Check if a message was received in the individual mailbox configured to receive
* the BOOT_COM_CAN_RX_MSG_ID message.
*/
if ((CANx->IFLAG1 & (1U << CAN_RX_MSGBOX_NUM)) != 0U)
{
/* Note that there is no need to verify the identifier of the CAN message because the
* mailbox is configured to only receive the BOOT_COM_CAN_TX_MSG_ID message. Start
* by reading out the DLC of the newly received CAN message.
*/
rxMsgLen = (CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 0U] & CAN_WMBn_CS_DLC_MASK) >> CAN_WMBn_CS_DLC_SHIFT;
/* Read the data bytes of the CAN message from the mailbox RAM. */
pMsgBoxData = (unsigned char *)(&CANx->RAMn[(CAN_RX_MSGBOX_NUM * 4U) + 2U]);
for (byteIdx = 0; byteIdx < rxMsgLen; byteIdx++)
{
rxMsgData[byteIdx] = pMsgBoxData[((byteIdx) & ~3U) + (3U - ((byteIdx) & 3U))];
}
/* Clear the mailbox interrupt flag by writing a 1 to the corresponding box. */
CANx->IFLAG1 = (1U << CAN_RX_MSGBOX_NUM);
/* Read the free running timer to unlock the mailbox. */
dummyTimerVal = CANx->TIMER;
/* check if this was an XCP CONNECT command */
if ((rxMsgData[0] == 0xff) && (rxMsgLen == 2))
{
/* connection request received so start the bootloader */
BootActivate();
}
}
} /*** end of BootComCanCheckActivationRequest ***/
#endif /* BOOT_COM_CAN_ENABLE > 0 */
/*********************************** end of boot.c *************************************/

40
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/boot.h Normal file
View File

@ -0,0 +1,40 @@
/************************************************************************************//**
* \file Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/boot.h
* \brief Demo program bootloader interface header file.
* \ingroup Prog_ARMCM0_S32K14_S32K118EVB_IAR
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef BOOT_H
#define BOOT_H
/****************************************************************************************
* Function prototypes
****************************************************************************************/
void BootComInit(void);
void BootComCheckActivationRequest(void);
void BootActivate(void);
#endif /* BOOT_H */
/*********************************** end of boot.h *************************************/

42
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/header.h Normal file
View File

@ -0,0 +1,42 @@
/************************************************************************************//**
* \file Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/header.h
* \brief Generic header file.
* \ingroup Prog_ARMCM0_S32K14_S32K118EVB_IAR
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef HEADER_H
#define HEADER_H
/****************************************************************************************
* Include files
****************************************************************************************/
#include "../Boot/blt_conf.h" /* bootloader configuration */
#include "boot.h" /* bootloader interface driver */
#include "led.h" /* LED driver */
#include "timer.h" /* Timer driver */
#include "device_registers.h" /* Device registers */
#include "system_S32K118.h" /* Device sconfiguration */
#endif /* HEADER_H */
/*********************************** end of header.h ***********************************/

247
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/ide/s32k118.dep Normal file
View File

@ -0,0 +1,247 @@
<?xml version="1.0" encoding="UTF-8"?>
<project>
<fileVersion>4</fileVersion>
<fileChecksum>544470611</fileChecksum>
<configuration>
<name>Debug</name>
<outputs>
<file>$PROJ_DIR$\..\obj\timer.__cstat.et</file>
<file>$PROJ_DIR$\..\obj\led.xcl</file>
<file>$TOOLKIT_DIR$\inc\c\yvals.h</file>
<file>$PROJ_DIR$\..\boot.h</file>
<file>$PROJ_DIR$\..\boot.c</file>
<file>$PROJ_DIR$\..\header.h</file>
<file>$PROJ_DIR$\..\timer.c</file>
<file>$PROJ_DIR$\..\obj\s32k118.pbd</file>
<file>$PROJ_DIR$\..\led.c</file>
<file>$PROJ_DIR$\..\obj\startup.__cstat.et</file>
<file>$PROJ_DIR$\..\obj\system_S32K118.o</file>
<file>$PROJ_DIR$\..\obj\system_S32K118.__cstat.et</file>
<file>$PROJ_DIR$\..\obj\timer.xcl</file>
<file>$PROJ_DIR$\..\lib\S32K118_features.h</file>
<file>$PROJ_DIR$\..\lib\system_S32K118.h</file>
<file>$PROJ_DIR$\..\obj\system_S32K118.xcl</file>
<file>$PROJ_DIR$\..\obj\startup.xcl</file>
<file>$PROJ_DIR$\..\obj\boot.xcl</file>
<file>$PROJ_DIR$\..\timer.h</file>
<file>$PROJ_DIR$\..\lib\startup.h</file>
<file>$PROJ_DIR$\..\obj\boot.o</file>
<file>$PROJ_DIR$\..\obj\startup_S32K118.o</file>
<file>$PROJ_DIR$\..\obj\main.xcl</file>
<file>$PROJ_DIR$\..\main.c</file>
<file>$PROJ_DIR$\..\lib\startup.c</file>
<file>$PROJ_DIR$\..\obj\main.o</file>
<file>$PROJ_DIR$\..\bin\demoprog_s32k118.out</file>
<file>$PROJ_DIR$\..\startup_S32K118.s</file>
<file>$PROJ_DIR$\..\obj\led.o</file>
<file>$PROJ_DIR$\..\lib\system_S32K118.c</file>
<file>$PROJ_DIR$\..\led.h</file>
<file>$PROJ_DIR$\..\obj\timer.o</file>
<file>$PROJ_DIR$\..\lib\s32_core_cm0.h</file>
<file>$PROJ_DIR$\..\lib\S32K118.h</file>
<file>$PROJ_DIR$\..\lib\devassert.h</file>
<file>$PROJ_DIR$\..\lib\device_registers.h</file>
<file>$PROJ_DIR$\..\obj\startup.o</file>
<file>$TOOLKIT_DIR$\inc\c\DLib_Product.h</file>
<file>$TOOLKIT_DIR$\inc\c\stdint.h</file>
<file>$TOOLKIT_DIR$\inc\c\DLib_Defaults.h</file>
<file>$TOOLKIT_DIR$\lib\m6M_tl.a</file>
<file>$TOOLKIT_DIR$\lib\shb_l.a</file>
<file>$PROJ_DIR$\..\obj\main.__cstat.et</file>
<file>$PROJ_DIR$\..\obj\boot.__cstat.et</file>
<file>$PROJ_DIR$\..\obj\led.__cstat.et</file>
<file>$PROJ_DIR$\..\obj\demoprog_s32k118.map</file>
<file>$PROJ_DIR$\..\S32K118_25_flash.icf</file>
<file>$TOOLKIT_DIR$\lib\rt6M_tl.a</file>
<file>$PROJ_DIR$\..\..\Boot\blt_conf.h</file>
<file>$PROJ_DIR$\..\bin\demoprog_s32k118.srec</file>
<file>$TOOLKIT_DIR$\inc\c\stdbool.h</file>
<file>$TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h</file>
<file>$TOOLKIT_DIR$\lib\dl6M_tln.a</file>
<file>$TOOLKIT_DIR$\inc\c\ycheck.h</file>
</outputs>
<file>
<name>[ROOT_NODE]</name>
<outputs>
<tool>
<name>ILINK</name>
<file> 26 45</file>
</tool>
</outputs>
</file>
<file>
<name>$PROJ_DIR$\..\boot.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 20</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 17</file>
</tool>
<tool>
<name>__cstat</name>
<file> 43</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 5 48 3 30 18 35 32 33 38 53 2 39 51 37 13 34 50 14</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\timer.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 31</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 12</file>
</tool>
<tool>
<name>__cstat</name>
<file> 0</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 5 48 3 30 18 35 32 33 38 53 2 39 51 37 13 34 50 14</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\led.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 28</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 1</file>
</tool>
<tool>
<name>__cstat</name>
<file> 44</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 5 48 3 30 18 35 32 33 38 53 2 39 51 37 13 34 50 14</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\main.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 25</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 22</file>
</tool>
<tool>
<name>__cstat</name>
<file> 42</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 5 48 3 30 18 35 32 33 38 53 2 39 51 37 13 34 50 14</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\lib\startup.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 36</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 16</file>
</tool>
<tool>
<name>__cstat</name>
<file> 9</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 19 38 53 2 39 51 37 35 32 33 13 34 50</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\bin\demoprog_s32k118.out</name>
<outputs>
<tool>
<name>OBJCOPY</name>
<file> 49</file>
</tool>
<tool>
<name>ILINK</name>
<file> 45</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ILINK</name>
<file> 46 20 28 25 36 21 10 31 41 47 40 52</file>
</tool>
</inputs>
</file>
<file>
<name>$PROJ_DIR$\..\startup_S32K118.s</name>
<outputs>
<tool>
<name>AARM</name>
<file> 21</file>
</tool>
</outputs>
</file>
<file>
<name>$PROJ_DIR$\..\lib\system_S32K118.c</name>
<outputs>
<tool>
<name>ICCARM</name>
<file> 10</file>
</tool>
<tool>
<name>BICOMP</name>
<file> 15</file>
</tool>
<tool>
<name>__cstat</name>
<file> 11</file>
</tool>
</outputs>
<inputs>
<tool>
<name>ICCARM</name>
<file> 35 32 33 38 53 2 39 51 37 13 34 50 14</file>
</tool>
</inputs>
</file>
</configuration>
<configuration>
<name>Release</name>
<outputs />
<forcedrebuild>
<name>[MULTI_TOOL]</name>
<tool>ILINK</tool>
</forcedrebuild>
</configuration>
</project>

2966
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/ide/s32k118.ewd Normal file
View File

File diff suppressed because it is too large Load Diff

2167
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/ide/s32k118.ewp Normal file
View File

File diff suppressed because it is too large Load Diff

2432
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/ide/s32k118.ewt Normal file
View File

File diff suppressed because it is too large Load Diff

7
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/ide/s32k118.eww Normal file
View File

@ -0,0 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<workspace>
<project>
<path>$WS_DIR$\s32k118.ewp</path>
</project>
<batchBuild />
</workspace>

96
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/led.c Normal file
View File

@ -0,0 +1,96 @@
/************************************************************************************//**
* \file Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/led.c
* \brief LED driver source file.
* \ingroup Prog_ARMCM0_S32K14_S32K118EVB_IAR
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
/****************************************************************************************
* Include files
****************************************************************************************/
#include "header.h" /* generic header */
/****************************************************************************************
* Macro definitions
****************************************************************************************/
/** \brief Toggle interval time in milliseconds. */
#define LED_TOGGLE_MS (500U)
/************************************************************************************//**
** \brief Initializes the LED.
** \return none.
**
****************************************************************************************/
void LedInit(void)
{
/* LED GPIO pin configuration. PE8 = GPIO, MUX = ALT1. */
PORTE->PCR[8] = PORT_PCR_MUX(1);
/* Configure Port E pin 8 GPIO as digital output. */
PTE->PDDR |= GPIO_PDDR_PDD(1 << 8U);
/* Turn the LED off on Port E pin 8. */
PTE->PCOR |= GPIO_PSOR_PTSO(1 << 8U);
} /*** end of LedInit ***/
/************************************************************************************//**
** \brief Toggles the LED at a fixed time interval.
** \return none.
**
****************************************************************************************/
void LedToggle(void)
{
static unsigned char led_toggle_state = 0;
static unsigned long timer_counter_last = 0;
unsigned long timer_counter_now;
/* Check if toggle interval time passed. */
timer_counter_now = TimerGet();
if ( (timer_counter_now - timer_counter_last) < LED_TOGGLE_MS)
{
/* Not yet time to toggle. */
return;
}
/* Determine toggle action. */
if (led_toggle_state == 0)
{
led_toggle_state = 1;
/* Turn the LED on. */
PTE->PSOR |= GPIO_PSOR_PTSO(1 << 8U);
}
else
{
led_toggle_state = 0;
/* Turn the LED off. */
PTE->PCOR |= GPIO_PSOR_PTSO(1 << 8U);
}
/* Store toggle time to determine next toggle interval. */
timer_counter_last = timer_counter_now;
} /*** end of LedToggle ***/
/*********************************** end of led.c **************************************/

39
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/led.h Normal file
View File

@ -0,0 +1,39 @@
/************************************************************************************//**
* \file Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/led.h
* \brief LED driver header file.
* \ingroup Prog_ARMCM0_S32K14_S32K118EVB_IAR
* \internal
*----------------------------------------------------------------------------------------
* C O P Y R I G H T
*----------------------------------------------------------------------------------------
* Copyright (c) 2020 by Feaser http://www.feaser.com All rights reserved
*
*----------------------------------------------------------------------------------------
* L I C E N S E
*----------------------------------------------------------------------------------------
* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published by the Free
* Software Foundation, either version 3 of the License, or (at your option) any later
* version.
*
* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You have received a copy of the GNU General Public License along with OpenBLT. It
* should be located in ".\Doc\license.html". If not, contact Feaser to obtain a copy.
*
* \endinternal
****************************************************************************************/
#ifndef LED_H
#define LED_H
/****************************************************************************************
* Function prototypes
****************************************************************************************/
void LedInit(void);
void LedToggle(void);
#endif /* LED_H */
/*********************************** end of led.h **************************************/

10438
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/lib/S32K118.h Normal file
View File

File diff suppressed because it is too large Load Diff

1302
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/lib/S32K118_features.h Normal file
View File

File diff suppressed because it is too large Load Diff

84
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/lib/devassert.h Normal file
View File

@ -0,0 +1,84 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef DEVASSERT_H
#define DEVASSERT_H
#include <stdbool.h>
/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 2.5, global macro not referenced.
* The macro is defined to be used by drivers to validate input parameters and can be disabled.
*
* @section [global]
* Violates MISRA 2012 Advisory Directive 4.9, Function-like macro defined.
* The macros are used to validate input parameters to driver functions.
*
*/
/**
\page Error_detection_and_reporting Error detection and reporting
S32 SDK drivers can use a mechanism to validate data coming from upper software layers (application code) by performing
a number of checks on input parameters' range or other invariants that can be statically checked (not dependent on
runtime conditions). A failed validation is indicative of a software bug in application code, therefore it is important
to use this mechanism during development.
The validation is performed by using DEV_ASSERT macro.
A default implementation of this macro is provided in this file. However, application developers can provide their own
implementation in a custom file. This requires defining the CUSTOM_DEVASSERT symbol with the specific file name in the
project configuration (for example: -DCUSTOM_DEVASSERT="custom_devassert.h")
The default implementation accommodates two behaviors, based on DEV_ERROR_DETECT symbol:
- When DEV_ERROR_DETECT symbol is defined in the project configuration (for example: -DDEV_ERROR_DETECT), the validation
performed by the DEV_ASSERT macro is enabled, and a failed validation triggers a software breakpoint and further execution is
prevented (application spins in an infinite loop)
This configuration is recommended for development environments, as it prevents further execution and allows investigating
potential problems from the point of error detection.
- When DEV_ERROR_DETECT symbol is not defined, the DEV_ASSERT macro is implemented as no-op, therefore disabling all validations.
This configuration can be used to eliminate the overhead of development-time checks.
It is the application developer's responsibility to decide the error detection strategy for production code: one can opt to
disable development-time checking altogether (by not defining DEV_ERROR_DETECT symbol), or one can opt to keep the checks
in place and implement a recovery mechanism in case of a failed validation, by defining CUSTOM_DEVASSERT to point
to the file containing the custom implementation.
*/
#if defined (CUSTOM_DEVASSERT)
/* If the CUSTOM_DEVASSERT symbol is defined, then add the custom implementation */
#include CUSTOM_DEVASSERT
#elif defined (DEV_ERROR_DETECT)
/* Implement default assert macro */
static inline void DevAssert(volatile bool x)
{
if(x) { } else { BKPT_ASM; for(;;) {} }
}
#define DEV_ASSERT(x) DevAssert(x)
#else
/* Assert macro does nothing */
#define DEV_ASSERT(x) ((void)0)
#endif
#endif /* DEVASSERT_H */
/*******************************************************************************
* EOF
******************************************************************************/

67
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/lib/device_registers.h Normal file
View File

@ -0,0 +1,67 @@
/*
** ###################################################################
** Abstract:
** Common include file for CMSIS register access layer headers.
**
** Copyright (c) 2015 Freescale Semiconductor, Inc.
** Copyright 2016-2017 NXP
** All rights reserved.
**
** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
** THE POSSIBILITY OF SUCH DAMAGE.
**
** http: www.nxp.com
** mail: support@nxp.com
** ###################################################################
*/
#ifndef DEVICE_REGISTERS_H
#define DEVICE_REGISTERS_H
/**
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 2.5, global macro not referenced.
* The macro defines the device currently in use and may be used by components for specific checks.
*
*/
/*
* Include the cpu specific register header files.
*
* The CPU macro should be declared in the project or makefile.
*/
#if defined(CPU_S32K118)
#define S32K11x_SERIES
/* Specific core definitions */
#include "s32_core_cm0.h"
/* Register definitions */
#include "S32K118.h"
/* CPU specific feature definitions */
#include "S32K118_features.h"
#else
#error "No valid CPU defined!"
#endif
#include "devassert.h"
#endif /* DEVICE_REGISTERS_H */
/*******************************************************************************
* EOF
******************************************************************************/

198
Target/Demo/ARMCM0_S32K14_S32K118EVB_IAR/Prog/lib/s32_core_cm0.h Normal file
View File

@ -0,0 +1,198 @@
/*
* Copyright (c) 2015-2016 Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/*!
* @file s32_core_cm0.h
*
* @page misra_violations MISRA-C:2012 violations
*
* @section [global]
* Violates MISRA 2012 Advisory Directive 4.9, Function-like macro
* Function-like macros are used instead of inline functions in order to ensure
* that the performance will not be decreased if the functions will not be
* inlined by the compiler.
*
* @section [global]
* Violates MISRA 2012 Advisory Rule 2.5, Global macro not referenced.
* The macros defined are used only on some of the drivers, so this might be reported
* when the analysis is made only on one driver.
*/
/*
* Tool Chains:
* GNUC flag is defined also by ARM compiler - it shows the current major version of the compatible GCC version
* __GNUC__ : GNU Compiler Collection
* __ghs__ : Green Hills ARM Compiler
* __ICCARM__ : IAR ARM Compiler
* __DCC__ : Wind River Diab Compiler
* __ARMCC_VERSION : ARM Compiler
*/
#if !defined (CORE_CM0_H)
#define CORE_CM0_H
#ifdef __cplusplus
extern "C" {
#endif
/** \brief BKPT_ASM
*
* Macro to be used to trigger an debug interrupt
*/
#if defined ( __DCC__ )
#define BKPT_ASM __asm ("BKPT 0\n\t")
#else
#define BKPT_ASM __asm ("BKPT #0\n\t")
#endif
/** \brief Enable interrupts
*/
#if defined (__GNUC__)
#define ENABLE_INTERRUPTS() __asm volatile ("cpsie i" : : : "memory");
#elif defined ( __DCC__ )
#define ENABLE_INTERRUPTS() __asm (".short 0xb662");
#else
#define ENABLE_INTERRUPTS() __asm("cpsie i")
#endif
/** \brief Disable interrupts
*/
#if defined (__GNUC__)
#define DISABLE_INTERRUPTS() __asm volatile ("cpsid i" : : : "memory");
#elif defined ( __DCC__ )
#define DISABLE_INTERRUPTS() __asm (".short 0xb672");
#else
#define DISABLE_INTERRUPTS() __asm("cpsid i")
#endif
/** \brief Enter low-power standby state
* WFI (Wait For Interrupt) makes the processor suspend execution (Clock is stopped) until an IRQ interrupts.
*/
#if defined (__GNUC__)
#define STANDBY() __asm volatile ("wfi")
#elif defined ( __DCC__ )
#define STANDBY() __asm (".short 0xbf30");
#else
#define STANDBY() __asm ("wfi")
#endif
/** \brief No-op
*/
#define NOP() __asm volatile ("nop")
/** \brief Reverse byte order in a word.
* ARM Documentation Cortex-M0 Devices Generic User Guide
* Accordingly to 3.5.7. REV, REV16, and REVSH
* Restriction "This function requires low registers R0-R7 register"
*/
#if defined (__GNUC__) || defined (__ICCARM__) || defined (__ARMCC_VERSION)
#define REV_BYTES_32(a, b) __asm volatile ("rev %0, %1" : "=l" (b) : "l" (a))
#elif defined (__ghs__)
#define REV_BYTES_32(a, b) __asm volatile ("rev %0, %1" : "=r" (b) : "r" (a))
#else
#define REV_BYTES_32(a, b) (b = ((a & 0xFF000000U) >> 24U) | ((a & 0xFF0000U) >> 8U) \
| ((a & 0xFF00U) << 8U) | ((a & 0xFFU) << 24U))
#endif
/** \brief Reverse byte order in each halfword independently.
* ARM Documentation Cortex-M0 Devices Generic User Guide
* Accordingly to 3.5.7. REV, REV16, and REVSH
* Restriction "This function requires low registers R0-R7 register"
*/
#if defined (__GNUC__) || defined (__ICCARM__) || defined (__ARMCC_VERSION)
#define REV_BYTES_16(a, b) __asm volatile ("rev16 %0, %1" : "=l" (b) : "l" (a))
#elif defined (__ghs__)
#define REV_BYTES_16(a, b) __asm volatile ("rev16 %0, %1" : "=r" (b) : "r" (a))
#else
#define REV_BYTES_16(a, b) (b = ((a & 0xFF000000U) >> 8U) | ((a & 0xFF0000U) << 8U) \
| ((a & 0xFF00U) >> 8U) | ((a & 0xFFU) << 8U))
#endif
/** \brief Places a function in RAM.
*/
#if defined ( __GNUC__ ) || defined (__ARMCC_VERSION)
#define START_FUNCTION_DECLARATION_RAMSECTION
#define END_FUNCTION_DECLARATION_RAMSECTION __attribute__((section (".code_ram")));
#elif defined ( __ghs__ )
#define START_FUNCTION_DECLARATION_RAMSECTION _Pragma("ghs callmode=far")
#define END_FUNCTION_DECLARATION_RAMSECTION __attribute__((section (".code_ram")));\
_Pragma("ghs callmode=default")
#elif defined ( __ICCARM__ )
#define START_FUNCTION_DECLARATION_RAMSECTION __ramfunc
#define END_FUNCTION_DECLARATION_RAMSECTION ;
#elif defined ( __DCC__ )
#define START_FUNCTION_DECLARATION_RAMSECTION _Pragma("section CODE \".code_ram\" \"\" far-absolute") \
_Pragma("use_section CODE")
#define END_FUNCTION_DECLARATION_RAMSECTION ; \
_Pragma("section CODE \".text\"")
#else
/* Keep compatibility with software analysis tools */
#define START_FUNCTION_DECLARATION_RAMSECTION
#define END_FUNCTION_DECLARATION_RAMSECTION ;
#endif
/* For GCC, IAR, GHS, Diab and ARMC there is no need to specify the section when
defining a function, it is enough to specify it at the declaration. This
also enables compatibility with software analysis tools. */
#define START_FUNCTION_DEFINITION_RAMSECTION
#define END_FUNCTION_DEFINITION_RAMSECTION
#if defined (__ICCARM__)
#define DISABLE_CHECK_RAMSECTION_FUNCTION_CALL _Pragma("diag_suppress=Ta022")
#define ENABLE_CHECK_RAMSECTION_FUNCTION_CALL _Pragma("diag_default=Ta022")
#else
#define DISABLE_CHECK_RAMSECTION_FUNCTION_CALL
#define ENABLE_CHECK_RAMSECTION_FUNCTION_CALL
#endif
/** \brief Get Core ID
*
* GET_CORE_ID returns the processor identification number for cm0
*/
#define GET_CORE_ID() 0U
/** \brief Data alignment.
*/
#if defined ( __GNUC__ ) || defined ( __ghs__ ) || defined ( __DCC__ ) || defined (__ARMCC_VERSION)
#define ALIGNED(x) __attribute__((aligned(x)))
#elif defined ( __ICCARM__ )
#define stringify(s) tostring(s)
#define tostring(s) #s
#define ALIGNED(x) _Pragma(stringify(data_alignment=x))
#else
/* Keep compatibility with software analysis tools */
#define ALIGNED(x)
#endif
/** \brief Endianness.
*/
#define CORE_LITTLE_ENDIAN
#ifdef __cplusplus
}
#endif
#endif /* CORE_CM0_H */
/*******************************************************************************
* EOF
******************************************************************************/

Some files were not shown because too many files have changed in this diff Show More