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Refs #1874. Documented/corrected timer APB bus selection for the STM32C0, STM32G0 and STM32G4 ports. 

git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@1137 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
This commit is contained in:
Frank Voorburg 2023-12-08 10:58:47 +00:00
parent b6765765ca
commit 9f68b1457c
3 changed files with 10 additions and 2 deletions
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4
Target/Source/ARMCM0_STM32C0/timer.c
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@ -73,6 +73,10 @@ void TimerInit(void)
/* All STM32C0 derivatives support a TIM1 peripheral. Its free running counter will be
* used to realize the polling based millisecond time reference in this module.
* Start by enabling the periperhal.
*
* Note that the STM32C0 features one PCLK clock that drives both APB1 and APB2 busses.
* The RCC LL drivers call PCLK PCLK1 and APB APB1. Therefore the following lines
* use the PCLK1/APB1 APIs, even though TIM1 is actually on ABP2.
*/
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1);
/* The TIM1 peripheral clock is derived from PCLK. Obtain the PCLK frequency. */

4
Target/Source/ARMCM0_STM32G0/timer.c
View File

@ -80,6 +80,10 @@ void TimerInit(void)
/* All STM32G0 derivatives support a TIM1 peripheral. Its free running counter will be
* used to realize the polling based millisecond time reference in this module.
* Start by enabling the periperhal.
*
* Note that the STM32G0 features one PCLK clock that drives both APB1 and APB2 busses.
* The RCC LL drivers call PCLK PCLK1 and APB APB1. Therefore the following lines
* use the PCLK1/APB1 APIs, even though TIM1 is actually on ABP2.
*/
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1);
/* The TIM1 peripheral clock is derived from PCLK. Obtain the PCLK frequency. */

4
Target/Source/ARMCM4_STM32G4/timer.c
View File

@ -76,12 +76,12 @@ void TimerInit(void)
*/
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1);
/* The TIM1 peripheral clock is derived from PCLK. Obtain the PCLK frequency. */
pclk_frequency = __LL_RCC_CALC_PCLK1_FREQ(SystemCoreClock, LL_RCC_GetAPB1Prescaler());
pclk_frequency = __LL_RCC_CALC_PCLK2_FREQ(SystemCoreClock, LL_RCC_GetAPB2Prescaler());
/* According to the clock tree diagram in the RCC chapter of the reference manual,
* the TPCLK frequency = PLCK * 1, when the APB1 prescaler is 1, otherwise it is
* PCLK * 2.
*/
tim_multiplier = (LL_RCC_GetAPB1Prescaler() == LL_RCC_APB1_DIV_1) ? 1U : 2U;
tim_multiplier = (LL_RCC_GetAPB2Prescaler() == LL_RCC_APB2_DIV_1) ? 1U : 2U;
/* Obtain the TPCLK frequency. */
pclk_tim_frequency = pclk_frequency * tim_multiplier;
/* Configure the free running counter as a 16-bit upwards counter that runs at the