mirror of https://github.com/rusefi/rusefi-1.git
auto-sync
This commit is contained in:
rusEfi
parent
8a0cf80012
commit
8ab8f6c4f7
|
|
@ -205,7 +205,7 @@
|
|||
</toolChain>
|
||||
</folderInfo>
|
||||
<sourceEntries>
|
||||
<entry excluding="config/stm32f0egt|egt2can.cpp|chibios/boards/simulator|chibios/boards/OLIMEX_STM32_E407|chibios/boards/ST_STM32F0_DISCOVERY|chibios/os/ports/GCC/ARMCMx/STM32F0xx|hw_layer/stm32f0|chibios/os/hal/platforms/STM32/I2Cv2|chibios/os/hal/platforms/STM32/SPIv2|chibios/os/hal/platforms/STM32/USARTv2|chibios/os/ports/IAR|chibios/os/hal/platforms/STM32F0xx|chibios/os/hal/platforms/Win32|chibios/os/ports/GCC/ARMCMx/chcore_v6m.c|chibios/os/ports/GCC/SIMIA32|chibios/os/ports/IAR/ARMCMx/chcore_v6m.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
|
||||
<entry excluding="chibios/os/ports/GCC/ARMCMx/STM32F1xx|chibios/os/hal/platforms/STM32F1xx|chibios/boards/ST_NUCLEO_F103RB|config/stm32f0egt|egt2can.cpp|chibios/boards/simulator|chibios/boards/OLIMEX_STM32_E407|chibios/boards/ST_STM32F0_DISCOVERY|chibios/os/ports/GCC/ARMCMx/STM32F0xx|hw_layer/stm32f0|chibios/os/hal/platforms/STM32/I2Cv2|chibios/os/hal/platforms/STM32/SPIv2|chibios/os/hal/platforms/STM32/USARTv2|chibios/os/ports/IAR|chibios/os/hal/platforms/STM32F0xx|chibios/os/hal/platforms/Win32|chibios/os/ports/GCC/ARMCMx/chcore_v6m.c|chibios/os/ports/GCC/SIMIA32|chibios/os/ports/IAR/ARMCMx/chcore_v6m.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
|
||||
</sourceEntries>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
|
|
@ -288,7 +288,7 @@
|
|||
</toolChain>
|
||||
</folderInfo>
|
||||
<sourceEntries>
|
||||
<entry excluding="config/stm32f0egt|egt2can.cpp|chibios/boards/simulator|chibios/boards/OLIMEX_STM32_E407|chibios/boards/ST_STM32F0_DISCOVERY|chibios/os/ports/GCC/ARMCMx/STM32F0xx|hw_layer/stm32f0|chibios/os/hal/platforms/STM32/I2Cv2|chibios/os/hal/platforms/STM32/SPIv2|chibios/os/hal/platforms/STM32/USARTv2|chibios/os/ports/IAR|chibios/os/hal/platforms/STM32F0xx|chibios/os/hal/platforms/Win32|chibios/os/ports/GCC/ARMCMx/chcore_v6m.c|chibios/os/ports/GCC/SIMIA32|chibios/os/ports/IAR/ARMCMx/chcore_v6m.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
|
||||
<entry excluding="chibios/os/ports/GCC/ARMCMx/STM32F1xx|chibios/os/hal/platforms/STM32F1xx|chibios/boards/ST_NUCLEO_F103RB|config/stm32f0egt|egt2can.cpp|chibios/boards/simulator|chibios/boards/OLIMEX_STM32_E407|chibios/boards/ST_STM32F0_DISCOVERY|chibios/os/ports/GCC/ARMCMx/STM32F0xx|hw_layer/stm32f0|chibios/os/hal/platforms/STM32/I2Cv2|chibios/os/hal/platforms/STM32/SPIv2|chibios/os/hal/platforms/STM32/USARTv2|chibios/os/ports/IAR|chibios/os/hal/platforms/STM32F0xx|chibios/os/hal/platforms/Win32|chibios/os/ports/GCC/ARMCMx/chcore_v6m.c|chibios/os/ports/GCC/SIMIA32|chibios/os/ports/IAR/ARMCMx/chcore_v6m.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
|
||||
</sourceEntries>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
|
|
|
|||
|
|
@ -0,0 +1,50 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
#include "ch.h"
|
||||
#include "hal.h"
|
||||
|
||||
/**
|
||||
* @brief PAL setup.
|
||||
* @details Digital I/O ports static configuration as defined in @p board.h.
|
||||
* This variable is used by the HAL when initializing the PAL driver.
|
||||
*/
|
||||
#if HAL_USE_PAL || defined(__DOXYGEN__)
|
||||
const PALConfig pal_default_config =
|
||||
{
|
||||
{VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
|
||||
{VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
|
||||
{VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
|
||||
{VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
|
||||
{VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
|
||||
};
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Early initialization code.
|
||||
* This initialization must be performed just after stack setup and before
|
||||
* any other initialization.
|
||||
*/
|
||||
void __early_init(void) {
|
||||
|
||||
stm32_clock_init();
|
||||
}
|
||||
|
||||
/*
|
||||
* Board-specific initialization code.
|
||||
*/
|
||||
void boardInit(void) {
|
||||
}
|
||||
|
|
@ -0,0 +1,202 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _BOARD_H_
|
||||
#define _BOARD_H_
|
||||
|
||||
/*
|
||||
* Setup for the ST INEMO-M1 Discovery board.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Board identifier.
|
||||
*/
|
||||
#define BOARD_ST_NUCLEO_F103RB
|
||||
#define BOARD_NAME "STMicroelectronics NUCLEO-F103RB"
|
||||
|
||||
/*
|
||||
* Board frequencies.
|
||||
*/
|
||||
#define STM32_LSECLK 0
|
||||
|
||||
#if defined(NUCLEO_EXTERNAL_OSCILLATOR)
|
||||
#define STM32_HSECLK 8000000
|
||||
#define STM32_HSE_BYPASS
|
||||
|
||||
#elif defined(NUCLEO_HSE_CRYSTAL)
|
||||
#define STM32_HSECLK 8000000
|
||||
|
||||
#else
|
||||
#define STM32_HSECLK 0
|
||||
#endif
|
||||
|
||||
/*
|
||||
* MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
|
||||
*/
|
||||
#define STM32F10X_MD
|
||||
|
||||
/*
|
||||
* IO pins assignments.
|
||||
*/
|
||||
#define GPIOA_PA0 0
|
||||
#define GPIOA_PA1 1
|
||||
#define GPIOA_USART_TX 2
|
||||
#define GPIOA_USART_RX 3
|
||||
#define GPIOA_PA4 4
|
||||
#define GPIOA_LED_GREEN 5
|
||||
#define GPIOA_PA6 6
|
||||
#define GPIOA_PA7 7
|
||||
#define GPIOA_PA8 8
|
||||
#define GPIOA_PA9 9
|
||||
#define GPIOA_PA10 10
|
||||
#define GPIOA_PA11 11
|
||||
#define GPIOA_PA12 12
|
||||
#define GPIOA_SWDIO 13
|
||||
#define GPIOA_SWCLK 14
|
||||
#define GPIOA_PA15 15
|
||||
|
||||
#define GPIOB_PB0 0
|
||||
#define GPIOB_PB1 1
|
||||
#define GPIOB_PB2 2
|
||||
#define GPIOB_SWO 3
|
||||
#define GPIOB_PB4 4
|
||||
#define GPIOB_PB5 5
|
||||
#define GPIOB_PB6 6
|
||||
#define GPIOB_PB7 7
|
||||
#define GPIOB_PB8 8
|
||||
#define GPIOB_PB9 9
|
||||
#define GPIOB_PB10 10
|
||||
#define GPIOB_PB11 11
|
||||
#define GPIOB_PB12 12
|
||||
#define GPIOB_PB13 13
|
||||
#define GPIOB_PB14 14
|
||||
#define GPIOB_PB15 15
|
||||
|
||||
#define GPIOC_PC0 0
|
||||
#define GPIOC_PC1 1
|
||||
#define GPIOC_PC2 2
|
||||
#define GPIOC_PC3 3
|
||||
#define GPIOC_PC4 4
|
||||
#define GPIOC_PC5 5
|
||||
#define GPIOC_PC6 6
|
||||
#define GPIOC_PC7 7
|
||||
#define GPIOC_PC8 8
|
||||
#define GPIOC_PC9 9
|
||||
#define GPIOC_PC10 10
|
||||
#define GPIOC_PC11 11
|
||||
#define GPIOC_PC12 12
|
||||
#define GPIOC_BUTTON 13
|
||||
#define GPIOC_PC14 14
|
||||
#define GPIOC_PC15 15
|
||||
|
||||
#define GPIOD_OSC_IN 0
|
||||
#define GPIOD_OSC_OUT 1
|
||||
#define GPIOD_PD2 2
|
||||
|
||||
/*
|
||||
* I/O ports initial setup, this configuration is established soon after reset
|
||||
* in the initialization code.
|
||||
*
|
||||
* The digits have the following meaning:
|
||||
* 0 - Analog input.
|
||||
* 1 - Push Pull output 10MHz.
|
||||
* 2 - Push Pull output 2MHz.
|
||||
* 3 - Push Pull output 50MHz.
|
||||
* 4 - Digital input.
|
||||
* 5 - Open Drain output 10MHz.
|
||||
* 6 - Open Drain output 2MHz.
|
||||
* 7 - Open Drain output 50MHz.
|
||||
* 8 - Digital input with PullUp or PullDown resistor depending on ODR.
|
||||
* 9 - Alternate Push Pull output 10MHz.
|
||||
* A - Alternate Push Pull output 2MHz.
|
||||
* B - Alternate Push Pull output 50MHz.
|
||||
* C - Reserved.
|
||||
* D - Alternate Open Drain output 10MHz.
|
||||
* E - Alternate Open Drain output 2MHz.
|
||||
* F - Alternate Open Drain output 50MHz.
|
||||
* Please refer to the STM32 Reference Manual for details.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Port A setup.
|
||||
* Everything input with pull-up except:
|
||||
* PA2 - Alternate output (GPIOA_USART_TX).
|
||||
* PA3 - Normal input (GPIOA_USART_RX).
|
||||
* PA5 - Push Pull output (GPIOA_LED_GREEN).
|
||||
* PA13 - Pull-up input (GPIOA_SWDIO).
|
||||
* PA14 - Pull-down input (GPIOA_SWCLK).
|
||||
*/
|
||||
#define VAL_GPIOACRL 0x88384B88 /* PA7...PA0 */
|
||||
#define VAL_GPIOACRH 0x88888888 /* PA15...PA8 */
|
||||
#define VAL_GPIOAODR 0xFFFFBFDF
|
||||
|
||||
/*
|
||||
* Port B setup.
|
||||
* Everything input with pull-up except:
|
||||
* PB3 - Pull-up input (GPIOA_SWO).
|
||||
*/
|
||||
#define VAL_GPIOBCRL 0x88888888 /* PB7...PB0 */
|
||||
#define VAL_GPIOBCRH 0x88888888 /* PB15...PB8 */
|
||||
#define VAL_GPIOBODR 0xFFFFFFFF
|
||||
|
||||
/*
|
||||
* Port C setup.
|
||||
* Everything input with pull-up except:
|
||||
* PC13 - Normal input (GPIOC_BUTTON).
|
||||
*/
|
||||
#define VAL_GPIOCCRL 0x88888888 /* PC7...PC0 */
|
||||
#define VAL_GPIOCCRH 0x88488888 /* PC15...PC8 */
|
||||
#define VAL_GPIOCODR 0xFFFFFFFF
|
||||
|
||||
/*
|
||||
* Port D setup.
|
||||
* Everything input with pull-up except:
|
||||
* PD0 - Normal input (GPIOD_OSC_IN).
|
||||
* PD1 - Normal input (GPIOD_OSC_OUT).
|
||||
*/
|
||||
#define VAL_GPIODCRL 0x88888844 /* PD7...PD0 */
|
||||
#define VAL_GPIODCRH 0x88888888 /* PD15...PD8 */
|
||||
#define VAL_GPIODODR 0xFFFFFFFF
|
||||
|
||||
/*
|
||||
* Port E setup.
|
||||
* Everything input with pull-up except:
|
||||
*/
|
||||
#define VAL_GPIOECRL 0x88888888 /* PE7...PE0 */
|
||||
#define VAL_GPIOECRH 0x88888888 /* PE15...PE8 */
|
||||
#define VAL_GPIOEODR 0xFFFFFFFF
|
||||
|
||||
/*
|
||||
* USB bus activation macro, required by the USB driver.
|
||||
*/
|
||||
#define usb_lld_connect_bus(usbp)
|
||||
|
||||
/*
|
||||
* USB bus de-activation macro, required by the USB driver.
|
||||
*/
|
||||
#define usb_lld_disconnect_bus(usbp)
|
||||
|
||||
#if !defined(_FROM_ASM_)
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void boardInit(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* _FROM_ASM_ */
|
||||
|
||||
#endif /* _BOARD_H_ */
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
# List of all the board related files.
|
||||
BOARDSRC = ${CHIBIOS}/boards/ST_NUCLEO_F103RB/board.c
|
||||
|
||||
# Required include directories
|
||||
BOARDINC = ${CHIBIOS}/boards/ST_NUCLEO_F103RB
|
||||
|
|
@ -0,0 +1,234 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file STM32F1xx/adc_lld.c
|
||||
* @brief STM32F1xx ADC subsystem low level driver source.
|
||||
*
|
||||
* @addtogroup ADC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "ch.h"
|
||||
#include "hal.h"
|
||||
|
||||
#if HAL_USE_ADC || defined(__DOXYGEN__)
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local definitions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported variables. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/** @brief ADC1 driver identifier.*/
|
||||
#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
|
||||
ADCDriver ADCD1;
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local variables and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Shared ADC DMA ISR service routine.
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object
|
||||
* @param[in] flags pre-shifted content of the ISR register
|
||||
*/
|
||||
static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
|
||||
|
||||
/* DMA errors handling.*/
|
||||
if ((flags & STM32_DMA_ISR_TEIF) != 0) {
|
||||
/* DMA, this could help only if the DMA tries to access an unmapped
|
||||
address space or violates alignment rules.*/
|
||||
_adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
|
||||
}
|
||||
else {
|
||||
if ((flags & STM32_DMA_ISR_TCIF) != 0) {
|
||||
/* Transfer complete processing.*/
|
||||
_adc_isr_full_code(adcp);
|
||||
}
|
||||
else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
|
||||
/* Half transfer processing.*/
|
||||
_adc_isr_half_code(adcp);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver interrupt handlers. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Low level ADC driver initialization.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void adc_lld_init(void) {
|
||||
|
||||
#if STM32_ADC_USE_ADC1
|
||||
/* Driver initialization.*/
|
||||
adcObjectInit(&ADCD1);
|
||||
ADCD1.adc = ADC1;
|
||||
ADCD1.dmastp = STM32_DMA1_STREAM1;
|
||||
ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
|
||||
STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
|
||||
STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
|
||||
STM32_DMA_CR_TEIE;
|
||||
|
||||
/* Temporary activation.*/
|
||||
rccEnableADC1(FALSE);
|
||||
ADC1->CR1 = 0;
|
||||
ADC1->CR2 = ADC_CR2_ADON;
|
||||
|
||||
/* Reset calibration just to be safe.*/
|
||||
ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL;
|
||||
while ((ADC1->CR2 & ADC_CR2_RSTCAL) != 0)
|
||||
;
|
||||
|
||||
/* Calibration.*/
|
||||
ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_CAL;
|
||||
while ((ADC1->CR2 & ADC_CR2_CAL) != 0)
|
||||
;
|
||||
|
||||
/* Return the ADC in low power mode.*/
|
||||
ADC1->CR2 = 0;
|
||||
rccDisableADC1(FALSE);
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures and activates the ADC peripheral.
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void adc_lld_start(ADCDriver *adcp) {
|
||||
|
||||
/* If in stopped state then enables the ADC and DMA clocks.*/
|
||||
if (adcp->state == ADC_STOP) {
|
||||
#if STM32_ADC_USE_ADC1
|
||||
if (&ADCD1 == adcp) {
|
||||
bool_t b;
|
||||
b = dmaStreamAllocate(adcp->dmastp,
|
||||
STM32_ADC_ADC1_IRQ_PRIORITY,
|
||||
(stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
|
||||
(void *)adcp);
|
||||
chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated");
|
||||
dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
|
||||
rccEnableADC1(FALSE);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* ADC setup, the calibration procedure has already been performed
|
||||
during initialization.*/
|
||||
adcp->adc->CR1 = 0;
|
||||
adcp->adc->CR2 = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deactivates the ADC peripheral.
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void adc_lld_stop(ADCDriver *adcp) {
|
||||
|
||||
/* If in ready state then disables the ADC clock.*/
|
||||
if (adcp->state == ADC_READY) {
|
||||
#if STM32_ADC_USE_ADC1
|
||||
if (&ADCD1 == adcp) {
|
||||
ADC1->CR1 = 0;
|
||||
ADC1->CR2 = 0;
|
||||
dmaStreamRelease(adcp->dmastp);
|
||||
rccDisableADC1(FALSE);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Starts an ADC conversion.
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void adc_lld_start_conversion(ADCDriver *adcp) {
|
||||
uint32_t mode, cr2;
|
||||
const ADCConversionGroup *grpp = adcp->grpp;
|
||||
|
||||
/* DMA setup.*/
|
||||
mode = adcp->dmamode;
|
||||
if (grpp->circular) {
|
||||
mode |= STM32_DMA_CR_CIRC;
|
||||
if (adcp->depth > 1) {
|
||||
/* If circular buffer depth > 1, then the half transfer interrupt
|
||||
is enabled in order to allow streaming processing.*/
|
||||
mode |= STM32_DMA_CR_HTIE;
|
||||
}
|
||||
}
|
||||
dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
|
||||
dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
|
||||
(uint32_t)adcp->depth);
|
||||
dmaStreamSetMode(adcp->dmastp, mode);
|
||||
dmaStreamEnable(adcp->dmastp);
|
||||
|
||||
/* ADC setup.*/
|
||||
adcp->adc->CR1 = grpp->cr1 | ADC_CR1_SCAN;
|
||||
cr2 = grpp->cr2 | ADC_CR2_DMA | ADC_CR2_ADON;
|
||||
if ((cr2 & (ADC_CR2_EXTTRIG | ADC_CR2_JEXTTRIG)) == 0)
|
||||
cr2 |= ADC_CR2_CONT;
|
||||
adcp->adc->CR2 = grpp->cr2 | cr2;
|
||||
adcp->adc->SMPR1 = grpp->smpr1;
|
||||
adcp->adc->SMPR2 = grpp->smpr2;
|
||||
adcp->adc->SQR1 = grpp->sqr1;
|
||||
adcp->adc->SQR2 = grpp->sqr2;
|
||||
adcp->adc->SQR3 = grpp->sqr3;
|
||||
|
||||
/* ADC start by writing ADC_CR2_ADON a second time.*/
|
||||
adcp->adc->CR2 = cr2;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stops an ongoing conversion.
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void adc_lld_stop_conversion(ADCDriver *adcp) {
|
||||
|
||||
dmaStreamDisable(adcp->dmastp);
|
||||
adcp->adc->CR2 = 0;
|
||||
}
|
||||
|
||||
#endif /* HAL_USE_ADC */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,393 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file STM32F1xx/adc_lld.h
|
||||
* @brief STM32F1xx ADC subsystem low level driver header.
|
||||
*
|
||||
* @addtogroup ADC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _ADC_LLD_H_
|
||||
#define _ADC_LLD_H_
|
||||
|
||||
#if HAL_USE_ADC || defined(__DOXYGEN__)
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Triggers selection
|
||||
* @{
|
||||
*/
|
||||
#define ADC_CR2_EXTSEL_SRC(n) ((n) << 17) /**< @brief Trigger source. */
|
||||
#define ADC_CR2_EXTSEL_SWSTART (7 << 17) /**< @brief Software trigger. */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Available analog channels
|
||||
* @{
|
||||
*/
|
||||
#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */
|
||||
#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */
|
||||
#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */
|
||||
#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */
|
||||
#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */
|
||||
#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */
|
||||
#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */
|
||||
#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */
|
||||
#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */
|
||||
#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */
|
||||
#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */
|
||||
#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */
|
||||
#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */
|
||||
#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */
|
||||
#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */
|
||||
#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */
|
||||
#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor.*/
|
||||
#define ADC_CHANNEL_VREFINT 17 /**< @brief Internal reference. */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Sampling rates
|
||||
* @{
|
||||
*/
|
||||
#define ADC_SAMPLE_1P5 0 /**< @brief 1.5 cycles sampling time. */
|
||||
#define ADC_SAMPLE_7P5 1 /**< @brief 7.5 cycles sampling time. */
|
||||
#define ADC_SAMPLE_13P5 2 /**< @brief 13.5 cycles sampling time. */
|
||||
#define ADC_SAMPLE_28P5 3 /**< @brief 28.5 cycles sampling time. */
|
||||
#define ADC_SAMPLE_41P5 4 /**< @brief 41.5 cycles sampling time. */
|
||||
#define ADC_SAMPLE_55P5 5 /**< @brief 55.5 cycles sampling time. */
|
||||
#define ADC_SAMPLE_71P5 6 /**< @brief 71.5 cycles sampling time. */
|
||||
#define ADC_SAMPLE_239P5 7 /**< @brief 239.5 cycles sampling time. */
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Configuration options
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief ADC1 driver enable switch.
|
||||
* @details If set to @p TRUE the support for ADC1 is included.
|
||||
* @note The default is @p TRUE.
|
||||
*/
|
||||
#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_USE_ADC1 FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC1 DMA priority (0..3|lowest..highest).
|
||||
*/
|
||||
#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY 2
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC1 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_ADC_ADC1_IRQ_PRIORITY 5
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
|
||||
#error "ADC1 not present in the selected device"
|
||||
#endif
|
||||
|
||||
#if !STM32_ADC_USE_ADC1
|
||||
#error "ADC driver activated but no ADC peripheral assigned"
|
||||
#endif
|
||||
|
||||
#if !defined(STM32_DMA_REQUIRED)
|
||||
#define STM32_DMA_REQUIRED
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief ADC sample data type.
|
||||
*/
|
||||
typedef uint16_t adcsample_t;
|
||||
|
||||
/**
|
||||
* @brief Channels number in a conversion group.
|
||||
*/
|
||||
typedef uint16_t adc_channels_num_t;
|
||||
|
||||
/**
|
||||
* @brief Possible ADC failure causes.
|
||||
* @note Error codes are architecture dependent and should not relied
|
||||
* upon.
|
||||
*/
|
||||
typedef enum {
|
||||
ADC_ERR_DMAFAILURE = 0 /**< DMA operations failure. */
|
||||
} adcerror_t;
|
||||
|
||||
/**
|
||||
* @brief Type of a structure representing an ADC driver.
|
||||
*/
|
||||
typedef struct ADCDriver ADCDriver;
|
||||
|
||||
/**
|
||||
* @brief ADC notification callback type.
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object triggering the
|
||||
* callback
|
||||
* @param[in] buffer pointer to the most recent samples data
|
||||
* @param[in] n number of buffer rows available starting from @p buffer
|
||||
*/
|
||||
typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
|
||||
|
||||
/**
|
||||
* @brief ADC error callback type.
|
||||
*
|
||||
* @param[in] adcp pointer to the @p ADCDriver object triggering the
|
||||
* callback
|
||||
* @param[in] err ADC error code
|
||||
*/
|
||||
typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
|
||||
|
||||
/**
|
||||
* @brief Conversion group configuration structure.
|
||||
* @details This implementation-dependent structure describes a conversion
|
||||
* operation.
|
||||
* @note The use of this configuration structure requires knowledge of
|
||||
* STM32 ADC cell registers interface, please refer to the STM32
|
||||
* reference manual for details.
|
||||
*/
|
||||
typedef struct {
|
||||
/**
|
||||
* @brief Enables the circular buffer mode for the group.
|
||||
*/
|
||||
bool_t circular;
|
||||
/**
|
||||
* @brief Number of the analog channels belonging to the conversion group.
|
||||
*/
|
||||
adc_channels_num_t num_channels;
|
||||
/**
|
||||
* @brief Callback function associated to the group or @p NULL.
|
||||
*/
|
||||
adccallback_t end_cb;
|
||||
/**
|
||||
* @brief Error callback or @p NULL.
|
||||
*/
|
||||
adcerrorcallback_t error_cb;
|
||||
/* End of the mandatory fields.*/
|
||||
/**
|
||||
* @brief ADC CR1 register initialization data.
|
||||
* @note All the required bits must be defined into this field except
|
||||
* @p ADC_CR1_SCAN that is enforced inside the driver.
|
||||
*/
|
||||
uint32_t cr1;
|
||||
/**
|
||||
* @brief ADC CR2 register initialization data.
|
||||
* @note All the required bits must be defined into this field except
|
||||
* @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are
|
||||
* enforced inside the driver.
|
||||
*/
|
||||
uint32_t cr2;
|
||||
/**
|
||||
* @brief ADC SMPR1 register initialization data.
|
||||
* @details In this field must be specified the sample times for channels
|
||||
* 10...17.
|
||||
*/
|
||||
uint32_t smpr1;
|
||||
/**
|
||||
* @brief ADC SMPR2 register initialization data.
|
||||
* @details In this field must be specified the sample times for channels
|
||||
* 0...9.
|
||||
*/
|
||||
uint32_t smpr2;
|
||||
/**
|
||||
* @brief ADC SQR1 register initialization data.
|
||||
* @details Conversion group sequence 13...16 + sequence length.
|
||||
*/
|
||||
uint32_t sqr1;
|
||||
/**
|
||||
* @brief ADC SQR2 register initialization data.
|
||||
* @details Conversion group sequence 7...12.
|
||||
*/
|
||||
uint32_t sqr2;
|
||||
/**
|
||||
* @brief ADC SQR3 register initialization data.
|
||||
* @details Conversion group sequence 1...6.
|
||||
*/
|
||||
uint32_t sqr3;
|
||||
} ADCConversionGroup;
|
||||
|
||||
/**
|
||||
* @brief Driver configuration structure.
|
||||
* @note It could be empty on some architectures.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t dummy;
|
||||
} ADCConfig;
|
||||
|
||||
/**
|
||||
* @brief Structure representing an ADC driver.
|
||||
*/
|
||||
struct ADCDriver {
|
||||
/**
|
||||
* @brief Driver state.
|
||||
*/
|
||||
adcstate_t state;
|
||||
/**
|
||||
* @brief Current configuration data.
|
||||
*/
|
||||
const ADCConfig *config;
|
||||
/**
|
||||
* @brief Current samples buffer pointer or @p NULL.
|
||||
*/
|
||||
adcsample_t *samples;
|
||||
/**
|
||||
* @brief Current samples buffer depth or @p 0.
|
||||
*/
|
||||
size_t depth;
|
||||
/**
|
||||
* @brief Current conversion group pointer or @p NULL.
|
||||
*/
|
||||
const ADCConversionGroup *grpp;
|
||||
#if ADC_USE_WAIT || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief Waiting thread.
|
||||
*/
|
||||
Thread *thread;
|
||||
#endif
|
||||
#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
|
||||
#if CH_USE_MUTEXES || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief Mutex protecting the peripheral.
|
||||
*/
|
||||
Mutex mutex;
|
||||
#elif CH_USE_SEMAPHORES
|
||||
Semaphore semaphore;
|
||||
#endif
|
||||
#endif /* ADC_USE_MUTUAL_EXCLUSION */
|
||||
#if defined(ADC_DRIVER_EXT_FIELDS)
|
||||
ADC_DRIVER_EXT_FIELDS
|
||||
#endif
|
||||
/* End of the mandatory fields.*/
|
||||
/**
|
||||
* @brief Pointer to the ADCx registers block.
|
||||
*/
|
||||
ADC_TypeDef *adc;
|
||||
/**
|
||||
* @brief Pointer to associated DMA channel.
|
||||
*/
|
||||
const stm32_dma_stream_t *dmastp;
|
||||
/**
|
||||
* @brief DMA mode bit mask.
|
||||
*/
|
||||
uint32_t dmamode;
|
||||
};
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Sequences building helper macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Number of channels in a conversion sequence.
|
||||
*/
|
||||
#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20)
|
||||
|
||||
#define ADC_SQR3_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */
|
||||
#define ADC_SQR3_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */
|
||||
#define ADC_SQR3_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */
|
||||
#define ADC_SQR3_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */
|
||||
#define ADC_SQR3_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */
|
||||
#define ADC_SQR3_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */
|
||||
|
||||
#define ADC_SQR2_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */
|
||||
#define ADC_SQR2_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */
|
||||
#define ADC_SQR2_SQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */
|
||||
#define ADC_SQR2_SQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/
|
||||
#define ADC_SQR2_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/
|
||||
#define ADC_SQR2_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/
|
||||
|
||||
#define ADC_SQR1_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/
|
||||
#define ADC_SQR1_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/
|
||||
#define ADC_SQR1_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/
|
||||
#define ADC_SQR1_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Sampling rate settings helper macros
|
||||
* @{
|
||||
*/
|
||||
#define ADC_SMPR2_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */
|
||||
#define ADC_SMPR2_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */
|
||||
#define ADC_SMPR2_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */
|
||||
#define ADC_SMPR2_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */
|
||||
#define ADC_SMPR2_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */
|
||||
#define ADC_SMPR2_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */
|
||||
#define ADC_SMPR2_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */
|
||||
#define ADC_SMPR2_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */
|
||||
#define ADC_SMPR2_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */
|
||||
#define ADC_SMPR2_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */
|
||||
|
||||
#define ADC_SMPR1_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */
|
||||
#define ADC_SMPR1_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */
|
||||
#define ADC_SMPR1_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */
|
||||
#define ADC_SMPR1_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */
|
||||
#define ADC_SMPR1_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */
|
||||
#define ADC_SMPR1_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */
|
||||
#define ADC_SMPR1_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor
|
||||
sampling time. */
|
||||
#define ADC_SMPR1_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference
|
||||
sampling time. */
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__)
|
||||
extern ADCDriver ADCD1;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void adc_lld_init(void);
|
||||
void adc_lld_start(ADCDriver *adcp);
|
||||
void adc_lld_stop(ADCDriver *adcp);
|
||||
void adc_lld_start_conversion(ADCDriver *adcp);
|
||||
void adc_lld_stop_conversion(ADCDriver *adcp);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* HAL_USE_ADC */
|
||||
|
||||
#endif /* _ADC_LLD_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,338 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file STM32F1xx/ext_lld_isr.c
|
||||
* @brief STM32F1xx EXT subsystem low level driver ISR code.
|
||||
*
|
||||
* @addtogroup EXT
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "ch.h"
|
||||
#include "hal.h"
|
||||
|
||||
#if HAL_USE_EXT || defined(__DOXYGEN__)
|
||||
|
||||
#include "ext_lld_isr.h"
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local definitions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported variables. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local variables. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver interrupt handlers. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief EXTI[0] interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(EXTI0_IRQHandler) {
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
EXTI->PR = (1 << 0);
|
||||
EXTD1.config->channels[0].cb(&EXTD1, 0);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EXTI[1] interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(EXTI1_IRQHandler) {
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
EXTI->PR = (1 << 1);
|
||||
EXTD1.config->channels[1].cb(&EXTD1, 1);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EXTI[2] interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(EXTI2_IRQHandler) {
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
EXTI->PR = (1 << 2);
|
||||
EXTD1.config->channels[2].cb(&EXTD1, 2);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EXTI[3] interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(EXTI3_IRQHandler) {
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
EXTI->PR = (1 << 3);
|
||||
EXTD1.config->channels[3].cb(&EXTD1, 3);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EXTI[4] interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(EXTI4_IRQHandler) {
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
EXTI->PR = (1 << 4);
|
||||
EXTD1.config->channels[4].cb(&EXTD1, 4);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EXTI[5]...EXTI[9] interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(EXTI9_5_IRQHandler) {
|
||||
uint32_t pr;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
pr = EXTI->PR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9));
|
||||
EXTI->PR = pr;
|
||||
if (pr & (1 << 5))
|
||||
EXTD1.config->channels[5].cb(&EXTD1, 5);
|
||||
if (pr & (1 << 6))
|
||||
EXTD1.config->channels[6].cb(&EXTD1, 6);
|
||||
if (pr & (1 << 7))
|
||||
EXTD1.config->channels[7].cb(&EXTD1, 7);
|
||||
if (pr & (1 << 8))
|
||||
EXTD1.config->channels[8].cb(&EXTD1, 8);
|
||||
if (pr & (1 << 9))
|
||||
EXTD1.config->channels[9].cb(&EXTD1, 9);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EXTI[10]...EXTI[15] interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(EXTI15_10_IRQHandler) {
|
||||
uint32_t pr;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
pr = EXTI->PR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) |
|
||||
(1 << 15));
|
||||
EXTI->PR = pr;
|
||||
if (pr & (1 << 10))
|
||||
EXTD1.config->channels[10].cb(&EXTD1, 10);
|
||||
if (pr & (1 << 11))
|
||||
EXTD1.config->channels[11].cb(&EXTD1, 11);
|
||||
if (pr & (1 << 12))
|
||||
EXTD1.config->channels[12].cb(&EXTD1, 12);
|
||||
if (pr & (1 << 13))
|
||||
EXTD1.config->channels[13].cb(&EXTD1, 13);
|
||||
if (pr & (1 << 14))
|
||||
EXTD1.config->channels[14].cb(&EXTD1, 14);
|
||||
if (pr & (1 << 15))
|
||||
EXTD1.config->channels[15].cb(&EXTD1, 15);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EXTI[16] interrupt handler (PVD).
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(PVD_IRQHandler) {
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
EXTI->PR = (1 << 16);
|
||||
EXTD1.config->channels[16].cb(&EXTD1, 16);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EXTI[17] interrupt handler (RTC).
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(RTC_Alarm_IRQHandler) {
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
EXTI->PR = (1 << 17);
|
||||
EXTD1.config->channels[17].cb(&EXTD1, 17);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
#if defined(STM32F10X_CL)
|
||||
/**
|
||||
* @brief EXTI[18] interrupt handler (OTG_FS_WKUP).
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(OTG_FS_WKUP_IRQHandler) {
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
EXTI->PR = (1 << 18);
|
||||
EXTD1.config->channels[18].cb(&EXTD1, 18);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EXTI[19] interrupt handler (ETH_WKUP).
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(ETH_WKUP_IRQHandler) {
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
EXTI->PR = (1 << 19);
|
||||
EXTD1.config->channels[19].cb(&EXTD1, 19);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \
|
||||
defined(STM32F10X_HD_VL)
|
||||
|
||||
#else /* Other STM32F1xx devices.*/
|
||||
/**
|
||||
* @brief EXTI[18] interrupt handler (USB_FS_WKUP).
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(USB_FS_WKUP_IRQHandler) {
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
EXTI->PR = (1 << 18);
|
||||
EXTD1.config->channels[18].cb(&EXTD1, 18);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Enables EXTI IRQ sources.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void ext_lld_exti_irq_enable(void) {
|
||||
|
||||
nvicEnableVector(EXTI0_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_IRQ_PRIORITY));
|
||||
nvicEnableVector(EXTI1_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI1_IRQ_PRIORITY));
|
||||
nvicEnableVector(EXTI2_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_IRQ_PRIORITY));
|
||||
nvicEnableVector(EXTI3_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI3_IRQ_PRIORITY));
|
||||
nvicEnableVector(EXTI4_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_IRQ_PRIORITY));
|
||||
nvicEnableVector(EXTI9_5_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI5_9_IRQ_PRIORITY));
|
||||
nvicEnableVector(EXTI15_10_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI10_15_IRQ_PRIORITY));
|
||||
nvicEnableVector(PVD_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY));
|
||||
nvicEnableVector(RTC_Alarm_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY));
|
||||
#if defined(STM32F10X_CL)
|
||||
/* EXTI vectors specific to STM32F1xx Connectivity Line.*/
|
||||
nvicEnableVector(OTG_FS_WKUP_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY));
|
||||
nvicEnableVector(ETH_WKUP_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY));
|
||||
#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \
|
||||
defined(STM32F10X_HD_VL)
|
||||
/* EXTI vectors specific to STM32F1xx Value Line.*/
|
||||
#else
|
||||
/* EXTI vectors specific to STM32F1xx except Connectivity Line.*/
|
||||
nvicEnableVector(USB_FS_WKUP_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY));
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables EXTI IRQ sources.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void ext_lld_exti_irq_disable(void) {
|
||||
|
||||
nvicDisableVector(EXTI0_IRQn);
|
||||
nvicDisableVector(EXTI1_IRQn);
|
||||
nvicDisableVector(EXTI2_IRQn);
|
||||
nvicDisableVector(EXTI3_IRQn);
|
||||
nvicDisableVector(EXTI4_IRQn);
|
||||
nvicDisableVector(EXTI9_5_IRQn);
|
||||
nvicDisableVector(EXTI15_10_IRQn);
|
||||
nvicDisableVector(PVD_IRQn);
|
||||
nvicDisableVector(RTC_Alarm_IRQn);
|
||||
#if defined(STM32F10X_CL)
|
||||
/* EXTI vectors specific to STM32F1xx Connectivity Line.*/
|
||||
nvicDisableVector(OTG_FS_WKUP_IRQn);
|
||||
nvicDisableVector(ETH_WKUP_IRQn);
|
||||
#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \
|
||||
defined(STM32F10X_HD_VL)
|
||||
/* EXTI vectors specific to STM32F1xx Value Line.*/
|
||||
#else
|
||||
/* EXTI vectors specific to STM32F1xx except Connectivity Line.*/
|
||||
nvicDisableVector(USB_FS_WKUP_IRQn);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* HAL_USE_EXT */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,149 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file STM32F1xx/ext_lld_isr.h
|
||||
* @brief STM32F1xx EXT subsystem low level driver ISR header.
|
||||
*
|
||||
* @addtogroup EXT
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _EXT_LLD_ISR_H_
|
||||
#define _EXT_LLD_ISR_H_
|
||||
|
||||
#if HAL_USE_EXT || defined(__DOXYGEN__)
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Configuration options
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief EXTI0 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI1 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI2 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI3 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI4 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI9..5 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI15..10 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI16 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI17 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI17_IRQ_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI18 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI19 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void ext_lld_exti_irq_enable(void);
|
||||
void ext_lld_exti_irq_disable(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* HAL_USE_EXT */
|
||||
|
||||
#endif /* _EXT_LLD_ISR_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,302 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file STM32F1xx/hal_lld.c
|
||||
* @brief STM32F1xx HAL subsystem low level driver source.
|
||||
*
|
||||
* @addtogroup HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "ch.h"
|
||||
#include "hal.h"
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local definitions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported variables. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local variables and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the backup domain.
|
||||
* @note WARNING! Changing clock source impossible without resetting
|
||||
* of the whole BKP domain.
|
||||
*/
|
||||
static void hal_lld_backup_domain_init(void) {
|
||||
|
||||
/* Backup domain access enabled and left open.*/
|
||||
PWR->CR |= PWR_CR_DBP;
|
||||
|
||||
#if HAL_USE_RTC
|
||||
/* Reset BKP domain if different clock source selected.*/
|
||||
if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){
|
||||
/* Backup domain reset.*/
|
||||
RCC->BDCR = RCC_BDCR_BDRST;
|
||||
RCC->BDCR = 0;
|
||||
}
|
||||
|
||||
/* If enabled then the LSE is started.*/
|
||||
#if STM32_LSE_ENABLED
|
||||
RCC->BDCR |= RCC_BDCR_LSEON;
|
||||
while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
|
||||
; /* Waits until LSE is stable. */
|
||||
#endif /* STM32_LSE_ENABLED */
|
||||
|
||||
#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
|
||||
/* If the backup domain hasn't been initialized yet then proceed with
|
||||
initialization.*/
|
||||
if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
|
||||
/* Selects clock source.*/
|
||||
RCC->BDCR |= STM32_RTCSEL;
|
||||
|
||||
/* Prescaler value loaded in registers.*/
|
||||
rtc_lld_set_prescaler();
|
||||
|
||||
/* RTC clock enabled.*/
|
||||
RCC->BDCR |= RCC_BDCR_RTCEN;
|
||||
}
|
||||
#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
|
||||
#endif /* HAL_USE_RTC */
|
||||
}
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver interrupt handlers. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Low level HAL driver initialization.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
void hal_lld_init(void) {
|
||||
|
||||
/* Reset of all peripherals.*/
|
||||
rccResetAPB1(0xFFFFFFFF);
|
||||
rccResetAPB2(0xFFFFFFFF);
|
||||
|
||||
/* SysTick initialization using the system clock.*/
|
||||
SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;
|
||||
SysTick->VAL = 0;
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk;
|
||||
|
||||
/* DWT cycle counter enable.*/
|
||||
SCS_DEMCR |= SCS_DEMCR_TRCENA;
|
||||
DWT_CTRL |= DWT_CTRL_CYCCNTENA;
|
||||
|
||||
/* PWR and BD clocks enabled.*/
|
||||
rccEnablePWRInterface(FALSE);
|
||||
rccEnableBKPInterface(FALSE);
|
||||
|
||||
/* Initializes the backup domain.*/
|
||||
hal_lld_backup_domain_init();
|
||||
|
||||
#if defined(STM32_DMA_REQUIRED)
|
||||
dmaInit();
|
||||
#endif
|
||||
|
||||
/* Programmable voltage detector enable.*/
|
||||
#if STM32_PVD_ENABLE
|
||||
PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
|
||||
#endif /* STM32_PVD_ENABLE */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief STM32 clocks and PLL initialization.
|
||||
* @note All the involved constants come from the file @p board.h.
|
||||
* @note This function should be invoked just after the system reset.
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
#if defined(STM32F10X_LD) || defined(STM32F10X_LD_VL) || \
|
||||
defined(STM32F10X_MD) || defined(STM32F10X_MD_VL) || \
|
||||
defined(STM32F10X_HD) || defined(STM32F10X_XL) || \
|
||||
defined(__DOXYGEN__)
|
||||
/*
|
||||
* Clocks initialization for all sub-families except CL.
|
||||
*/
|
||||
void stm32_clock_init(void) {
|
||||
|
||||
#if !STM32_NO_INIT
|
||||
/* HSI setup, it enforces the reset situation in order to handle possible
|
||||
problems with JTAG probes and re-initializations.*/
|
||||
RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */
|
||||
while (!(RCC->CR & RCC_CR_HSIRDY))
|
||||
; /* Wait until HSI is stable. */
|
||||
RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */
|
||||
RCC->CFGR = 0; /* CFGR reset value. */
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
|
||||
; /* Waits until HSI is selected. */
|
||||
|
||||
#if STM32_HSE_ENABLED
|
||||
#if defined(STM32_HSE_BYPASS)
|
||||
/* HSE Bypass.*/
|
||||
RCC->CR |= RCC_CR_HSEBYP;
|
||||
#endif
|
||||
/* HSE activation.*/
|
||||
RCC->CR |= RCC_CR_HSEON;
|
||||
while (!(RCC->CR & RCC_CR_HSERDY))
|
||||
; /* Waits until HSE is stable. */
|
||||
#endif
|
||||
|
||||
#if STM32_LSI_ENABLED
|
||||
/* LSI activation.*/
|
||||
RCC->CSR |= RCC_CSR_LSION;
|
||||
while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
|
||||
; /* Waits until LSI is stable. */
|
||||
#endif
|
||||
|
||||
#if STM32_ACTIVATE_PLL
|
||||
/* PLL activation.*/
|
||||
RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC;
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
while (!(RCC->CR & RCC_CR_PLLRDY))
|
||||
; /* Waits until PLL is stable. */
|
||||
#endif
|
||||
|
||||
/* Clock settings.*/
|
||||
#if STM32_HAS_USB
|
||||
RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE |
|
||||
STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 |
|
||||
STM32_HPRE;
|
||||
#else
|
||||
RCC->CFGR = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLXTPRE |
|
||||
STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 |
|
||||
STM32_HPRE;
|
||||
#endif
|
||||
|
||||
/* Flash setup and final clock selection. */
|
||||
FLASH->ACR = STM32_FLASHBITS;
|
||||
|
||||
/* Switching to the configured clock source if it is different from HSI.*/
|
||||
#if (STM32_SW != STM32_SW_HSI)
|
||||
/* Switches clock source.*/
|
||||
RCC->CFGR |= STM32_SW;
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
|
||||
; /* Waits selection complete. */
|
||||
#endif
|
||||
|
||||
#if !STM32_HSI_ENABLED
|
||||
RCC->CR &= ~RCC_CR_HSION;
|
||||
#endif
|
||||
#endif /* !STM32_NO_INIT */
|
||||
}
|
||||
|
||||
#elif defined(STM32F10X_CL)
|
||||
/*
|
||||
* Clocks initialization for the CL sub-family.
|
||||
*/
|
||||
void stm32_clock_init(void) {
|
||||
|
||||
#if !STM32_NO_INIT
|
||||
/* HSI setup.*/
|
||||
RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */
|
||||
while (!(RCC->CR & RCC_CR_HSIRDY))
|
||||
; /* Wait until HSI is stable. */
|
||||
RCC->CFGR = 0;
|
||||
RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
|
||||
; /* Wait until HSI is the source.*/
|
||||
|
||||
#if STM32_HSE_ENABLED
|
||||
#if defined(STM32_HSE_BYPASS)
|
||||
/* HSE Bypass.*/
|
||||
RCC->CR |= RCC_CR_HSEBYP;
|
||||
#endif
|
||||
/* HSE activation.*/
|
||||
RCC->CR |= RCC_CR_HSEON;
|
||||
while (!(RCC->CR & RCC_CR_HSERDY))
|
||||
; /* Waits until HSE is stable. */
|
||||
#endif
|
||||
|
||||
#if STM32_LSI_ENABLED
|
||||
/* LSI activation.*/
|
||||
RCC->CSR |= RCC_CSR_LSION;
|
||||
while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
|
||||
; /* Waits until LSI is stable. */
|
||||
#endif
|
||||
|
||||
/* Settings of various dividers and multipliers in CFGR2.*/
|
||||
RCC->CFGR2 = STM32_PLL3MUL | STM32_PLL2MUL | STM32_PREDIV2 |
|
||||
STM32_PREDIV1 | STM32_PREDIV1SRC;
|
||||
|
||||
/* PLL2 setup, if activated.*/
|
||||
#if STM32_ACTIVATE_PLL2
|
||||
RCC->CR |= RCC_CR_PLL2ON;
|
||||
while (!(RCC->CR & RCC_CR_PLL2RDY))
|
||||
; /* Waits until PLL2 is stable. */
|
||||
#endif
|
||||
|
||||
/* PLL3 setup, if activated.*/
|
||||
#if STM32_ACTIVATE_PLL3
|
||||
RCC->CR |= RCC_CR_PLL3ON;
|
||||
while (!(RCC->CR & RCC_CR_PLL3RDY))
|
||||
; /* Waits until PLL3 is stable. */
|
||||
#endif
|
||||
|
||||
/* PLL1 setup, if activated.*/
|
||||
#if STM32_ACTIVATE_PLL1
|
||||
RCC->CFGR |= STM32_PLLMUL | STM32_PLLSRC;
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
while (!(RCC->CR & RCC_CR_PLLRDY))
|
||||
; /* Waits until PLL1 is stable. */
|
||||
#endif
|
||||
|
||||
/* Clock settings.*/
|
||||
#if STM32_HAS_OTG1
|
||||
RCC->CFGR = STM32_MCOSEL | STM32_OTGFSPRE | STM32_PLLMUL | STM32_PLLSRC |
|
||||
STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
|
||||
#else
|
||||
RCC->CFGR = STM32_MCO | STM32_PLLMUL | STM32_PLLSRC |
|
||||
STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
|
||||
#endif
|
||||
|
||||
/* Flash setup and final clock selection. */
|
||||
FLASH->ACR = STM32_FLASHBITS; /* Flash wait states depending on clock. */
|
||||
|
||||
/* Switching to the configured clock source if it is different from HSI.*/
|
||||
#if (STM32_SW != STM32_SW_HSI)
|
||||
RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
|
||||
;
|
||||
#endif
|
||||
|
||||
#if !STM32_HSI_ENABLED
|
||||
RCC->CR &= ~RCC_CR_HSION;
|
||||
#endif
|
||||
#endif /* !STM32_NO_INIT */
|
||||
}
|
||||
#else
|
||||
void stm32_clock_init(void) {}
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,255 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file STM32F1xx/hal_lld.h
|
||||
* @brief STM32F1xx HAL subsystem low level driver header.
|
||||
* @pre This module requires the following macros to be defined in the
|
||||
* @p board.h file:
|
||||
* - STM32_LSECLK.
|
||||
* - STM32_HSECLK.
|
||||
* - STM32_HSE_BYPASS (optionally).
|
||||
* .
|
||||
* One of the following macros must also be defined:
|
||||
* - STM32F10X_LD_VL for Value Line Low Density devices.
|
||||
* - STM32F10X_MD_VL for Value Line Medium Density devices.
|
||||
* - STM32F10X_LD for Performance Low Density devices.
|
||||
* - STM32F10X_MD for Performance Medium Density devices.
|
||||
* - STM32F10X_HD for Performance High Density devices.
|
||||
* - STM32F10X_XL for Performance eXtra Density devices.
|
||||
* - STM32F10X_CL for Connectivity Line devices.
|
||||
* .
|
||||
*
|
||||
* @addtogroup HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _HAL_LLD_H_
|
||||
#define _HAL_LLD_H_
|
||||
|
||||
#include "stm32.h"
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Defines the support for realtime counters in the HAL.
|
||||
*/
|
||||
#define HAL_IMPLEMENTS_COUNTERS TRUE
|
||||
|
||||
/**
|
||||
* @name Internal clock sources
|
||||
* @{
|
||||
*/
|
||||
#define STM32_HSICLK 8000000 /**< High speed internal clock. */
|
||||
#define STM32_LSICLK 40000 /**< Low speed internal clock. */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name PWR_CR register bits definitions
|
||||
* @{
|
||||
*/
|
||||
#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */
|
||||
#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
|
||||
#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */
|
||||
#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 2. */
|
||||
#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 3. */
|
||||
#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 4. */
|
||||
#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 5. */
|
||||
#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 6. */
|
||||
#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 7. */
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Platform capabilities. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name STM32F1xx capabilities
|
||||
* @{
|
||||
*/
|
||||
/* RTC attributes.*/
|
||||
#define STM32_HAS_RTC TRUE
|
||||
#define STM32_RTC_HAS_SUBSECONDS TRUE
|
||||
#define STM32_RTC_IS_CALENDAR FALSE
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Configuration options
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Disables the PWR/RCC initialization in the HAL.
|
||||
*/
|
||||
#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
|
||||
#define STM32_NO_INIT FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the programmable voltage detector.
|
||||
*/
|
||||
#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
|
||||
#define STM32_PVD_ENABLE FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Sets voltage level for programmable voltage detector.
|
||||
*/
|
||||
#if !defined(STM32_PLS) || defined(__DOXYGEN__)
|
||||
#define STM32_PLS STM32_PLS_LEV0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the HSI clock source.
|
||||
*/
|
||||
#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
|
||||
#define STM32_HSI_ENABLED TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the LSI clock source.
|
||||
*/
|
||||
#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
|
||||
#define STM32_LSI_ENABLED FALSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the HSE clock source.
|
||||
*/
|
||||
#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
|
||||
#define STM32_HSE_ENABLED TRUE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the LSE clock source.
|
||||
*/
|
||||
#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
|
||||
#define STM32_LSE_ENABLED FALSE
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if defined(__DOXYGEN__)
|
||||
/**
|
||||
* @name Platform identification
|
||||
* @{
|
||||
*/
|
||||
#define PLATFORM_NAME "STM32"
|
||||
/** @} */
|
||||
|
||||
#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \
|
||||
defined(STM32F10X_HD_VL) || defined(__DOXYGEN__)
|
||||
#include "hal_lld_f100.h"
|
||||
|
||||
#elif defined(STM32F10X_LD) || defined(STM32F10X_MD) || \
|
||||
defined(STM32F10X_HD) || defined(STM32F10X_XL) || \
|
||||
defined(__DOXYGEN__)
|
||||
#include "hal_lld_f103.h"
|
||||
|
||||
#elif defined(STM32F10X_CL) || defined(__DOXYGEN__)
|
||||
#include "hal_lld_f105_f107.h"
|
||||
|
||||
#else
|
||||
#error "unspecified, unsupported or invalid STM32 platform"
|
||||
#endif
|
||||
|
||||
/* There are differences in vector names in the various sub-families,
|
||||
normalizing.*/
|
||||
#if defined(STM32F10X_XL)
|
||||
#define TIM1_BRK_IRQn TIM1_BRK_TIM9_IRQn
|
||||
#define TIM1_UP_IRQn TIM1_UP_TIM10_IRQn
|
||||
#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM11_IRQn
|
||||
#define TIM8_BRK_IRQn TIM8_BRK_TIM12_IRQn
|
||||
#define TIM8_UP_IRQn TIM8_UP_TIM13_IRQn
|
||||
#define TIM8_TRG_COM_IRQn TIM8_TRG_COM_TIM14_IRQn
|
||||
|
||||
#elif defined(STM32F10X_LD_VL)|| defined(STM32F10X_MD_VL) || \
|
||||
defined(STM32F10X_HD_VL)
|
||||
#define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn
|
||||
#define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn
|
||||
#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Type representing a system clock frequency.
|
||||
*/
|
||||
typedef uint32_t halclock_t;
|
||||
|
||||
/**
|
||||
* @brief Type of the realtime free counter value.
|
||||
*/
|
||||
typedef uint32_t halrtcnt_t;
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Returns the current value of the system free running counter.
|
||||
* @note This service is implemented by returning the content of the
|
||||
* DWT_CYCCNT register.
|
||||
*
|
||||
* @return The value of the system free running counter of
|
||||
* type halrtcnt_t.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define hal_lld_get_counter_value() DWT_CYCCNT
|
||||
|
||||
/**
|
||||
* @brief Realtime counter frequency.
|
||||
* @note The DWT_CYCCNT register is incremented directly by the system
|
||||
* clock so this function returns STM32_HCLK.
|
||||
*
|
||||
* @return The realtime counter frequency of type halclock_t.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#define hal_lld_get_counter_frequency() STM32_HCLK
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/* STM32 ISR, DMA and RCC helpers.*/
|
||||
#include "stm32_isr.h"
|
||||
#include "stm32_dma.h"
|
||||
#include "stm32_rcc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void hal_lld_init(void);
|
||||
void stm32_clock_init(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _HAL_LLD_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,950 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STM32F100_HAL STM32F100 HAL Support
|
||||
* @details HAL support for STM32 Value Line LD, MD and HD sub-families.
|
||||
*
|
||||
* @ingroup HAL
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file STM32F1xx/hal_lld_f100.h
|
||||
* @brief STM32F100 Value Line HAL subsystem low level driver header.
|
||||
*
|
||||
* @addtogroup STM32F100_HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _HAL_LLD_F100_H_
|
||||
#define _HAL_LLD_F100_H_
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Platform identification
|
||||
* @{
|
||||
*/
|
||||
#if defined(__DOXYGEN__)
|
||||
#define PLATFORM_NAME "STM32F100 Value Line"
|
||||
|
||||
#elif defined(STM32F10X_LD_VL)
|
||||
#define PLATFORM_NAME "STM32F100 Value Line Low Density"
|
||||
|
||||
#elif defined(STM32F10X_MD_VL)
|
||||
#define PLATFORM_NAME "STM32F100 Value Line Medium Density"
|
||||
#else
|
||||
#error "unsupported STM32 Value Line member"
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Absolute Maximum Ratings
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Maximum system clock frequency.
|
||||
*/
|
||||
#define STM32_SYSCLK_MAX 24000000
|
||||
|
||||
/**
|
||||
* @brief Maximum HSE clock frequency.
|
||||
*/
|
||||
#define STM32_HSECLK_MAX 24000000
|
||||
|
||||
/**
|
||||
* @brief Minimum HSE clock frequency.
|
||||
*/
|
||||
#define STM32_HSECLK_MIN 1000000
|
||||
|
||||
/**
|
||||
* @brief Maximum LSE clock frequency.
|
||||
*/
|
||||
#define STM32_LSECLK_MAX 1000000
|
||||
|
||||
/**
|
||||
* @brief Minimum LSE clock frequency.
|
||||
*/
|
||||
#define STM32_LSECLK_MIN 32768
|
||||
|
||||
/**
|
||||
* @brief Maximum PLLs input clock frequency.
|
||||
*/
|
||||
#define STM32_PLLIN_MAX 24000000
|
||||
|
||||
/**
|
||||
* @brief Maximum PLLs input clock frequency.
|
||||
*/
|
||||
#define STM32_PLLIN_MIN 1000000
|
||||
|
||||
/**
|
||||
* @brief Maximum PLL output clock frequency.
|
||||
*/
|
||||
#define STM32_PLLOUT_MAX 24000000
|
||||
|
||||
/**
|
||||
* @brief Maximum PLL output clock frequency.
|
||||
*/
|
||||
#define STM32_PLLOUT_MIN 16000000
|
||||
|
||||
/**
|
||||
* @brief Maximum APB1 clock frequency.
|
||||
*/
|
||||
#define STM32_PCLK1_MAX 24000000
|
||||
|
||||
/**
|
||||
* @brief Maximum APB2 clock frequency.
|
||||
*/
|
||||
#define STM32_PCLK2_MAX 24000000
|
||||
|
||||
/**
|
||||
* @brief Maximum ADC clock frequency.
|
||||
*/
|
||||
#define STM32_ADCCLK_MAX 12000000
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name RCC_CFGR register bits definitions
|
||||
* @{
|
||||
*/
|
||||
#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */
|
||||
#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */
|
||||
#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */
|
||||
|
||||
#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
|
||||
#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
|
||||
#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
|
||||
#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
|
||||
#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
|
||||
#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
|
||||
#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
|
||||
#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
|
||||
#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
|
||||
|
||||
#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */
|
||||
#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */
|
||||
#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */
|
||||
#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */
|
||||
#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */
|
||||
|
||||
#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */
|
||||
#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */
|
||||
#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */
|
||||
#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */
|
||||
#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */
|
||||
|
||||
#define STM32_ADCPRE_DIV2 (0 << 14) /**< PPRE2 divided by 2. */
|
||||
#define STM32_ADCPRE_DIV4 (1 << 14) /**< PPRE2 divided by 4. */
|
||||
#define STM32_ADCPRE_DIV6 (2 << 14) /**< PPRE2 divided by 6. */
|
||||
#define STM32_ADCPRE_DIV8 (3 << 14) /**< PPRE2 divided by 8. */
|
||||
|
||||
#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */
|
||||
#define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */
|
||||
|
||||
#define STM32_PLLXTPRE_DIV1 (0 << 17) /**< HSE divided by 1. */
|
||||
#define STM32_PLLXTPRE_DIV2 (1 << 17) /**< HSE divided by 2. */
|
||||
|
||||
#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
|
||||
#define STM32_MCOSEL_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */
|
||||
#define STM32_MCOSEL_HSI (5 << 24) /**< HSI clock on MCO pin. */
|
||||
#define STM32_MCOSEL_HSE (6 << 24) /**< HSE clock on MCO pin. */
|
||||
#define STM32_MCOSEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name RCC_BDCR register bits definitions
|
||||
* @{
|
||||
*/
|
||||
#define STM32_RTCSEL_MASK (3 << 8) /**< RTC clock source mask. */
|
||||
#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */
|
||||
#define STM32_RTCSEL_LSE (1 << 8) /**< LSE used as RTC clock. */
|
||||
#define STM32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */
|
||||
#define STM32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 128 used as
|
||||
RTC clock. */
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Platform capabilities. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if defined(STM32F10X_LD_VL) || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @name STM32F100 LD capabilities
|
||||
* @{
|
||||
*/
|
||||
/* ADC attributes.*/
|
||||
#define STM32_HAS_ADC1 TRUE
|
||||
#define STM32_HAS_ADC2 FALSE
|
||||
#define STM32_HAS_ADC3 FALSE
|
||||
|
||||
/* CAN attributes.*/
|
||||
#define STM32_HAS_CAN1 FALSE
|
||||
#define STM32_HAS_CAN2 FALSE
|
||||
#define STM32_CAN_MAX_FILTERS 0
|
||||
|
||||
/* DAC attributes.*/
|
||||
#define STM32_HAS_DAC TRUE
|
||||
|
||||
/* DMA attributes.*/
|
||||
#define STM32_ADVANCED_DMA FALSE
|
||||
#define STM32_HAS_DMA1 TRUE
|
||||
#define STM32_HAS_DMA2 FALSE
|
||||
|
||||
/* ETH attributes.*/
|
||||
#define STM32_HAS_ETH FALSE
|
||||
|
||||
/* EXTI attributes.*/
|
||||
#define STM32_EXTI_NUM_CHANNELS 18
|
||||
|
||||
/* GPIO attributes.*/
|
||||
#define STM32_HAS_GPIOA TRUE
|
||||
#define STM32_HAS_GPIOB TRUE
|
||||
#define STM32_HAS_GPIOC TRUE
|
||||
#define STM32_HAS_GPIOD TRUE
|
||||
#define STM32_HAS_GPIOE FALSE
|
||||
#define STM32_HAS_GPIOF FALSE
|
||||
#define STM32_HAS_GPIOG FALSE
|
||||
#define STM32_HAS_GPIOH FALSE
|
||||
#define STM32_HAS_GPIOI FALSE
|
||||
|
||||
/* I2C attributes.*/
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
|
||||
#define STM32_I2C1_RX_DMA_CHN 0x00000000
|
||||
#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
|
||||
#define STM32_I2C1_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_I2C2 FALSE
|
||||
#define STM32_I2C2_RX_DMA_MSK 0
|
||||
#define STM32_I2C2_RX_DMA_CHN 0x00000000
|
||||
#define STM32_I2C2_TX_DMA_MSK 0
|
||||
#define STM32_I2C2_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_I2C3 FALSE
|
||||
#define STM32_SPI3_RX_DMA_MSK 0
|
||||
#define STM32_SPI3_RX_DMA_CHN 0x00000000
|
||||
#define STM32_SPI3_TX_DMA_MSK 0
|
||||
#define STM32_SPI3_TX_DMA_CHN 0x00000000
|
||||
|
||||
/* SDIO attributes.*/
|
||||
#define STM32_HAS_SDIO FALSE
|
||||
|
||||
/* SPI attributes.*/
|
||||
#define STM32_HAS_SPI1 TRUE
|
||||
#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
|
||||
#define STM32_SPI1_RX_DMA_CHN 0x00000000
|
||||
#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
|
||||
#define STM32_SPI1_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_SPI2 FALSE
|
||||
#define STM32_SPI2_RX_DMA_MSK 0
|
||||
#define STM32_SPI2_RX_DMA_CHN 0x00000000
|
||||
#define STM32_SPI2_TX_DMA_MSK 0
|
||||
#define STM32_SPI2_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_SPI3 FALSE
|
||||
#define STM32_SPI3_RX_DMA_MSK 0
|
||||
#define STM32_SPI3_RX_DMA_CHN 0x00000000
|
||||
#define STM32_SPI3_TX_DMA_MSK 0
|
||||
#define STM32_SPI3_TX_DMA_CHN 0x00000000
|
||||
|
||||
/* TIM attributes.*/
|
||||
#define STM32_HAS_TIM1 TRUE
|
||||
#define STM32_HAS_TIM2 TRUE
|
||||
#define STM32_HAS_TIM3 TRUE
|
||||
#define STM32_HAS_TIM4 FALSE
|
||||
#define STM32_HAS_TIM5 FALSE
|
||||
#define STM32_HAS_TIM6 TRUE
|
||||
#define STM32_HAS_TIM7 TRUE
|
||||
#define STM32_HAS_TIM8 FALSE
|
||||
#define STM32_HAS_TIM9 FALSE
|
||||
#define STM32_HAS_TIM10 FALSE
|
||||
#define STM32_HAS_TIM11 FALSE
|
||||
#define STM32_HAS_TIM12 FALSE
|
||||
#define STM32_HAS_TIM13 FALSE
|
||||
#define STM32_HAS_TIM14 FALSE
|
||||
#define STM32_HAS_TIM15 TRUE
|
||||
#define STM32_HAS_TIM16 TRUE
|
||||
#define STM32_HAS_TIM17 TRUE
|
||||
#define STM32_HAS_TIM18 FALSE
|
||||
#define STM32_HAS_TIM19 FALSE
|
||||
|
||||
/* USART attributes.*/
|
||||
#define STM32_HAS_USART1 TRUE
|
||||
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
|
||||
#define STM32_USART1_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
|
||||
#define STM32_USART1_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_USART2 TRUE
|
||||
#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
|
||||
#define STM32_USART2_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
|
||||
#define STM32_USART2_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_USART3 FALSE
|
||||
#define STM32_USART3_RX_DMA_MSK 0
|
||||
#define STM32_USART3_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART3_TX_DMA_MSK 0
|
||||
#define STM32_USART3_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_UART4 FALSE
|
||||
#define STM32_UART4_RX_DMA_MSK 0
|
||||
#define STM32_UART4_RX_DMA_CHN 0x00000000
|
||||
#define STM32_UART4_TX_DMA_MSK 0
|
||||
#define STM32_UART4_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_UART5 FALSE
|
||||
#define STM32_UART5_RX_DMA_MSK 0
|
||||
#define STM32_UART5_RX_DMA_CHN 0x00000000
|
||||
#define STM32_UART5_TX_DMA_MSK 0
|
||||
#define STM32_UART5_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_USART6 FALSE
|
||||
#define STM32_USART6_RX_DMA_MSK 0
|
||||
#define STM32_USART6_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART6_TX_DMA_MSK 0
|
||||
#define STM32_USART6_TX_DMA_CHN 0x00000000
|
||||
|
||||
/* USB attributes.*/
|
||||
#define STM32_HAS_USB FALSE
|
||||
#define STM32_HAS_OTG1 FALSE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
/** @} */
|
||||
#endif /* defined(STM32F10X_LD_VL) */
|
||||
|
||||
#if defined(STM32F10X_MD_VL) || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @name STM32F100 MD capabilities
|
||||
* @{
|
||||
*/
|
||||
/* ADC attributes.*/
|
||||
#define STM32_HAS_ADC1 TRUE
|
||||
#define STM32_HAS_ADC2 FALSE
|
||||
#define STM32_HAS_ADC3 FALSE
|
||||
#define STM32_HAS_ADC4 FALSE
|
||||
|
||||
/* CAN attributes.*/
|
||||
#define STM32_HAS_CAN1 FALSE
|
||||
#define STM32_HAS_CAN2 FALSE
|
||||
#define STM32_CAN_MAX_FILTERS 0
|
||||
|
||||
/* DAC attributes.*/
|
||||
#define STM32_HAS_DAC TRUE
|
||||
|
||||
/* DMA attributes.*/
|
||||
#define STM32_ADVANCED_DMA FALSE
|
||||
#define STM32_HAS_DMA1 TRUE
|
||||
#define STM32_HAS_DMA2 FALSE
|
||||
|
||||
/* ETH attributes.*/
|
||||
#define STM32_HAS_ETH FALSE
|
||||
|
||||
/* EXTI attributes.*/
|
||||
#define STM32_EXTI_NUM_CHANNELS 19
|
||||
|
||||
/* GPIO attributes.*/
|
||||
#define STM32_HAS_GPIOA TRUE
|
||||
#define STM32_HAS_GPIOB TRUE
|
||||
#define STM32_HAS_GPIOC TRUE
|
||||
#define STM32_HAS_GPIOD TRUE
|
||||
#define STM32_HAS_GPIOE TRUE
|
||||
#define STM32_HAS_GPIOF FALSE
|
||||
#define STM32_HAS_GPIOG FALSE
|
||||
#define STM32_HAS_GPIOH FALSE
|
||||
#define STM32_HAS_GPIOI FALSE
|
||||
|
||||
/* I2C attributes.*/
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
|
||||
#define STM32_I2C1_RX_DMA_CHN 0x00000000
|
||||
#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
|
||||
#define STM32_I2C1_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_I2C2 TRUE
|
||||
#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
|
||||
#define STM32_I2C2_RX_DMA_CHN 0x00000000
|
||||
#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
|
||||
#define STM32_I2C2_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_I2C3 FALSE
|
||||
#define STM32_I2C3_RX_DMA_MSK 0
|
||||
#define STM32_I2C3_RX_DMA_CHN 0x00000000
|
||||
#define STM32_I2C3_TX_DMA_MSK 0
|
||||
#define STM32_I2C3_TX_DMA_CHN 0x00000000
|
||||
|
||||
/* RTC attributes.*/
|
||||
#define STM32_HAS_RTC TRUE
|
||||
|
||||
/* SDIO attributes.*/
|
||||
#define STM32_HAS_SDIO FALSE
|
||||
|
||||
/* SPI attributes.*/
|
||||
#define STM32_HAS_SPI1 TRUE
|
||||
#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
|
||||
#define STM32_SPI1_RX_DMA_CHN 0x00000000
|
||||
#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
|
||||
#define STM32_SPI1_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_SPI2 TRUE
|
||||
#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
||||
#define STM32_SPI2_RX_DMA_CHN 0x00000000
|
||||
#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
|
||||
#define STM32_SPI2_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_SPI3 FALSE
|
||||
#define STM32_HAS_SPI4 FALSE
|
||||
#define STM32_HAS_SPI5 FALSE
|
||||
#define STM32_HAS_SPI6 FALSE
|
||||
|
||||
/* TIM attributes.*/
|
||||
#define STM32_HAS_TIM1 TRUE
|
||||
#define STM32_HAS_TIM2 TRUE
|
||||
#define STM32_HAS_TIM3 TRUE
|
||||
#define STM32_HAS_TIM4 TRUE
|
||||
#define STM32_HAS_TIM5 FALSE
|
||||
#define STM32_HAS_TIM6 TRUE
|
||||
#define STM32_HAS_TIM7 TRUE
|
||||
#define STM32_HAS_TIM8 FALSE
|
||||
#define STM32_HAS_TIM9 FALSE
|
||||
#define STM32_HAS_TIM10 FALSE
|
||||
#define STM32_HAS_TIM11 FALSE
|
||||
#define STM32_HAS_TIM12 FALSE
|
||||
#define STM32_HAS_TIM13 FALSE
|
||||
#define STM32_HAS_TIM14 FALSE
|
||||
#define STM32_HAS_TIM15 TRUE
|
||||
#define STM32_HAS_TIM16 TRUE
|
||||
#define STM32_HAS_TIM17 TRUE
|
||||
|
||||
/* USART attributes.*/
|
||||
#define STM32_HAS_USART1 TRUE
|
||||
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
|
||||
#define STM32_USART1_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
|
||||
#define STM32_USART1_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_USART2 TRUE
|
||||
#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
|
||||
#define STM32_USART2_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
|
||||
#define STM32_USART2_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_USART3 TRUE
|
||||
#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
|
||||
#define STM32_USART3_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
|
||||
#define STM32_USART3_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_UART4 FALSE
|
||||
#define STM32_UART4_RX_DMA_MSK 0
|
||||
#define STM32_UART4_RX_DMA_CHN 0x00000000
|
||||
#define STM32_UART4_TX_DMA_MSK 0
|
||||
#define STM32_UART4_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_UART5 FALSE
|
||||
#define STM32_UART5_RX_DMA_MSK 0
|
||||
#define STM32_UART5_RX_DMA_CHN 0x00000000
|
||||
#define STM32_UART5_TX_DMA_MSK 0
|
||||
#define STM32_UART5_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_USART6 FALSE
|
||||
#define STM32_USART6_RX_DMA_MSK 0
|
||||
#define STM32_USART6_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART6_TX_DMA_MSK 0
|
||||
#define STM32_USART6_TX_DMA_CHN 0x00000000
|
||||
|
||||
/* USB attributes.*/
|
||||
#define STM32_HAS_USB FALSE
|
||||
#define STM32_HAS_OTG1 FALSE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
/** @} */
|
||||
#endif /* defined(STM32F10X_MD_VL) */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Platform specific friendly IRQ names. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name IRQ VECTOR names
|
||||
* @{
|
||||
*/
|
||||
#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */
|
||||
#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line
|
||||
detect. */
|
||||
#define TAMPER_IRQHandler Vector48 /**< Tamper. */
|
||||
#define RTC_IRQHandler Vector4C /**< RTC. */
|
||||
#define FLASH_IRQHandler Vector50 /**< Flash. */
|
||||
#define RCC_IRQHandler Vector54 /**< RCC. */
|
||||
#define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */
|
||||
#define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */
|
||||
#define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */
|
||||
#define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */
|
||||
#define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */
|
||||
#define DMA1_Ch1_IRQHandler Vector6C /**< DMA1 Channel 1. */
|
||||
#define DMA1_Ch2_IRQHandler Vector70 /**< DMA1 Channel 2. */
|
||||
#define DMA1_Ch3_IRQHandler Vector74 /**< DMA1 Channel 3. */
|
||||
#define DMA1_Ch4_IRQHandler Vector78 /**< DMA1 Channel 4. */
|
||||
#define DMA1_Ch5_IRQHandler Vector7C /**< DMA1 Channel 5. */
|
||||
#define DMA1_Ch6_IRQHandler Vector80 /**< DMA1 Channel 6. */
|
||||
#define DMA1_Ch7_IRQHandler Vector84 /**< DMA1 Channel 7. */
|
||||
#define ADC1_2_IRQHandler Vector88 /**< ADC1_2. */
|
||||
#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */
|
||||
#define TIM1_BRK_IRQHandler VectorA0 /**< TIM1 Break. */
|
||||
#define TIM1_UP_IRQHandler VectorA4 /**< TIM1 Update. */
|
||||
#define TIM1_TRG_COM_IRQHandler VectorA8 /**< TIM1 Trigger and
|
||||
Commutation. */
|
||||
#define TIM1_CC_IRQHandler VectorAC /**< TIM1 Capture Compare. */
|
||||
#define TIM2_IRQHandler VectorB0 /**< TIM2. */
|
||||
#define TIM3_IRQHandler VectorB4 /**< TIM3. */
|
||||
#if !defined(STM32F10X_LD_VL) || defined(__DOXYGEN__)
|
||||
#define TIM4_IRQHandler VectorB8 /**< TIM4. */
|
||||
#endif
|
||||
#define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */
|
||||
#define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */
|
||||
#if !defined(STM32F10X_LD_VL) || defined(__DOXYGEN__)
|
||||
#define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */
|
||||
#define I2C2_ER_IRQHandler VectorC8 /**< I2C2 Error. */
|
||||
#endif
|
||||
#define SPI1_IRQHandler VectorCC /**< SPI1. */
|
||||
#if !defined(STM32F10X_LD_VL) || defined(__DOXYGEN__)
|
||||
#define SPI2_IRQHandler VectorD0 /**< SPI2. */
|
||||
#endif
|
||||
#define USART1_IRQHandler VectorD4 /**< USART1. */
|
||||
#define USART2_IRQHandler VectorD8 /**< USART2. */
|
||||
#if !defined(STM32F10X_LD_VL) || defined(__DOXYGEN__)
|
||||
#define USART3_IRQHandler VectorDC /**< USART3. */
|
||||
#endif
|
||||
#define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */
|
||||
#define RTC_Alarm_IRQHandler VectorE4 /**< RTC Alarm through EXTI. */
|
||||
#define CEC_IRQHandler VectorE8 /**< CEC. */
|
||||
#define TIM12_IRQHandler VectorEC /**< TIM12. */
|
||||
#define TIM13_IRQHandler VectorF0 /**< TIM13. */
|
||||
#define TIM14_IRQHandler VectorF4 /**< TIM14. */
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Configuration options
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Main clock source selection.
|
||||
* @note If the selected clock source is not the PLL then the PLL is not
|
||||
* initialized and started.
|
||||
* @note The default value is calculated for a 72MHz system clock from
|
||||
* a 8MHz crystal using the PLL.
|
||||
*/
|
||||
#if !defined(STM32_SW) || defined(__DOXYGEN__)
|
||||
#define STM32_SW STM32_SW_PLL
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Clock source for the PLL.
|
||||
* @note This setting has only effect if the PLL is selected as the
|
||||
* system clock source.
|
||||
* @note The default value is calculated for a 72MHz system clock from
|
||||
* a 8MHz crystal using the PLL.
|
||||
*/
|
||||
#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLSRC STM32_PLLSRC_HSE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Crystal PLL pre-divider.
|
||||
* @note This setting has only effect if the PLL is selected as the
|
||||
* system clock source.
|
||||
* @note The default value is calculated for a 72MHz system clock from
|
||||
* a 8MHz crystal using the PLL.
|
||||
*/
|
||||
#if !defined(STM32_PLLXTPRE) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLL multiplier value.
|
||||
* @note The allowed range is 2...16.
|
||||
* @note The default value is calculated for a 24MHz system clock from
|
||||
* a 8MHz crystal using the PLL.
|
||||
*/
|
||||
#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
|
||||
#define STM32_PLLMUL_VALUE 3
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief AHB prescaler value.
|
||||
* @note The default value is calculated for a 24MHz system clock from
|
||||
* a 8MHz crystal using the PLL.
|
||||
*/
|
||||
#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
|
||||
#define STM32_HPRE STM32_HPRE_DIV1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief APB1 prescaler value.
|
||||
*/
|
||||
#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
|
||||
#define STM32_PPRE1 STM32_PPRE1_DIV1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief APB2 prescaler value.
|
||||
*/
|
||||
#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
|
||||
#define STM32_PPRE2 STM32_PPRE2_DIV1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC prescaler value.
|
||||
*/
|
||||
#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__)
|
||||
#define STM32_ADCPRE STM32_ADCPRE_DIV2
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief MCO pin setting.
|
||||
*/
|
||||
#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
|
||||
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief RTC clock source.
|
||||
*/
|
||||
#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
|
||||
#define STM32_RTCSEL STM32_RTCSEL_LSI
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*
|
||||
* Configuration-related checks.
|
||||
*/
|
||||
#if !defined(STM32F100_MCUCONF)
|
||||
#error "Using a wrong mcuconf.h file, STM32F100_MCUCONF not defined"
|
||||
#endif
|
||||
|
||||
/*
|
||||
* HSI related checks.
|
||||
*/
|
||||
#if STM32_HSI_ENABLED
|
||||
#else /* !STM32_HSI_ENABLED */
|
||||
|
||||
#if STM32_SW == STM32_SW_HSI
|
||||
#error "HSI not enabled, required by STM32_SW"
|
||||
#endif
|
||||
|
||||
#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
|
||||
#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
|
||||
#endif
|
||||
|
||||
#if (STM32_MCOSEL == STM32_MCOSEL_HSI) || \
|
||||
((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \
|
||||
(STM32_PLLSRC == STM32_PLLSRC_HSI))
|
||||
#error "HSI not enabled, required by STM32_MCOSEL"
|
||||
#endif
|
||||
|
||||
#endif /* !STM32_HSI_ENABLED */
|
||||
|
||||
/*
|
||||
* HSE related checks.
|
||||
*/
|
||||
#if STM32_HSE_ENABLED
|
||||
|
||||
#if STM32_HSECLK == 0
|
||||
#error "HSE frequency not defined"
|
||||
#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
|
||||
#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
|
||||
#endif
|
||||
|
||||
#else /* !STM32_HSE_ENABLED */
|
||||
|
||||
#if STM32_SW == STM32_SW_HSE
|
||||
#error "HSE not enabled, required by STM32_SW"
|
||||
#endif
|
||||
|
||||
#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
|
||||
#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
|
||||
#endif
|
||||
|
||||
#if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \
|
||||
((STM32_MCOSEL == STM32_MCOSEL_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE))
|
||||
#error "HSE not enabled, required by STM32_MCOSEL"
|
||||
#endif
|
||||
|
||||
#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
|
||||
#error "HSE not enabled, required by STM32_RTCSELSEL"
|
||||
#endif
|
||||
|
||||
#endif /* !STM32_HSE_ENABLED */
|
||||
|
||||
/*
|
||||
* LSI related checks.
|
||||
*/
|
||||
#if STM32_LSI_ENABLED
|
||||
#else /* !STM32_LSI_ENABLED */
|
||||
|
||||
#if STM32_RTCSEL == STM32_RTCSEL_LSI
|
||||
#error "LSI not enabled, required by STM32_RTCSEL"
|
||||
#endif
|
||||
|
||||
#endif /* !STM32_LSI_ENABLED */
|
||||
|
||||
/*
|
||||
* LSE related checks.
|
||||
*/
|
||||
#if STM32_LSE_ENABLED
|
||||
|
||||
#if (STM32_LSECLK == 0)
|
||||
#error "LSE frequency not defined"
|
||||
#endif
|
||||
|
||||
#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
|
||||
#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
|
||||
#endif
|
||||
|
||||
#else /* !STM32_LSE_ENABLED */
|
||||
|
||||
#if STM32_RTCSEL == STM32_RTCSEL_LSE
|
||||
#error "LSE not enabled, required by STM32_RTCSEL"
|
||||
#endif
|
||||
|
||||
#endif /* !STM32_LSE_ENABLED */
|
||||
|
||||
/* PLL activation conditions.*/
|
||||
#if (STM32_SW == STM32_SW_PLL) || \
|
||||
(STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) || \
|
||||
defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief PLL activation flag.
|
||||
*/
|
||||
#define STM32_ACTIVATE_PLL TRUE
|
||||
#else
|
||||
#define STM32_ACTIVATE_PLL FALSE
|
||||
#endif
|
||||
|
||||
/* HSE prescaler setting check.*/
|
||||
#if (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV1) && \
|
||||
(STM32_PLLXTPRE != STM32_PLLXTPRE_DIV2)
|
||||
#error "invalid STM32_PLLXTPRE value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLLMUL field.
|
||||
*/
|
||||
#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) || \
|
||||
defined(__DOXYGEN__)
|
||||
#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18)
|
||||
#else
|
||||
#error "invalid STM32_PLLMUL_VALUE value specified"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLL input clock frequency.
|
||||
*/
|
||||
#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
|
||||
#if STM32_PLLXTPRE == STM32_PLLXTPRE_DIV1
|
||||
#define STM32_PLLCLKIN (STM32_HSECLK / 1)
|
||||
#else
|
||||
#define STM32_PLLCLKIN (STM32_HSECLK / 2)
|
||||
#endif
|
||||
#elif STM32_PLLSRC == STM32_PLLSRC_HSI
|
||||
#define STM32_PLLCLKIN (STM32_HSICLK / 2)
|
||||
#else
|
||||
#error "invalid STM32_PLLSRC value specified"
|
||||
#endif
|
||||
|
||||
/* PLL input frequency range check.*/
|
||||
#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
|
||||
#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief PLL output clock frequency.
|
||||
*/
|
||||
#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
|
||||
|
||||
/* PLL output frequency range check.*/
|
||||
#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX)
|
||||
#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief System clock source.
|
||||
*/
|
||||
#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)
|
||||
#define STM32_SYSCLK STM32_PLLCLKOUT
|
||||
#elif (STM32_SW == STM32_SW_HSI)
|
||||
#define STM32_SYSCLK STM32_HSICLK
|
||||
#elif (STM32_SW == STM32_SW_HSE)
|
||||
#define STM32_SYSCLK STM32_HSECLK
|
||||
#else
|
||||
#error "invalid STM32_SW value specified"
|
||||
#endif
|
||||
|
||||
/* Check on the system clock.*/
|
||||
#if STM32_SYSCLK > STM32_SYSCLK_MAX
|
||||
#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief AHB frequency.
|
||||
*/
|
||||
#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
|
||||
#define STM32_HCLK (STM32_SYSCLK / 1)
|
||||
#elif STM32_HPRE == STM32_HPRE_DIV2
|
||||
#define STM32_HCLK (STM32_SYSCLK / 2)
|
||||
#elif STM32_HPRE == STM32_HPRE_DIV4
|
||||
#define STM32_HCLK (STM32_SYSCLK / 4)
|
||||
#elif STM32_HPRE == STM32_HPRE_DIV8
|
||||
#define STM32_HCLK (STM32_SYSCLK / 8)
|
||||
#elif STM32_HPRE == STM32_HPRE_DIV16
|
||||
#define STM32_HCLK (STM32_SYSCLK / 16)
|
||||
#elif STM32_HPRE == STM32_HPRE_DIV64
|
||||
#define STM32_HCLK (STM32_SYSCLK / 64)
|
||||
#elif STM32_HPRE == STM32_HPRE_DIV128
|
||||
#define STM32_HCLK (STM32_SYSCLK / 128)
|
||||
#elif STM32_HPRE == STM32_HPRE_DIV256
|
||||
#define STM32_HCLK (STM32_SYSCLK / 256)
|
||||
#elif STM32_HPRE == STM32_HPRE_DIV512
|
||||
#define STM32_HCLK (STM32_SYSCLK / 512)
|
||||
#else
|
||||
#error "invalid STM32_HPRE value specified"
|
||||
#endif
|
||||
|
||||
/* AHB frequency check.*/
|
||||
#if STM32_HCLK > STM32_SYSCLK_MAX
|
||||
#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief APB1 frequency.
|
||||
*/
|
||||
#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
|
||||
#define STM32_PCLK1 (STM32_HCLK / 1)
|
||||
#elif STM32_PPRE1 == STM32_PPRE1_DIV2
|
||||
#define STM32_PCLK1 (STM32_HCLK / 2)
|
||||
#elif STM32_PPRE1 == STM32_PPRE1_DIV4
|
||||
#define STM32_PCLK1 (STM32_HCLK / 4)
|
||||
#elif STM32_PPRE1 == STM32_PPRE1_DIV8
|
||||
#define STM32_PCLK1 (STM32_HCLK / 8)
|
||||
#elif STM32_PPRE1 == STM32_PPRE1_DIV16
|
||||
#define STM32_PCLK1 (STM32_HCLK / 16)
|
||||
#else
|
||||
#error "invalid STM32_PPRE1 value specified"
|
||||
#endif
|
||||
|
||||
/* APB1 frequency check.*/
|
||||
#if STM32_PCLK1 > STM32_PCLK1_MAX
|
||||
#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief APB2 frequency.
|
||||
*/
|
||||
#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
|
||||
#define STM32_PCLK2 (STM32_HCLK / 1)
|
||||
#elif STM32_PPRE2 == STM32_PPRE2_DIV2
|
||||
#define STM32_PCLK2 (STM32_HCLK / 2)
|
||||
#elif STM32_PPRE2 == STM32_PPRE2_DIV4
|
||||
#define STM32_PCLK2 (STM32_HCLK / 4)
|
||||
#elif STM32_PPRE2 == STM32_PPRE2_DIV8
|
||||
#define STM32_PCLK2 (STM32_HCLK / 8)
|
||||
#elif STM32_PPRE2 == STM32_PPRE2_DIV16
|
||||
#define STM32_PCLK2 (STM32_HCLK / 16)
|
||||
#else
|
||||
#error "invalid STM32_PPRE2 value specified"
|
||||
#endif
|
||||
|
||||
/* APB2 frequency check.*/
|
||||
#if STM32_PCLK2 > STM32_PCLK2_MAX
|
||||
#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief RTC clock.
|
||||
*/
|
||||
#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__)
|
||||
#define STM32_RTCCLK STM32_LSECLK
|
||||
#elif STM32_RTCSEL == STM32_RTCSEL_LSI
|
||||
#define STM32_RTCCLK STM32_LSICLK
|
||||
#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
|
||||
#define STM32_RTCCLK (STM32_HSECLK / 128)
|
||||
#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
|
||||
#define STM32_RTCCLK 0
|
||||
#else
|
||||
#error "invalid source selected for RTC clock"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ADC frequency.
|
||||
*/
|
||||
#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__)
|
||||
#define STM32_ADCCLK (STM32_PCLK2 / 2)
|
||||
#elif STM32_ADCPRE == STM32_ADCPRE_DIV4
|
||||
#define STM32_ADCCLK (STM32_PCLK2 / 4)
|
||||
#elif STM32_ADCPRE == STM32_ADCPRE_DIV6
|
||||
#define STM32_ADCCLK (STM32_PCLK2 / 6)
|
||||
#elif STM32_ADCPRE == STM32_ADCPRE_DIV8
|
||||
#define STM32_ADCCLK (STM32_PCLK2 / 8)
|
||||
#else
|
||||
#error "invalid STM32_ADCPRE value specified"
|
||||
#endif
|
||||
|
||||
/* ADC frequency check.*/
|
||||
#if STM32_ADCCLK > STM32_ADCCLK_MAX
|
||||
#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Timers 2, 3, 4, 5, 6, 7, 12, 13, 14 clock.
|
||||
*/
|
||||
#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
|
||||
#define STM32_TIMCLK1 (STM32_PCLK1 * 1)
|
||||
#else
|
||||
#define STM32_TIMCLK1 (STM32_PCLK1 * 2)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Timers 1, 8, 9, 10, 11 clock.
|
||||
*/
|
||||
#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
|
||||
#define STM32_TIMCLK2 (STM32_PCLK2 * 1)
|
||||
#else
|
||||
#define STM32_TIMCLK2 (STM32_PCLK2 * 2)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Flash settings.
|
||||
*/
|
||||
#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__)
|
||||
#define STM32_FLASHBITS 0x00000010
|
||||
#elif STM32_HCLK <= 48000000
|
||||
#define STM32_FLASHBITS 0x00000011
|
||||
#else
|
||||
#define STM32_FLASHBITS 0x00000012
|
||||
#endif
|
||||
|
||||
#endif /* _HAL_LLD_F100_H_ */
|
||||
|
||||
/** @} */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,398 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STM32F1xx_DRIVERS STM32F1xx Drivers
|
||||
* @details This section describes all the supported drivers on the STM32F1xx
|
||||
* platform and the implementation details of the single drivers.
|
||||
*
|
||||
* @ingroup platforms
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STM32F1xx_HAL STM32F1xx Initialization Support
|
||||
* @details The STM32F1xx HAL support is responsible for system initialization.
|
||||
*
|
||||
* @section stm32f1xx_hal_1 Supported HW resources
|
||||
* - PLL1.
|
||||
* - PLL2 (where present).
|
||||
* - RCC.
|
||||
* - Flash.
|
||||
* .
|
||||
* @section stm32f1xx_hal_2 STM32F1xx HAL driver implementation features
|
||||
* - PLLs startup and stabilization.
|
||||
* - Clock tree initialization.
|
||||
* - Clock source selection.
|
||||
* - Flash wait states initialization based on the selected clock options.
|
||||
* - SYSTICK initialization based on current clock and kernel required rate.
|
||||
* - DMA support initialization.
|
||||
* .
|
||||
* @ingroup STM32F1xx_DRIVERS
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STM32F1xx_ADC STM32F1xx ADC Support
|
||||
* @details The STM32F1xx ADC driver supports the ADC peripherals using DMA
|
||||
* channels for maximum performance.
|
||||
*
|
||||
* @section stm32f1xx_adc_1 Supported HW resources
|
||||
* - ADC1.
|
||||
* - DMA1.
|
||||
* .
|
||||
* @section stm32f1xx_adc_2 STM32F1xx ADC driver implementation features
|
||||
* - Clock stop for reduced power usage when the driver is in stop state.
|
||||
* - Streaming conversion using DMA for maximum performance.
|
||||
* - Programmable ADC interrupt priority level.
|
||||
* - Programmable DMA bus priority for each DMA channel.
|
||||
* - Programmable DMA interrupt priority for each DMA channel.
|
||||
* - DMA errors detection.
|
||||
* .
|
||||
* @ingroup STM32F1xx_DRIVERS
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STM32F1xx_CAN STM32F1xx CAN Support
|
||||
* @details The STM32F1xx CAN driver uses the CAN peripherals.
|
||||
*
|
||||
* @section stm32f1xx_can_1 Supported HW resources
|
||||
* - bxCAN1.
|
||||
* .
|
||||
* @section stm32f1xx_can_2 STM32F1xx CAN driver implementation features
|
||||
* - Clock stop for reduced power usage when the driver is in stop state.
|
||||
* - Support for bxCAN sleep mode.
|
||||
* - Programmable bxCAN interrupts priority level.
|
||||
* .
|
||||
* @ingroup STM32F1xx_DRIVERS
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STM32F1xx_EXT STM32F1xx EXT Support
|
||||
* @details The STM32F1xx EXT driver uses the EXTI peripheral.
|
||||
*
|
||||
* @section stm32f1xx_ext_1 Supported HW resources
|
||||
* - EXTI.
|
||||
* .
|
||||
* @section stm32f1xx_ext_2 STM32F1xx EXT driver implementation features
|
||||
* - Each EXTI channel can be independently enabled and programmed.
|
||||
* - Programmable EXTI interrupts priority level.
|
||||
* - Capability to work as event sources (WFE) rather than interrupt sources.
|
||||
* .
|
||||
* @ingroup STM32F1xx_DRIVERS
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STM32F1xx_GPT STM32F1xx GPT Support
|
||||
* @details The STM32F1xx GPT driver uses the TIMx peripherals.
|
||||
*
|
||||
* @section stm32f1xx_gpt_1 Supported HW resources
|
||||
* - TIM1.
|
||||
* - TIM2.
|
||||
* - TIM3.
|
||||
* - TIM4.
|
||||
* - TIM5.
|
||||
* .
|
||||
* @section stm32f1xx_gpt_2 STM32F1xx GPT driver implementation features
|
||||
* - Each timer can be independently enabled and programmed. Unused
|
||||
* peripherals are left in low power mode.
|
||||
* - Programmable TIMx interrupts priority level.
|
||||
* .
|
||||
* @ingroup STM32F1xx_DRIVERS
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STM32F1xx_I2C STM32F1xx I2C Support
|
||||
* @details The STM32F1xx I2C driver uses the I2Cx peripherals.
|
||||
*
|
||||
* @section stm32f1xx_i2c_1 Supported HW resources
|
||||
* - I2C1.
|
||||
* - I2C2.
|
||||
* .
|
||||
* @section stm32f1xx_i2c_2 STM32F1xx I2C driver implementation features
|
||||
* - Each I2C port can be independently enabled and programmed. Unused
|
||||
* peripherals are left in low power mode.
|
||||
* - Programmable I2Cx interrupts priority level.
|
||||
* .
|
||||
* @ingroup STM32F1xx_DRIVERS
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STM32F1xx_ICU STM32F1xx ICU Support
|
||||
* @details The STM32F1xx ICU driver uses the TIMx peripherals.
|
||||
*
|
||||
* @section stm32f1xx_icu_1 Supported HW resources
|
||||
* - TIM1.
|
||||
* - TIM2.
|
||||
* - TIM3.
|
||||
* - TIM4.
|
||||
* - TIM5.
|
||||
* .
|
||||
* @section stm32f1xx_icu_2 STM32F1xx ICU driver implementation features
|
||||
* - Each timer can be independently enabled and programmed. Unused
|
||||
* peripherals are left in low power mode.
|
||||
* - Programmable TIMx interrupts priority level.
|
||||
* .
|
||||
* @ingroup STM32F1xx_DRIVERS
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STM32F1xx_MAC STM32F1xx MAC Support
|
||||
* @details The STM32 MAC driver supports the ETH peripheral.
|
||||
*
|
||||
* @section at91sam7_mac_1 Supported HW resources
|
||||
* - ETH.
|
||||
* .
|
||||
* @ingroup STM32F1xx_DRIVERS
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STM32F1xx_PAL STM32F1xx PAL Support
|
||||
* @details The STM32F1xx PAL driver uses the GPIO peripherals.
|
||||
*
|
||||
* @section stm32f1xx_pal_1 Supported HW resources
|
||||
* - AFIO.
|
||||
* - GPIOA.
|
||||
* - GPIOB.
|
||||
* - GPIOC.
|
||||
* - GPIOD.
|
||||
* - GPIOE (where present).
|
||||
* - GPIOF (where present).
|
||||
* - GPIOG (where present).
|
||||
* .
|
||||
* @section stm32f1xx_pal_2 STM32F1xx PAL driver implementation features
|
||||
* The PAL driver implementation fully supports the following hardware
|
||||
* capabilities:
|
||||
* - 16 bits wide ports.
|
||||
* - Atomic set/reset functions.
|
||||
* - Atomic set+reset function (atomic bus operations).
|
||||
* - Output latched regardless of the pad setting.
|
||||
* - Direct read of input pads regardless of the pad setting.
|
||||
* .
|
||||
* @section stm32f1xx_pal_3 Supported PAL setup modes
|
||||
* The STM32F1xx PAL driver supports the following I/O modes:
|
||||
* - @p PAL_MODE_RESET.
|
||||
* - @p PAL_MODE_UNCONNECTED.
|
||||
* - @p PAL_MODE_INPUT.
|
||||
* - @p PAL_MODE_INPUT_PULLUP.
|
||||
* - @p PAL_MODE_INPUT_PULLDOWN.
|
||||
* - @p PAL_MODE_INPUT_ANALOG.
|
||||
* - @p PAL_MODE_OUTPUT_PUSHPULL.
|
||||
* - @p PAL_MODE_OUTPUT_OPENDRAIN.
|
||||
* - @p PAL_MODE_STM32F1xx_ALTERNATE_PUSHPULL (non standard).
|
||||
* - @p PAL_MODE_STM32F1xx_ALTERNATE_OPENDRAIN (non standard).
|
||||
* .
|
||||
* Any attempt to setup an invalid mode is ignored.
|
||||
*
|
||||
* @section stm32f1xx_pal_4 Suboptimal behavior
|
||||
* The STM32F1xx GPIO is less than optimal in several areas, the limitations
|
||||
* should be taken in account while using the PAL driver:
|
||||
* - Pad/port toggling operations are not atomic.
|
||||
* - Pad/group mode setup is not atomic.
|
||||
* - Writing on pads/groups/ports programmed as input with pull-up/down
|
||||
* resistor can change the resistor setting because the output latch is
|
||||
* used for resistor selection.
|
||||
* .
|
||||
* @ingroup STM32F1xx_DRIVERS
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STM32F1xx_PWM STM32F1xx PWM Support
|
||||
* @details The STM32F1xx PWM driver uses the TIMx peripherals.
|
||||
*
|
||||
* @section stm32f1xx_pwm_1 Supported HW resources
|
||||
* - TIM1.
|
||||
* - TIM2.
|
||||
* - TIM3.
|
||||
* - TIM4.
|
||||
* - TIM5.
|
||||
* .
|
||||
* @section stm32f1xx_pwm_2 STM32F1xx PWM driver implementation features
|
||||
* - Each timer can be independently enabled and programmed. Unused
|
||||
* peripherals are left in low power mode.
|
||||
* - Four independent PWM channels per timer.
|
||||
* - Programmable TIMx interrupts priority level.
|
||||
* .
|
||||
* @ingroup STM32F1xx_DRIVERS
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STM32F1xx_RTC STM32F1xx RTC Support
|
||||
* @details The STM32F1xx RTC driver uses the RTC peripheral.
|
||||
*
|
||||
* @section stm32f1xx_rtc_1 Supported HW resources
|
||||
* - RTC.
|
||||
* .
|
||||
* @ingroup STM32F1xx_DRIVERS
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STM32F1xx_SDC STM32F1xx SDC Support
|
||||
* @details The STM32F1xx SDC driver uses the SDIO peripheral.
|
||||
*
|
||||
* @section stm32f1xx_sdc_1 Supported HW resources
|
||||
* - SDIO.
|
||||
* - DMA2.
|
||||
* .
|
||||
* @section stm32f1xx_sdc_2 STM32F1xx SDC driver implementation features
|
||||
* - Clock stop for reduced power usage when the driver is in stop state.
|
||||
* - Programmable interrupt priority.
|
||||
* - DMA is used for receiving and transmitting.
|
||||
* - Programmable DMA bus priority for each DMA channel.
|
||||
* .
|
||||
* @ingroup STM32F1xx_DRIVERS
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STM32F1xx_SERIAL STM32F1xx Serial Support
|
||||
* @details The STM32F1xx Serial driver uses the USART/UART peripherals in a
|
||||
* buffered, interrupt driven, implementation.
|
||||
*
|
||||
* @section stm32f1xx_serial_1 Supported HW resources
|
||||
* The serial driver can support any of the following hardware resources:
|
||||
* - USART1.
|
||||
* - USART2.
|
||||
* - USART3 (where present).
|
||||
* - UART4 (where present).
|
||||
* - UART5 (where present).
|
||||
* .
|
||||
* @section stm32f1xx_serial_2 STM32F1xx Serial driver implementation features
|
||||
* - Clock stop for reduced power usage when the driver is in stop state.
|
||||
* - Each UART/USART can be independently enabled and programmed. Unused
|
||||
* peripherals are left in low power mode.
|
||||
* - Fully interrupt driven.
|
||||
* - Programmable priority levels for each UART/USART.
|
||||
* .
|
||||
* @ingroup STM32F1xx_DRIVERS
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STM32F1xx_SPI STM32F1xx SPI Support
|
||||
* @details The SPI driver supports the STM32F1xx SPI peripherals using DMA
|
||||
* channels for maximum performance.
|
||||
*
|
||||
* @section stm32f1xx_spi_1 Supported HW resources
|
||||
* - SPI1.
|
||||
* - SPI2.
|
||||
* - SPI3 (where present).
|
||||
* - DMA1.
|
||||
* - DMA2 (where present).
|
||||
* .
|
||||
* @section stm32f1xx_spi_2 STM32F1xx SPI driver implementation features
|
||||
* - Clock stop for reduced power usage when the driver is in stop state.
|
||||
* - Each SPI can be independently enabled and programmed. Unused
|
||||
* peripherals are left in low power mode.
|
||||
* - Programmable interrupt priority levels for each SPI.
|
||||
* - DMA is used for receiving and transmitting.
|
||||
* - Programmable DMA bus priority for each DMA channel.
|
||||
* - Programmable DMA interrupt priority for each DMA channel.
|
||||
* - Programmable DMA error hook.
|
||||
* .
|
||||
* @ingroup STM32F1xx_DRIVERS
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STM32F1xx_UART STM32F1xx UART Support
|
||||
* @details The UART driver supports the STM32F1xx USART peripherals using DMA
|
||||
* channels for maximum performance.
|
||||
*
|
||||
* @section stm32f1xx_uart_1 Supported HW resources
|
||||
* The UART driver can support any of the following hardware resources:
|
||||
* - USART1.
|
||||
* - USART2.
|
||||
* - USART3 (where present).
|
||||
* - UART4 (where present).
|
||||
* - DMA1.
|
||||
* - DMA2 (where present).
|
||||
* .
|
||||
* @section stm32f1xx_uart_2 STM32F1xx UART driver implementation features
|
||||
* - Clock stop for reduced power usage when the driver is in stop state.
|
||||
* - Each UART/USART can be independently enabled and programmed. Unused
|
||||
* peripherals are left in low power mode.
|
||||
* - Programmable interrupt priority levels for each UART/USART.
|
||||
* - DMA is used for receiving and transmitting.
|
||||
* - Programmable DMA bus priority for each DMA channel.
|
||||
* - Programmable DMA interrupt priority for each DMA channel.
|
||||
* - Programmable DMA error hook.
|
||||
* .
|
||||
* @ingroup STM32F1xx_DRIVERS
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STM32F1xx_USB STM32F1xx USB Support
|
||||
* @details The USB driver supports the STM32F1xx USB peripheral.
|
||||
*
|
||||
* @section stm32f1xx_usb_1 Supported HW resources
|
||||
* The USB driver can support any of the following hardware resources:
|
||||
* - USB.
|
||||
* .
|
||||
* @section stm32f1xx_usb_2 STM32F1xx USB driver implementation features
|
||||
* - Clock stop for reduced power usage when the driver is in stop state.
|
||||
* - Programmable interrupt priority levels.
|
||||
* - Each endpoint programmable in Control, Bulk and Interrupt modes.
|
||||
* .
|
||||
* @ingroup STM32F1xx_DRIVERS
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STM32F1xx_PLATFORM_DRIVERS STM32F1xx Platform Drivers
|
||||
* @details Platform support drivers. Platform drivers do not implement HAL
|
||||
* standard driver templates, their role is to support platform
|
||||
* specific functionalities.
|
||||
*
|
||||
* @ingroup STM32F1xx_DRIVERS
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STM32F1xx_DMA STM32F1xx DMA Support
|
||||
* @details This DMA helper driver is used by the other drivers in order to
|
||||
* access the shared DMA resources in a consistent way.
|
||||
*
|
||||
* @section stm32f1xx_dma_1 Supported HW resources
|
||||
* The DMA driver can support any of the following hardware resources:
|
||||
* - DMA1.
|
||||
* - DMA2 (where present).
|
||||
* .
|
||||
* @section stm32f1xx_dma_2 STM32F1xx DMA driver implementation features
|
||||
* - Exports helper functions/macros to the other drivers that share the
|
||||
* DMA resource.
|
||||
* - Automatic DMA clock stop when not in use by any driver.
|
||||
* - DMA streams and interrupt vectors sharing among multiple drivers.
|
||||
* .
|
||||
* @ingroup STM32F1xx_PLATFORM_DRIVERS
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STM32F1xx_ISR STM32F1xx ISR Support
|
||||
* @details This ISR helper driver is used by the other drivers in order to
|
||||
* map ISR names to physical vector names.
|
||||
*
|
||||
* @ingroup STM32F1xx_PLATFORM_DRIVERS
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup STM32F1xx_RCC STM32F1xx RCC Support
|
||||
* @details This RCC helper driver is used by the other drivers in order to
|
||||
* access the shared RCC resources in a consistent way.
|
||||
*
|
||||
* @section stm32f1xx_rcc_1 Supported HW resources
|
||||
* - RCC.
|
||||
* .
|
||||
* @section stm32f1xx_rcc_2 STM32F1xx RCC driver implementation features
|
||||
* - Peripherals reset.
|
||||
* - Peripherals clock enable.
|
||||
* - Peripherals clock disable.
|
||||
* .
|
||||
* @ingroup STM32F1xx_PLATFORM_DRIVERS
|
||||
*/
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
# List of all the STM32F1xx platform files.
|
||||
PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F1xx/stm32_dma.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32F1xx/hal_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32F1xx/adc_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32F1xx/ext_lld_isr.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/mac_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/sdc_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/GPIOv1/pal_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/I2Cv1/i2c_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/RTCv1/rtc_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/SPIv1/spi_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/TIMv1/gpt_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/TIMv1/icu_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/TIMv1/pwm_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/USARTv1/serial_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/USARTv1/uart_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/USBv1/usb_lld.c
|
||||
|
||||
# Required include directories
|
||||
PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F1xx \
|
||||
${CHIBIOS}/os/hal/platforms/STM32 \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/GPIOv1 \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/I2Cv1 \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/RTCv1 \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/SPIv1 \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/TIMv1 \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/USARTv1 \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/USBv1
|
||||
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
# List of all the STM32F1xx platform files.
|
||||
PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F1xx/stm32_dma.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32F1xx/hal_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32F1xx/adc_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32F1xx/ext_lld_isr.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/mac_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/sdc_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/GPIOv1/pal_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/I2Cv1/i2c_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/RTCv1/rtc_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/SPIv1/spi_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/TIMv1/gpt_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/TIMv1/icu_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/TIMv1/pwm_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/USARTv1/serial_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/USARTv1/uart_lld.c \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/OTGv1/usb_lld.c
|
||||
|
||||
# Required include directories
|
||||
PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F1xx \
|
||||
${CHIBIOS}/os/hal/platforms/STM32 \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/GPIOv1 \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/I2Cv1 \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/RTCv1 \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/SPIv1 \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/TIMv1 \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/USARTv1 \
|
||||
${CHIBIOS}/os/hal/platforms/STM32/OTGv1
|
||||
|
|
@ -0,0 +1,503 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file STM32F1xx/stm32_dma.c
|
||||
* @brief DMA helper driver code.
|
||||
*
|
||||
* @addtogroup STM32F1xx_DMA
|
||||
* @details DMA sharing helper driver. In the STM32 the DMA streams are a
|
||||
* shared resource, this driver allows to allocate and free DMA
|
||||
* streams at runtime in order to allow all the other device
|
||||
* drivers to coordinate the access to the resource.
|
||||
* @note The DMA ISR handlers are all declared into this module because
|
||||
* sharing, the various device drivers can associate a callback to
|
||||
* ISRs when allocating streams.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "ch.h"
|
||||
#include "hal.h"
|
||||
|
||||
/* The following macro is only defined if some driver requiring DMA services
|
||||
has been enabled.*/
|
||||
#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local definitions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Mask of the DMA1 streams in @p dma_streams_mask.
|
||||
*/
|
||||
#define STM32_DMA1_STREAMS_MASK 0x0000007F
|
||||
|
||||
/**
|
||||
* @brief Mask of the DMA2 streams in @p dma_streams_mask.
|
||||
*/
|
||||
#define STM32_DMA2_STREAMS_MASK 0x00000F80
|
||||
|
||||
/**
|
||||
* @brief Post-reset value of the stream CCR register.
|
||||
*/
|
||||
#define STM32_DMA_CCR_RESET_VALUE 0x00000000
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported variables. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief DMA streams descriptors.
|
||||
* @details This table keeps the association between an unique stream
|
||||
* identifier and the involved physical registers.
|
||||
* @note Don't use this array directly, use the appropriate wrapper macros
|
||||
* instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc.
|
||||
*/
|
||||
const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
|
||||
{DMA1_Channel1, &DMA1->IFCR, 0, 0, DMA1_Channel1_IRQn},
|
||||
{DMA1_Channel2, &DMA1->IFCR, 4, 1, DMA1_Channel2_IRQn},
|
||||
{DMA1_Channel3, &DMA1->IFCR, 8, 2, DMA1_Channel3_IRQn},
|
||||
{DMA1_Channel4, &DMA1->IFCR, 12, 3, DMA1_Channel4_IRQn},
|
||||
{DMA1_Channel5, &DMA1->IFCR, 16, 4, DMA1_Channel5_IRQn},
|
||||
{DMA1_Channel6, &DMA1->IFCR, 20, 5, DMA1_Channel6_IRQn},
|
||||
{DMA1_Channel7, &DMA1->IFCR, 24, 6, DMA1_Channel7_IRQn},
|
||||
#if STM32_HAS_DMA2 || defined(__DOXYGEN__)
|
||||
{DMA2_Channel1, &DMA2->IFCR, 0, 7, DMA2_Channel1_IRQn},
|
||||
{DMA2_Channel2, &DMA2->IFCR, 4, 8, DMA2_Channel2_IRQn},
|
||||
{DMA2_Channel3, &DMA2->IFCR, 8, 9, DMA2_Channel3_IRQn},
|
||||
#if defined(STM32F10X_CL) || defined(__DOXYGEN__)
|
||||
{DMA2_Channel4, &DMA2->IFCR, 12, 10, DMA2_Channel4_IRQn},
|
||||
{DMA2_Channel5, &DMA2->IFCR, 16, 11, DMA2_Channel5_IRQn},
|
||||
#else /* !STM32F10X_CL */
|
||||
{DMA2_Channel4, &DMA2->IFCR, 12, 10, DMA2_Channel4_5_IRQn},
|
||||
{DMA2_Channel5, &DMA2->IFCR, 16, 11, DMA2_Channel4_5_IRQn},
|
||||
#endif /* !STM32F10X_CL */
|
||||
#endif /* STM32_HAS_DMA2 */
|
||||
};
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local variables and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief DMA ISR redirector type.
|
||||
*/
|
||||
typedef struct {
|
||||
stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */
|
||||
void *dma_param; /**< @brief DMA callback parameter. */
|
||||
} dma_isr_redir_t;
|
||||
|
||||
/**
|
||||
* @brief Mask of the allocated streams.
|
||||
*/
|
||||
static uint32_t dma_streams_mask;
|
||||
|
||||
/**
|
||||
* @brief DMA IRQ redirectors.
|
||||
*/
|
||||
static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver local functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver interrupt handlers. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief DMA1 stream 1 shared interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(DMA1_Ch1_IRQHandler) {
|
||||
uint32_t flags;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
|
||||
DMA1->IFCR = flags << 0;
|
||||
if (dma_isr_redir[0].dma_func)
|
||||
dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA1 stream 2 shared interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(DMA1_Ch2_IRQHandler) {
|
||||
uint32_t flags;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
|
||||
DMA1->IFCR = flags << 4;
|
||||
if (dma_isr_redir[1].dma_func)
|
||||
dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA1 stream 3 shared interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(DMA1_Ch3_IRQHandler) {
|
||||
uint32_t flags;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;
|
||||
DMA1->IFCR = flags << 8;
|
||||
if (dma_isr_redir[2].dma_func)
|
||||
dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA1 stream 4 shared interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(DMA1_Ch4_IRQHandler) {
|
||||
uint32_t flags;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
|
||||
DMA1->IFCR = flags << 12;
|
||||
if (dma_isr_redir[3].dma_func)
|
||||
dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA1 stream 5 shared interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(DMA1_Ch5_IRQHandler) {
|
||||
uint32_t flags;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;
|
||||
DMA1->IFCR = flags << 16;
|
||||
if (dma_isr_redir[4].dma_func)
|
||||
dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA1 stream 6 shared interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(DMA1_Ch6_IRQHandler) {
|
||||
uint32_t flags;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK;
|
||||
DMA1->IFCR = flags << 20;
|
||||
if (dma_isr_redir[5].dma_func)
|
||||
dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA1 stream 7 shared interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(DMA1_Ch7_IRQHandler) {
|
||||
uint32_t flags;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK;
|
||||
DMA1->IFCR = flags << 24;
|
||||
if (dma_isr_redir[6].dma_func)
|
||||
dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
#if STM32_HAS_DMA2 || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief DMA2 stream 1 shared interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(DMA2_Ch1_IRQHandler) {
|
||||
uint32_t flags;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK;
|
||||
DMA2->IFCR = flags << 0;
|
||||
if (dma_isr_redir[7].dma_func)
|
||||
dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA2 stream 2 shared interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(DMA2_Ch2_IRQHandler) {
|
||||
uint32_t flags;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK;
|
||||
DMA2->IFCR = flags << 4;
|
||||
if (dma_isr_redir[8].dma_func)
|
||||
dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA2 stream 3 shared interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(DMA2_Ch3_IRQHandler) {
|
||||
uint32_t flags;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK;
|
||||
DMA2->IFCR = flags << 8;
|
||||
if (dma_isr_redir[9].dma_func)
|
||||
dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
#if defined(STM32F10X_CL) || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief DMA2 stream 4 shared interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(DMA2_Ch4_IRQHandler) {
|
||||
uint32_t flags;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK;
|
||||
DMA2->IFCR = flags << 12;
|
||||
if (dma_isr_redir[10].dma_func)
|
||||
dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA2 stream 5 shared interrupt handler.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(DMA2_Ch5_IRQHandler) {
|
||||
uint32_t flags;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK;
|
||||
DMA2->IFCR = flags << 16;
|
||||
if (dma_isr_redir[11].dma_func)
|
||||
dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
#else /* !STM32F10X_CL */
|
||||
/**
|
||||
* @brief DMA2 streams 4 and 5 shared interrupt handler.
|
||||
* @note This IRQ is shared between DMA2 channels 4 and 5 so it is a
|
||||
* bit less efficient because an extra check.
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(DMA2_Ch4_5_IRQHandler) {
|
||||
uint32_t flags;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
/* Check on channel 4.*/
|
||||
flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK;
|
||||
if (flags & STM32_DMA_ISR_MASK) {
|
||||
DMA2->IFCR = flags << 12;
|
||||
if (dma_isr_redir[10].dma_func)
|
||||
dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
|
||||
}
|
||||
|
||||
/* Check on channel 5.*/
|
||||
flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK;
|
||||
if (flags & STM32_DMA_ISR_MASK) {
|
||||
DMA2->IFCR = flags << 16;
|
||||
if (dma_isr_redir[11].dma_func)
|
||||
dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
|
||||
}
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
#endif /* !STM32F10X_CL */
|
||||
#endif /* STM32_HAS_DMA2 */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported functions. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief STM32 DMA helper initialization.
|
||||
*
|
||||
* @init
|
||||
*/
|
||||
void dmaInit(void) {
|
||||
int i;
|
||||
|
||||
dma_streams_mask = 0;
|
||||
for (i = 0; i < STM32_DMA_STREAMS; i++) {
|
||||
_stm32_dma_streams[i].channel->CCR = 0;
|
||||
dma_isr_redir[i].dma_func = NULL;
|
||||
}
|
||||
DMA1->IFCR = 0xFFFFFFFF;
|
||||
#if STM32_HAS_DMA2
|
||||
DMA2->IFCR = 0xFFFFFFFF;
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Allocates a DMA stream.
|
||||
* @details The stream is allocated and, if required, the DMA clock enabled.
|
||||
* The function also enables the IRQ vector associated to the stream
|
||||
* and initializes its priority.
|
||||
* @pre The stream must not be already in use or an error is returned.
|
||||
* @post The stream is allocated and the default ISR handler redirected
|
||||
* to the specified function.
|
||||
* @post The stream ISR vector is enabled and its priority configured.
|
||||
* @post The stream must be freed using @p dmaStreamRelease() before it can
|
||||
* be reused with another peripheral.
|
||||
* @post The stream is in its post-reset state.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
* @param[in] priority IRQ priority mask for the DMA stream
|
||||
* @param[in] func handling function pointer, can be @p NULL
|
||||
* @param[in] param a parameter to be passed to the handling function
|
||||
* @return The operation status.
|
||||
* @retval FALSE no error, stream taken.
|
||||
* @retval TRUE error, stream already taken.
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
|
||||
uint32_t priority,
|
||||
stm32_dmaisr_t func,
|
||||
void *param) {
|
||||
|
||||
chDbgCheck(dmastp != NULL, "dmaStreamAllocate");
|
||||
|
||||
/* Checks if the stream is already taken.*/
|
||||
if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)
|
||||
return TRUE;
|
||||
|
||||
/* Marks the stream as allocated.*/
|
||||
dma_isr_redir[dmastp->selfindex].dma_func = func;
|
||||
dma_isr_redir[dmastp->selfindex].dma_param = param;
|
||||
dma_streams_mask |= (1 << dmastp->selfindex);
|
||||
|
||||
/* Enabling DMA clocks required by the current streams set.*/
|
||||
if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0)
|
||||
rccEnableDMA1(FALSE);
|
||||
#if STM32_HAS_DMA2
|
||||
if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0)
|
||||
rccEnableDMA2(FALSE);
|
||||
#endif
|
||||
|
||||
/* Putting the stream in a safe state.*/
|
||||
dmaStreamDisable(dmastp);
|
||||
dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE;
|
||||
|
||||
/* Enables the associated IRQ vector if a callback is defined.*/
|
||||
if (func != NULL)
|
||||
nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority));
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Releases a DMA stream.
|
||||
* @details The stream is freed and, if required, the DMA clock disabled.
|
||||
* Trying to release a unallocated stream is an illegal operation
|
||||
* and is trapped if assertions are enabled.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post The stream is again available.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
|
||||
|
||||
chDbgCheck(dmastp != NULL, "dmaStreamRelease");
|
||||
|
||||
/* Check if the streams is not taken.*/
|
||||
chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
|
||||
"dmaStreamRelease(), #1", "not allocated");
|
||||
|
||||
/* Marks the stream as not allocated.*/
|
||||
dma_streams_mask &= ~(1 << dmastp->selfindex);
|
||||
|
||||
/* Disables the associated IRQ vector.*/
|
||||
#if !(STM32_HAS_DMA2 && !defined(STM32F10X_CL))
|
||||
nvicDisableVector(dmastp->vector);
|
||||
#else
|
||||
/* Check unless it is 10 or 11 stream. If yes, make additional check before
|
||||
disabling IRQ.*/
|
||||
if (dmastp->selfindex < 10)
|
||||
nvicDisableVector(dmastp->vector);
|
||||
else {
|
||||
if ((dma_streams_mask & (3 << 10)) == 0)
|
||||
nvicDisableVector(dmastp->vector);
|
||||
}
|
||||
#endif /* STM32_HAS_DMA2 && !STM32F10X_CL */
|
||||
|
||||
/* Shutting down clocks that are no more required, if any.*/
|
||||
if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0)
|
||||
rccDisableDMA1(FALSE);
|
||||
#if STM32_HAS_DMA2
|
||||
if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0)
|
||||
rccDisableDMA2(FALSE);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* STM32_DMA_REQUIRED */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,406 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file STM32F1xx/stm32_dma.h
|
||||
* @brief DMA helper driver header.
|
||||
* @note This file requires definitions from the ST header file stm32f10x.h.
|
||||
* @note This driver uses the new naming convention used for the STM32F2xx
|
||||
* so the "DMA channels" are referred as "DMA streams".
|
||||
*
|
||||
* @addtogroup STM32F1xx_DMA
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _STM32_DMA_H_
|
||||
#define _STM32_DMA_H_
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Total number of DMA streams.
|
||||
* @note This is the total number of streams among all the DMA units.
|
||||
*/
|
||||
#if STM32_HAS_DMA2 || defined(__DOXYGEN__)
|
||||
#define STM32_DMA_STREAMS 12
|
||||
#else
|
||||
#define STM32_DMA_STREAMS 7
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Mask of the ISR bits passed to the DMA callback functions.
|
||||
*/
|
||||
#define STM32_DMA_ISR_MASK 0x0F
|
||||
|
||||
/**
|
||||
* @brief Returns the channel associated to the specified stream.
|
||||
*
|
||||
* @param[in] n the stream number (0...STM32_DMA_STREAMS-1)
|
||||
* @param[in] c a stream/channel association word, one channel per
|
||||
* nibble, not associated channels must be set to 0xF
|
||||
* @return Always zero, in this platform there is no dynamic
|
||||
* association between streams and channels.
|
||||
*/
|
||||
#define STM32_DMA_GETCHANNEL(n, c) 0
|
||||
|
||||
/**
|
||||
* @brief Checks if a DMA priority is within the valid range.
|
||||
* @param[in] prio DMA priority
|
||||
*
|
||||
* @retval The check result.
|
||||
* @retval FALSE invalid DMA priority.
|
||||
* @retval TRUE correct DMA priority.
|
||||
*/
|
||||
#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3))
|
||||
|
||||
/**
|
||||
* @brief Returns an unique numeric identifier for a DMA stream.
|
||||
*
|
||||
* @param[in] dma the DMA unit number
|
||||
* @param[in] stream the stream number
|
||||
* @return An unique numeric stream identifier.
|
||||
*/
|
||||
#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 7) + ((stream) - 1))
|
||||
|
||||
/**
|
||||
* @brief Returns a DMA stream identifier mask.
|
||||
*
|
||||
*
|
||||
* @param[in] dma the DMA unit number
|
||||
* @param[in] stream the stream number
|
||||
* @return A DMA stream identifier mask.
|
||||
*/
|
||||
#define STM32_DMA_STREAM_ID_MSK(dma, stream) \
|
||||
(1 << STM32_DMA_STREAM_ID(dma, stream))
|
||||
|
||||
/**
|
||||
* @brief Checks if a DMA stream unique identifier belongs to a mask.
|
||||
* @param[in] id the stream numeric identifier
|
||||
* @param[in] mask the stream numeric identifiers mask
|
||||
*
|
||||
* @retval The check result.
|
||||
* @retval FALSE id does not belong to the mask.
|
||||
* @retval TRUE id belongs to the mask.
|
||||
*/
|
||||
#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask)))
|
||||
|
||||
/**
|
||||
* @name DMA streams identifiers
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Returns a pointer to a stm32_dma_stream_t structure.
|
||||
*
|
||||
* @param[in] id the stream numeric identifier
|
||||
* @return A pointer to the stm32_dma_stream_t constant structure
|
||||
* associated to the DMA stream.
|
||||
*/
|
||||
#define STM32_DMA_STREAM(id) (&_stm32_dma_streams[id])
|
||||
|
||||
#define STM32_DMA1_STREAM1 STM32_DMA_STREAM(0)
|
||||
#define STM32_DMA1_STREAM2 STM32_DMA_STREAM(1)
|
||||
#define STM32_DMA1_STREAM3 STM32_DMA_STREAM(2)
|
||||
#define STM32_DMA1_STREAM4 STM32_DMA_STREAM(3)
|
||||
#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(4)
|
||||
#define STM32_DMA1_STREAM6 STM32_DMA_STREAM(5)
|
||||
#define STM32_DMA1_STREAM7 STM32_DMA_STREAM(6)
|
||||
#define STM32_DMA2_STREAM1 STM32_DMA_STREAM(7)
|
||||
#define STM32_DMA2_STREAM2 STM32_DMA_STREAM(8)
|
||||
#define STM32_DMA2_STREAM3 STM32_DMA_STREAM(9)
|
||||
#define STM32_DMA2_STREAM4 STM32_DMA_STREAM(10)
|
||||
#define STM32_DMA2_STREAM5 STM32_DMA_STREAM(11)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name CR register constants common to all DMA types
|
||||
* @{
|
||||
*/
|
||||
#define STM32_DMA_CR_EN DMA_CCR1_EN
|
||||
#define STM32_DMA_CR_TEIE DMA_CCR1_TEIE
|
||||
#define STM32_DMA_CR_HTIE DMA_CCR1_HTIE
|
||||
#define STM32_DMA_CR_TCIE DMA_CCR1_TCIE
|
||||
#define STM32_DMA_CR_DIR_MASK (DMA_CCR1_DIR | DMA_CCR1_MEM2MEM)
|
||||
#define STM32_DMA_CR_DIR_P2M 0
|
||||
#define STM32_DMA_CR_DIR_M2P DMA_CCR1_DIR
|
||||
#define STM32_DMA_CR_DIR_M2M DMA_CCR1_MEM2MEM
|
||||
#define STM32_DMA_CR_CIRC DMA_CCR1_CIRC
|
||||
#define STM32_DMA_CR_PINC DMA_CCR1_PINC
|
||||
#define STM32_DMA_CR_MINC DMA_CCR1_MINC
|
||||
#define STM32_DMA_CR_PSIZE_MASK DMA_CCR1_PSIZE
|
||||
#define STM32_DMA_CR_PSIZE_BYTE 0
|
||||
#define STM32_DMA_CR_PSIZE_HWORD DMA_CCR1_PSIZE_0
|
||||
#define STM32_DMA_CR_PSIZE_WORD DMA_CCR1_PSIZE_1
|
||||
#define STM32_DMA_CR_MSIZE_MASK DMA_CCR1_MSIZE
|
||||
#define STM32_DMA_CR_MSIZE_BYTE 0
|
||||
#define STM32_DMA_CR_MSIZE_HWORD DMA_CCR1_MSIZE_0
|
||||
#define STM32_DMA_CR_MSIZE_WORD DMA_CCR1_MSIZE_1
|
||||
#define STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_PSIZE_MASK | \
|
||||
STM32_DMA_CR_MSIZE_MASK)
|
||||
#define STM32_DMA_CR_PL_MASK DMA_CCR1_PL
|
||||
#define STM32_DMA_CR_PL(n) ((n) << 12)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name CR register constants only found in enhanced DMA
|
||||
* @{
|
||||
*/
|
||||
#define STM32_DMA_CR_DMEIE 0 /**< @brief Ignored by normal DMA. */
|
||||
#define STM32_DMA_CR_CHSEL_MASK 0 /**< @brief Ignored by normal DMA. */
|
||||
#define STM32_DMA_CR_CHSEL(n) 0 /**< @brief Ignored by normal DMA. */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Status flags passed to the ISR callbacks
|
||||
* @{
|
||||
*/
|
||||
#define STM32_DMA_ISR_FEIF 0
|
||||
#define STM32_DMA_ISR_DMEIF 0
|
||||
#define STM32_DMA_ISR_TEIF DMA_ISR_TEIF1
|
||||
#define STM32_DMA_ISR_HTIF DMA_ISR_HTIF1
|
||||
#define STM32_DMA_ISR_TCIF DMA_ISR_TCIF1
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief STM32 DMA stream descriptor structure.
|
||||
*/
|
||||
typedef struct {
|
||||
DMA_Channel_TypeDef *channel; /**< @brief Associated DMA channel. */
|
||||
volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */
|
||||
uint8_t ishift; /**< @brief Bits offset in xIFCR
|
||||
register. */
|
||||
uint8_t selfindex; /**< @brief Index to self in array. */
|
||||
uint8_t vector; /**< @brief Associated IRQ vector. */
|
||||
} stm32_dma_stream_t;
|
||||
|
||||
/**
|
||||
* @brief STM32 DMA ISR function type.
|
||||
*
|
||||
* @param[in] p parameter for the registered function
|
||||
* @param[in] flags pre-shifted content of the ISR register, the bits
|
||||
* are aligned to bit zero
|
||||
*/
|
||||
typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name Macro Functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Associates a peripheral data register to a DMA stream.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
* @param[in] addr value to be written in the CPAR register
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
#define dmaStreamSetPeripheral(dmastp, addr) { \
|
||||
(dmastp)->channel->CPAR = (uint32_t)(addr); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Associates a memory destination to a DMA stream.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
* @param[in] addr value to be written in the CMAR register
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
#define dmaStreamSetMemory0(dmastp, addr) { \
|
||||
(dmastp)->channel->CMAR = (uint32_t)(addr); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the number of transfers to be performed.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
* @param[in] size value to be written in the CNDTR register
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
#define dmaStreamSetTransactionSize(dmastp, size) { \
|
||||
(dmastp)->channel->CNDTR = (uint32_t)(size); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the number of transfers to be performed.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
* @return The number of transfers to be performed.
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR))
|
||||
|
||||
/**
|
||||
* @brief Programs the stream mode settings.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
* @param[in] mode value to be written in the CCR register
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
#define dmaStreamSetMode(dmastp, mode) { \
|
||||
(dmastp)->channel->CCR = (uint32_t)(mode); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA stream enable.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
#define dmaStreamEnable(dmastp) { \
|
||||
(dmastp)->channel->CCR |= STM32_DMA_CR_EN; \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA stream disable.
|
||||
* @details The function disables the specified stream and then clears any
|
||||
* pending interrupt.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
* @note Interrupts enabling flags are set to zero after this call, see
|
||||
* bug 3607518.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
#define dmaStreamDisable(dmastp) { \
|
||||
(dmastp)->channel->CCR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \
|
||||
STM32_DMA_CR_TEIE | STM32_DMA_CR_EN); \
|
||||
dmaStreamClearInterrupt(dmastp); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DMA stream interrupt sources clear.
|
||||
* @note This function can be invoked in both ISR or thread context.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
*
|
||||
* @special
|
||||
*/
|
||||
#define dmaStreamClearInterrupt(dmastp) { \
|
||||
*(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Starts a memory to memory operation using the specified stream.
|
||||
* @note The default transfer data mode is "byte to byte" but it can be
|
||||
* changed by specifying extra options in the @p mode parameter.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
* @param[in] mode value to be written in the CCR register, this value
|
||||
* is implicitly ORed with:
|
||||
* - @p STM32_DMA_CR_MINC
|
||||
* - @p STM32_DMA_CR_PINC
|
||||
* - @p STM32_DMA_CR_DIR_M2M
|
||||
* - @p STM32_DMA_CR_EN
|
||||
* .
|
||||
* @param[in] src source address
|
||||
* @param[in] dst destination address
|
||||
* @param[in] n number of data units to copy
|
||||
*/
|
||||
#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \
|
||||
dmaStreamSetPeripheral(dmastp, src); \
|
||||
dmaStreamSetMemory0(dmastp, dst); \
|
||||
dmaStreamSetTransactionSize(dmastp, n); \
|
||||
dmaStreamSetMode(dmastp, (mode) | \
|
||||
STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \
|
||||
STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Polled wait for DMA transfer end.
|
||||
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||||
* @post After use the stream can be released using @p dmaStreamRelease().
|
||||
*
|
||||
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||||
*/
|
||||
#define dmaWaitCompletion(dmastp) { \
|
||||
while ((dmastp)->channel->CNDTR > 0) \
|
||||
; \
|
||||
dmaStreamDisable(dmastp); \
|
||||
}
|
||||
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void dmaInit(void);
|
||||
bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
|
||||
uint32_t priority,
|
||||
stm32_dmaisr_t func,
|
||||
void *param);
|
||||
void dmaStreamRelease(const stm32_dma_stream_t *dmastp);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _STM32_DMA_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,156 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file STM32F1xx/stm32_isr.h
|
||||
* @brief ISR remapper driver header.
|
||||
*
|
||||
* @addtogroup STM32F1xx_ISR
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _STM32_ISR_H_
|
||||
#define _STM32_ISR_H_
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name ISR names and numbers remapping
|
||||
* @{
|
||||
*/
|
||||
/*
|
||||
* CAN units.
|
||||
*/
|
||||
#define STM32_CAN1_TX_HANDLER Vector8C
|
||||
#define STM32_CAN1_RX0_HANDLER Vector90
|
||||
#define STM32_CAN1_RX1_HANDLER Vector94
|
||||
#define STM32_CAN1_SCE_HANDLER Vector98
|
||||
#define STM32_CAN2_TX_HANDLER Vector13C
|
||||
#define STM32_CAN2_RX0_HANDLER Vector140
|
||||
#define STM32_CAN2_RX1_HANDLER Vector144
|
||||
#define STM32_CAN2_SCE_HANDLER Vector148
|
||||
|
||||
#define STM32_CAN1_TX_NUMBER 19
|
||||
#define STM32_CAN1_RX0_NUMBER 20
|
||||
#define STM32_CAN1_RX1_NUMBER 21
|
||||
#define STM32_CAN1_SCE_NUMBER 22
|
||||
#define STM32_CAN2_TX_NUMBER 63
|
||||
#define STM32_CAN2_RX0_NUMBER 64
|
||||
#define STM32_CAN2_RX1_NUMBER 65
|
||||
#define STM32_CAN2_SCE_NUMBER 66
|
||||
|
||||
/*
|
||||
* I2C units.
|
||||
*/
|
||||
#define STM32_I2C1_EVENT_HANDLER VectorBC
|
||||
#define STM32_I2C1_ERROR_HANDLER VectorC0
|
||||
#define STM32_I2C1_EVENT_NUMBER 31
|
||||
#define STM32_I2C1_ERROR_NUMBER 32
|
||||
|
||||
#define STM32_I2C2_EVENT_HANDLER VectorC4
|
||||
#define STM32_I2C2_ERROR_HANDLER VectorC8
|
||||
#define STM32_I2C2_EVENT_NUMBER 33
|
||||
#define STM32_I2C2_ERROR_NUMBER 34
|
||||
|
||||
/*
|
||||
* OTG units.
|
||||
*/
|
||||
#define STM32_OTG1_HANDLER Vector14C
|
||||
|
||||
#define STM32_OTG1_NUMBER 67
|
||||
|
||||
/*
|
||||
* SDIO unit.
|
||||
*/
|
||||
#define STM32_SDIO_HANDLER Vector104
|
||||
|
||||
#define STM32_SDIO_NUMBER 49
|
||||
|
||||
/*
|
||||
* TIM units.
|
||||
*/
|
||||
#define STM32_TIM1_UP_HANDLER VectorA4
|
||||
#define STM32_TIM1_CC_HANDLER VectorAC
|
||||
#define STM32_TIM2_HANDLER VectorB0
|
||||
#define STM32_TIM3_HANDLER VectorB4
|
||||
#define STM32_TIM4_HANDLER VectorB8
|
||||
#define STM32_TIM5_HANDLER Vector108
|
||||
#define STM32_TIM6_HANDLER Vector118
|
||||
#define STM32_TIM7_HANDLER Vector11C
|
||||
#define STM32_TIM8_UP_HANDLER VectorF0
|
||||
#define STM32_TIM8_CC_HANDLER VectorF8
|
||||
|
||||
#define STM32_TIM1_UP_NUMBER 25
|
||||
#define STM32_TIM1_CC_NUMBER 27
|
||||
#define STM32_TIM2_NUMBER 28
|
||||
#define STM32_TIM3_NUMBER 29
|
||||
#define STM32_TIM4_NUMBER 30
|
||||
#define STM32_TIM5_NUMBER 50
|
||||
#define STM32_TIM6_NUMBER 54
|
||||
#define STM32_TIM7_NUMBER 55
|
||||
#define STM32_TIM8_UP_NUMBER 44
|
||||
#define STM32_TIM8_CC_NUMBER 46
|
||||
|
||||
/*
|
||||
* USART units.
|
||||
*/
|
||||
#define STM32_USART1_HANDLER VectorD4
|
||||
#define STM32_USART2_HANDLER VectorD8
|
||||
#define STM32_USART3_HANDLER VectorDC
|
||||
#define STM32_UART4_HANDLER Vector110
|
||||
#define STM32_UART5_HANDLER Vector114
|
||||
|
||||
#define STM32_USART1_NUMBER 37
|
||||
#define STM32_USART2_NUMBER 38
|
||||
#define STM32_USART3_NUMBER 39
|
||||
#define STM32_UART4_NUMBER 52
|
||||
#define STM32_UART5_NUMBER 53
|
||||
|
||||
/*
|
||||
* USB units.
|
||||
*/
|
||||
#define STM32_USB1_HP_HANDLER Vector8C
|
||||
#define STM32_USB1_LP_HANDLER Vector90
|
||||
|
||||
#define STM32_USB1_HP_NUMBER 19
|
||||
#define STM32_USB1_LP_NUMBER 20
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#endif /* _STM32_ISR_H_ */
|
||||
|
||||
/** @} */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,69 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
|
||||
2011,2012,2013 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS/RT.
|
||||
|
||||
ChibiOS/RT is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS/RT is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
|
||||
---
|
||||
|
||||
A special exception to the GPL can be applied should you wish to distribute
|
||||
a combined work that includes ChibiOS/RT, without being obliged to provide
|
||||
the source code for any proprietary components. See the file exception.txt
|
||||
for full details of how and when the exception can be applied.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file GCC/ARMCMx/STM32F1xx/cmparams.h
|
||||
* @brief ARM Cortex-M3 parameters for the STM32F1xx.
|
||||
*
|
||||
* @defgroup ARMCMx_STM32F1xx STM32F1xx Specific Parameters
|
||||
* @ingroup ARMCMx_SPECIFIC
|
||||
* @details This file contains the Cortex-M3 specific parameters for the
|
||||
* STM32F1xx platform.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _CMPARAMS_H_
|
||||
#define _CMPARAMS_H_
|
||||
|
||||
/**
|
||||
* @brief Cortex core model.
|
||||
*/
|
||||
#define CORTEX_MODEL CORTEX_M3
|
||||
|
||||
/**
|
||||
* @brief Systick unit presence.
|
||||
*/
|
||||
#define CORTEX_HAS_ST TRUE
|
||||
|
||||
/**
|
||||
* @brief Memory Protection unit presence.
|
||||
*/
|
||||
#define CORTEX_HAS_MPU FALSE
|
||||
|
||||
/**
|
||||
* @brief Floating Point unit presence.
|
||||
*/
|
||||
#define CORTEX_HAS_FPU FALSE
|
||||
|
||||
/**
|
||||
* @brief Number of bits in priority masks.
|
||||
*/
|
||||
#define CORTEX_PRIORITY_BITS 4
|
||||
|
||||
#endif /* _CMPARAMS_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
# List of the ChibiOS/RT Cortex-M3 STM32 port files.
|
||||
PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \
|
||||
$(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F1xx/vectors.c \
|
||||
${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \
|
||||
${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v7m.c \
|
||||
${CHIBIOS}/os/ports/common/ARMCMx/nvic.c
|
||||
|
||||
PORTASM =
|
||||
|
||||
PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \
|
||||
${CHIBIOS}/os/ports/common/ARMCMx \
|
||||
${CHIBIOS}/os/ports/GCC/ARMCMx \
|
||||
${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F1xx
|
||||
|
||||
PORTLD = ${CHIBIOS}/os/ports/GCC/ARMCMx/STM32F1xx/ld
|
||||
|
|
@ -0,0 +1,337 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
|
||||
2011,2012,2013 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS/RT.
|
||||
|
||||
ChibiOS/RT is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS/RT is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
|
||||
---
|
||||
|
||||
A special exception to the GPL can be applied should you wish to distribute
|
||||
a combined work that includes ChibiOS/RT, without being obliged to provide
|
||||
the source code for any proprietary components. See the file exception.txt
|
||||
for full details of how and when the exception can be applied.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file GCC/ARMCMx/STM32F1xx/vectors.c
|
||||
* @brief Interrupt vectors for the STM32F1xx family.
|
||||
*
|
||||
* @defgroup ARMCMx_STM32F1xx_VECTORS STM32F1xx Interrupt Vectors
|
||||
* @ingroup ARMCMx_SPECIFIC
|
||||
* @details Interrupt vectors for the STM32F1xx family.
|
||||
* One of the following macros must be defined on the
|
||||
* compiler command line or in a file named <tt>board.h</tt>:
|
||||
* - @p STM32F10X_LD
|
||||
* - @p STM32F10X_LD_VL
|
||||
* - @p STM32F10X_MD
|
||||
* - @p STM32F10X_MD_VL
|
||||
* - @p STM32F10X_HD
|
||||
* - @p STM32F10X_XL
|
||||
* - @p STM32F10X_CL
|
||||
* .
|
||||
* This is required in order to include a vectors table with
|
||||
* the correct length for the specified STM32 model.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "ch.h"
|
||||
|
||||
#if !defined(STM32F10X_LD) && !defined(STM32F10X_LD_VL) && \
|
||||
!defined(STM32F10X_MD) && !defined(STM32F10X_MD_VL) && \
|
||||
!defined(STM32F10X_HD) && !defined(STM32F10X_XL) && \
|
||||
!defined(STM32F10X_CL)
|
||||
#include "board.h"
|
||||
#endif
|
||||
|
||||
#if defined(STM32F10X_MD_VL) || defined(__DOXYGEN__)
|
||||
#define NUM_VECTORS 46
|
||||
#elif defined(STM32F10X_HD) || defined(STM32F10X_XL)
|
||||
#define NUM_VECTORS 60
|
||||
#elif defined(STM32F10X_CL)
|
||||
#define NUM_VECTORS 68
|
||||
#else
|
||||
#define NUM_VECTORS 43
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Type of an IRQ vector.
|
||||
*/
|
||||
typedef void (*irq_vector_t)(void);
|
||||
|
||||
/**
|
||||
* @brief Type of a structure representing the whole vectors table.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t *init_stack;
|
||||
irq_vector_t reset_vector;
|
||||
irq_vector_t nmi_vector;
|
||||
irq_vector_t hardfault_vector;
|
||||
irq_vector_t memmanage_vector;
|
||||
irq_vector_t busfault_vector;
|
||||
irq_vector_t usagefault_vector;
|
||||
irq_vector_t vector1c;
|
||||
irq_vector_t vector20;
|
||||
irq_vector_t vector24;
|
||||
irq_vector_t vector28;
|
||||
irq_vector_t svcall_vector;
|
||||
irq_vector_t debugmonitor_vector;
|
||||
irq_vector_t vector34;
|
||||
irq_vector_t pendsv_vector;
|
||||
irq_vector_t systick_vector;
|
||||
irq_vector_t vectors[NUM_VECTORS];
|
||||
} vectors_t;
|
||||
|
||||
#if !defined(__DOXYGEN__)
|
||||
extern uint32_t __main_stack_end__;
|
||||
extern void ResetHandler(void);
|
||||
extern void NMIVector(void);
|
||||
extern void HardFaultVector(void);
|
||||
extern void MemManageVector(void);
|
||||
extern void BusFaultVector(void);
|
||||
extern void UsageFaultVector(void);
|
||||
extern void Vector1C(void);
|
||||
extern void Vector20(void);
|
||||
extern void Vector24(void);
|
||||
extern void Vector28(void);
|
||||
extern void SVCallVector(void);
|
||||
extern void DebugMonitorVector(void);
|
||||
extern void Vector34(void);
|
||||
extern void PendSVVector(void);
|
||||
extern void SysTickVector(void);
|
||||
extern void Vector40(void);
|
||||
extern void Vector44(void);
|
||||
extern void Vector48(void);
|
||||
extern void Vector4C(void);
|
||||
extern void Vector50(void);
|
||||
extern void Vector54(void);
|
||||
extern void Vector58(void);
|
||||
extern void Vector5C(void);
|
||||
extern void Vector60(void);
|
||||
extern void Vector64(void);
|
||||
extern void Vector68(void);
|
||||
extern void Vector6C(void);
|
||||
extern void Vector70(void);
|
||||
extern void Vector74(void);
|
||||
extern void Vector78(void);
|
||||
extern void Vector7C(void);
|
||||
extern void Vector80(void);
|
||||
extern void Vector84(void);
|
||||
extern void Vector88(void);
|
||||
extern void Vector8C(void);
|
||||
extern void Vector90(void);
|
||||
extern void Vector94(void);
|
||||
extern void Vector98(void);
|
||||
extern void Vector9C(void);
|
||||
extern void VectorA0(void);
|
||||
extern void VectorA4(void);
|
||||
extern void VectorA8(void);
|
||||
extern void VectorAC(void);
|
||||
extern void VectorB0(void);
|
||||
extern void VectorB4(void);
|
||||
extern void VectorB8(void);
|
||||
extern void VectorBC(void);
|
||||
extern void VectorC0(void);
|
||||
extern void VectorC4(void);
|
||||
extern void VectorC8(void);
|
||||
extern void VectorCC(void);
|
||||
extern void VectorD0(void);
|
||||
extern void VectorD4(void);
|
||||
extern void VectorD8(void);
|
||||
extern void VectorDC(void);
|
||||
extern void VectorE0(void);
|
||||
extern void VectorE4(void);
|
||||
extern void VectorE8(void);
|
||||
#if defined(STM32F10X_MD_VL) || defined(STM32F10X_HD) || \
|
||||
defined(STM32F10X_XL) || defined(STM32F10X_CL)
|
||||
extern void VectorEC(void);
|
||||
extern void VectorF0(void);
|
||||
extern void VectorF4(void);
|
||||
#endif
|
||||
#if defined(STM32F10X_HD) || defined(STM32F10X_XL) || defined(STM32F10X_CL)
|
||||
extern void VectorF8(void);
|
||||
extern void VectorFC(void);
|
||||
extern void Vector100(void);
|
||||
extern void Vector104(void);
|
||||
extern void Vector108(void);
|
||||
extern void Vector10C(void);
|
||||
extern void Vector110(void);
|
||||
extern void Vector114(void);
|
||||
extern void Vector118(void);
|
||||
extern void Vector11C(void);
|
||||
extern void Vector120(void);
|
||||
extern void Vector124(void);
|
||||
extern void Vector128(void);
|
||||
extern void Vector12C(void);
|
||||
#endif
|
||||
#if defined(STM32F10X_CL)
|
||||
extern void Vector130(void);
|
||||
extern void Vector134(void);
|
||||
extern void Vector138(void);
|
||||
extern void Vector13C(void);
|
||||
extern void Vector140(void);
|
||||
extern void Vector144(void);
|
||||
extern void Vector148(void);
|
||||
extern void Vector14C(void);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief STM32 vectors table.
|
||||
*/
|
||||
#if !defined(__DOXYGEN__)
|
||||
__attribute__ ((section("vectors")))
|
||||
#endif
|
||||
vectors_t _vectors = {
|
||||
&__main_stack_end__,ResetHandler, NMIVector, HardFaultVector,
|
||||
MemManageVector, BusFaultVector, UsageFaultVector, Vector1C,
|
||||
Vector20, Vector24, Vector28, SVCallVector,
|
||||
DebugMonitorVector, Vector34, PendSVVector, SysTickVector,
|
||||
{
|
||||
Vector40, Vector44, Vector48, Vector4C,
|
||||
Vector50, Vector54, Vector58, Vector5C,
|
||||
Vector60, Vector64, Vector68, Vector6C,
|
||||
Vector70, Vector74, Vector78, Vector7C,
|
||||
Vector80, Vector84, Vector88, Vector8C,
|
||||
Vector90, Vector94, Vector98, Vector9C,
|
||||
VectorA0, VectorA4, VectorA8, VectorAC,
|
||||
VectorB0, VectorB4, VectorB8, VectorBC,
|
||||
VectorC0, VectorC4, VectorC8, VectorCC,
|
||||
VectorD0, VectorD4, VectorD8, VectorDC,
|
||||
VectorE0, VectorE4, VectorE8,
|
||||
#if defined(STM32F10X_MD_VL) || defined(STM32F10X_HD) || \
|
||||
defined(STM32F10X_XL) || defined(STM32F10X_CL)
|
||||
VectorEC, VectorF0, VectorF4,
|
||||
#endif
|
||||
#if defined(STM32F10X_HD) || defined(STM32F10X_XL) || defined(STM32F10X_CL)
|
||||
VectorF8, VectorFC, Vector100, Vector104,
|
||||
Vector108, Vector10C, Vector110, Vector114,
|
||||
Vector118, Vector11C, Vector120, Vector124,
|
||||
Vector128, Vector12C,
|
||||
#endif
|
||||
#if defined(STM32F10X_CL)
|
||||
Vector130, Vector134, Vector138, Vector13C,
|
||||
Vector140, Vector144, Vector148, Vector14C
|
||||
#endif
|
||||
}
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Unhandled exceptions handler.
|
||||
* @details Any undefined exception vector points to this function by default.
|
||||
* This function simply stops the system into an infinite loop.
|
||||
*
|
||||
* @notapi
|
||||
*/
|
||||
#if !defined(__DOXYGEN__)
|
||||
__attribute__ ((naked))
|
||||
#endif
|
||||
void _unhandled_exception(void) {
|
||||
|
||||
while (TRUE)
|
||||
;
|
||||
}
|
||||
|
||||
void NMIVector(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void MemManageVector(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void BusFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void UsageFaultVector(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector1C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector20(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector24(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector28(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void DebugMonitorVector(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector34(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector40(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector44(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector48(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector4C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector50(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector54(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector58(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector5C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector60(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector64(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector68(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector6C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector70(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector74(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector78(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector7C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector80(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector84(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector88(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector8C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector90(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector94(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector98(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector9C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void VectorA0(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void VectorA4(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void VectorA8(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void VectorAC(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void VectorB0(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void VectorB4(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void VectorB8(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void VectorBC(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void VectorC0(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void VectorC4(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void VectorC8(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void VectorCC(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void VectorD0(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void VectorD4(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void VectorD8(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void VectorDC(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void VectorE0(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void VectorE4(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void VectorE8(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
#if defined(STM32F10X_MD_VL) || defined(STM32F10X_HD) || \
|
||||
defined(STM32F10X_XL) || defined(STM32F10X_CL)
|
||||
void VectorEC(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void VectorF0(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void VectorF4(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
#endif
|
||||
#if defined(STM32F10X_HD) || defined(STM32F10X_XL) || defined(STM32F10X_CL)
|
||||
void VectorF8(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void VectorFC(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector100(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector104(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector108(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector10C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector110(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector114(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector118(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector11C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector120(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector124(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector128(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector12C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
#endif
|
||||
#if defined(STM32F10X_CL)
|
||||
void Vector130(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector134(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector138(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector13C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector140(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector144(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector148(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
void Vector14C(void) __attribute__((weak, alias("_unhandled_exception")));
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
Loading…
Reference in New Issue