Chibios-Contrib for stm32 (#2903)
* Add Chibios-Contrib for STM32F/H too * ports: stm32: add community hal and cmu configs for STM32 * ports: stm32: community: disable CRC driver
This commit is contained in:
Andrey G
GitHub
parent
3574de1da3
commit
ca4caf1df8
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@ -151,7 +151,7 @@ include $(CHIBIOS)/os/license/license.mk
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include $(CPU_STARTUP_DIR)
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# HAL-OSAL files (optional).
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include $(CHIBIOS_CONTRIB)/os/hal/hal.mk
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include $(CPU_PLATFORM_DIR)
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include $(CPU_PLATFORM)
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include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk
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# RTOS files (optional).
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include $(CHIBIOS)/os/rt/rt.mk
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@ -0,0 +1,157 @@
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/*
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ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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#ifndef _HALCONF_COMMUNITY_H_
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#define _HALCONF_COMMUNITY_H_
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/**
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* @brief Enables the community overlay.
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*/
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#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__)
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#define HAL_USE_COMMUNITY TRUE
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#endif
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/**
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* @brief Enables the FSMC subsystem.
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*/
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#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__)
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#define HAL_USE_FSMC FALSE
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#endif
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/**
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* @brief Enables the NAND subsystem.
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*/
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#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__)
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#define HAL_USE_NAND FALSE
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#endif
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/**
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* @brief Enables the 1-wire subsystem.
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*/
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#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__)
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#define HAL_USE_ONEWIRE FALSE
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#endif
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/**
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* @brief Enables the EICU subsystem.
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*/
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#if !defined(HAL_USE_EICU) || defined(__DOXYGEN__)
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#define HAL_USE_EICU FALSE
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#endif
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/**
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* @brief Enables the CRC subsystem.
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*/
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#if !defined(HAL_USE_CRC) || defined(__DOXYGEN__)
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#define HAL_USE_CRC FALSE
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#endif
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/**
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* @brief Enables the USBH subsystem.
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*/
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#if !defined(HAL_USE_USBH) || defined(__DOXYGEN__)
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#define HAL_USE_USBH FALSE
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#endif
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/**
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* @brief Enables the EEPROM subsystem.
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*/
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#if !defined(HAL_USE_EEPROM) || defined(__DOXYGEN__)
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#define HAL_USE_EEPROM FALSE
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#endif
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/**
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* @brief Enables the TIMCAP subsystem.
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*/
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#if !defined(HAL_USE_TIMCAP) || defined(__DOXYGEN__)
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#define HAL_USE_TIMCAP FALSE
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#endif
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/**
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* @brief Enables the RNG subsystem.
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*/
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#if !defined(HAL_USE_RNG) || defined(__DOXYGEN__)
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#define HAL_USE_RNG FALSE
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#endif
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/**
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* @brief Enables the USB_MSD subsystem.
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*/
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#if !defined(HAL_USE_USB_MSD) || defined(__DOXYGEN__)
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#define HAL_USE_USB_MSD TRUE
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#endif
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/*===========================================================================*/
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/* FSMCNAND driver related settings. */
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/*===========================================================================*/
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/**
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* @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs.
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* @note Disabling this option saves both code and data space.
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*/
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#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
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#define NAND_USE_MUTUAL_EXCLUSION TRUE
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#endif
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/*===========================================================================*/
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/* 1-wire driver related settings. */
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/*===========================================================================*/
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/**
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* @brief Enables strong pull up feature.
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* @note Disabling this option saves both code and data space.
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*/
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#define ONEWIRE_USE_STRONG_PULLUP FALSE
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/**
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* @brief Enables search ROM feature.
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* @note Disabling this option saves both code and data space.
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*/
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#define ONEWIRE_USE_SEARCH_ROM FALSE
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/*===========================================================================*/
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/* EEProm driver related settings. */
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/*===========================================================================*/
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#define EEPROM_USE_EE24XX FALSE
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#define EEPROM_USE_EE25XX TRUE
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/*===========================================================================*/
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/* CRC driver settings. */
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/*===========================================================================*/
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/**
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* @brief Enables DMA engine when performing CRC transactions.
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* @note Enabling this option also enables asynchronous API.
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*/
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#if !defined(CRC_USE_DMA) || defined(__DOXYGEN__)
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#define CRC_USE_DMA FALSE
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#endif
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/**
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* @brief Enables the @p crcAcquireUnit() and @p crcReleaseUnit() APIs.
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* @note Disabling this option saves both code and data space.
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*/
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#if !defined(CRC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
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#define CRC_USE_MUTUAL_EXCLUSION TRUE
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#endif
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#endif /* _HALCONF_COMMUNITY_H_ */
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/** @} */
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@ -0,0 +1,157 @@
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/*
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ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/*
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* FSMC driver system settings.
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*/
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#define STM32_FSMC_USE_FSMC1 FALSE
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#define STM32_FSMC_FSMC1_IRQ_PRIORITY 10
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/*
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* FSMC NAND driver system settings.
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*/
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#define STM32_NAND_USE_NAND1 FALSE
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#define STM32_NAND_USE_NAND2 FALSE
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#define STM32_NAND_USE_EXT_INT FALSE
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#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#define STM32_NAND_DMA_PRIORITY 0
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#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure")
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/*
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* FSMC SRAM driver system settings.
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*/
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#define STM32_USE_FSMC_SRAM FALSE
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#define STM32_SRAM_USE_FSMC_SRAM1 FALSE
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#define STM32_SRAM_USE_FSMC_SRAM2 FALSE
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#define STM32_SRAM_USE_FSMC_SRAM3 FALSE
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#define STM32_SRAM_USE_FSMC_SRAM4 FALSE
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/*
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* FSMC SDRAM driver system settings.
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*/
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#define STM32_USE_FSMC_SDRAM FALSE
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#define STM32_SDRAM_USE_FSMC_SDRAM1 FALSE
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#define STM32_SDRAM_USE_FSMC_SDRAM2 FASLE
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/*
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* TIMCAP driver system settings.
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*/
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#define STM32_TIMCAP_USE_TIM1 FASLE
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#define STM32_TIMCAP_USE_TIM2 FALSE
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#define STM32_TIMCAP_USE_TIM3 FASLE
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#define STM32_TIMCAP_USE_TIM4 FASLE
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#define STM32_TIMCAP_USE_TIM5 FASLE
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#define STM32_TIMCAP_USE_TIM8 FASLE
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#define STM32_TIMCAP_USE_TIM9 FASLE
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#define STM32_TIMCAP_TIM1_IRQ_PRIORITY 3
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#define STM32_TIMCAP_TIM2_IRQ_PRIORITY 3
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#define STM32_TIMCAP_TIM3_IRQ_PRIORITY 3
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#define STM32_TIMCAP_TIM4_IRQ_PRIORITY 3
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#define STM32_TIMCAP_TIM5_IRQ_PRIORITY 3
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#define STM32_TIMCAP_TIM8_IRQ_PRIORITY 3
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#define STM32_TIMCAP_TIM9_IRQ_PRIORITY 3
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/*
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* COMP driver system settings.
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*/
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#define STM32_COMP_USE_COMP1 FASLE
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#define STM32_COMP_USE_COMP2 FASLE
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#define STM32_COMP_USE_COMP3 FASLE
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#define STM32_COMP_USE_COMP4 FASLE
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#define STM32_COMP_USE_COMP5 FASLE
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#define STM32_COMP_USE_COMP6 FASLE
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#define STM32_COMP_USE_COMP7 FASLE
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#define STM32_COMP_USE_INTERRUPTS TRUE
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#define STM32_COMP_1_2_3_IRQ_PRIORITY 5
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#define STM32_COMP_4_5_6_IRQ_PRIORITY 5
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#define STM32_COMP_7_IRQ_PRIORITY 5
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#if STM32_COMP_USE_INTERRUPTS
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#define STM32_DISABLE_EXTI21_22_29_HANDLER
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#define STM32_DISABLE_EXTI30_32_HANDLER
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#define STM32_DISABLE_EXTI33_HANDLER
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#endif
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/*
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* USBH driver system settings.
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*/
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#define STM32_OTG_FS_CHANNELS_NUMBER 8
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#define STM32_OTG_HS_CHANNELS_NUMBER 12
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#define STM32_USBH_USE_OTG1 1
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#define STM32_OTG_FS_RXFIFO_SIZE 1024
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#define STM32_OTG_FS_PTXFIFO_SIZE 128
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#define STM32_OTG_FS_NPTXFIFO_SIZE 128
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#define STM32_USBH_USE_OTG2 0
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#define STM32_OTG_HS_RXFIFO_SIZE 2048
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#define STM32_OTG_HS_PTXFIFO_SIZE 1024
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#define STM32_OTG_HS_NPTXFIFO_SIZE 1024
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#define STM32_USBH_MIN_QSPACE 4
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#define STM32_USBH_CHANNELS_NP 4
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/*
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* CRC driver system settings.
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*/
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#define STM32_CRC_USE_CRC1 FALSE
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#define STM32_CRC_CRC1_DMA_IRQ_PRIORITY 1
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#define STM32_CRC_CRC1_DMA_PRIORITY 2
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#define STM32_CRC_CRC1_DMA_STREAM STM32_DMA1_STREAM2
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#define CRCSW_USE_CRC1 FALSE
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#define CRCSW_CRC32_TABLE TRUE
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#define CRCSW_CRC16_TABLE TRUE
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#define CRCSW_PROGRAMMABLE TRUE
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/*
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* EICU driver system settings.
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*/
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#define STM32_EICU_USE_TIM1 FALSE
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#define STM32_EICU_USE_TIM2 FALSE
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#define STM32_EICU_USE_TIM3 FASLE
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#define STM32_EICU_USE_TIM4 FALSE
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#define STM32_EICU_USE_TIM5 FALSE
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#define STM32_EICU_USE_TIM8 FALSE
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#define STM32_EICU_USE_TIM9 FALSE
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#define STM32_EICU_USE_TIM10 FALSE
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#define STM32_EICU_USE_TIM11 FALSE
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#define STM32_EICU_USE_TIM12 FALSE
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#define STM32_EICU_USE_TIM13 FALSE
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#define STM32_EICU_USE_TIM14 FALSE
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#define STM32_EICU_TIM1_IRQ_PRIORITY 7
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#define STM32_EICU_TIM2_IRQ_PRIORITY 7
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#define STM32_EICU_TIM3_IRQ_PRIORITY 7
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#define STM32_EICU_TIM4_IRQ_PRIORITY 7
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#define STM32_EICU_TIM5_IRQ_PRIORITY 7
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#define STM32_EICU_TIM8_IRQ_PRIORITY 7
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#define STM32_EICU_TIM9_IRQ_PRIORITY 7
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#define STM32_EICU_TIM10_IRQ_PRIORITY 7
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#define STM32_EICU_TIM11_IRQ_PRIORITY 7
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#define STM32_EICU_TIM12_IRQ_PRIORITY 7
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#define STM32_EICU_TIM13_IRQ_PRIORITY 7
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#define STM32_EICU_TIM14_IRQ_PRIORITY 7
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/*
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* QEI driver system settings.
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*/
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#define STM32_QEI_USE_TIM1 FASLE
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#define STM32_QEI_USE_TIM2 FALSE
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#define STM32_QEI_USE_TIM3 FASLE
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#define STM32_QEI_TIM1_IRQ_PRIORITY 3
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#define STM32_QEI_TIM2_IRQ_PRIORITY 3
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#define STM32_QEI_TIM3_IRQ_PRIORITY 3
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@ -204,6 +204,9 @@
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#define UART_USE_MUTUAL_EXCLUSION FALSE
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#endif
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/* common for all STM32 */
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#include "../../cfg/halconf_community.h"
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#endif /* HALCONF_H */
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/** @} */
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@ -110,4 +110,7 @@
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#include "mcuconf_common_f4_f7.h"
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/* common for all STM32 */
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#include "../../cfg/mcuconf_community.h"
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#endif /* _MCUCONF_H_ */
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@ -215,6 +215,9 @@
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#define UART_USE_MUTUAL_EXCLUSION FALSE
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#endif
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/* common for all STM32 */
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#include "../../cfg/halconf_community.h"
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#endif /* HALCONF_H */
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/** @} */
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@ -159,4 +159,7 @@
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#include "mcuconf_common_f4_f7.h"
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/* common for all STM32 */
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#include "../../cfg/mcuconf_community.h"
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#endif /* MCUCONF_H */
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@ -294,6 +294,9 @@
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#define UART_USE_MUTUAL_EXCLUSION FALSE
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#endif
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/* common for all STM32 */
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#include "../../cfg/halconf_community.h"
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#endif /* HALCONF_H */
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/** @} */
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@ -485,4 +485,7 @@
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#define STM32_SYSCLK STM32_SYS_CK
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/* common for all STM32 */
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#include "../../cfg/mcuconf_community.h"
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#endif /* MCUCONF_H */
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@ -20,38 +20,39 @@ endif
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# CPU-dependent defs
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ifeq ($(PROJECT_CPU),ARCH_STM32F7)
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CPU_STARTUP = startup_stm32f7xx.mk
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CPU_PLATFORM = STM32F7xx/platform.mk
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# next file is included through Contrib's platform.ml
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#CPU_PLATFORM = $(CHIBIOS)/os/hal/ports/STM32/STM32F7xx/platform.mk
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CPU_PLATFORM = ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/STM32F7xx/platform.mk
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CPU_HWLAYER = ports/stm32/stm32f7
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else ifeq ($(PROJECT_CPU),ARCH_STM32F4)
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CPU_STARTUP = startup_stm32f4xx.mk
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CPU_PLATFORM = STM32F4xx/platform.mk
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# next file is included through Contrib's platform.ml
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#CPU_PLATFORM = $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/platform.mk
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CPU_PLATFORM = ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/STM32F4xx/platform.mk
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CPU_HWLAYER = ports/stm32/stm32f4
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else ifeq ($(PROJECT_CPU),ARCH_STM32H7)
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CPU_STARTUP = startup_stm32h7xx.mk
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CPU_PLATFORM = STM32H7xx/platform.mk
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# next file is included through Contrib's platform.ml
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#CPU_PLATFORM = $(CHIBIOS)/os/hal/ports/STM32/STM32H7xx/platform.mk
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CPU_PLATFORM = ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/STM32H7xx/platform.mk
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CPU_HWLAYER = ports/stm32/stm32h7
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else ifeq ($(PROJECT_CPU),kinetis)
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CPU_STARTUP_DIR = $(KINETIS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_ke1xf.mk
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CPU_PLATFORM_DIR = $(KINETIS_CONTRIB)/os/hal/ports/KINETIS/KE1xF/platform.mk
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CPU_PLATFORM = $(KINETIS_CONTRIB)/os/hal/ports/KINETIS/KE1xF/platform.mk
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CPU_HWLAYER = ports/kinetis
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else ifeq ($(PROJECT_CPU),cypress)
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CPU_STARTUP_DIR = $(CYPRESS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_S6E2CxAH.mk
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CPU_PLATFORM_DIR = $(CYPRESS_CONTRIB)/os/hal/ports/Cypress/S6E2CxAH/platform.mk
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CPU_PLATFORM = $(CYPRESS_CONTRIB)/os/hal/ports/Cypress/S6E2CxAH/platform.mk
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CPU_HWLAYER = ports/cypress
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else ifeq ($(PROJECT_CPU),simulator)
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else
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$(error Unexpected PROJECT_CPU)
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endif
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ifeq ($(CPU_STARTUP_DIR),)
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CPU_STARTUP_DIR = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/$(CPU_STARTUP)
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endif
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ifeq ($(CPU_PLATFORM_DIR),)
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CPU_PLATFORM_DIR = $(CHIBIOS)/os/hal/ports/STM32/$(CPU_PLATFORM)
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endif
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ifeq ($(GENERATED_ENUMS_DIR),)
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GENERATED_ENUMS_DIR = $(PROJECT_DIR)/controllers/algo
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endif
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