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wideband
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faster f1 clocks (#172) 

* faster f1 clocks

* PWM happy
This commit is contained in:
Matthew Kennedy 2022-12-03 17:23:02 -08:00 committed by GitHub
parent e015576e71
commit 85365bcb68
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GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 10 additions and 10 deletions
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3
firmware/auxout.cpp
View File

@ -16,8 +16,9 @@
// Rev2 low pass filter cut frequency is about 21Hz (sic!) // Rev2 low pass filter cut frequency is about 21Hz (sic!)
// 48Mhz / (2 ^ 12) ~= 12 KHz // 48Mhz / (2 ^ 12) ~= 12 KHz
// 64mhz / (2 ^ 12) ~= 16 KHz
static const PWMConfig auxPwmConfig = { static const PWMConfig auxPwmConfig = {
48'000'000, STM32_SYSCLK,
1 << 12, 1 << 12,
nullptr, nullptr,
{ {

7
firmware/boards/f1_dual/mcuconf.h
View File

@ -35,8 +35,7 @@
/* /*
* HAL driver system settings. * HAL driver system settings.
* TL,DR: we run at 48MHz. * Main clock runs at 64MHz, impossible to run maximum rated 72 using HSI due to PLL limitations
* It's not possible to run at 72 on HSI because of the PLL's limited configuration options, so 48MHz right now.
*/ */
#define STM32_NO_INIT FALSE #define STM32_NO_INIT FALSE
#define STM32_HSI_ENABLED TRUE #define STM32_HSI_ENABLED TRUE
@ -46,11 +45,11 @@
#define STM32_SW STM32_SW_PLL #define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSI #define STM32_PLLSRC STM32_PLLSRC_HSI
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 #define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
#define STM32_PLLMUL_VALUE 12 #define STM32_PLLMUL_VALUE 16
#define STM32_HPRE STM32_HPRE_DIV1 #define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV2 #define STM32_PPRE1 STM32_PPRE1_DIV2
#define STM32_PPRE2 STM32_PPRE2_DIV1 #define STM32_PPRE2 STM32_PPRE2_DIV1
#define STM32_ADCPRE STM32_ADCPRE_DIV4 #define STM32_ADCPRE STM32_ADCPRE_DIV6
#define STM32_USB_CLOCK_REQUIRED TRUE #define STM32_USB_CLOCK_REQUIRED TRUE
#define STM32_USBPRE STM32_USBPRE_DIV1 #define STM32_USBPRE STM32_USBPRE_DIV1
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK

7
firmware/boards/f1_rev3/mcuconf.h
View File

@ -35,8 +35,7 @@
/* /*
* HAL driver system settings. * HAL driver system settings.
* TL,DR: we run at 48MHz. * Main clock runs at 64MHz, impossible to run maximum rated 72 using HSI due to PLL limitations
* It's not possible to run at 72 on HSI because of the PLL's limited configuration options, so 48MHz right now.
*/ */
#define STM32_NO_INIT FALSE #define STM32_NO_INIT FALSE
#define STM32_HSI_ENABLED TRUE #define STM32_HSI_ENABLED TRUE
@ -46,11 +45,11 @@
#define STM32_SW STM32_SW_PLL #define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSI #define STM32_PLLSRC STM32_PLLSRC_HSI
#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 #define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
#define STM32_PLLMUL_VALUE 12 #define STM32_PLLMUL_VALUE 16
#define STM32_HPRE STM32_HPRE_DIV1 #define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV2 #define STM32_PPRE1 STM32_PPRE1_DIV2
#define STM32_PPRE2 STM32_PPRE2_DIV1 #define STM32_PPRE2 STM32_PPRE2_DIV1
#define STM32_ADCPRE STM32_ADCPRE_DIV4 #define STM32_ADCPRE STM32_ADCPRE_DIV6
#define STM32_USB_CLOCK_REQUIRED TRUE #define STM32_USB_CLOCK_REQUIRED TRUE
#define STM32_USBPRE STM32_USBPRE_DIV1 #define STM32_USBPRE STM32_USBPRE_DIV1
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK

3
firmware/pump_dac.cpp
View File

@ -7,8 +7,9 @@
#include "hal.h" #include "hal.h"
// 48MHz / 1024 = 46.8khz PWM // 48MHz / 1024 = 46.8khz PWM
// 64MHz / 1024 = 62.5khz PWM
static const PWMConfig pumpDacConfig = { static const PWMConfig pumpDacConfig = {
48'000'000, STM32_SYSCLK,
1024, 1024,
nullptr, nullptr,
{ {