Commit Graph

5 Commits

Author SHA1 Message Date
rusefillc 2fa9549d83
0701 rev2 2 (#91)
* Rev 2: VM_RESISTOR_VALUE

(cherry picked from commit 84ae91fc67cf6764afd5b00210edbc3cfe4444a5)

* Rev 2: default settings for LSU4.9

(cherry picked from commit 5a1fe84bc1ec8d7ee6e0a5f2906a1b18d2ff8a8e)

* Per-board VM_RESISTOR_VALUE

(cherry picked from commit 0bdd19e058db579bed13488066df1176ea9addb2)

* Rev2: ID correct pins

(cherry picked from commit 59e4b36ad9bc7c166c3dae7e25b6317caf562056)

* Rev2: LSU 4.2 and ADV ESR drive pins

(cherry picked from commit 2f2b4399431136951fe2fa6819f44ba28c3cda17)

* Rev2: aux pwm pins: no need to be 50MHz fast

(cherry picked from commit b0af5c07c391438ca561118174df498207255f3b)

Co-authored-by: Andrey Gusakov <dron0gus@gmail.com>
2022-07-01 15:57:05 -07:00
rusefillc 076406e4b0
f1_rev2: add OpenBLT (#92)
(cherry picked from commit 85e1ac8e5e75e22b247db0f5a512656453425729)

Co-authored-by: Andrey Gusakov <dron0gus@gmail.com>
2022-07-01 12:12:24 -07:00
Andrey G d3d260b828
f1_rev2: set O0 optimization level due to issue with ADC on GD32 (#94) 2022-07-01 12:10:28 -07:00
Andrey G 5ec79b52a5
f1_rev2: this is single channel board (#93) 2022-07-01 12:03:48 -07:00
rusefillc 7d8eaab3d1
Min rev2 (#90)
* Board Rev 2

(cherry picked from commit 2f1e2bd3e27fdfd43f0ccf8292aacfb1194060fc)

* CI good

(cherry picked from commit 2163af402ebc40f76fa53ac8f1648949b12aa50f)

* min r2

* min r2

Co-authored-by: Andrey Gusakov <dron0gus@gmail.com>
Co-authored-by: rusefillc <sdfsdfqsf2334234234>
2022-07-01 01:17:04 -07:00