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srsLTE
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6,208 Commits 3 Branches 23 Tags 67 MiB
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105 Commits

Author SHA1 Message Date
Francisco Paisana 8b174ce2f4 changed interval interface to disallow interval::stop < interval::start via an assertion 2020-08-14 15:06:06 +01:00
Francisco Paisana c1755727d7 changed interval method names, and added comments and assertions 2020-08-14 15:06:06 +01:00
Francisco Paisana 20b69fb22e substitution of ul_alloc_t for prb_interval 2020-08-14 15:06:06 +01:00
Francisco Paisana fe8f8be62d apply separate cqi configurations to scells 2020-07-09 18:56:01 +02:00
Francisco Paisana 504e3a1b7a fix max retx configuration in scheduler and updated tester to catch the error 2020-07-03 17:34:37 +01:00
Francisco Paisana cb7f620254 created separate class to manage bearers buffers/status reports in the scheduler 2020-06-29 17:31:07 +01:00
Francisco Paisana 2f421d3e30 added cqi configuration in ca testing 2020-06-10 22:22:41 +01:00
Francisco Paisana 53b85691b5 moved sf result to sched class. This way each carrier has a view to the results of the remaining carriers in the same subframe 2020-06-10 22:22:41 +01:00
Francisco Paisana 5d33acdb53 changed name of sched_ue_carrier class 2020-06-10 22:22:41 +01:00
Francisco Paisana 7713df2cf9 fix fixed mcs issue 2020-05-15 14:29:17 +01:00
Francisco Paisana 94b8dd39a9 cleanup of sched testing cfg generation 2020-05-05 14:35:40 +01:00
Francisco Paisana d5f1581759 remove old tti counter class 2020-05-05 14:35:40 +01:00
Francisco Paisana 3c29bce014 apply segmentation break check to newtxs only. Allow configurable cqi 2020-05-05 14:35:40 +01:00
Francisco Paisana c75e31db03 added random cqi to sched tester 2020-05-05 14:35:40 +01:00
Francisco Paisana d40b4040b0 scell activation as part of the single ue tester 2020-05-05 14:35:40 +01:00
Francisco Paisana 0db2bd1cb5 moved test_ra to ue test class 2020-05-05 14:35:40 +01:00
Francisco Paisana 5d41fd0aec renamed ue test structs 2020-05-05 14:35:40 +01:00
Francisco Paisana 1e56082214 use ul/dl harq info storing at the ue side to evalue info stored in the dl/ul sched result dcis 2020-05-05 14:35:40 +01:00
Francisco Paisana 500a7f6357 created new separate ue class in sched tester to handle acks and harq tests 2020-05-05 14:35:40 +01:00
Francisco Paisana b506e29b72 removed common ce_typeenum 2020-04-24 11:55:53 +01:00
Francisco Paisana 372126deac created ul-sch and mch lcid types 2020-04-24 11:55:53 +01:00
Francisco Paisana 367a190829 created dl-sch lcid type 2020-04-24 11:55:53 +01:00
Francisco Paisana 64557740fc use mac_buffer_state interface to schedule CEs in scheduler 2020-04-22 11:34:08 +01:00
Francisco Paisana ec94819f08 changed mechanism for conres ce scheduling to be controlled by rrc 2020-04-22 11:34:08 +01:00
Francisco Paisana 66a38f53f5 fix req_bytes methods to account for new method to calculate conres scheduling. 2020-04-22 11:34:08 +01:00
Francisco Paisana d716d8bf7e use mini state machine for ConRes CE scheduling instead of relying that there is data in the DL buffer 2020-04-22 11:34:08 +01:00
Francisco Paisana 6ddedd5972 moved pdu to common mac folder 2020-04-22 10:06:08 +01:00
Francisco Paisana 179e959d05 fix msg3 retx issue. Now nof_prb for pucch above 1 are forbidden for prb==6 2020-04-01 15:02:21 +01:00
Francisco Paisana 34bc48d31a fix cfi to cc assignment 2020-03-18 19:55:39 +00:00
Francisco Paisana ede09cb9b2 added dynamic CFI capability to the eNB scheduler 2020-03-17 22:06:37 +00:00
Xavier Arteaga e832769ae6 Updated copyright 2020-03-16 11:26:06 +01:00
Francisco Paisana afd7ea9e83 Fixed the check for msg3 delay to account for retxs 2020-03-13 19:57:48 +00:00
Francisco Paisana 5330249625 created tti_point type and unit test. Added also the tti_point to the scheduler harqs, and rrc procedure 2020-03-13 19:20:40 +00:00
Francisco Paisana 4217dba7e0 fix msg3 delayed allocation and update test 2020-03-13 08:30:42 +01:00
Francisco Paisana 7548402632 change scell activation interface to use arrays. Added a method to the scheduler to get the current set of activated carriers 2020-03-11 21:56:33 +01:00
Xavier Arteaga 76408b195e Rename TX_DELAY and FDD_HARQ_DELAY_MS 2020-03-11 21:16:36 +01:00
Francisco Paisana 9ad80ee29f added initial_dl_cqi to the enb rr.cfg parser 2020-03-10 22:06:07 +00:00
Francisco Paisana bcbb08ebae use initial_dl_cqi for first DL tx. 2020-03-10 22:06:07 +00:00
Francisco Paisana ab69c6fe43 account for delays in RAR tx in scheduler CA tester 2020-03-10 22:06:07 +00:00
Francisco Paisana f3c3c52fcd added ue_cc_idx to dci allocation 2020-03-10 14:17:49 +01:00
Francisco Paisana e62972d38e fix fdd delays in scheduler 2020-03-10 14:17:49 +01:00
Francisco Paisana ec1f1cc677 remove const_casts from scheduler. Fix ODR issue 2020-03-05 20:23:07 +00:00
Francisco Paisana e9a599857a created a header for all common structs and helper functions 2020-03-05 20:23:07 +00:00
Francisco Paisana 02ccb8b32b fix wrong calculation of sched tx and rx delays 2020-03-05 20:23:07 +00:00
Francisco Paisana 43e67b8536 created a harq entity that handles all harq procs. This entity accepts as arg the number of harq procs. 2020-03-05 17:51:33 +00:00
Francisco Paisana d1356568e0 separated sf sched result from sf_sched class. The interface became way simpler. No need for finish_tti() method, sf_sched::new_tti() is called automatically when we access the sf_sched. 2020-03-05 00:04:21 +00:00
Francisco Paisana bb38fa7119 fixed tti resetting after tti end 2020-03-05 00:04:21 +00:00
Francisco Paisana 47b05118ad simplified msg3 allocation. Now we can allocate resources ahead of time (e.g. msg3 is 2 ttis ahead) using the sf_sched interface. It's guaranteed that the given allocations wont be erased when the respective tti starts 2020-03-05 00:04:21 +00:00
Francisco Paisana 8f7890c60a store mask results in separate variables for testing, and reset sf_sched state at the end of the tti 2020-03-05 00:04:21 +00:00
Francisco Paisana b37d9b9930 fixed msg4 setting in sched tester 2020-03-03 21:26:17 +00:00