This is the beginning of the process to enable full floor planning
capabilities in `halo2`. For now, all that a floor planner can do is
synthesize a circuit, which makes it no more powerful than a layouter,
but easier to use (as moving to a multi-pass layouter no longer requires
changes to `Circuit::synthesize`).
These were all early examples that used the Circuit trait without any
layouter, which is incompatible with upcoming changes.
The minimal change to the PinnedVerificationKey is because the lookup
table is being allocated at the top of its columns instead of in-place.
This is more useful for developers, as the absolute cell row may be
obfuscated by the layouter, whereas the offset within a row is controlled
by the developer.
Current layouters measure the shape of regions by looking at the cells
they assign. If a chip developer forgets to assign a cell in a region,
it is possible for active gates to "stick out" past the edge of a
measured region shape.
`MockProver` checks that all active gates have their cells assigned,
but this was previously checked globally. If a layouter happened to
position the buggy region such that the dangling gate overlapped an
assigned cell in in adjacent region, this check would pass.
In this commit, we extend the check to be per-region. We map enabled
selectors and assigned cells to a specific region, and then if a gate
is active within a region, we require that its cells be assigned within
that same region.
Closeszcash/halo2#297.
The regions are now rendered uniformly the same colour, by removing the
background bleed-through (which was more complex now that the fixed
columns are rendered in two colours).
This layouter improves on the single-pass strategy in two ways:
- Regions are layed out with a "first fit" strategy (using the algorithm
described in https://github.com/zcash/halo2/issues/93) instead of a
"last fit" strategy. This enables gaps in the circuit to be filled.
- Regions are sorted by their "advice area" (columns * rows), and are
then layed out biggest-first. This takes advantage of the regularity
of circuits, and that the advice columns have the most contention. It
also leads to larger gaps between early layed-out regions that are more
easily filled by subsequent smaller regions.
The V1 layouter is a dual-pass layouter, that has visibility into the
entire `Circuit::synthesize` step.
This first commit implements the same strategy as `SingleChipLayouter`,
behaving as if it were a single-pass layouter.
Sean Bowe
str4d
Daira Hopwood
ying tong