andreika-git
/
ChibiOS
mirror of https://github.com/andreika-git/ChibiOS.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fixed ADC-related regressions and some harmless errors in F4/F7 RCC macros. Fixed some warning in F4 DMA_STORM test application. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@15732 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2022-08-21 16:53:55 +00:00
parent 1d89914815
commit 1edca64954
4 changed files with 36 additions and 51 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
os/hal/ports/STM32/LLD/ADCv2/hal_adc_lld.c
View File

@ -224,6 +224,11 @@ void adc_lld_init(void) {
STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
#endif #endif
#if defined(rccResetADC)
/* Shared reset case.*/
rccResetADC();
#endif
/* The shared vector is initialized on driver initialization and never /* The shared vector is initialized on driver initialization and never
disabled because sharing.*/ disabled because sharing.*/
nvicEnableVector(STM32_ADC_NUMBER, STM32_ADC_IRQ_PRIORITY); nvicEnableVector(STM32_ADC_NUMBER, STM32_ADC_IRQ_PRIORITY);
@ -248,7 +253,9 @@ void adc_lld_start(ADCDriver *adcp) {
(void *)adcp); (void *)adcp);
osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream"); osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream");
dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR); dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
rccResetADC1(true); #if defined(rccResetADC1)
rccResetADC1();
#endif
rccEnableADC1(true); rccEnableADC1(true);
} }
#endif /* STM32_ADC_USE_ADC1 */ #endif /* STM32_ADC_USE_ADC1 */
@ -261,7 +268,9 @@ void adc_lld_start(ADCDriver *adcp) {
(void *)adcp); (void *)adcp);
osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream"); osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream");
dmaStreamSetPeripheral(adcp->dmastp, &ADC2->DR); dmaStreamSetPeripheral(adcp->dmastp, &ADC2->DR);
rccResetADC2(true); #if defined(rccResetADC2)
rccResetADC2();
#endif
rccEnableADC2(true); rccEnableADC2(true);
} }
#endif /* STM32_ADC_USE_ADC2 */ #endif /* STM32_ADC_USE_ADC2 */
@ -274,7 +283,9 @@ void adc_lld_start(ADCDriver *adcp) {
(void *)adcp); (void *)adcp);
osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream"); osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream");
dmaStreamSetPeripheral(adcp->dmastp, &ADC3->DR); dmaStreamSetPeripheral(adcp->dmastp, &ADC3->DR);
rccResetADC3(true); #if defined(rccResetADC3)
rccResetADC3();
#endif
rccEnableADC3(true); rccEnableADC3(true);
} }
#endif /* STM32_ADC_USE_ADC3 */ #endif /* STM32_ADC_USE_ADC3 */

28
os/hal/ports/STM32/STM32F4xx/stm32_rcc.h
View File

@ -269,6 +269,13 @@
* @name ADC peripherals specific RCC operations * @name ADC peripherals specific RCC operations
* @{ * @{
*/ */
/**
* @brief Resets ADC peripherals.
*
* @api
*/
#define rccResetADC() rccResetAPB2(RCC_APB2RSTR_ADCRST)
/** /**
* @brief Enables the ADC1 peripheral clock. * @brief Enables the ADC1 peripheral clock.
* *
@ -285,13 +292,6 @@
*/ */
#define rccDisableADC1() rccDisableAPB2(RCC_APB2ENR_ADC1EN) #define rccDisableADC1() rccDisableAPB2(RCC_APB2ENR_ADC1EN)
/**
* @brief Resets the ADC1 peripheral.
*
* @api
*/
#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST)
/** /**
* @brief Enables the ADC2 peripheral clock. * @brief Enables the ADC2 peripheral clock.
* *
@ -308,13 +308,6 @@
*/ */
#define rccDisableADC2() rccDisableAPB2(RCC_APB2ENR_ADC2EN) #define rccDisableADC2() rccDisableAPB2(RCC_APB2ENR_ADC2EN)
/**
* @brief Resets the ADC2 peripheral.
*
* @api
*/
#define rccResetADC2() rccResetAPB2(RCC_APB2RSTR_ADC2RST)
/** /**
* @brief Enables the ADC3 peripheral clock. * @brief Enables the ADC3 peripheral clock.
* *
@ -330,13 +323,6 @@
* @api * @api
*/ */
#define rccDisableADC3() rccDisableAPB2(RCC_APB2ENR_ADC3EN) #define rccDisableADC3() rccDisableAPB2(RCC_APB2ENR_ADC3EN)
/**
* @brief Resets the ADC3 peripheral.
*
* @api
*/
#define rccResetADC3() rccResetAPB2(RCC_APB2RSTR_ADC3RST)
/** @} */ /** @} */
/** /**

28
os/hal/ports/STM32/STM32F7xx/stm32_rcc.h
View File

@ -270,6 +270,13 @@
* @name ADC peripherals specific RCC operations * @name ADC peripherals specific RCC operations
* @{ * @{
*/ */
/**
* @brief Resets ADC peripherals.
*
* @api
*/
#define rccResetADC() rccResetAPB2(RCC_APB2RSTR_ADCRST)
/** /**
* @brief Enables the ADC1 peripheral clock. * @brief Enables the ADC1 peripheral clock.
* *
@ -286,13 +293,6 @@
*/ */
#define rccDisableADC1() rccDisableAPB2(RCC_APB2ENR_ADC1EN) #define rccDisableADC1() rccDisableAPB2(RCC_APB2ENR_ADC1EN)
/**
* @brief Resets the ADC1 peripheral.
*
* @api
*/
#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST)
/** /**
* @brief Enables the ADC2 peripheral clock. * @brief Enables the ADC2 peripheral clock.
* *
@ -309,13 +309,6 @@
*/ */
#define rccDisableADC2() rccDisableAPB2(RCC_APB2ENR_ADC2EN) #define rccDisableADC2() rccDisableAPB2(RCC_APB2ENR_ADC2EN)
/**
* @brief Resets the ADC2 peripheral.
*
* @api
*/
#define rccResetADC2() rccResetAPB2(RCC_APB2RSTR_ADC2RST)
/** /**
* @brief Enables the ADC3 peripheral clock. * @brief Enables the ADC3 peripheral clock.
* *
@ -331,13 +324,6 @@
* @api * @api
*/ */
#define rccDisableADC3() rccDisableAPB2(RCC_APB2ENR_ADC3EN) #define rccDisableADC3() rccDisableAPB2(RCC_APB2ENR_ADC3EN)
/**
* @brief Resets the ADC3 peripheral.
*
* @api
*/
#define rccResetADC3() rccResetAPB2(RCC_APB2RSTR_ADC3RST)
/** @} */ /** @} */
/** /**

14
testhal/STM32/STM32F4xx/DMA_STORM/main.c
View File

@ -88,12 +88,14 @@ static const ADCConversionGroup adcgrpcfg2 = {
* Maximum speed SPI configuration (21MHz, CPHA=0, CPOL=0, MSb first). * Maximum speed SPI configuration (21MHz, CPHA=0, CPOL=0, MSb first).
*/ */
static const SPIConfig hs_spicfg = { static const SPIConfig hs_spicfg = {
false, .circular = false,
NULL, .slave = false,
GPIOB, .data_cb = NULL,
12, .error_cb = NULL,
0, .ssport = GPIOB,
0 .sspad = 12,
.cr1 = 0,
.cr2 = 0
}; };
/* /*