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Added polling on wait states setup. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14409 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2021-05-21 12:15:07 +00:00
parent 0a1a2b6125
commit 33df3af7ab
2 changed files with 6 additions and 0 deletions
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3
os/hal/ports/STM32/STM32G4xx/hal_lld.c
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@ -461,6 +461,9 @@ bool hal_lld_clock_raw_switch(const halclkcfg_t *ccp) {
/* Resetting flash ACR settings to the default value.*/ /* Resetting flash ACR settings to the default value.*/
FLASH->ACR = 0x00040600U; FLASH->ACR = 0x00040600U;
while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) != 0U) {
/* Waiting for flash wait states setup.*/
}
/* Resetting all other clock sources and PLLs.*/ /* Resetting all other clock sources and PLLs.*/
RCC->CRRCR = 0U; RCC->CRRCR = 0U;

3
os/hal/ports/STM32/STM32L4xx+/hal_lld.c
View File

@ -537,6 +537,9 @@ bool hal_lld_clock_raw_switch(const halclkcfg_t *ccp) {
/* Resetting flash ACR settings to the default value.*/ /* Resetting flash ACR settings to the default value.*/
FLASH->ACR = 0x00000600U; FLASH->ACR = 0x00000600U;
while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) != 0U) {
/* Waiting for flash wait states setup.*/
}
/* Resetting all other clock sources and PLLs.*/ /* Resetting all other clock sources and PLLs.*/
RCC->CRRCR = 0U; RCC->CRRCR = 0U;