git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_2.4.x@4482 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -212,11 +212,14 @@ static void i2c_lld_set_clock(I2CDriver *i2cp) {
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"Invalid standard mode duty cycle");
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/* Standard mode clock_div calculate: Tlow/Thigh = 1/1.*/
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chDbgAssert((STM32_PCLK1 % (clock_speed * 2)) == 0,
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"i2c_lld_set_clock(), #2",
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"PCLK1 must be divided without remainder");
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clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 2));
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/* Clock divider values under four are not allowed.*/
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if (clock_div < 0x04)
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clock_div = 0x04;
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chDbgAssert(clock_div >= 0x04,
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"i2c_lld_set_clock(), #3",
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"Clock divider less then 0x04 not allowed");
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regCCR |= (clock_div & I2C_CCR_CCR);
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/* Sets the Maximum Rise Time for standard mode.*/
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@ -225,21 +228,28 @@ static void i2c_lld_set_clock(I2CDriver *i2cp) {
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else if (clock_speed <= 400000) {
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/* Configure clock_div in fast mode.*/
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chDbgAssert((duty == FAST_DUTY_CYCLE_2) || (duty == FAST_DUTY_CYCLE_16_9),
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"i2c_lld_set_clock(), #2",
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"i2c_lld_set_clock(), #4",
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"Invalid fast mode duty cycle");
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if (duty == FAST_DUTY_CYCLE_2) {
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/* Fast mode clock_div calculate: Tlow/Thigh = 2/1.*/
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chDbgAssert((STM32_PCLK1 % (clock_speed * 3)) == 0,
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"i2c_lld_set_clock(), #5",
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"PCLK1 must be divided without remainder");
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clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 3));
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}
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else if (duty == FAST_DUTY_CYCLE_16_9) {
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/* Fast mode clock_div calculate: Tlow/Thigh = 16/9.*/
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chDbgAssert((STM32_PCLK1 % (clock_speed * 25)) == 0,
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"i2c_lld_set_clock(), #6",
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"PCLK1 must be divided without remainder");
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clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 25));
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regCCR |= I2C_CCR_DUTY;
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}
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/* Clock divider values under one are not allowed.*/
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if (clock_div < 0x01)
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clock_div = 0x01;
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chDbgAssert(clock_div >= 0x01,
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"i2c_lld_set_clock(), #7",
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"Clock divider less then 0x04 not allowed");
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regCCR |= (I2C_CCR_FS | (clock_div & I2C_CCR_CCR));
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/* Sets the Maximum Rise Time for fast mode.*/
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@ -247,7 +257,7 @@ static void i2c_lld_set_clock(I2CDriver *i2cp) {
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}
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chDbgAssert((clock_div <= I2C_CCR_CCR),
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"i2c_lld_set_clock(), #3", "the selected clock is too low");
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"i2c_lld_set_clock(), #8", "the selected clock is too low");
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dp->CCR = regCCR;
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}
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@ -797,7 +807,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
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is completed, alternatively for a timeout condition.*/
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while ((dp->SR2 & I2C_SR2_BUSY) || (dp->CR1 & I2C_CR1_STOP)) {
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chSysLock();
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if (!chVTIsArmedI(&vt))
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if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
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return RDY_TIMEOUT;
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chSysUnlock();
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}
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@ -807,7 +817,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
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/* Atomic check on the timer in order to make sure that a timeout didn't
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happen outside the critical zone.*/
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if (!chVTIsArmedI(&vt))
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if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
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return RDY_TIMEOUT;
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/* Starts the operation.*/
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@ -817,7 +827,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
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/* Waits for the operation completion or a timeout.*/
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i2cp->thread = chThdSelf();
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chSchGoSleepS(THD_STATE_SUSPENDED);
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if (chVTIsArmedI(&vt))
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if ((timeout != TIME_INFINITE) && chVTIsArmedI(&vt))
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chVTResetI(&vt);
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return chThdSelf()->p_u.rdymsg;
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@ -881,7 +891,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
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is completed, alternatively for a timeout condition.*/
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while ((dp->SR2 & I2C_SR2_BUSY) || (dp->CR1 & I2C_CR1_STOP)) {
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chSysLock();
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if (!chVTIsArmedI(&vt))
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if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
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return RDY_TIMEOUT;
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chSysUnlock();
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}
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@ -891,7 +901,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
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/* Atomic check on the timer in order to make sure that a timeout didn't
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happen outside the critical zone.*/
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if (!chVTIsArmedI(&vt))
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if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
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return RDY_TIMEOUT;
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/* Starts the operation.*/
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@ -901,7 +911,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
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/* Waits for the operation completion or a timeout.*/
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i2cp->thread = chThdSelf();
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chSchGoSleepS(THD_STATE_SUSPENDED);
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if (chVTIsArmedI(&vt))
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if ((timeout != TIME_INFINITE) && chVTIsArmedI(&vt))
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chVTResetI(&vt);
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return chThdSelf()->p_u.rdymsg;
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