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Added STM32WL support. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14617 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
vrepetenko 2021-07-25 06:50:44 +00:00
parent 91e6d923a2
commit 94be09c796
3 changed files with 13 additions and 13 deletions
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16
os/hal/ports/STM32/LLD/ADCv5/hal_adc_lld.c
View File

@ -173,7 +173,7 @@ void adc_lld_init(void) {
rccEnableADC1(true);
/* CCR setup.*/
ADC->CCR = STM32_ADC_PRESC << 18;
ADC1_COMMON->CCR = STM32_ADC_PRESC << 18;
/* Regulator enabled and stabilized before calibration.*/
adc_lld_vreg_on(ADC1);
@ -241,7 +241,7 @@ void adc_lld_stop(ADCDriver *adcp) {
adcp->dmastp = NULL;
/* Restoring CCR default.*/
ADC->CCR = STM32_ADC_PRESC << 18;
ADC1_COMMON->CCR = STM32_ADC_PRESC << 18;
/* Disabling ADC.*/
if (adcp->adc->CR & ADC_CR_ADEN) {
@ -385,7 +385,7 @@ void adcSTM32EnableVREF(ADCDriver *adcp) {
(void)adcp;
ADC->CCR |= ADC_CCR_VREFEN;
ADC1_COMMON->CCR |= ADC_CCR_VREFEN;
}
/**
@ -402,7 +402,7 @@ void adcSTM32DisableVREF(ADCDriver *adcp) {
(void)adcp;
ADC->CCR &= ~ADC_CCR_VREFEN;
ADC1_COMMON->CCR &= ~ADC_CCR_VREFEN;
}
/**
@ -419,7 +419,7 @@ void adcSTM32EnableTS(ADCDriver *adcp) {
(void)adcp;
ADC->CCR |= ADC_CCR_TSEN;
ADC1_COMMON->CCR |= ADC_CCR_TSEN;
}
/**
@ -436,7 +436,7 @@ void adcSTM32DisableTS(ADCDriver *adcp) {
(void)adcp;
ADC->CCR &= ~ADC_CCR_TSEN;
ADC1_COMMON->CCR &= ~ADC_CCR_TSEN;
}
#if defined(ADC_CCR_VBATEN) || defined(__DOXYGEN__)
@ -454,7 +454,7 @@ void adcSTM32EnableVBAT(ADCDriver *adcp) {
(void)adcp;
ADC->CCR |= ADC_CCR_VBATEN;
ADC1_COMMON->CCR |= ADC_CCR_VBATEN;
}
/**
@ -471,7 +471,7 @@ void adcSTM32DisableVBAT(ADCDriver *adcp) {
(void)adcp;
ADC->CCR &= ~ADC_CCR_VBATEN;
ADC1_COMMON->CCR &= ~ADC_CCR_VBATEN;
}
#endif /* defined(ADC_CCR_VBATEN) */

6
os/hal/ports/STM32/LLD/ADCv5/hal_adc_lld.h
View File

@ -200,8 +200,8 @@
/*===========================================================================*/
/* Supported devices checks.*/
#if !defined(STM32G0XX)
#error "ADCv5 only supports G0 STM32 devices"
#if !defined(STM32G0XX) && !defined(STM32WLXX)
#error "ADCv5 only supports G0 and WL STM32 devices"
#endif
/* Registry checks.*/
@ -366,7 +366,7 @@ typedef uint32_t adcerror_t;
* Manual.
* @note PRESC bits must not be specified and left to zero.
*/
#define adcSTM32SetCCR(ccr) (ADC->CCR = (ccr))
#define adcSTM32SetCCR(ccr) (ADC1_COMMON->CCR = (ccr))
/*===========================================================================*/
/* External declarations. */

4
os/hal/ports/STM32/LLD/ADCv5/notes.txt
View File

@ -1,8 +1,8 @@
STM32 ADCv1 driver.
STM32 ADCv5 driver.
Driver capability:
- Supports the STM32 "simple" ADC, the one found on small devices (G0).
- Supports the STM32 "simple" ADC, the one found on small devices (G0 and WL).
The file registry must export: