Reverted.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12626 110e8d01-0319-4d1e-a829-52ad28d1bb01
This commit is contained in:
Giovanni Di Sirio
parent
d4e670fc44
commit
f4736fba02
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@ -15,7 +15,7 @@
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*/
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/**
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* @file STM32F4xx/stm32_isr.c
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* @file STM32F4xx/stm32_isr.h
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* @brief STM32F4xx ISR handler code.
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*
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* @addtogroup STM32F4xx_ISR
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@ -212,236 +212,6 @@ OSAL_IRQ_HANDLER(VectorE0) {
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#endif /* HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS) */
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#if HAL_USE_GPT || HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__)
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/**
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* @brief TIM1-BRK, TIM9 interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(VectorA0) {
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OSAL_IRQ_PROLOGUE();
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#if HAL_USE_GPT
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#if STM32_GPT_USE_TIM9
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gpt_lld_serve_interrupt(&GPTD9);
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#endif
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#endif
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#if HAL_USE_ICU
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#if STM32_ICU_USE_TIM9
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icu_lld_serve_interrupt(&ICUD9);
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#endif
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#endif
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#if HAL_USE_PWM
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#if STM32_PWM_USE_TIM9
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pwm_lld_serve_interrupt(&PWMD9);
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#endif
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#endif
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OSAL_IRQ_EPILOGUE();
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}
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/**
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* @brief TIM1-UP, TIM10 interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(VectorA4) {
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OSAL_IRQ_PROLOGUE();
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#if HAL_USE_GPT
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#if STM32_GPT_USE_TIM1
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gpt_lld_serve_interrupt(&GPTD1);
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#endif
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#if STM32_GPT_USE_TIM10
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gpt_lld_serve_interrupt(&GPTD10);
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#endif
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#endif
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#if HAL_USE_ICU
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#if STM32_ICU_USE_TIM1
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icu_lld_serve_interrupt(&ICUD1);
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#endif
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#endif
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#if HAL_USE_PWM
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#if STM32_PWM_USE_TIM1
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pwm_lld_serve_interrupt(&PWMD1);
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#endif
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#if STM32_PWM_USE_TIM10
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pwm_lld_serve_interrupt(&PWMD10);
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#endif
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#endif
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OSAL_IRQ_EPILOGUE();
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}
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/**
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* @brief TIM1-TRG-COM, TIM11 interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(VectorA8) {
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OSAL_IRQ_PROLOGUE();
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#if HAL_USE_GPT
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#if STM32_GPT_USE_TIM11
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gpt_lld_serve_interrupt(&GPTD11);
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#endif
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#endif
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#if HAL_USE_ICU
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/* Not used by ICU.*/
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#endif
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#if HAL_USE_PWM
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#if STM32_PWM_USE_TIM11
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pwm_lld_serve_interrupt(&PWMD11);
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#endif
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#endif
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OSAL_IRQ_EPILOGUE();
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}
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/**
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* @brief TIM1-CC interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(VectorAC) {
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OSAL_IRQ_PROLOGUE();
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#if HAL_USE_GPT
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/* Not used by GPT.*/
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#endif
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#if HAL_USE_ICU
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#if STM32_ICU_USE_TIM1
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icu_lld_serve_interrupt(&ICUD1);
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#endif
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#endif
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#if HAL_USE_PWM
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#if STM32_PWM_USE_TIM1
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pwm_lld_serve_interrupt(&PWMD1);
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#endif
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#endif
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OSAL_IRQ_EPILOGUE();
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}
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/**
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* @brief TIM8-BRK, TIM12 interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(VectorEC) {
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OSAL_IRQ_PROLOGUE();
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#if HAL_USE_GPT
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#if STM32_GPT_USE_TIM12
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gpt_lld_serve_interrupt(&GPTD12);
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#endif
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#endif
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#if HAL_USE_ICU
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#if STM32_ICU_USE_TIM12
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icu_lld_serve_interrupt(&ICUD12);
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#endif
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#endif
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#if HAL_USE_PWM
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#if STM32_PWM_USE_TIM12
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pwm_lld_serve_interrupt(&PWMD12);
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#endif
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#endif
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OSAL_IRQ_EPILOGUE();
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}
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/**
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* @brief TIM8-UP, TIM13 interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(VectorF0) {
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OSAL_IRQ_PROLOGUE();
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#if HAL_USE_GPT
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#if STM32_GPT_USE_TIM8
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gpt_lld_serve_interrupt(&GPTD8);
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#endif
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#if STM32_GPT_USE_TIM13
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gpt_lld_serve_interrupt(&GPTD13);
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#endif
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#endif
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#if HAL_USE_ICU
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#if STM32_ICU_USE_TIM8
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icu_lld_serve_interrupt(&ICUD8);
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#endif
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#endif
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#if HAL_USE_PWM
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#if STM32_PWM_USE_TIM8
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pwm_lld_serve_interrupt(&PWMD8);
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#endif
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#if STM32_PWM_USE_TIM13
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pwm_lld_serve_interrupt(&PWMD13);
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#endif
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#endif
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OSAL_IRQ_EPILOGUE();
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}
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/**
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* @brief TIM8-TRG-COM, TIM14 interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(VectorF4) {
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OSAL_IRQ_PROLOGUE();
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#if HAL_USE_GPT
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#if STM32_GPT_USE_TIM14
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gpt_lld_serve_interrupt(&GPTD14);
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#endif
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#endif
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#if HAL_USE_ICU
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/* Not used by ICU.*/
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#endif
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#if HAL_USE_PWM
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#if STM32_PWM_USE_TIM14
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pwm_lld_serve_interrupt(&PWMD14);
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#endif
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#endif
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OSAL_IRQ_EPILOGUE();
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}
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/**
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* @brief TIM8-CC interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(VectorF8) {
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OSAL_IRQ_PROLOGUE();
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#if HAL_USE_GPT
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/* Not used by GPT.*/
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#endif
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#if HAL_USE_ICU
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#if STM32_ICU_USE_TIM8
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icu_lld_serve_interrupt(&ICUD8);
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#endif
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#endif
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#if HAL_USE_PWM
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#if STM32_PWM_USE_TIM8
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pwm_lld_serve_interrupt(&PWMD8);
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#endif
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#endif
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OSAL_IRQ_EPILOGUE();
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}
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#endif /* HAL_USE_GPT || HAL_USE_ICU || HAL_USE_PWM */
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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@ -462,16 +232,6 @@ void irqInit(void) {
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nvicEnableVector(EXTI9_5_IRQn, STM32_IRQ_EXTI5_9_PRIORITY);
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nvicEnableVector(EXTI15_10_IRQn, STM32_IRQ_EXTI10_15_PRIORITY);
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#endif
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#if HAL_USE_GPT || HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__)
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nvicEnableVector(TIM1_BRK_TIM9_IRQn, STM32_IRQ_TIM1_BRK_TIM9_PRIORITY);
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nvicEnableVector(TIM1_UP_TIM10_IRQn, STM32_IRQ_TIM1_UP_TIM10_PRIORITY);
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nvicEnableVector(TIM1_TRG_COM_TIM11_IRQn, STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY);
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nvicEnableVector(TIM1_CC_IRQn, STM32_IRQ_TIM1_CC_PRIORITY);
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nvicEnableVector(TIM8_BRK_TIM12_IRQn, STM32_IRQ_TIM8_BRK_TIM12_PRIORITY);
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nvicEnableVector(TIM8_UP_TIM13_IRQn, STM32_IRQ_TIM8_UP_TIM13_PRIORITY);
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nvicEnableVector(TIM8_TRG_COM_TIM14_IRQn, STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY);
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nvicEnableVector(TIM8_CC_IRQn, STM32_IRQ_TIM8_CC_PRIORITY);
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#endif
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}
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/**
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nvicDisableVector(EXTI9_5_IRQn);
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nvicDisableVector(EXTI15_10_IRQn);
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#endif
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#if HAL_USE_GPT || HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__)
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nvicDisableVector(TIM1_BRK_TIM9_IRQn);
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nvicDisableVector(TIM1_UP_TIM10_IRQn);
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nvicDisableVector(TIM1_TRG_COM_TIM11_IRQn);
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nvicDisableVector(TIM1_CC_IRQn);
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nvicDisableVector(TIM8_BRK_TIM12_IRQn);
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nvicDisableVector(TIM8_UP_TIM13_IRQn);
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nvicDisableVector(TIM8_TRG_COM_TIM14_IRQn);
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nvicDisableVector(TIM8_CC_IRQn);
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#endif
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}
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/** @} */
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@ -33,14 +33,157 @@
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* @name ISR names and numbers remapping
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* @{
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*/
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#define STM32_TIM1_SUPPRESS_ISR
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#define STM32_TIM9_SUPPRESS_ISR
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#define STM32_TIM10_SUPPRESS_ISR
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#define STM32_TIM11_SUPPRESS_ISR
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#define STM32_TIM8_SUPPRESS_ISR
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#define STM32_TIM12_SUPPRESS_ISR
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#define STM32_TIM13_SUPPRESS_ISR
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#define STM32_TIM14_SUPPRESS_ISR
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/*
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* CAN units.
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*/
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#define STM32_CAN1_TX_HANDLER Vector8C
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#define STM32_CAN1_RX0_HANDLER Vector90
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#define STM32_CAN1_RX1_HANDLER Vector94
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#define STM32_CAN1_SCE_HANDLER Vector98
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#define STM32_CAN2_TX_HANDLER Vector13C
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#define STM32_CAN2_RX0_HANDLER Vector140
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#define STM32_CAN2_RX1_HANDLER Vector144
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#define STM32_CAN2_SCE_HANDLER Vector148
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#define STM32_CAN1_TX_NUMBER 19
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#define STM32_CAN1_RX0_NUMBER 20
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#define STM32_CAN1_RX1_NUMBER 21
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#define STM32_CAN1_SCE_NUMBER 22
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#define STM32_CAN2_TX_NUMBER 63
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#define STM32_CAN2_RX0_NUMBER 64
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#define STM32_CAN2_RX1_NUMBER 65
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#define STM32_CAN2_SCE_NUMBER 66
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/*
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* I2C units.
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*/
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#define STM32_I2C1_EVENT_HANDLER VectorBC
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#define STM32_I2C1_ERROR_HANDLER VectorC0
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#define STM32_I2C1_EVENT_NUMBER 31
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#define STM32_I2C1_ERROR_NUMBER 32
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#define STM32_I2C2_EVENT_HANDLER VectorC4
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#define STM32_I2C2_ERROR_HANDLER VectorC8
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#define STM32_I2C2_EVENT_NUMBER 33
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#define STM32_I2C2_ERROR_NUMBER 34
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#define STM32_I2C3_EVENT_HANDLER Vector160
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#define STM32_I2C3_ERROR_HANDLER Vector164
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#define STM32_I2C3_EVENT_NUMBER 72
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#define STM32_I2C3_ERROR_NUMBER 73
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/*
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* OTG units.
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*/
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#define STM32_OTG1_HANDLER Vector14C
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#define STM32_OTG2_HANDLER Vector174
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#define STM32_OTG2_EP1OUT_HANDLER Vector168
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#define STM32_OTG2_EP1IN_HANDLER Vector16C
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#define STM32_OTG1_NUMBER 67
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#define STM32_OTG2_NUMBER 77
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#define STM32_OTG2_EP1OUT_NUMBER 74
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#define STM32_OTG2_EP1IN_NUMBER 75
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/*
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* SDIO unit.
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*/
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#define STM32_SDIO_HANDLER Vector104
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#define STM32_SDIO_NUMBER 49
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/*
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* TIM units.
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*/
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#define STM32_TIM1_UP_HANDLER VectorA4
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#define STM32_TIM1_CC_HANDLER VectorAC
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#define STM32_TIM2_HANDLER VectorB0
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#define STM32_TIM3_HANDLER VectorB4
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#define STM32_TIM4_HANDLER VectorB8
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#define STM32_TIM5_HANDLER Vector108
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#define STM32_TIM6_HANDLER Vector118
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#define STM32_TIM7_HANDLER Vector11C
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#define STM32_TIM8_UP_HANDLER VectorF0
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#define STM32_TIM8_CC_HANDLER VectorF8
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#define STM32_TIM9_HANDLER VectorA0
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#define STM32_TIM10_HANDLER VectorA4 /* Note: same as STM32_TIM1_UP */
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#define STM32_TIM11_HANDLER VectorA8
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#define STM32_TIM12_HANDLER VectorEC
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#define STM32_TIM13_HANDLER VectorF0 /* Note: same as STM32_TIM8_UP */
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#define STM32_TIM14_HANDLER VectorF4
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#define STM32_TIM1_UP_NUMBER 25
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#define STM32_TIM1_CC_NUMBER 27
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#define STM32_TIM2_NUMBER 28
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#define STM32_TIM3_NUMBER 29
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#define STM32_TIM4_NUMBER 30
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#define STM32_TIM5_NUMBER 50
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#define STM32_TIM6_NUMBER 54
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#define STM32_TIM7_NUMBER 55
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#define STM32_TIM8_UP_NUMBER 44
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#define STM32_TIM8_CC_NUMBER 46
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#define STM32_TIM9_NUMBER 24
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#define STM32_TIM10_NUMBER 25 /* Note: same as STM32_TIM1_UP */
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#define STM32_TIM11_NUMBER 26
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#define STM32_TIM12_NUMBER 43
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#define STM32_TIM13_NUMBER 44 /* Note: same as STM32_TIM8_UP */
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#define STM32_TIM14_NUMBER 45
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/*
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* LPTIM units.
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*/
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#define STM32_LPTIM1_HANDLER Vector1C4
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#define STM32_LPTIM1_NUMBER 97
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/*
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* USART units.
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*/
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#define STM32_USART1_HANDLER VectorD4
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#define STM32_USART2_HANDLER VectorD8
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#define STM32_USART3_HANDLER VectorDC
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#define STM32_UART4_HANDLER Vector110
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#define STM32_UART5_HANDLER Vector114
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#define STM32_USART6_HANDLER Vector15C
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#define STM32_UART7_HANDLER Vector188
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#define STM32_UART8_HANDLER Vector18C
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#define STM32_USART1_NUMBER 37
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#define STM32_USART2_NUMBER 38
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#define STM32_USART3_NUMBER 39
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#define STM32_UART4_NUMBER 52
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#define STM32_UART5_NUMBER 53
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#define STM32_USART6_NUMBER 71
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#define STM32_UART7_NUMBER 82
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#define STM32_UART8_NUMBER 83
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/*
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* Ethernet
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*/
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#define ETH_IRQHandler Vector134
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/*
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* FSMC
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*/
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#define STM32_FSMC_HANDLER Vector100
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#define STM32_FSMC_NUMBER 48
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/*
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* LTDC
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*/
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#define STM32_LTDC_EV_HANDLER Vector1A0
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#define STM32_LTDC_ER_HANDLER Vector1A4
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#define STM32_LTDC_EV_NUMBER 88
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#define STM32_LTDC_ER_NUMBER 89
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/*
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* DMA2D
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*/
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#define STM32_DMA2D_HANDLER Vector1A8
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#define STM32_DMA2D_NUMBER 90
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/** @} */
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/*===========================================================================*/
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@ -99,139 +242,12 @@
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#if !defined(STM32_IRQ_EXTI10_15_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_IRQ_EXTI10_15_PRIORITY 6
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#endif
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/**
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* @brief EXTI16 interrupt priority level setting.
|
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*/
|
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#if !defined(STM32_IRQ_EXTI16_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_IRQ_EXTI16_PRIORITY 6
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#endif
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/**
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* @brief EXTI17 interrupt priority level setting.
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*/
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#if !defined(STM32_IRQ_EXTI17_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_IRQ_EXTI17_PRIORITY 6
|
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#endif
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/**
|
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* @brief EXTI18 interrupt priority level setting.
|
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*/
|
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#if !defined(STM32_IRQ_EXTI18_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_IRQ_EXTI18_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI21 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_IRQ_EXTI21_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_IRQ_EXTI21_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI22 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_IRQ_EXTI22_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_IRQ_EXTI22_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI23 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_IRQ_EXTI23_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_IRQ_EXTI23_PRIORITY 6
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Derived constants and error checks. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/* IRQ priority checks.*/
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI0_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI0_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI1_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI1_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI2_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI2_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI3_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI3_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI4_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI4_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI5_9_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI5_9_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI10_15_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI10_15_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI16_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI16_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI17_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI17_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI18_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI18_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI21_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI21_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI22_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI22_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI23_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI23_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_BRK_TIM9_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_BRK_TIM9_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_UP_TIM10_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_UP_TIM10_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_CC_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_CC_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM8_BRK_TIM12_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_BRK_TIM12_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM8_UP_TIM13_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_UP_TIM13_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_TRGCO_TIM14_PRIORITY"
|
||||
#endif
|
||||
|
||||
#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM8_CC_PRIORITY)
|
||||
#error "Invalid IRQ priority assigned to STM32_IRQ_TIM8_CC_PRIORITY"
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
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Reference in New Issue