2009-06-01 01:32:11 -07:00
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/*
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HardwareSerial.cpp - Hardware serial library for Wiring
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Copyright (c) 2006 Nicholas Zambetti. All right reserved.
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with this library; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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Modified 23 November 2006 by David A. Mellis
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2010-10-17 10:36:02 -07:00
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Modified 28 September 2010 by Mark Sproul
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2012-08-14 06:50:36 -07:00
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Modified 14 August 2012 by Alarus
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2014-02-07 07:52:10 -08:00
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Modified 3 December 2013 by Matthijs Kooijman
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2009-06-01 01:32:11 -07:00
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*/
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2010-07-04 16:22:34 -07:00
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#include <stdlib.h>
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2009-06-01 01:32:11 -07:00
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
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2011-03-01 17:00:16 -08:00
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#include "Arduino.h"
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2009-06-01 01:32:11 -07:00
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2013-12-01 08:21:54 -08:00
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#include "HardwareSerial.h"
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2014-01-22 01:12:56 -08:00
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#include "HardwareSerial_private.h"
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2013-12-01 08:21:54 -08:00
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2010-10-17 10:36:02 -07:00
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// this next line disables the entire HardwareSerial.cpp,
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// this is so I can support Attiny series and any other chip without a uart
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2013-12-01 08:21:54 -08:00
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#if defined(HAVE_HWSERIAL0) || defined(HAVE_HWSERIAL1) || defined(HAVE_HWSERIAL2) || defined(HAVE_HWSERIAL3)
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2009-06-01 01:32:11 -07:00
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2013-12-03 12:15:17 -08:00
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// SerialEvent functions are weak, so when the user doesn't define them,
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// the linker just sets their address to 0 (which is checked below).
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// The Serialx_available is just a wrapper around Serialx.available(),
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// but we can refer to it weakly so we don't pull in the entire
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// HardwareSerial instance if the user doesn't also refer to it.
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2013-12-01 08:21:54 -08:00
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#if defined(HAVE_HWSERIAL0)
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2011-05-07 10:04:13 -07:00
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void serialEvent() __attribute__((weak));
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2013-12-03 12:15:17 -08:00
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bool Serial0_available() __attribute__((weak));
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2010-10-17 10:36:02 -07:00
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#endif
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2009-06-01 01:32:11 -07:00
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2013-12-01 08:21:54 -08:00
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#if defined(HAVE_HWSERIAL1)
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2011-05-07 10:04:13 -07:00
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void serialEvent1() __attribute__((weak));
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2013-12-03 12:15:17 -08:00
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bool Serial1_available() __attribute__((weak));
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2009-06-01 01:32:11 -07:00
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#endif
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2010-10-17 10:36:02 -07:00
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2013-12-01 08:21:54 -08:00
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#if defined(HAVE_HWSERIAL2)
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2011-05-07 10:04:13 -07:00
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void serialEvent2() __attribute__((weak));
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2013-12-03 12:15:17 -08:00
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bool Serial2_available() __attribute__((weak));
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2009-06-01 01:32:11 -07:00
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#endif
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2013-12-01 08:21:54 -08:00
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#if defined(HAVE_HWSERIAL3)
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2011-05-07 10:04:13 -07:00
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void serialEvent3() __attribute__((weak));
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2013-12-03 12:15:17 -08:00
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bool Serial3_available() __attribute__((weak));
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2009-06-01 01:32:11 -07:00
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#endif
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2011-08-31 12:52:56 -07:00
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void serialEventRun(void)
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{
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2013-12-01 08:21:54 -08:00
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#if defined(HAVE_HWSERIAL0)
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2013-12-03 12:15:17 -08:00
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if (Serial0_available && serialEvent && Serial0_available()) serialEvent();
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2011-08-31 12:52:56 -07:00
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#endif
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2013-12-01 08:21:54 -08:00
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#if defined(HAVE_HWSERIAL1)
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2013-12-03 12:15:17 -08:00
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if (Serial1_available && serialEvent1 && Serial1_available()) serialEvent1();
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2011-08-31 12:52:56 -07:00
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#endif
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2013-12-01 08:21:54 -08:00
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#if defined(HAVE_HWSERIAL2)
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2013-12-03 12:15:17 -08:00
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if (Serial2_available && serialEvent2 && Serial2_available()) serialEvent2();
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2011-08-31 12:52:56 -07:00
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#endif
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2013-12-01 08:21:54 -08:00
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#if defined(HAVE_HWSERIAL3)
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2014-03-27 11:20:54 -07:00
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if (Serial3_available && serialEvent3 && Serial3_available()) serialEvent3();
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2011-03-05 11:17:26 -08:00
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#endif
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}
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2013-04-18 02:38:13 -07:00
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// Actual interrupt handlers //////////////////////////////////////////////////////////////
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void HardwareSerial::_tx_udr_empty_irq(void)
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{
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2013-04-18 10:06:00 -07:00
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// If interrupts are enabled, there must be more data in the output
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// buffer. Send the next byte
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unsigned char c = _tx_buffer[_tx_buffer_tail];
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2014-03-23 15:12:00 -07:00
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_tx_buffer_tail = (_tx_buffer_tail + 1) % SERIAL_TX_BUFFER_SIZE;
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2013-04-18 10:06:00 -07:00
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*_udr = c;
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// clear the TXC bit -- "can be cleared by writing a one to its bit
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// location". This makes sure flush() won't return until the bytes
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// actually got written
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sbi(*_ucsra, TXC0);
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2013-04-18 02:38:13 -07:00
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if (_tx_buffer_head == _tx_buffer_tail) {
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// Buffer empty, so disable interrupts
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cbi(*_ucsrb, UDRIE0);
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2011-03-05 11:17:26 -08:00
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}
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}
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2009-06-01 01:32:11 -07:00
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// Public Methods //////////////////////////////////////////////////////////////
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2012-08-14 06:50:36 -07:00
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void HardwareSerial::begin(unsigned long baud, byte config)
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2012-08-12 07:57:57 -07:00
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{
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2013-04-19 07:32:33 -07:00
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// Try u2x mode first
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uint16_t baud_setting = (F_CPU / 4 / baud - 1) / 2;
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Use constants for register bit positions in HardwareSerial
Previously, the constants to use for the bit positions of the various
UARTs were passed to the HardwareSerial constructor. However, this
meant that whenever these values were used, the had to be indirectly
loaded, resulting in extra code overhead. Additionally, since there is
no instruction to shift a value by a variable amount, the 1 << x
expressions (inside _BV and sbi() / cbi()) would be compiled as a loop
instead of being evaluated at compiletime.
Now, the HardwareSerial class always uses the constants for the bit
positions of UART 0 (and some code is present to make sure these
constants exist, even for targets that only have a single unnumbered
UART or start at UART1).
This was already done for the TXC0 constant, for some reason. For the
actual register addresses, this approach does not work, since these are
of course different between the different UARTs on a single chip.
Of course, always using the UART 0 constants is only correct when the
constants are actually identical for the different UARTs. It has been
verified that this is currently the case for all targets supported by
avr-gcc 4.7.2, and the code contains compile-time checks to verify this
for the current target, in case a new target is added for which this
does not hold. This verification was done using:
for i in TXC RXEN TXEN RXCIE UDRIE U2X UPE; do echo $i; grep --no-filename -r "#define $i[0-9]\? " /usr/lib/avr/include/avr/io* | sed "s/#define $i[0-9]\?\s*\(\S\)\+\s*\(\/\*.*\*\/\)\?$/\1/" | sort | uniq ; done
This command shows that the above constants are identical for all uarts
on all platforms, except for TXC, which is sometimes 6 and sometimes 0.
Further investigation shows that it is always 6, except in io90scr100.h,
but that file defines TXC0 with value 6 for the UART and uses TXC with
value 0 for some USB-related register.
This commit reduces program size on the uno by around 120 bytes.
2013-04-18 05:17:47 -07:00
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*_ucsra = 1 << U2X0;
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2012-08-12 07:57:57 -07:00
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2013-04-19 07:32:33 -07:00
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// hardcoded exception for 57600 for compatibility with the bootloader
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// shipped with the Duemilanove and previous boards and the firmware
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// on the 8U2 on the Uno and Mega 2560. Also, The baud_setting cannot
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// be > 4095, so switch back to non-u2x mode if the baud rate is too
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// low.
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if (((F_CPU == 16000000UL) && (baud == 57600)) || (baud_setting >4095))
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{
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2012-08-12 07:57:57 -07:00
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*_ucsra = 0;
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baud_setting = (F_CPU / 8 / baud - 1) / 2;
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}
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2014-05-06 01:19:08 -07:00
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// assign the baud_setting, a.k.a. ubrr (USART Baud Rate Register)
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2012-08-12 07:57:57 -07:00
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*_ubrrh = baud_setting >> 8;
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*_ubrrl = baud_setting;
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Improve HardwareSerial::flush()
The flush() method blocks until all characters in the serial buffer have
been written to the uart _and_ transmitted. This is checked by waiting
until the "TXC" (TX Complete) bit is set by the UART, signalling
completion. This bit is cleared by write() when adding a new byte to the
buffer and set by the hardware after tranmission ends, so it is always
guaranteed to be zero from the moment the first byte in a sequence is
queued until the moment the last byte is transmitted, and it is one from
the moment the last byte in the buffer is transmitted until the first
byte in the next sequence is queued.
However, the TXC bit is also zero from initialization to the moment the
first byte ever is queued (and then continues to be zero until the first
sequence of bytes completes transmission). Unfortunately we cannot
manually set the TXC bit during initialization, we can only clear it. To
make sure that flush() would not (indefinitely) block when it is called
_before_ anything was written to the serial device, the "transmitting"
variable was introduced.
This variable suggests that it is only true when something is
transmitting, which isn't currently the case (it remains true after
transmission is complete until flush() is called, for example).
Furthermore, there is no need to keep the status of transmission, the
only thing needed is to remember if anything has ever been written, so
the corner case described above can be detected.
This commit improves the code by:
- Renaming the "transmitting" variable to _written (making it more
clear and following the leading underscore naming convention).
- Not resetting the value of _written at the end of flush(), there is
no point to this.
- Only checking the "_written" value once in flush(), since it can
never be toggled off anyway.
- Initializing the value of _written in both versions of _begin (though
it probably gets initialized to 0 by default anyway, better to be
explicit).
2013-04-18 12:12:01 -07:00
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_written = false;
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2012-08-30 05:47:35 -07:00
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//set the data bits, parity, and stop bits
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#if defined(__AVR_ATmega8__)
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config |= 0x80; // select UCSRC register (shared with UBRRH)
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#endif
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*_ucsrc = config;
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2012-08-12 07:57:57 -07:00
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Use constants for register bit positions in HardwareSerial
Previously, the constants to use for the bit positions of the various
UARTs were passed to the HardwareSerial constructor. However, this
meant that whenever these values were used, the had to be indirectly
loaded, resulting in extra code overhead. Additionally, since there is
no instruction to shift a value by a variable amount, the 1 << x
expressions (inside _BV and sbi() / cbi()) would be compiled as a loop
instead of being evaluated at compiletime.
Now, the HardwareSerial class always uses the constants for the bit
positions of UART 0 (and some code is present to make sure these
constants exist, even for targets that only have a single unnumbered
UART or start at UART1).
This was already done for the TXC0 constant, for some reason. For the
actual register addresses, this approach does not work, since these are
of course different between the different UARTs on a single chip.
Of course, always using the UART 0 constants is only correct when the
constants are actually identical for the different UARTs. It has been
verified that this is currently the case for all targets supported by
avr-gcc 4.7.2, and the code contains compile-time checks to verify this
for the current target, in case a new target is added for which this
does not hold. This verification was done using:
for i in TXC RXEN TXEN RXCIE UDRIE U2X UPE; do echo $i; grep --no-filename -r "#define $i[0-9]\? " /usr/lib/avr/include/avr/io* | sed "s/#define $i[0-9]\?\s*\(\S\)\+\s*\(\/\*.*\*\/\)\?$/\1/" | sort | uniq ; done
This command shows that the above constants are identical for all uarts
on all platforms, except for TXC, which is sometimes 6 and sometimes 0.
Further investigation shows that it is always 6, except in io90scr100.h,
but that file defines TXC0 with value 6 for the UART and uses TXC with
value 0 for some USB-related register.
This commit reduces program size on the uno by around 120 bytes.
2013-04-18 05:17:47 -07:00
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sbi(*_ucsrb, RXEN0);
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sbi(*_ucsrb, TXEN0);
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sbi(*_ucsrb, RXCIE0);
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cbi(*_ucsrb, UDRIE0);
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2012-08-12 07:57:57 -07:00
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}
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2009-12-22 16:00:17 -08:00
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void HardwareSerial::end()
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{
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2011-03-06 09:20:42 -08:00
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// wait for transmission of outgoing data
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2013-04-18 09:52:48 -07:00
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while (_tx_buffer_head != _tx_buffer_tail)
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2011-03-06 09:20:42 -08:00
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;
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Use constants for register bit positions in HardwareSerial
Previously, the constants to use for the bit positions of the various
UARTs were passed to the HardwareSerial constructor. However, this
meant that whenever these values were used, the had to be indirectly
loaded, resulting in extra code overhead. Additionally, since there is
no instruction to shift a value by a variable amount, the 1 << x
expressions (inside _BV and sbi() / cbi()) would be compiled as a loop
instead of being evaluated at compiletime.
Now, the HardwareSerial class always uses the constants for the bit
positions of UART 0 (and some code is present to make sure these
constants exist, even for targets that only have a single unnumbered
UART or start at UART1).
This was already done for the TXC0 constant, for some reason. For the
actual register addresses, this approach does not work, since these are
of course different between the different UARTs on a single chip.
Of course, always using the UART 0 constants is only correct when the
constants are actually identical for the different UARTs. It has been
verified that this is currently the case for all targets supported by
avr-gcc 4.7.2, and the code contains compile-time checks to verify this
for the current target, in case a new target is added for which this
does not hold. This verification was done using:
for i in TXC RXEN TXEN RXCIE UDRIE U2X UPE; do echo $i; grep --no-filename -r "#define $i[0-9]\? " /usr/lib/avr/include/avr/io* | sed "s/#define $i[0-9]\?\s*\(\S\)\+\s*\(\/\*.*\*\/\)\?$/\1/" | sort | uniq ; done
This command shows that the above constants are identical for all uarts
on all platforms, except for TXC, which is sometimes 6 and sometimes 0.
Further investigation shows that it is always 6, except in io90scr100.h,
but that file defines TXC0 with value 6 for the UART and uses TXC with
value 0 for some USB-related register.
This commit reduces program size on the uno by around 120 bytes.
2013-04-18 05:17:47 -07:00
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cbi(*_ucsrb, RXEN0);
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cbi(*_ucsrb, TXEN0);
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cbi(*_ucsrb, RXCIE0);
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cbi(*_ucsrb, UDRIE0);
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2011-03-06 09:20:42 -08:00
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// clear any received data
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2013-04-18 09:52:48 -07:00
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_rx_buffer_head = _rx_buffer_tail;
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2009-12-22 16:00:17 -08:00
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}
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2010-08-02 15:23:48 -07:00
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int HardwareSerial::available(void)
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2009-06-01 01:32:11 -07:00
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{
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2014-10-21 08:47:59 -07:00
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return ((unsigned int)(SERIAL_RX_BUFFER_SIZE + _rx_buffer_head - _rx_buffer_tail)) % SERIAL_RX_BUFFER_SIZE;
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2009-06-01 01:32:11 -07:00
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}
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2010-07-04 16:31:55 -07:00
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int HardwareSerial::peek(void)
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{
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2013-04-18 09:52:48 -07:00
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if (_rx_buffer_head == _rx_buffer_tail) {
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2010-07-04 16:31:55 -07:00
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return -1;
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} else {
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2013-04-18 09:52:48 -07:00
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return _rx_buffer[_rx_buffer_tail];
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2010-07-04 16:31:55 -07:00
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}
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}
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2009-06-01 01:32:11 -07:00
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int HardwareSerial::read(void)
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{
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2009-07-11 18:58:15 -07:00
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// if the head isn't ahead of the tail, we don't have any characters
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2013-04-18 09:52:48 -07:00
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if (_rx_buffer_head == _rx_buffer_tail) {
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2009-07-11 18:58:15 -07:00
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return -1;
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} else {
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2013-04-18 09:52:48 -07:00
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unsigned char c = _rx_buffer[_rx_buffer_tail];
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2014-03-24 13:40:12 -07:00
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_rx_buffer_tail = (rx_buffer_index_t)(_rx_buffer_tail + 1) % SERIAL_RX_BUFFER_SIZE;
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2009-07-11 18:58:15 -07:00
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return c;
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}
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2009-06-01 01:32:11 -07:00
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}
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2014-07-18 07:01:26 -07:00
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int HardwareSerial::availableForWrite(void)
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{
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#if (SERIAL_TX_BUFFER_SIZE>256)
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uint8_t oldSREG = SREG;
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cli();
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#endif
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tx_buffer_index_t head = _tx_buffer_head;
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tx_buffer_index_t tail = _tx_buffer_tail;
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#if (SERIAL_TX_BUFFER_SIZE>256)
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SREG = oldSREG;
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#endif
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if (head >= tail) return SERIAL_TX_BUFFER_SIZE - 1 - head + tail;
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return tail - head - 1;
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}
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2009-06-01 01:32:11 -07:00
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void HardwareSerial::flush()
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{
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Improve HardwareSerial::flush()
The flush() method blocks until all characters in the serial buffer have
been written to the uart _and_ transmitted. This is checked by waiting
until the "TXC" (TX Complete) bit is set by the UART, signalling
completion. This bit is cleared by write() when adding a new byte to the
buffer and set by the hardware after tranmission ends, so it is always
guaranteed to be zero from the moment the first byte in a sequence is
queued until the moment the last byte is transmitted, and it is one from
the moment the last byte in the buffer is transmitted until the first
byte in the next sequence is queued.
However, the TXC bit is also zero from initialization to the moment the
first byte ever is queued (and then continues to be zero until the first
sequence of bytes completes transmission). Unfortunately we cannot
manually set the TXC bit during initialization, we can only clear it. To
make sure that flush() would not (indefinitely) block when it is called
_before_ anything was written to the serial device, the "transmitting"
variable was introduced.
This variable suggests that it is only true when something is
transmitting, which isn't currently the case (it remains true after
transmission is complete until flush() is called, for example).
Furthermore, there is no need to keep the status of transmission, the
only thing needed is to remember if anything has ever been written, so
the corner case described above can be detected.
This commit improves the code by:
- Renaming the "transmitting" variable to _written (making it more
clear and following the leading underscore naming convention).
- Not resetting the value of _written at the end of flush(), there is
no point to this.
- Only checking the "_written" value once in flush(), since it can
never be toggled off anyway.
- Initializing the value of _written in both versions of _begin (though
it probably gets initialized to 0 by default anyway, better to be
explicit).
2013-04-18 12:12:01 -07:00
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// If we have never written a byte, no need to flush. This special
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|
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// case is needed since there is no way to force the TXC (transmit
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// complete) bit to 1 during initialization
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if (!_written)
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return;
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2013-04-18 12:34:00 -07:00
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while (bit_is_set(*_ucsrb, UDRIE0) || bit_is_clear(*_ucsra, TXC0)) {
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if (bit_is_clear(SREG, SREG_I) && bit_is_set(*_ucsrb, UDRIE0))
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// Interrupts are globally disabled, but the DR empty
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// interrupt should be enabled, so poll the DR empty flag to
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// prevent deadlock
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if (bit_is_set(*_ucsra, UDRE0))
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_tx_udr_empty_irq();
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}
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Fix HardwareSerial::flush() when interrupts are kept disabled for a while
It turns out there is an additional corner case. The analysis in the
previous commit wrt to flush() assumes that the data register is always
kept filled by the interrupt handler, so the TXC bit won't get set until
all the queued bytes have been transmitted. But, when interrupts are
disabled for a longer period (for example when an interrupt handler for
another device is running for longer than 1-2 byte times), it could
happen that the UART stops transmitting while there are still more bytes
queued (but these are in the buffer, not in the UDR register, so the
UART can't know about them).
In this case, the TXC bit would get set, but the transmission is not
complete yet. We can easily detect this case by looking at the head and
tail pointers, but it seems easier to instead look at the UDRIE bit
(the TX interrupt is enabled if and only if there are bytes in the
queue). To fix this corner case, this commit:
- Checks the UDRIE bit and only if it is unset, looks at the TXC bit.
- Moves the clearing of TXC from write() to the tx interrupt handler.
This (still) causes the TXC bit to be cleared whenever a byte is
queued when the buffer is empty (in this case the tx interrupt will
trigger directly after write() is called). It also causes the TXC bit
to be cleared whenever transmission is resumed after it halted
because interrupts have been disabled for too long.
As a side effect, another race condition is prevented. This could occur
at very high bitrates, where the transmission would be completed before
the code got time to clear the TXC0 register, making the clear happen
_after_ the transmission was already complete. With the new code, the
clearing of TXC happens directly after writing to the UDR register,
while interrupts are disabled, and we can be certain the data
transmission needs more time than one instruction to complete. This
fixes #1463 and replaces #1456.
2013-04-19 03:56:54 -07:00
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// If we get here, nothing is queued anymore (DRIE is disabled) and
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// the hardware finished tranmission (TXC is set).
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2009-06-01 01:32:11 -07:00
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}
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2011-08-26 13:08:14 -07:00
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size_t HardwareSerial::write(uint8_t c)
|
2009-06-01 01:32:11 -07:00
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{
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2013-12-18 14:21:45 -08:00
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// If the buffer and the data register is empty, just write the byte
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// to the data register and be done. This shortcut helps
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// significantly improve the effective datarate at high (>
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// 500kbit/s) bitrates, where interrupt overhead becomes a slowdown.
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if (_tx_buffer_head == _tx_buffer_tail && bit_is_set(*_ucsra, UDRE0)) {
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*_udr = c;
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sbi(*_ucsra, TXC0);
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return 1;
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}
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2014-03-24 13:40:12 -07:00
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tx_buffer_index_t i = (_tx_buffer_head + 1) % SERIAL_TX_BUFFER_SIZE;
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2011-03-05 11:17:26 -08:00
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// If the output buffer is full, there's nothing for it other than to
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// wait for the interrupt handler to empty it a bit
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2013-04-18 12:34:00 -07:00
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|
while (i == _tx_buffer_tail) {
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if (bit_is_clear(SREG, SREG_I)) {
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// Interrupts are disabled, so we'll have to poll the data
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// register empty flag ourselves. If it is set, pretend an
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// interrupt has happened and call the handler to free up
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// space for us.
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if(bit_is_set(*_ucsra, UDRE0))
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_tx_udr_empty_irq();
|
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} else {
|
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|
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// nop, the interrupt handler will free up space for us
|
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|
}
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}
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2013-04-18 09:52:48 -07:00
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_tx_buffer[_tx_buffer_head] = c;
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_tx_buffer_head = i;
|
2011-03-05 11:17:26 -08:00
|
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|
Use constants for register bit positions in HardwareSerial
Previously, the constants to use for the bit positions of the various
UARTs were passed to the HardwareSerial constructor. However, this
meant that whenever these values were used, the had to be indirectly
loaded, resulting in extra code overhead. Additionally, since there is
no instruction to shift a value by a variable amount, the 1 << x
expressions (inside _BV and sbi() / cbi()) would be compiled as a loop
instead of being evaluated at compiletime.
Now, the HardwareSerial class always uses the constants for the bit
positions of UART 0 (and some code is present to make sure these
constants exist, even for targets that only have a single unnumbered
UART or start at UART1).
This was already done for the TXC0 constant, for some reason. For the
actual register addresses, this approach does not work, since these are
of course different between the different UARTs on a single chip.
Of course, always using the UART 0 constants is only correct when the
constants are actually identical for the different UARTs. It has been
verified that this is currently the case for all targets supported by
avr-gcc 4.7.2, and the code contains compile-time checks to verify this
for the current target, in case a new target is added for which this
does not hold. This verification was done using:
for i in TXC RXEN TXEN RXCIE UDRIE U2X UPE; do echo $i; grep --no-filename -r "#define $i[0-9]\? " /usr/lib/avr/include/avr/io* | sed "s/#define $i[0-9]\?\s*\(\S\)\+\s*\(\/\*.*\*\/\)\?$/\1/" | sort | uniq ; done
This command shows that the above constants are identical for all uarts
on all platforms, except for TXC, which is sometimes 6 and sometimes 0.
Further investigation shows that it is always 6, except in io90scr100.h,
but that file defines TXC0 with value 6 for the UART and uses TXC with
value 0 for some USB-related register.
This commit reduces program size on the uno by around 120 bytes.
2013-04-18 05:17:47 -07:00
|
|
|
sbi(*_ucsrb, UDRIE0);
|
Improve HardwareSerial::flush()
The flush() method blocks until all characters in the serial buffer have
been written to the uart _and_ transmitted. This is checked by waiting
until the "TXC" (TX Complete) bit is set by the UART, signalling
completion. This bit is cleared by write() when adding a new byte to the
buffer and set by the hardware after tranmission ends, so it is always
guaranteed to be zero from the moment the first byte in a sequence is
queued until the moment the last byte is transmitted, and it is one from
the moment the last byte in the buffer is transmitted until the first
byte in the next sequence is queued.
However, the TXC bit is also zero from initialization to the moment the
first byte ever is queued (and then continues to be zero until the first
sequence of bytes completes transmission). Unfortunately we cannot
manually set the TXC bit during initialization, we can only clear it. To
make sure that flush() would not (indefinitely) block when it is called
_before_ anything was written to the serial device, the "transmitting"
variable was introduced.
This variable suggests that it is only true when something is
transmitting, which isn't currently the case (it remains true after
transmission is complete until flush() is called, for example).
Furthermore, there is no need to keep the status of transmission, the
only thing needed is to remember if anything has ever been written, so
the corner case described above can be detected.
This commit improves the code by:
- Renaming the "transmitting" variable to _written (making it more
clear and following the leading underscore naming convention).
- Not resetting the value of _written at the end of flush(), there is
no point to this.
- Only checking the "_written" value once in flush(), since it can
never be toggled off anyway.
- Initializing the value of _written in both versions of _begin (though
it probably gets initialized to 0 by default anyway, better to be
explicit).
2013-04-18 12:12:01 -07:00
|
|
|
_written = true;
|
2011-08-23 16:12:03 -07:00
|
|
|
|
|
|
|
return 1;
|
2009-06-01 01:32:11 -07:00
|
|
|
}
|
|
|
|
|
2010-10-17 10:36:02 -07:00
|
|
|
|
|
|
|
#endif // whole file
|