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Style clean up

This commit is contained in:
Alex Lewontin 2020-12-11 12:39:59 -05:00
parent 0b4b1d7542
commit 6faa8b96a9
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GPG Key ID: 52A3855FC3BB8CD7
7 changed files with 345 additions and 362 deletions
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11
os/hal/ports/NUMICRO/LLD/GPIOv1/hal_pal_lld.c
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@ -51,7 +51,6 @@
OSAL_IRQ_HANDLER(NUC123_GPIOAB_HANDLER){ OSAL_IRQ_HANDLER(NUC123_GPIOAB_HANDLER){
OSAL_IRQ_PROLOGUE(); OSAL_IRQ_PROLOGUE();
GPIO_TOGGLE(PB4); GPIO_TOGGLE(PB4);
GPIO_TOGGLE(PB5); GPIO_TOGGLE(PB5);
GPIO_TOGGLE(PB6); GPIO_TOGGLE(PB6);
@ -88,7 +87,7 @@ OSAL_IRQ_HANDLER(NUC123_GPIOCDF_HANDLER){
*/ */
void _pal_lld_init(const PALConfig *config) { void _pal_lld_init(const PALConfig *config) {
//(void)config; /* (void)config; */
/* Turn on GPIO subsystem /* Turn on GPIO subsystem
* Set all GPIO to Input/HZ * Set all GPIO to Input/HZ
* Clear all GPIO Interrupts * Clear all GPIO Interrupts
@ -148,7 +147,7 @@ void _pal_lld_init(const PALConfig *config) {
/* Enable External Crystal Oscillator pins */ /* Enable External Crystal Oscillator pins */
SYS->GPF_MFP |= SYS_GPF_MFP_PF0_XT1_OUT | SYS_GPF_MFP_PF1_XT1_IN; SYS->GPF_MFP |= SYS_GPF_MFP_PF0_XT1_OUT | SYS_GPF_MFP_PF1_XT1_IN;
// SYS->GPD_MFP |= SYS_GPD_MFP_PD10_CLKO; /* SYS->GPD_MFP |= SYS_GPD_MFP_PD10_CLKO; */
/* Enable UART1 data pins */ /* Enable UART1 data pins */
SYS->GPB_MFP |= SYS_GPB_MFP_PB1_UART0_TXD | SYS_GPB_MFP_PB0_UART0_RXD; SYS->GPB_MFP |= SYS_GPB_MFP_PB1_UART0_TXD | SYS_GPB_MFP_PB0_UART0_RXD;
@ -181,10 +180,10 @@ void _pal_lld_setgroupmode(ioportid_t port,
else else
nucMode = GPIO_PMD_QUASI; nucMode = GPIO_PMD_QUASI;
// GPIO_SetMode(port, mask, nucMode); /* GPIO_SetMode(port, mask, nucMode); */
for (uint32_t i = 0; i < PAL_IOPORTS_WIDTH; i++) { for (uint32_t i = 0; i < PAL_IOPORTS_WIDTH; i++) {
// for(uint32_t i = 0; i < GPIO_PINSPERPORT_MAX; i++) { /* for (uint32_t i = 0; i < GPIO_PINSPERPORT_MAX; i++) { */
if(mask & (1 << i)) { if (mask & (1 << i)) {
port->PMD = (port->PMD & ~(0x03ul << (i << 1))) | (nucMode << (i << 1)); port->PMD = (port->PMD & ~(0x03ul << (i << 1))) | (nucMode << (i << 1));
} }
} }

481
os/hal/ports/NUMICRO/LLD/GPIOv1/hal_pal_lld.h
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File diff suppressed because it is too large Load Diff

24
os/hal/ports/NUMICRO/NUC123/hal_lld.c
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@ -60,7 +60,7 @@ void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */
register settings. register settings.
This function can be used to retrieve the system core clock frequeny This function can be used to retrieve the system core clock frequeny
after user changed register sittings. */ after user changed register sittings. */
// SystemCoreClock = SYSTEM_CLOCK; /* SystemCoreClock = SYSTEM_CLOCK; */
uint32_t clkFreq; uint32_t clkFreq;
uint32_t PllReg; uint32_t PllReg;
@ -68,7 +68,7 @@ void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */
uint32_t pllFIN, pllNF, pllNR, pllNO; uint32_t pllFIN, pllNF, pllNR, pllNO;
/* Update PLL Clock */ /* Update PLL Clock */
// PllClock = clks_lld_get_pll_clock_freq(); /* PllClock = clks_lld_get_pll_clock_freq(); */
PllReg = CLK->PLLCON; PllReg = CLK->PLLCON;
if (PllReg & (CLK_PLLCON_PD_Msk | CLK_PLLCON_OE_Msk)) { if (PllReg & (CLK_PLLCON_PD_Msk | CLK_PLLCON_OE_Msk)) {
@ -106,19 +106,19 @@ void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */
/* Pick Clock Source */ /* Pick Clock Source */
switch (CLK->CLKSEL0 & CLK_CLKSEL0_HCLK_S_Msk) { switch (CLK->CLKSEL0 & CLK_CLKSEL0_HCLK_S_Msk) {
case 0: // External HF Xtal case 0: /* External HF Xtal */
clkFreq = __HXT; clkFreq = __HXT;
break; break;
case 1: // PLL clock / 2 case 1: /* PLL clock / 2 */
clkFreq = PllClock >> 1; clkFreq = PllClock >> 1;
break; break;
case 3: // Internal 10kHz case 3: /* Internal 10kHz */
clkFreq = __LIRC; clkFreq = __LIRC;
break; break;
case 2: // PLL clock case 2: /* PLL clock */
clkFreq = PllClock; clkFreq = PllClock;
break; break;
case 7: // Internal 22.184MHz case 7: /* Internal 22.184MHz */
clkFreq = __HIRC; clkFreq = __HIRC;
break; break;
default: default:
@ -157,13 +157,13 @@ static inline uint32_t get_pll_clock_freq(void)
PllClock = pllFIN; PllClock = pllFIN;
} else { } else {
switch (((PllReg & CLK_PLLCON_OUT_DV_Msk) >> CLK_PLLCON_OUT_DV_Pos)) { switch (((PllReg & CLK_PLLCON_OUT_DV_Msk) >> CLK_PLLCON_OUT_DV_Pos)) {
case 0: // OUT_DIV == 00 : NO = 1 case 0: /* OUT_DIV == 00 : NO = 1 */
pllNO = 1; pllNO = 1;
break; break;
case 3: // OUT_DIV == 11 : NO = 4 case 3: /* OUT_DIV == 11 : NO = 4 */
pllNO = 4; pllNO = 4;
break; break;
default: // OUT_DIV == 01 or 10 : NO = 2 default: /* OUT_DIV == 01 or 10 : NO = 2 */
pllNO = 2; pllNO = 2;
break; break;
} }
@ -171,7 +171,7 @@ static inline uint32_t get_pll_clock_freq(void)
pllNF = ((PllReg & CLK_PLLCON_FB_DV_Msk) >> CLK_PLLCON_FB_DV_Pos) + 2; pllNF = ((PllReg & CLK_PLLCON_FB_DV_Msk) >> CLK_PLLCON_FB_DV_Pos) + 2;
pllNR = ((PllReg & CLK_PLLCON_IN_DV_Msk) >> CLK_PLLCON_IN_DV_Pos) + 2; pllNR = ((PllReg & CLK_PLLCON_IN_DV_Msk) >> CLK_PLLCON_IN_DV_Pos) + 2;
/* shift to avoid overflow condition */ /* Shift to avoid overflow condition */
PllClock = (((pllFIN >> 2) * pllNF) / (pllNR * pllNO) << 2); PllClock = (((pllFIN >> 2) * pllNF) / (pllNR * pllNO) << 2);
} }
} }
@ -385,7 +385,7 @@ static uint32_t enable_pll(uint32_t pllSrc, uint32_t pllFreq)
/** @brief Set Core Clock /** @brief Set Core Clock
* *
* @description Set the core system clock some reference speed (Hz). * @description Set the core system clock some reference speed (Hz).
* This should be between 25MHz and 72MHz. * This should be between 25MHz and 72MHz for the NUC123SD4AN0.
* *
* Use either the HXT (exact) or HIRC (nearest using 22.1184MHz) * Use either the HXT (exact) or HIRC (nearest using 22.1184MHz)
* as the clock source. * as the clock source.

2
os/hal/ports/NUMICRO/NUC123/nuc123_isr.h
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@ -37,13 +37,11 @@
/* /*
* GPIO units. * GPIO units.
*/ */
#if defined(NUC123SD4AN0)
#define NUC123_GPIOAB_HANDLER Vector50 #define NUC123_GPIOAB_HANDLER Vector50
#define NUC123_GPIOCDF_HANDLER Vector54 #define NUC123_GPIOCDF_HANDLER Vector54
#define NUC123_GPIOAB_NUMBER GPAB_IRQn #define NUC123_GPIOAB_NUMBER GPAB_IRQn
#define NUC123_GPIOCDF_NUMBER GPCDF_IRQn #define NUC123_GPIOCDF_NUMBER GPCDF_IRQn
#endif
/* /*
* Special ST unit * Special ST unit

10
os/hal/ports/NUMICRO/NUC123/nuc123_registry.h
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@ -95,8 +95,8 @@
#define NUC123_HAS_ETH FALSE #define NUC123_HAS_ETH FALSE
/* EXTI attributes.*/ /* EXTI attributes.*/
//#define NUC123_EXTI_NUM_LINES 20 /* #define NUC123_EXTI_NUM_LINES 20 */
//#define NUC123_EXTI_IMR_MASK 0xFFF50000U /* #define NUC123_EXTI_IMR_MASK 0xFFF50000U */
/* GPIO attributes.*/ /* GPIO attributes.*/
#define NUC123_HAS_GPIOA TRUE #define NUC123_HAS_GPIOA TRUE
@ -199,7 +199,7 @@
#define NUC123_HAS_TIM22 FALSE #define NUC123_HAS_TIM22 FALSE
/* USART attributes.*/ /* USART attributes.*/
/*#define NUC123_HAS_USART1 TRUE /* #define NUC123_HAS_USART1 TRUE
#define NUC123_USART1_RX_DMA_MSK (NUC123_DMA_STREAM_ID_MSK(1, 1) |\ #define NUC123_USART1_RX_DMA_MSK (NUC123_DMA_STREAM_ID_MSK(1, 1) |\
NUC123_DMA_STREAM_ID_MSK(1, 3) |\ NUC123_DMA_STREAM_ID_MSK(1, 3) |\
NUC123_DMA_STREAM_ID_MSK(1, 5)) NUC123_DMA_STREAM_ID_MSK(1, 5))
@ -215,8 +215,8 @@
#define NUC123_USART2_RX_DMA_CHN 0x00090909 #define NUC123_USART2_RX_DMA_CHN 0x00090909
#define NUC123_USART2_TX_DMA_MSK (NUC123_DMA_STREAM_ID_MSK(1, 2) |\ #define NUC123_USART2_TX_DMA_MSK (NUC123_DMA_STREAM_ID_MSK(1, 2) |\
NUC123_DMA_STREAM_ID_MSK(1, 4)) NUC123_DMA_STREAM_ID_MSK(1, 4))
#define NUC123_USART2_TX_DMA_CHN 0x00009090 #define NUC123_USART2_TX_DMA_CHN 0x00009090 */
*/
#define NUC123_HAS_USART1 FALSE #define NUC123_HAS_USART1 FALSE
#define NUC123_HAS_USART2 FALSE #define NUC123_HAS_USART2 FALSE
#define NUC123_HAS_USART3 FALSE #define NUC123_HAS_USART3 FALSE

3
testhal/NUMICRO/NUC123/NUTINY-SDK-NUC123-V2.0/Blinky/readme.txt
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@ -1,5 +1,5 @@
***************************************************************************** *****************************************************************************
** ChibiOS/HAL - USB driver demo for NUC123. ** ** ChibiOS/HAL - Blinky demo for NUC123. **
***************************************************************************** *****************************************************************************
** TARGET ** ** TARGET **
@ -12,7 +12,6 @@ The application demonstrates the use of the NUC123 platform driver, and a little
bit of the PAL. A successful run of the test involves the on-board LED blinking at .5 Hz bit of the PAL. A successful run of the test involves the on-board LED blinking at .5 Hz
(on for 1 second, then off for one second). (on for 1 second, then off for one second).
** Board Setup ** ** Board Setup **
- None - None