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Style clean up

This commit is contained in:
Alex Lewontin 2020-12-11 12:39:59 -05:00
parent 0b4b1d7542
commit 6faa8b96a9
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GPG Key ID: 52A3855FC3BB8CD7
7 changed files with 345 additions and 362 deletions
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9
os/hal/ports/NUMICRO/LLD/GPIOv1/hal_pal_lld.c
View File

@ -51,7 +51,6 @@
OSAL_IRQ_HANDLER(NUC123_GPIOAB_HANDLER){
OSAL_IRQ_PROLOGUE();
GPIO_TOGGLE(PB4);
GPIO_TOGGLE(PB5);
GPIO_TOGGLE(PB6);
@ -88,7 +87,7 @@ OSAL_IRQ_HANDLER(NUC123_GPIOCDF_HANDLER){
*/
void _pal_lld_init(const PALConfig *config) {
//(void)config;
/* (void)config; */
/* Turn on GPIO subsystem
* Set all GPIO to Input/HZ
* Clear all GPIO Interrupts
@ -148,7 +147,7 @@ void _pal_lld_init(const PALConfig *config) {
/* Enable External Crystal Oscillator pins */
SYS->GPF_MFP |= SYS_GPF_MFP_PF0_XT1_OUT | SYS_GPF_MFP_PF1_XT1_IN;
// SYS->GPD_MFP |= SYS_GPD_MFP_PD10_CLKO;
/* SYS->GPD_MFP |= SYS_GPD_MFP_PD10_CLKO; */
/* Enable UART1 data pins */
SYS->GPB_MFP |= SYS_GPB_MFP_PB1_UART0_TXD | SYS_GPB_MFP_PB0_UART0_RXD;
@ -181,9 +180,9 @@ void _pal_lld_setgroupmode(ioportid_t port,
else
nucMode = GPIO_PMD_QUASI;
// GPIO_SetMode(port, mask, nucMode);
/* GPIO_SetMode(port, mask, nucMode); */
for (uint32_t i = 0; i < PAL_IOPORTS_WIDTH; i++) {
// for(uint32_t i = 0; i < GPIO_PINSPERPORT_MAX; i++) {
/* for (uint32_t i = 0; i < GPIO_PINSPERPORT_MAX; i++) { */
if (mask & (1 << i)) {
port->PMD = (port->PMD & ~(0x03ul << (i << 1))) | (nucMode << (i << 1));
}

23
os/hal/ports/NUMICRO/LLD/GPIOv1/hal_pal_lld.h
View File

@ -66,7 +66,6 @@
#define PAL_MODE_NUC123_ALTERNATE_QUASI GPIO_PMD_QUASI
/** @} */
/**
* @brief Alternate GPIO pin defines
*
@ -75,7 +74,6 @@
*
*/
/**
* GPIO Port A Alternative Pin Modes
*
@ -201,7 +199,6 @@
#define SYS_ALT_MFP_PA15_Msk (0x01ul << SYS_ALT_MFP_PA15_MFP1_Pos)
#define SYS_ALT_MFP1_PA15_Msk NULL
/**
* GPIO Port B Alternative Pin Modes
*
@ -487,7 +484,6 @@
#define SYS_ALT_MFP_PB15_Msk (0x01ul << SYS_ALT_MFP_PB15_MFP1_Pos)
#define SYS_ALT_MFP1_PB15_Msk NULL
/**
* GPIO Port C Alternative Pin Modes
*
@ -728,7 +724,6 @@
#define SYS_ALT_MFP_PC13_Msk (0x01ul << SYS_ALT_MFP_PC13_MFP1_Pos)
#define SYS_ALT_MFP1_PC13_Msk NULL
/**
* GPIO Port D Alternative Pin Modes
*
@ -924,7 +919,6 @@
#define SYS_ALT_MFP_PD11_Msk NULL
#define SYS_ALT_MFP1_PD11_Msk NULL
/**
* GPIO Port F Alternative Pin Modes
*
@ -1010,7 +1004,6 @@
#define SYS_ALT_MFP_PF3_Msk NULL
#define SYS_ALT_MFP1_PF3_Msk (0x03ul << SYS_ALT_MFP1_PF3_MFP1_Pos)
/*
#undef PAL_MODE_RESET
#undef PAL_MODE_UNCONNECTED
@ -1040,7 +1033,8 @@
#define GPIO_PINSPERPORT_MAX 16
/* GPIO PORT/PIN TO BASE ADDRESS MACRO */
#define GPIO_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2))))
#define GPIO_PIN_DATA(port, pin) \
(*((volatile uint32_t *)((GPIO_PIN_DATA_BASE + (0x40 * (port))) + ((pin) << 2))))
/* GPIO Port A (10~15) */
#define PA10 GPIO_PIN_DATA(0, 10)
@ -1099,7 +1093,6 @@
#define PF2 GPIO_PIN_DATA(5, 2)
#define PF3 GPIO_PIN_DATA(5, 3)
/**
* @name Port Abstraction Layer related definitions
* @{
@ -1113,7 +1106,7 @@
* @brief Whole port mask.
* @details This macro specifies all the valid bits into a port.
*/
//#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFU)
/* #define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFU) */
#define PAL_WHOLE_PORT ((ioportmask_t)(2^PAL_IOPORTS_WIDTH) - 1)
/** @} */
@ -1254,7 +1247,6 @@ typedef GPIO_T * ioportid_t;
*/
#define pal_lld_writeport(port, bits) (port->DOUT = bits)
/**
* @brief Sets a bits mask on a I/O port.
* @note The @ref PAL provides a default software implementation of this
@ -1268,7 +1260,6 @@ typedef GPIO_T * ioportid_t;
*/
#define pal_lld_setport(port, bits) (port->DOUT |= bits)
/**
* @brief Clears a bits mask on a I/O port.
* @note The @ref PAL provides a default software implementation of this
@ -1282,7 +1273,6 @@ typedef GPIO_T * ioportid_t;
*/
#define pal_lld_clearport(port, bits) (port->DOUT &= ~bits)
/**
* @brief Toggles a bits mask on a I/O port.
* @note The @ref PAL provides a default software implementation of this
@ -1309,7 +1299,7 @@ typedef GPIO_T * ioportid_t;
*
* @notapi
*/
//#define pal_lld_readgroup(port, mask, offset) 0U
/* #define pal_lld_readgroup(port, mask, offset) 0U */
/**
* @brief Writes a group of bits.
@ -1417,7 +1407,6 @@ typedef GPIO_T * ioportid_t;
#define pal_lld_setpad(port, pad) \
(port->DOUT |= PAL_PORT_BIT(pad))
/**
* @brief Clears a pad logical state to @p PAL_LOW.
* @note The @ref PAL provides a default software implementation of this
@ -1432,7 +1421,6 @@ typedef GPIO_T * ioportid_t;
#define pal_lld_clearpad(port, pad) \
(port->DOUT &= ~(0xFFFF0000U | PAL_PORT_BIT(pad)))
/**
* @brief Toggles a pad logical state.
* @note The @ref PAL provides a default software implementation of this
@ -1447,7 +1435,6 @@ typedef GPIO_T * ioportid_t;
#define pal_lld_togglepad(port, pad) \
(port->DOUT ^= PAL_PORT_BIT(pad))
/**
* @brief Pad mode setup.
* @details This function programs a pad with the specified mode.
@ -1464,7 +1451,7 @@ typedef GPIO_T * ioportid_t;
*/
#define pal_lld_setpadmode(port, pad, mode) \
_pal_lld_setgroupmode(port, PAL_PORT_BIT(pad), mode)
//GPIO_SetMode(port, PAL_PORT_BIT(pad), mode)
/* GPIO_SetMode(port, PAL_PORT_BIT(pad), mode) */
#if !defined(__DOXYGEN__)
extern const PALConfig pal_default_config;

24
os/hal/ports/NUMICRO/NUC123/hal_lld.c
View File

@ -60,7 +60,7 @@ void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */
register settings.
This function can be used to retrieve the system core clock frequeny
after user changed register sittings. */
// SystemCoreClock = SYSTEM_CLOCK;
/* SystemCoreClock = SYSTEM_CLOCK; */
uint32_t clkFreq;
uint32_t PllReg;
@ -68,7 +68,7 @@ void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */
uint32_t pllFIN, pllNF, pllNR, pllNO;
/* Update PLL Clock */
// PllClock = clks_lld_get_pll_clock_freq();
/* PllClock = clks_lld_get_pll_clock_freq(); */
PllReg = CLK->PLLCON;
if (PllReg & (CLK_PLLCON_PD_Msk | CLK_PLLCON_OE_Msk)) {
@ -106,19 +106,19 @@ void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */
/* Pick Clock Source */
switch (CLK->CLKSEL0 & CLK_CLKSEL0_HCLK_S_Msk) {
case 0: // External HF Xtal
case 0: /* External HF Xtal */
clkFreq = __HXT;
break;
case 1: // PLL clock / 2
case 1: /* PLL clock / 2 */
clkFreq = PllClock >> 1;
break;
case 3: // Internal 10kHz
case 3: /* Internal 10kHz */
clkFreq = __LIRC;
break;
case 2: // PLL clock
case 2: /* PLL clock */
clkFreq = PllClock;
break;
case 7: // Internal 22.184MHz
case 7: /* Internal 22.184MHz */
clkFreq = __HIRC;
break;
default:
@ -157,13 +157,13 @@ static inline uint32_t get_pll_clock_freq(void)
PllClock = pllFIN;
} else {
switch (((PllReg & CLK_PLLCON_OUT_DV_Msk) >> CLK_PLLCON_OUT_DV_Pos)) {
case 0: // OUT_DIV == 00 : NO = 1
case 0: /* OUT_DIV == 00 : NO = 1 */
pllNO = 1;
break;
case 3: // OUT_DIV == 11 : NO = 4
case 3: /* OUT_DIV == 11 : NO = 4 */
pllNO = 4;
break;
default: // OUT_DIV == 01 or 10 : NO = 2
default: /* OUT_DIV == 01 or 10 : NO = 2 */
pllNO = 2;
break;
}
@ -171,7 +171,7 @@ static inline uint32_t get_pll_clock_freq(void)
pllNF = ((PllReg & CLK_PLLCON_FB_DV_Msk) >> CLK_PLLCON_FB_DV_Pos) + 2;
pllNR = ((PllReg & CLK_PLLCON_IN_DV_Msk) >> CLK_PLLCON_IN_DV_Pos) + 2;
/* shift to avoid overflow condition */
/* Shift to avoid overflow condition */
PllClock = (((pllFIN >> 2) * pllNF) / (pllNR * pllNO) << 2);
}
}
@ -385,7 +385,7 @@ static uint32_t enable_pll(uint32_t pllSrc, uint32_t pllFreq)
/** @brief Set Core Clock
*
* @description Set the core system clock some reference speed (Hz).
* This should be between 25MHz and 72MHz.
* This should be between 25MHz and 72MHz for the NUC123SD4AN0.
*
* Use either the HXT (exact) or HIRC (nearest using 22.1184MHz)
* as the clock source.

2
os/hal/ports/NUMICRO/NUC123/nuc123_isr.h
View File

@ -37,13 +37,11 @@
/*
* GPIO units.
*/
#if defined(NUC123SD4AN0)
#define NUC123_GPIOAB_HANDLER Vector50
#define NUC123_GPIOCDF_HANDLER Vector54
#define NUC123_GPIOAB_NUMBER GPAB_IRQn
#define NUC123_GPIOCDF_NUMBER GPCDF_IRQn
#endif
/*
* Special ST unit

8
os/hal/ports/NUMICRO/NUC123/nuc123_registry.h
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@ -95,8 +95,8 @@
#define NUC123_HAS_ETH FALSE
/* EXTI attributes.*/
//#define NUC123_EXTI_NUM_LINES 20
//#define NUC123_EXTI_IMR_MASK 0xFFF50000U
/* #define NUC123_EXTI_NUM_LINES 20 */
/* #define NUC123_EXTI_IMR_MASK 0xFFF50000U */
/* GPIO attributes.*/
#define NUC123_HAS_GPIOA TRUE
@ -215,8 +215,8 @@
#define NUC123_USART2_RX_DMA_CHN 0x00090909
#define NUC123_USART2_TX_DMA_MSK (NUC123_DMA_STREAM_ID_MSK(1, 2) |\
NUC123_DMA_STREAM_ID_MSK(1, 4))
#define NUC123_USART2_TX_DMA_CHN 0x00009090
*/
#define NUC123_USART2_TX_DMA_CHN 0x00009090 */
#define NUC123_HAS_USART1 FALSE
#define NUC123_HAS_USART2 FALSE
#define NUC123_HAS_USART3 FALSE

3
testhal/NUMICRO/NUC123/NUTINY-SDK-NUC123-V2.0/Blinky/readme.txt
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@ -1,5 +1,5 @@
*****************************************************************************
** ChibiOS/HAL - USB driver demo for NUC123. **
** ChibiOS/HAL - Blinky demo for NUC123. **
*****************************************************************************
** TARGET **
@ -12,7 +12,6 @@ The application demonstrates the use of the NUC123 platform driver, and a little
bit of the PAL. A successful run of the test involves the on-board LED blinking at .5 Hz
(on for 1 second, then off for one second).
** Board Setup **
- None