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Merge pull request #277 from KarlK90/risc-v-eclic-t0-restore-fix 

[RISC-V ECLIC] Fix t0 restore when exiting interrupt
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Fabien Poussin 2021-04-26 16:59:35 +02:00 committed by GitHub
parent d53c82a884 0a66a0660b
commit 9c2bfa6aeb
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1 changed files with 7 additions and 7 deletions
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14
os/common/ports/RISCV-ECLIC/compilers/GCC/chcoreasm.S
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@ -103,6 +103,13 @@
# registers and status csr registers from stack.
# --------------------------------------------------------------------------
.macro RESTORE_CONTEXT
LOAD t0, 17*REGBYTES(sp)
csrw CSR_MEPC, t0
LOAD t0, 18*REGBYTES(sp)
csrw CSR_MCAUSE, t0
LOAD t0, 19*REGBYTES(sp)
csrw CSR_MSUBM, t0
LOAD ra, 0*REGBYTES(sp)
LOAD tp, 1*REGBYTES(sp)
LOAD t0, 2*REGBYTES(sp)
@ -121,13 +128,6 @@
LOAD t5, 15*REGBYTES(sp)
LOAD t6, 16*REGBYTES(sp)
LOAD t0, 17*REGBYTES(sp)
csrw CSR_MEPC, t0
LOAD t0, 18*REGBYTES(sp)
csrw CSR_MCAUSE, t0
LOAD t0, 19*REGBYTES(sp)
csrw CSR_MSUBM, t0
# De-allocate the stack space
addi sp, sp, 20*REGBYTES
.endm