bb254fb11c
Fixed 75/300 R3 hwconf
2020-04-06 13:09:09 +02:00
76fd7a3917
Added COMM_SET_CAN_MODE and added support for HW75_300_R3
2020-04-04 22:28:41 +02:00
8a76c9aaf4
Axiom: Add resolver build switch
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For some reason SPI encoder was not set by default in axiom builds.
Signed-off-by: Marcos Chaparro <mchaparro@powerdesigns.ca>
2020-01-20 11:01:21 -03:00
356f3db20e
Add Break function for instant PWM disable
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When enabled, the Break (or BRK) is a mechanism that upon a active
level in the TIMx_BRK pin disables asynchronously the PWM output pins,
achieving fast reaction times when an external fault even happens.
See AN4277.
Signed-off-by: Marcos Chaparro <mchaparro@paltatech.com>
2020-01-19 15:36:40 -03:00
08de81e950
Add basic support for Luna BBSHD
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Signed-off-by: Marcos Chaparro <mchaparro@paltatech.com>
2020-01-19 15:36:40 -03:00
b002e5d78e
FW 3.66: Many changes, see changelog
2020-01-12 21:25:21 +01:00
210ec40d74
PTC motor thermistor support, APP_PPM sleep fix
2019-12-22 21:22:07 +01:00
ceb8b7bf7d
HW60_MK3 support, shutdown fix, added COMM_SET_CURRENT_REL, ramp fix, PPM timeout fix, IRQ prio fix
2019-12-19 16:55:38 +01:00
78d3cef3ff
Added support for HW60_MK3 and disable shutdown when watchdog runs slowly
2019-12-09 10:57:33 +01:00
23e61925b6
FW upload compression support, TS5700N8501 support
2019-12-05 19:50:17 +01:00
61fb33f17e
Fix phase voltage sense gain and add HASS 400-S current sensor
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Signed-off-by: Marcos Chaparro <mchaparro@powerdesigns.ca>
2019-10-29 09:54:25 -03:00
f8279e4583
Axiom: Add FPGA image
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Signed-off-by: Marcos Chaparro <mchaparro@powerdesigns.ca>
2019-10-29 09:43:06 -03:00
9fd6844e36
Axiom: FPGA image compression
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Reduces the binary blob size from 104kB to 5kB.
Signed-off-by: Marcos Chaparro <mchaparro@powerdesigns.ca>
2019-10-29 09:22:53 -03:00
dfc3ed2319
Final v3.62
2019-09-27 12:56:49 +02:00
c875d4f3ee
Add hwconf for A200S V2
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Adds hwconf files for A200S V2.1 and V2.2
2019-09-15 00:48:20 +01:00
602db7435b
FW3.59. Many updates, see changelog for details
2019-09-03 20:39:05 +02:00
b4f8cd1a87
Fixed compilation of HW_40 and HW_45
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ADC_IND_TEMP_MOS was missing for both and has been added
ADC_IND_TEMP_MOTOR has been added for HW_40
2019-07-24 23:11:00 +02:00
90dee2b31e
Axiom: Individual IGBT temperature monitoring
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Signed-off-by: Marcos Chaparro <mchaparro@powerdesigns.ca>
2019-05-09 19:12:54 -03:00
05b1a9483e
Merge branch 'Axiom-board-support' of https://github.com/powerdesigns/bldc into powerdesigns-Axiom-board-support
2019-05-04 10:44:03 +02:00
404bbcf64b
Fixed current offset fault bug, added support for multiple IMUs and ICM-20948
2019-05-03 19:55:36 +02:00
4d93f2fef1
Axiom: configurable current sensor gain
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Signed-off-by: Marcos Chaparro <mchaparro@powerdesigns.ca>
2019-04-27 16:57:35 -03:00
1d08745376
Axiom control board support
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Rename paltatech naming to Axiom.
For safety set Axiom default max input voltage to 0.0V so it can not run a
motor without mc_conf being explicitly configured by the user.
Signed-off-by: Marcos Chaparro <mchaparro@powerdesigns.ca>
2019-04-27 08:21:46 -03:00
8313b32c0c
Some fixes on PR
2019-04-26 12:02:57 +02:00
1e4078a713
Merge pull request #88 from paltatech/current-sensor-fault-detection
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Detect current sensor failures
2019-04-26 11:25:30 +02:00
0551117351
Some HW cleanup and documentation, fixed DRV8301 fault readout bug, added mpu_read_reg terminal command
2019-04-26 11:07:31 +02:00
6d758b38f2
Detect current sensor failures
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2 failure modes added:
* On boot, when calculating DC offsets generate a fault if the offset is beyond
HW_MAX_CURRENT_OFFSET. Fault code reports which sensor is having issues (1, 2 or 3).
Most likely cause is a disconnected sensor, if hw has fault-detecting pullups.
* On runtime, in setups with 3 in-line phase current sensors, checks that the sum
of the currents is below MCCONF_MAX_CURRENT_UNBALANCE, with a configurable low pass
filter. If unbalanced current is high, it means a fault to ground, or a disconnected
sensor (this works at 0 Amp if hw has pullups in the sensor input to detect the
failure).
Signed-off-by: Marcos Chaparro <mchaparro@powerdesigns.ca>
2019-04-20 09:43:08 -03:00
8ec5723f89
Merge pull request #82 from paltatech/virtual-motor
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Add command to connect a virtual motor with configurable parameters
2019-04-14 07:24:23 +02:00
8c4fc35ca0
Move sin/cos signal pin definitions to hwconf/
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Signed-off-by: Marcos Chaparro <mchaparro@powerdesigns.ca>
2019-04-08 18:59:07 -03:00
4a94d0ec4c
Add command to connect a virtual motor with configurable parameters
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This commit adds a motor model running within the vesc firmware,and
from the vesc terminal a user or a test script can set the
mechanical load torque, inertia, phase resistance, Lq and Ld phase
inductances (this generic model includes IPM motors), flux linkage
and battery voltage.
Virtual motor parameters set at the command line should match with
vesc configuration, for example phase resistance, inductance and
flux linkage should match and have the correct observer gain.
Observer works with the virtual motor, with some hiccups during
startup
For solid results its better to use sensored mode. If vesc is
configured to use an SPI encoder the virtual motor phase angle
will be injected as an encoder angle readout.
For safety PWM outputs are disabled during simulation.
Signed-off-by: Maximiliano Cordoba <mcordoba@powerdesigns.ca>
2019-04-06 10:36:00 -03:00
b155d5219a
Basic SinCos encoder support
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Reads sine and cosine on ADC_IND_EXT and ADC_IND_EXT2, usually
used for ACCEL and REGEN inputs. Provides offset and gain
compensation and is implemented using floating point math.
Note it includes the full mc_interface.h into encoder.c only
to access the ADC readings, and no filtering is performed on
the signals.
Signed-off-by: Marcos Chaparro <mchaparro@powerdesigns.ca>
2019-04-01 08:35:22 -03:00
3ab585cb9a
Force high current measuments when using big powerstages
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Signed-off-by: Marcos Chaparro <mchaparro@powerdesigns.ca>
2019-03-28 20:33:21 -03:00
b2311b9eca
Extend support to older PowerDesigns RevB boards
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Signed-off-by: Marcos Chaparro <mchaparro@powerdesigns.ca>
2019-03-25 18:02:26 -03:00
39bb8a6b09
FW 3.53: Limit foc_current_filter_const range, 1Mbit/de NRF speed, lower detect f_sw for resistance, no temp_comp by default
2019-03-20 22:46:36 +01:00
65298263b6
75/300 R2 support, terminal sync cmd, IMU support, option to disable permanent UART, collected timer functions in one place
2019-03-10 14:57:42 +01:00
35c1c72ab4
Commands restructuring for thread safety, 75/300 vreg fix, fixed relative current commands
2019-03-04 19:23:38 +01:00
01e72eb555
Autogenerated config parsing with signatures, fixed previous PRs
2019-03-01 21:36:58 +01:00
723abcb09f
Remove ST DAC library and use the DAC by direct register access
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Signed-off-by: Marcos Chaparro <mchaparro@powerdesigns.ca>
2019-02-19 11:40:49 -03:00
b344e873b6
Remove duplicated flux linkage detection function
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Signed-off-by: Marcos Chaparro <mchaparro@powerdesigns.ca>
2019-02-19 10:55:40 -03:00
32cf05629d
Resolve merge conficts with major 2019 release
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Signed-off-by: Marcos Chaparro <mchaparro@powerdesigns.ca>
2019-02-18 20:25:52 -03:00
123bb00ab4
Major 2019 update
2019-02-18 19:30:19 +01:00
4ac69232d9
Configure deadtime by just defining it in nanoseconds. Firmware will calculate the required DTG register value.
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Signed-off-by: Marcos Chaparro <mchaparro@powerdesigns.ca>
2019-01-31 00:51:35 -03:00
9652231edb
Allow to run PWM at frequencies multiples FOC loop to support applications with PWM running at 100+kHz.
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Signed-off-by: Marcos Chaparro <mchaparro@powerdesigns.ca>
2019-01-30 00:33:56 -03:00
43dbe80de5
Fix DAC init assertion
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Signed-off-by: Marcos Chaparro <mchaparro@powerdesigns.ca>
2019-01-28 02:21:47 -03:00
69bdc73536
Put a safe limit on ADC ISR frequency to avoid kernel panics. Currently ADC ISR duration is around 26usec, it can not be executed at more than 38kHz
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Signed-off-by: Marcos Chaparro <mchaparro@powerdesigns.ca>
2019-01-26 02:36:12 -03:00
834056a9e5
Use ice40UP5K FPGA bitstream length
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Signed-off-by: Marcos Chaparro <mchaparro@paltatech.com>
2019-01-18 19:02:18 -03:00
95d8f70f87
Define on build-time some basic limits for this hardware
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Signed-off-by: Marcos Chaparro <mchaparro@paltatech.com>
2019-01-10 18:22:47 -03:00
34bacefe99
Configure Brown Out Reset to keep mcu under reset until VDD reaches 2.7V. Configure Programmable Voltage Detector to interrupt and log a fault when mcu VDD drops below 2.9V.
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Signed-off-by: Marcos Chaparro <mchaparro@paltatech.com>
2019-01-08 11:36:42 -03:00
8152d61760
New flux linkage measurement based on open loop FOC to spin up the motor. Removes all calls to BLDC mode to reach the requested erpm
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Signed-off-by: Marcos Chaparro <mchaparro@paltatech.com>
2019-01-05 19:24:42 -03:00
89e6022698
Gate driver supply voltage monitoring
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Signed-off-by: Marcos Chaparro <mchaparro@paltatech.com>
2018-12-12 20:03:12 -03:00
e284d1ae5e
Compensate for line-to-line measurement in FOC
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Signed-off-by: Marcos Chaparro <mchaparro@paltatech.com>
2018-12-12 18:41:10 -03:00
Benjamin Vedder
Marcos Chaparro
Marcos Chaparro
Euan
Michael Albrecht
Maximiliano Cordoba