Commit Graph

111 Commits

Author SHA1 Message Date
rusefillc d1a2ee2b5b
Rev 2: default settings for LSU4.9 (#99)
* Rev 2: default settings for LSU4.9

* Rev2: LSU 4.2 and ADV ESR drive pins

Co-authored-by: Andrey Gusakov <dron0gus@gmail.com>
2022-07-03 00:00:17 -07:00
rusefillc 1efc499126
Rev2: GD32 ADC workaround (#96)
Co-authored-by: Andrey Gusakov <dron0gus@gmail.com>
2022-07-02 13:48:27 -07:00
rusefillc 0430e4a7ba
board: common make script (#73)
* board: common make script

(cherry picked from commit cb087c60e9)

* common_make -> build_f1_board

* f1_rev2: use build_f1_board.sh helper

* Add encedo hex2dfu tools (bin for linux and win)

See https://github.com/encedo/hex2dfu

* Makefile: priduce srec too

* f1_rev2: OpenBLT: build bin and hex files

* f1_rev2: OpenBLT: optimize for size to fit into 8K flash

Co-authored-by: Andrey Gusakov <dron0gus@gmail.com>
2022-07-02 13:47:55 -07:00
rusefillc 2fa9549d83
0701 rev2 2 (#91)
* Rev 2: VM_RESISTOR_VALUE

(cherry picked from commit 84ae91fc67cf6764afd5b00210edbc3cfe4444a5)

* Rev 2: default settings for LSU4.9

(cherry picked from commit 5a1fe84bc1ec8d7ee6e0a5f2906a1b18d2ff8a8e)

* Per-board VM_RESISTOR_VALUE

(cherry picked from commit 0bdd19e058db579bed13488066df1176ea9addb2)

* Rev2: ID correct pins

(cherry picked from commit 59e4b36ad9bc7c166c3dae7e25b6317caf562056)

* Rev2: LSU 4.2 and ADV ESR drive pins

(cherry picked from commit 2f2b4399431136951fe2fa6819f44ba28c3cda17)

* Rev2: aux pwm pins: no need to be 50MHz fast

(cherry picked from commit b0af5c07c391438ca561118174df498207255f3b)

Co-authored-by: Andrey Gusakov <dron0gus@gmail.com>
2022-07-01 15:57:05 -07:00
rusefillc 076406e4b0
f1_rev2: add OpenBLT (#92)
(cherry picked from commit 85e1ac8e5e75e22b247db0f5a512656453425729)

Co-authored-by: Andrey Gusakov <dron0gus@gmail.com>
2022-07-01 12:12:24 -07:00
Andrey G d3d260b828
f1_rev2: set O0 optimization level due to issue with ADC on GD32 (#94) 2022-07-01 12:10:28 -07:00
Andrey G 5ec79b52a5
f1_rev2: this is single channel board (#93) 2022-07-01 12:03:48 -07:00
rusefillc 7d8eaab3d1
Min rev2 (#90)
* Board Rev 2

(cherry picked from commit 2f1e2bd3e27fdfd43f0ccf8292aacfb1194060fc)

* CI good

(cherry picked from commit 2163af402ebc40f76fa53ac8f1648949b12aa50f)

* min r2

* min r2

Co-authored-by: Andrey Gusakov <dron0gus@gmail.com>
Co-authored-by: rusefillc <sdfsdfqsf2334234234>
2022-07-01 01:17:04 -07:00
rusefillc fad49f553f
Crc bootloader (#88)
* more code reuse

* more code reuse

* more code reuse

* more code reuse

* more code reuse

* more code reuse

* make it compile and actually include all the functions

Co-authored-by: rusefillc <sdfsdfqsf2334234234>
Co-authored-by: Matthew Kennedy <makenne@microsoft.com>
2022-06-30 10:07:33 -07:00
rusefillc e34094e13d
Prepare for multi-channel boards (#72)
* Prepare for multi-channel boards

(cherry picked from commit 8b713cebfc)

* this belongs in wideband_board_config.h they say

Co-authored-by: Andrey Gusakov <dron0gus@gmail.com>
Co-authored-by: rusefillc <sdfsdfqsf2334234234>
2022-06-24 14:51:22 -07:00
rusefillc f6b4b3a34c
f1_dave: PA1 is pump PWM output, should be alternate (#75)
(cherry picked from commit b31e642943)

Co-authored-by: Andrey Gusakov <dron0gus@gmail.com>
2022-06-22 11:10:51 -07:00
Andrey G 87763c55a4
f1_dave: port: use designated initializers (#65) 2022-05-06 22:36:44 -07:00
Andrey G bcc62880da
f1_dave: board cleanup and pinmux fixes (#56)
* f1_dave: clean-up board.h

* f1_dave: PB6 should be output+alternate

Set using VAL_GPIOBCRL, no need to call palSetPadMode

* f1_dave: PB12 ESR driver, should be high speed (hi current)

* f1_dave: PB13 - Blue LED should be output push-pull

* f1_dave: fix pinmuxes, add comments
2022-04-06 14:07:00 -07:00
Matthew Kennedy ea262c3822 battery voltage config 2022-04-06 01:07:29 -07:00
Matthew Kennedy b838c414fa sample battery voltage 2022-04-06 01:07:18 -07:00
rusefillc 3f3cb4a7ad
PB6 with hardware mod is the simplest way forward (#50)
Co-authored-by: rusefillc <sdfsdfqsf2334234234>
2022-04-05 14:46:46 -07:00
rusefillc a981063a8b
UART (#52)
Co-authored-by: rusefillc <sdfsdfqsf2334234234>
2022-04-04 14:18:08 -07:00
Matthew Kennedy 2849b984dd some per board config 2022-01-28 11:21:38 -08:00
Matthew Kennedy 86034506b0 can runs at 24mhz 2022-01-13 12:09:44 -08:00
rusefillc d9b83379f3
CAN options (#42)
Co-authored-by: rusefillc <sdfsdfqsf2334234234>
2022-01-13 10:55:03 -08:00
Matthew Kennedy 660dad473c let's go back to 48 2022-01-13 10:45:12 -08:00
Matthew Kennedy 23a05968d3 run at 64MHz 2022-01-13 10:28:33 -08:00
rusefillc 51775e719b
ID pins to pinout header (#41)
Co-authored-by: rusefillc <sdfsdfqsf2334234234>
2022-01-11 17:44:46 -08:00
Matthew Kennedy 4f2fd95c46 f1 analog mapping 2022-01-04 11:08:17 -08:00
Matthew Kennedy 085b0419db clarify for f1 2022-01-04 11:06:01 -08:00
Matthew Kennedy b910db45ba f1 board.h 2022-01-04 11:03:09 -08:00
rusefillc cbb0665e54
Correct dac timer (#38)
* io mapping typo

* DAC uses proper timer now

Co-authored-by: rusefillc <sdfsdfqsf2334234234>
2022-01-01 20:01:05 -08:00
rusefillc 0ac2e043e1
Board cleanup (#39)
* io mapping typo

* board.h clean-up

Co-authored-by: rusefillc <sdfsdfqsf2334234234>
2022-01-01 19:57:57 -08:00
rusefillc 3c92151fc6
io mapping typo (#37)
Co-authored-by: rusefillc <sdfsdfqsf2334234234>
2022-01-01 19:27:56 -08:00
rusefillc 3a23d6bdbc
io mapping (#35)
Co-authored-by: rusefillc <sdfsdfqsf2334234234>
2022-01-01 16:14:32 -08:00
Matthew Kennedy 03aec72af7 now this should work 2021-12-27 20:56:55 -08:00
Matthew Kennedy fc67088982 don't fail if missing 2021-12-27 20:54:25 -08:00
Matthew Kennedy 1764c38783 this build should fail 2021-12-27 20:51:09 -08:00
Matthew Kennedy 0bc41184e8 word order 2021-12-27 20:45:55 -08:00
Matthew Kennedy dd8d3c5c20 pal pump dac 2021-12-27 20:44:15 -08:00
Matthew Kennedy 8cb60d5b18 pal heater device 2021-12-27 20:42:57 -08:00
rusefillc 41105cd29f
extracting hardware-specifc CAN from BL (#32)
* extracting hardware-specifc CAN from BL
reusing CAN settings between FW and BL
moving CRC into better location

* spelling M0 stuff as M0 stuff

Co-authored-by: rusefillc <sdfsdfqsf2334234234>
2021-12-27 20:39:02 -08:00
Matthew Kennedy 17bf809a5f io pins f1 2021-12-27 20:35:45 -08:00
Matthew Kennedy df07bb4ec8 chmod +x 2021-12-27 20:34:02 -08:00
Matthew Kennedy 637ed6cbe0 scripts and ci 2021-12-27 20:23:26 -08:00
Matthew Kennedy 020dd4a392 wild swing at ADC 2021-12-27 20:20:03 -08:00
rusefillc fa8e2b1deb
better io file arrangement - Makefile gives more flexibility than relative path from .cpp file (#30)
Co-authored-by: rusefillc <sdfsdfqsf2334234234>
2021-12-27 19:08:58 -08:00
Matthew Kennedy 455e5381b6 pragma once 2021-11-07 22:55:07 -08:00
rusefillc b1372e47f6
Extract io (#25)
* LEDs for BL

* more reuse

* Windows exists

* extract NERNST pin

* Matt is asking to move

Co-authored-by: rusefillc <sdfsdfqsf2334234234>
2021-11-07 22:52:13 -08:00
Matthew Kennedy 48dbdb842e hardware index selection works 2021-05-19 00:54:10 -07:00
Matthew Kennedy 8397807cb2 progress on #11 2021-05-19 00:33:36 -07:00
Matthew Kennedy d0889d6115 dave's board build now 2021-04-26 17:47:17 -07:00
Matthew Kennedy 78f6f4c284 dave chconf 2021-04-26 17:43:09 -07:00
Matthew Kennedy 9163d44962 pwm doesn't work without this 2021-03-17 22:53:24 -07:00
Matthew Kennedy 374b9aaf11 implement index set 2021-03-14 00:22:58 -08:00
Matthew Kennedy b7675e6411 enable auto retransmit 2021-03-13 15:34:19 -08:00
Matthew Kennedy ab8c24564f make the compiler happy 2021-02-25 23:12:22 -08:00
Matthew Kennedy b0763f3023 dave CAN 2021-02-25 22:59:02 -08:00
Matthew Kennedy 1759245dca move CAN to port 2021-02-25 22:57:44 -08:00
Matthew Kennedy a15a71f545 stub for Dave's board 2021-02-25 22:51:32 -08:00
Matthew Kennedy 98a4dd41b2 no advanced timer 2021-02-25 22:48:35 -08:00
Matthew Kennedy d878252b48 move adc to port 2021-02-25 22:39:51 -08:00
Matthew Kennedy b2b05b0c45 extract mcu 2021-02-25 22:35:26 -08:00
Matthew Kennedy cdd4a60fdc grumble grumble this changes the link order 2021-02-25 22:26:55 -08:00
Matthew Kennedy e2fcaa40fc make bootloader optional 2021-02-25 22:10:53 -08:00
Matthew Kennedy a61b23cd44 move board-specific stuff in to its own folder 2021-02-25 22:02:15 -08:00