2007-10-06 06:02:43 -07:00
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/*
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wiring.c - Partial implementation of the Wiring API for the ATmega8.
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Part of Arduino - http://www.arduino.cc/
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Copyright (c) 2005-2006 David A. Mellis
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General
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Public License along with this library; if not, write to the
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Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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Boston, MA 02111-1307 USA
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*/
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#include "wiring_private.h"
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2009-05-12 03:55:26 -07:00
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// the prescaler is set so that timer0 ticks every 64 clock cycles, and the
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// the overflow handler is called every 256 ticks.
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#define MICROSECONDS_PER_TIMER0_OVERFLOW (clockCyclesToMicroseconds(64 * 256))
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// the whole number of milliseconds per timer0 overflow
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#define MILLIS_INC (MICROSECONDS_PER_TIMER0_OVERFLOW / 1000)
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// the fractional number of milliseconds per timer0 overflow. we shift right
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// by three to fit these numbers into a byte. (for the clock speeds we care
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// about - 8 and 16 MHz - this doesn't lose precision.)
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#define FRACT_INC ((MICROSECONDS_PER_TIMER0_OVERFLOW % 1000) >> 3)
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#define FRACT_MAX (1000 >> 3)
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2008-11-26 06:14:59 -08:00
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volatile unsigned long timer0_overflow_count = 0;
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2008-04-18 14:56:14 -07:00
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volatile unsigned long timer0_millis = 0;
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2009-05-12 03:55:26 -07:00
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static unsigned char timer0_fract = 0;
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2007-10-06 06:02:43 -07:00
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2011-09-30 08:24:44 -07:00
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#if defined(__AVR_ATtiny24__) || defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__)
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2013-03-29 06:41:36 -07:00
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ISR(TIM0_OVF_vect)
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2011-09-30 08:24:44 -07:00
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#else
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2013-03-29 06:41:36 -07:00
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ISR(TIMER0_OVF_vect)
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2011-09-30 08:24:44 -07:00
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#endif
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2007-10-06 06:02:43 -07:00
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{
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2009-05-12 03:55:26 -07:00
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// copy these to local variables so they can be stored in registers
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// (volatile variables must be read from memory on every access)
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unsigned long m = timer0_millis;
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unsigned char f = timer0_fract;
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m += MILLIS_INC;
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f += FRACT_INC;
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if (f >= FRACT_MAX) {
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f -= FRACT_MAX;
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m += 1;
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2008-04-18 14:56:14 -07:00
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}
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2009-05-12 03:55:26 -07:00
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timer0_fract = f;
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timer0_millis = m;
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timer0_overflow_count++;
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2007-10-06 06:02:43 -07:00
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}
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unsigned long millis()
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{
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2008-04-18 14:56:14 -07:00
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unsigned long m;
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uint8_t oldSREG = SREG;
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2009-05-12 03:55:26 -07:00
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2008-07-02 12:06:27 -07:00
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// disable interrupts while we read timer0_millis or we might get an
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2009-05-12 03:55:26 -07:00
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// inconsistent value (e.g. in the middle of a write to timer0_millis)
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2008-04-18 14:56:14 -07:00
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cli();
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m = timer0_millis;
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SREG = oldSREG;
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2009-05-12 03:55:26 -07:00
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2008-04-18 14:56:14 -07:00
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return m;
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2007-10-06 06:02:43 -07:00
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}
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2008-11-26 06:14:59 -08:00
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unsigned long micros() {
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2009-12-18 09:44:08 -08:00
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unsigned long m;
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uint8_t oldSREG = SREG, t;
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2008-11-26 06:14:59 -08:00
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2009-12-18 09:44:08 -08:00
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cli();
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m = timer0_overflow_count;
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2010-10-17 14:55:53 -07:00
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#if defined(TCNT0)
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2008-11-26 06:14:59 -08:00
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t = TCNT0;
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2010-10-17 14:55:53 -07:00
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#elif defined(TCNT0L)
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t = TCNT0L;
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#else
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#error TIMER 0 not defined
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#endif
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2008-12-22 16:17:14 -08:00
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#ifdef TIFR0
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2009-12-18 09:44:08 -08:00
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if ((TIFR0 & _BV(TOV0)) && (t < 255))
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m++;
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2008-12-22 16:17:14 -08:00
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#else
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2009-12-18 09:44:08 -08:00
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if ((TIFR & _BV(TOV0)) && (t < 255))
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m++;
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2008-12-22 16:17:14 -08:00
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#endif
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2008-11-26 06:14:59 -08:00
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SREG = oldSREG;
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return ((m << 8) + t) * (64 / clockCyclesPerMicrosecond());
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}
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2007-10-06 06:02:43 -07:00
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void delay(unsigned long ms)
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{
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2015-12-27 05:49:25 -08:00
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uint32_t start = micros();
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2010-05-25 13:16:15 -07:00
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while (ms > 0) {
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2012-11-02 10:12:21 -07:00
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yield();
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2015-12-27 05:49:25 -08:00
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while ( ms > 0 && (micros() - start) >= 1000) {
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2010-05-25 13:16:15 -07:00
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ms--;
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start += 1000;
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}
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}
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2007-10-06 06:02:43 -07:00
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}
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2013-11-12 14:32:57 -08:00
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/* Delay for the given number of microseconds. Assumes a 1, 8, 12, 16, 20 or 24 MHz clock. */
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2007-10-06 06:02:43 -07:00
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void delayMicroseconds(unsigned int us)
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{
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2015-05-22 07:58:20 -07:00
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// call = 4 cycles + 2 to 4 cycles to init us(2 for constant delay, 4 for variable)
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2007-10-06 06:02:43 -07:00
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// calling avrlib's delay_us() function with low values (e.g. 1 or
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// 2 microseconds) gives delays longer than desired.
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//delay_us(us);
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2013-11-12 14:32:57 -08:00
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#if F_CPU >= 24000000L
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// for the 24 MHz clock for the aventurous ones, trying to overclock
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2014-02-03 08:19:49 -08:00
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// zero delay fix
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2015-05-22 07:58:20 -07:00
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if (!us) return; // = 3 cycles, (4 when true)
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2013-11-12 14:32:57 -08:00
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// the following loop takes a 1/6 of a microsecond (4 cycles)
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// per iteration, so execute it six times for each microsecond of
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// delay requested.
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2014-02-03 08:19:49 -08:00
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us *= 6; // x6 us, = 7 cycles
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2013-11-12 14:32:57 -08:00
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// account for the time taken in the preceeding commands.
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2014-02-03 08:19:49 -08:00
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// we just burned 22 (24) cycles above, remove 5, (5*4=20)
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2015-05-22 07:58:20 -07:00
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// us is at least 6 so we can substract 5
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2014-02-03 08:19:49 -08:00
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us -= 5; //=2 cycles
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2013-11-12 14:32:57 -08:00
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#elif F_CPU >= 20000000L
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2011-12-02 14:04:20 -08:00
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// for the 20 MHz clock on rare Arduino boards
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2014-02-03 08:19:49 -08:00
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// for a one-microsecond delay, simply return. the overhead
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// of the function call takes 18 (20) cycles, which is 1us
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2011-12-02 14:04:20 -08:00
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__asm__ __volatile__ (
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"nop" "\n\t"
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2014-02-03 08:19:49 -08:00
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"nop" "\n\t"
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"nop" "\n\t"
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"nop"); //just waiting 4 cycles
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2015-05-22 07:58:20 -07:00
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if (us <= 1) return; // = 3 cycles, (4 when true)
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2011-12-02 14:04:20 -08:00
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// the following loop takes a 1/5 of a microsecond (4 cycles)
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// per iteration, so execute it five times for each microsecond of
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// delay requested.
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2014-02-03 08:19:49 -08:00
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us = (us << 2) + us; // x5 us, = 7 cycles
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2011-12-02 14:04:20 -08:00
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// account for the time taken in the preceeding commands.
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2014-02-03 08:19:49 -08:00
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// we just burned 26 (28) cycles above, remove 7, (7*4=28)
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2015-05-22 07:58:20 -07:00
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// us is at least 10 so we can substract 7
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2014-02-03 08:19:49 -08:00
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us -= 7; // 2 cycles
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2007-10-06 06:02:43 -07:00
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2011-12-02 14:04:20 -08:00
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#elif F_CPU >= 16000000L
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2008-03-08 14:05:23 -08:00
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// for the 16 MHz clock on most Arduino boards
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2007-10-06 06:02:43 -07:00
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// for a one-microsecond delay, simply return. the overhead
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2014-02-03 08:19:49 -08:00
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// of the function call takes 14 (16) cycles, which is 1us
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if (us <= 1) return; // = 3 cycles, (4 when true)
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2007-10-06 06:02:43 -07:00
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2013-11-12 14:32:57 -08:00
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// the following loop takes 1/4 of a microsecond (4 cycles)
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2007-10-06 06:02:43 -07:00
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// per iteration, so execute it four times for each microsecond of
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// delay requested.
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2014-02-03 08:19:49 -08:00
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us <<= 2; // x4 us, = 4 cycles
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2007-10-06 06:02:43 -07:00
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// account for the time taken in the preceeding commands.
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2014-02-03 08:19:49 -08:00
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// we just burned 19 (21) cycles above, remove 5, (5*4=20)
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2015-05-22 07:58:20 -07:00
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// us is at least 8 so we can substract 5
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us -= 5; // = 2 cycles,
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2013-11-12 14:32:57 -08:00
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#elif F_CPU >= 12000000L
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// for the 12 MHz clock if somebody is working with USB
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2014-02-03 08:19:49 -08:00
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// for a 1 microsecond delay, simply return. the overhead
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// of the function call takes 14 (16) cycles, which is 1.5us
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if (us <= 1) return; // = 3 cycles, (4 when true)
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2013-11-12 14:32:57 -08:00
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// the following loop takes 1/3 of a microsecond (4 cycles)
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// per iteration, so execute it three times for each microsecond of
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// delay requested.
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2014-02-03 08:19:49 -08:00
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us = (us << 1) + us; // x3 us, = 5 cycles
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2013-11-12 14:32:57 -08:00
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// account for the time taken in the preceeding commands.
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2014-02-03 08:19:49 -08:00
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// we just burned 20 (22) cycles above, remove 5, (5*4=20)
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2015-05-22 07:58:20 -07:00
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// us is at least 6 so we can substract 5
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2014-02-03 08:19:49 -08:00
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us -= 5; //2 cycles
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2013-11-12 14:32:57 -08:00
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#elif F_CPU >= 8000000L
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// for the 8 MHz internal clock
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2007-10-06 06:02:43 -07:00
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2014-02-03 08:19:49 -08:00
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// for a 1 and 2 microsecond delay, simply return. the overhead
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// of the function call takes 14 (16) cycles, which is 2us
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if (us <= 2) return; // = 3 cycles, (4 when true)
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2007-10-06 06:02:43 -07:00
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2013-11-12 14:32:57 -08:00
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// the following loop takes 1/2 of a microsecond (4 cycles)
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2007-10-06 06:02:43 -07:00
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// per iteration, so execute it twice for each microsecond of
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// delay requested.
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2014-02-03 08:19:49 -08:00
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us <<= 1; //x2 us, = 2 cycles
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// account for the time taken in the preceeding commands.
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// we just burned 17 (19) cycles above, remove 4, (4*4=16)
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2015-05-22 07:58:20 -07:00
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// us is at least 6 so we can substract 4
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2014-02-03 08:19:49 -08:00
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us -= 4; // = 2 cycles
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2013-11-12 14:32:57 -08:00
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#else
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// for the 1 MHz internal clock (default settings for common Atmega microcontrollers)
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2014-02-03 08:19:49 -08:00
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// the overhead of the function calls is 14 (16) cycles
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if (us <= 16) return; //= 3 cycles, (4 when true)
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if (us <= 25) return; //= 3 cycles, (4 when true), (must be at least 25 if we want to substract 22)
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2013-11-12 14:32:57 -08:00
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2014-02-03 08:19:49 -08:00
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// compensate for the time taken by the preceeding and next commands (about 22 cycles)
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us -= 22; // = 2 cycles
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2013-11-12 14:32:57 -08:00
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// the following loop takes 4 microseconds (4 cycles)
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// per iteration, so execute it us/4 times
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2015-05-22 07:58:20 -07:00
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// us is at least 4, divided by 4 gives us 1 (no zero delay bug)
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2014-02-03 08:19:49 -08:00
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us >>= 2; // us div 4, = 4 cycles
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2007-10-06 06:02:43 -07:00
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#endif
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// busy wait
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__asm__ __volatile__ (
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"1: sbiw %0,1" "\n\t" // 2 cycles
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"brne 1b" : "=w" (us) : "0" (us) // 2 cycles
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);
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2013-11-12 14:32:57 -08:00
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// return = 4 cycles
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2007-10-06 06:02:43 -07:00
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}
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void init()
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{
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// this needs to be called before setup() or some functions won't
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// work there
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sei();
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// on the ATmega168, timer 0 is also used for fast hardware pwm
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// (using phase-correct PWM would mean that timer 0 overflowed half as often
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// resulting in different millis() behavior on the ATmega8 and ATmega168)
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2010-10-17 14:55:53 -07:00
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#if defined(TCCR0A) && defined(WGM01)
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2007-10-06 06:02:43 -07:00
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sbi(TCCR0A, WGM01);
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sbi(TCCR0A, WGM00);
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2015-05-22 07:58:20 -07:00
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#endif
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2010-10-17 14:55:53 -07:00
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2007-10-06 06:02:43 -07:00
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// set timer 0 prescale factor to 64
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2010-10-17 14:55:53 -07:00
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#if defined(__AVR_ATmega128__)
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// CPU specific: different values for the ATmega128
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sbi(TCCR0, CS02);
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#elif defined(TCCR0) && defined(CS01) && defined(CS00)
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// this combination is for the standard atmega8
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2007-10-06 06:02:43 -07:00
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sbi(TCCR0, CS01);
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sbi(TCCR0, CS00);
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2010-10-17 14:55:53 -07:00
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#elif defined(TCCR0B) && defined(CS01) && defined(CS00)
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// this combination is for the standard 168/328/1280/2560
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2008-11-01 15:06:13 -07:00
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sbi(TCCR0B, CS01);
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sbi(TCCR0B, CS00);
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2010-10-17 14:55:53 -07:00
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#elif defined(TCCR0A) && defined(CS01) && defined(CS00)
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// this combination is for the __AVR_ATmega645__ series
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sbi(TCCR0A, CS01);
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sbi(TCCR0A, CS00);
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#else
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#error Timer 0 prescale factor 64 not set correctly
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2007-10-06 06:02:43 -07:00
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#endif
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2010-10-17 14:55:53 -07:00
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2007-10-06 06:02:43 -07:00
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// enable timer 0 overflow interrupt
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2010-10-17 14:55:53 -07:00
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#if defined(TIMSK) && defined(TOIE0)
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2007-10-06 06:02:43 -07:00
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sbi(TIMSK, TOIE0);
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2010-10-17 14:55:53 -07:00
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#elif defined(TIMSK0) && defined(TOIE0)
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2008-11-01 15:06:13 -07:00
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sbi(TIMSK0, TOIE0);
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2010-10-17 14:55:53 -07:00
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#else
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#error Timer 0 overflow interrupt not set correctly
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2007-10-06 06:02:43 -07:00
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|
#endif
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|
|
|
|
|
|
|
// timers 1 and 2 are used for phase-correct hardware pwm
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|
|
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// this is better for motors as it ensures an even waveform
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|
|
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// note, however, that fast pwm mode can achieve a frequency of up
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|
|
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// 8 MHz (with a 16 MHz clock) at 50% duty cycle
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2010-10-17 14:55:53 -07:00
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2011-03-06 08:29:35 -08:00
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#if defined(TCCR1B) && defined(CS11) && defined(CS10)
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2010-10-17 14:55:53 -07:00
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TCCR1B = 0;
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2007-10-06 06:02:43 -07:00
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|
|
|
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// set timer 1 prescale factor to 64
|
|
|
|
sbi(TCCR1B, CS11);
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2011-10-21 08:54:11 -07:00
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#if F_CPU >= 8000000L
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2007-10-06 06:02:43 -07:00
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sbi(TCCR1B, CS10);
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2011-10-21 08:54:11 -07:00
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|
|
#endif
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2010-10-17 14:55:53 -07:00
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|
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#elif defined(TCCR1) && defined(CS11) && defined(CS10)
|
|
|
|
sbi(TCCR1, CS11);
|
2011-10-21 08:54:11 -07:00
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|
|
#if F_CPU >= 8000000L
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2010-10-17 14:55:53 -07:00
|
|
|
sbi(TCCR1, CS10);
|
2011-10-21 08:54:11 -07:00
|
|
|
#endif
|
2010-10-17 14:55:53 -07:00
|
|
|
#endif
|
2007-10-06 06:02:43 -07:00
|
|
|
// put timer 1 in 8-bit phase correct pwm mode
|
2010-10-17 14:55:53 -07:00
|
|
|
#if defined(TCCR1A) && defined(WGM10)
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2007-10-06 06:02:43 -07:00
|
|
|
sbi(TCCR1A, WGM10);
|
2010-10-17 14:55:53 -07:00
|
|
|
#endif
|
2007-10-06 06:02:43 -07:00
|
|
|
|
|
|
|
// set timer 2 prescale factor to 64
|
2010-10-17 14:55:53 -07:00
|
|
|
#if defined(TCCR2) && defined(CS22)
|
2007-10-06 06:02:43 -07:00
|
|
|
sbi(TCCR2, CS22);
|
2010-10-17 14:55:53 -07:00
|
|
|
#elif defined(TCCR2B) && defined(CS22)
|
2008-11-01 15:06:13 -07:00
|
|
|
sbi(TCCR2B, CS22);
|
2015-09-25 00:30:41 -07:00
|
|
|
//#else
|
|
|
|
// Timer 2 not finished (may not be present on this CPU)
|
2007-10-06 06:02:43 -07:00
|
|
|
#endif
|
2010-10-17 14:55:53 -07:00
|
|
|
|
2007-10-06 06:02:43 -07:00
|
|
|
// configure timer 2 for phase correct pwm (8-bit)
|
2010-10-17 14:55:53 -07:00
|
|
|
#if defined(TCCR2) && defined(WGM20)
|
2007-10-06 06:02:43 -07:00
|
|
|
sbi(TCCR2, WGM20);
|
2010-10-17 14:55:53 -07:00
|
|
|
#elif defined(TCCR2A) && defined(WGM20)
|
2008-11-01 15:06:13 -07:00
|
|
|
sbi(TCCR2A, WGM20);
|
2015-09-25 00:30:41 -07:00
|
|
|
//#else
|
|
|
|
// Timer 2 not finished (may not be present on this CPU)
|
2010-10-17 14:55:53 -07:00
|
|
|
#endif
|
|
|
|
|
|
|
|
#if defined(TCCR3B) && defined(CS31) && defined(WGM30)
|
|
|
|
sbi(TCCR3B, CS31); // set timer 3 prescale factor to 64
|
|
|
|
sbi(TCCR3B, CS30);
|
|
|
|
sbi(TCCR3A, WGM30); // put timer 3 in 8-bit phase correct pwm mode
|
|
|
|
#endif
|
2011-12-11 16:56:50 -08:00
|
|
|
|
|
|
|
#if defined(TCCR4A) && defined(TCCR4B) && defined(TCCR4D) /* beginning of timer4 block for 32U4 and similar */
|
|
|
|
sbi(TCCR4B, CS42); // set timer4 prescale factor to 64
|
|
|
|
sbi(TCCR4B, CS41);
|
|
|
|
sbi(TCCR4B, CS40);
|
|
|
|
sbi(TCCR4D, WGM40); // put timer 4 in phase- and frequency-correct PWM mode
|
2011-12-18 11:18:38 -08:00
|
|
|
sbi(TCCR4A, PWM4A); // enable PWM mode for comparator OCR4A
|
|
|
|
sbi(TCCR4C, PWM4D); // enable PWM mode for comparator OCR4D
|
2011-12-11 16:56:50 -08:00
|
|
|
#else /* beginning of timer4 block for ATMEGA1280 and ATMEGA2560 */
|
2010-10-17 14:55:53 -07:00
|
|
|
#if defined(TCCR4B) && defined(CS41) && defined(WGM40)
|
|
|
|
sbi(TCCR4B, CS41); // set timer 4 prescale factor to 64
|
|
|
|
sbi(TCCR4B, CS40);
|
|
|
|
sbi(TCCR4A, WGM40); // put timer 4 in 8-bit phase correct pwm mode
|
2007-10-06 06:02:43 -07:00
|
|
|
#endif
|
2011-12-11 16:56:50 -08:00
|
|
|
#endif /* end timer4 block for ATMEGA1280/2560 and similar */
|
2007-10-06 06:02:43 -07:00
|
|
|
|
2010-10-17 14:55:53 -07:00
|
|
|
#if defined(TCCR5B) && defined(CS51) && defined(WGM50)
|
|
|
|
sbi(TCCR5B, CS51); // set timer 5 prescale factor to 64
|
|
|
|
sbi(TCCR5B, CS50);
|
|
|
|
sbi(TCCR5A, WGM50); // put timer 5 in 8-bit phase correct pwm mode
|
2009-03-25 03:50:00 -07:00
|
|
|
#endif
|
|
|
|
|
2010-10-17 14:55:53 -07:00
|
|
|
#if defined(ADCSRA)
|
2014-02-03 08:19:49 -08:00
|
|
|
// set a2d prescaler so we are inside the desired 50-200 KHz range.
|
2015-05-22 07:58:20 -07:00
|
|
|
#if F_CPU >= 16000000 // 16 MHz / 128 = 125 KHz
|
|
|
|
sbi(ADCSRA, ADPS2);
|
|
|
|
sbi(ADCSRA, ADPS1);
|
|
|
|
sbi(ADCSRA, ADPS0);
|
|
|
|
#elif F_CPU >= 8000000 // 8 MHz / 64 = 125 KHz
|
|
|
|
sbi(ADCSRA, ADPS2);
|
|
|
|
sbi(ADCSRA, ADPS1);
|
|
|
|
cbi(ADCSRA, ADPS0);
|
|
|
|
#elif F_CPU >= 4000000 // 4 MHz / 32 = 125 KHz
|
|
|
|
sbi(ADCSRA, ADPS2);
|
|
|
|
cbi(ADCSRA, ADPS1);
|
|
|
|
sbi(ADCSRA, ADPS0);
|
|
|
|
#elif F_CPU >= 2000000 // 2 MHz / 16 = 125 KHz
|
|
|
|
sbi(ADCSRA, ADPS2);
|
|
|
|
cbi(ADCSRA, ADPS1);
|
|
|
|
cbi(ADCSRA, ADPS0);
|
|
|
|
#elif F_CPU >= 1000000 // 1 MHz / 8 = 125 KHz
|
|
|
|
cbi(ADCSRA, ADPS2);
|
|
|
|
sbi(ADCSRA, ADPS1);
|
|
|
|
sbi(ADCSRA, ADPS0);
|
|
|
|
#else // 128 kHz / 2 = 64 KHz -> This is the closest you can get, the prescaler is 2
|
|
|
|
cbi(ADCSRA, ADPS2);
|
|
|
|
cbi(ADCSRA, ADPS1);
|
|
|
|
sbi(ADCSRA, ADPS0);
|
|
|
|
#endif
|
2007-10-06 06:02:43 -07:00
|
|
|
// enable a2d conversions
|
|
|
|
sbi(ADCSRA, ADEN);
|
2010-10-17 14:55:53 -07:00
|
|
|
#endif
|
2007-10-06 06:02:43 -07:00
|
|
|
|
|
|
|
// the bootloader connects pins 0 and 1 to the USART; disconnect them
|
|
|
|
// here so they can be used as normal digital i/o; they will be
|
|
|
|
// reconnected in Serial.begin()
|
2010-10-17 14:55:53 -07:00
|
|
|
#if defined(UCSRB)
|
2007-10-06 06:02:43 -07:00
|
|
|
UCSRB = 0;
|
2010-10-17 14:55:53 -07:00
|
|
|
#elif defined(UCSR0B)
|
2008-11-01 15:06:13 -07:00
|
|
|
UCSR0B = 0;
|
2007-10-06 06:02:43 -07:00
|
|
|
#endif
|
2010-10-17 14:55:53 -07:00
|
|
|
}
|