treewide: fix typo intterrupt -> interrupt
Ref: [1] https://www.dictionary.com/browse/interrupt Signed-off-by: Du Huanpeng <dhu@hodcarrier.org>
This commit is contained in:
parent
622456829b
commit
c3122ee121
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@ -47,10 +47,10 @@ extern "C" {
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* @{
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* @{
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*/
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*/
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#define EDMA_DMERR_INT ((uint32_t)0x00000002) /* edma direct mode error intterrupt */
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#define EDMA_DMERR_INT ((uint32_t)0x00000002) /* edma direct mode error interrupt */
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#define EDMA_DTERR_INT ((uint32_t)0x00000004) /* edma data transfer error intterrupt */
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#define EDMA_DTERR_INT ((uint32_t)0x00000004) /* edma data transfer error interrupt */
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#define EDMA_HDT_INT ((uint32_t)0x00000008) /* edma half data transfer intterrupt */
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#define EDMA_HDT_INT ((uint32_t)0x00000008) /* edma half data transfer interrupt */
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#define EDMA_FDT_INT ((uint32_t)0x00000010) /* edma full data transfer intterrupt */
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#define EDMA_FDT_INT ((uint32_t)0x00000010) /* edma full data transfer interrupt */
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#define EDMA_FERR_INT ((uint32_t)0x00000080) /* edma fifo error interrupt */
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#define EDMA_FERR_INT ((uint32_t)0x00000080) /* edma fifo error interrupt */
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/**
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/**
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@ -98,7 +98,7 @@ static void edma_config(void)
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edmamux_enable(TRUE);
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edmamux_enable(TRUE);
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edmamux_init(EDMAMUX_CHANNEL1, EDMAMUX_DMAREQ_ID_ADC1);
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edmamux_init(EDMAMUX_CHANNEL1, EDMAMUX_DMAREQ_ID_ADC1);
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/* enable edma full data transfer intterrupt */
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/* enable edma full data transfer interrupt */
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edma_interrupt_enable(EDMA_STREAM1, EDMA_FDT_INT, TRUE);
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edma_interrupt_enable(EDMA_STREAM1, EDMA_FDT_INT, TRUE);
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edma_stream_enable(EDMA_STREAM1, TRUE);
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edma_stream_enable(EDMA_STREAM1, TRUE);
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}
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}
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@ -100,7 +100,7 @@ static void edma_config(void)
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/* enable the double memory mode */
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/* enable the double memory mode */
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edma_double_buffer_mode_enable(EDMA_STREAM1, TRUE);
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edma_double_buffer_mode_enable(EDMA_STREAM1, TRUE);
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/* enable edma full data transfer intterrupt */
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/* enable edma full data transfer interrupt */
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edma_interrupt_enable(EDMA_STREAM1, EDMA_FDT_INT, TRUE);
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edma_interrupt_enable(EDMA_STREAM1, EDMA_FDT_INT, TRUE);
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edma_stream_enable(EDMA_STREAM1, TRUE);
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edma_stream_enable(EDMA_STREAM1, TRUE);
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}
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}
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@ -86,7 +86,7 @@ int main(void)
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dma_init_struct.loop_mode_enable = FALSE;
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dma_init_struct.loop_mode_enable = FALSE;
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dma_init(DMA2_CHANNEL1, &dma_init_struct);
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dma_init(DMA2_CHANNEL1, &dma_init_struct);
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/* enable transfer full data intterrupt */
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/* enable transfer full data interrupt */
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dma_interrupt_enable(DMA2_CHANNEL1, DMA_FDT_INT, TRUE);
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dma_interrupt_enable(DMA2_CHANNEL1, DMA_FDT_INT, TRUE);
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/* dma2 channel1 interrupt nvic init */
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/* dma2 channel1 interrupt nvic init */
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@ -116,7 +116,7 @@ int main(void)
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dmamux_gen_init_struct.gen_enable = TRUE;
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dmamux_gen_init_struct.gen_enable = TRUE;
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dmamux_generator_config(DMA2MUX_GENERATOR1, &dmamux_gen_init_struct);
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dmamux_generator_config(DMA2MUX_GENERATOR1, &dmamux_gen_init_struct);
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/* enable transfer full data intterrupt */
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/* enable transfer full data interrupt */
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dma_interrupt_enable(DMA2_CHANNEL4, DMA_FDT_INT, TRUE);
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dma_interrupt_enable(DMA2_CHANNEL4, DMA_FDT_INT, TRUE);
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/* dma2 channel4 interrupt nvic init */
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/* dma2 channel4 interrupt nvic init */
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@ -118,7 +118,7 @@ int main(void)
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dmamux_sync_init_struct.sync_enable = TRUE;
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dmamux_sync_init_struct.sync_enable = TRUE;
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dmamux_sync_config(DMA2MUX_CHANNEL4, &dmamux_sync_init_struct);
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dmamux_sync_config(DMA2MUX_CHANNEL4, &dmamux_sync_init_struct);
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/* enable transfer full data intterrupt */
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/* enable transfer full data interrupt */
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dma_interrupt_enable(DMA2_CHANNEL4, DMA_FDT_INT, TRUE);
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dma_interrupt_enable(DMA2_CHANNEL4, DMA_FDT_INT, TRUE);
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/* dma2 channel4 interrupt nvic init */
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/* dma2 channel4 interrupt nvic init */
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@ -102,7 +102,7 @@ int main(void)
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dma_init_struct.loop_mode_enable = FALSE;
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dma_init_struct.loop_mode_enable = FALSE;
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dma_init(DMA1_CHANNEL1, &dma_init_struct);
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dma_init(DMA1_CHANNEL1, &dma_init_struct);
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/* enable transfer full data intterrupt */
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/* enable transfer full data interrupt */
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dma_interrupt_enable(DMA1_CHANNEL1, DMA_FDT_INT, TRUE);
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dma_interrupt_enable(DMA1_CHANNEL1, DMA_FDT_INT, TRUE);
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/* dma1 channel1 interrupt nvic init */
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/* dma1 channel1 interrupt nvic init */
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@ -136,7 +136,7 @@ int main(void)
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dmamux_gen_init_struct.gen_enable = TRUE;
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dmamux_gen_init_struct.gen_enable = TRUE;
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edmamux_generator_config(EDMAMUX_GENERATOR1, &dmamux_gen_init_struct);
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edmamux_generator_config(EDMAMUX_GENERATOR1, &dmamux_gen_init_struct);
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/* enable transfer full data intterrupt */
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/* enable transfer full data interrupt */
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edma_interrupt_enable(EDMA_STREAM4, EDMA_FDT_INT, TRUE);
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edma_interrupt_enable(EDMA_STREAM4, EDMA_FDT_INT, TRUE);
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/* edma stream4 interrupt nvic init */
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/* edma stream4 interrupt nvic init */
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@ -138,7 +138,7 @@ int main(void)
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edmamux_sync_init_struct.sync_signal_sel = EDMAMUX_SYNC_ID_EXINT1;
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edmamux_sync_init_struct.sync_signal_sel = EDMAMUX_SYNC_ID_EXINT1;
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edmamux_sync_config(EDMAMUX_CHANNEL4, &edmamux_sync_init_struct);
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edmamux_sync_config(EDMAMUX_CHANNEL4, &edmamux_sync_init_struct);
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/* enable transfer full data intterrupt */
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/* enable transfer full data interrupt */
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edma_interrupt_enable(EDMA_STREAM4, EDMA_FDT_INT, TRUE);
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edma_interrupt_enable(EDMA_STREAM4, EDMA_FDT_INT, TRUE);
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/* edma stream4 interrupt nvic init */
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/* edma stream4 interrupt nvic init */
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@ -119,7 +119,7 @@ int main(void)
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edma_init_struct.loop_mode_enable = FALSE;
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edma_init_struct.loop_mode_enable = FALSE;
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edma_init(EDMA_STREAM1, &edma_init_struct);
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edma_init(EDMA_STREAM1, &edma_init_struct);
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/* enable transfer full data intterrupt */
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/* enable transfer full data interrupt */
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edma_interrupt_enable(EDMA_STREAM1, EDMA_FDT_INT, TRUE);
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edma_interrupt_enable(EDMA_STREAM1, EDMA_FDT_INT, TRUE);
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/* edma stream1 interrupt nvic init */
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/* edma stream1 interrupt nvic init */
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@ -165,7 +165,7 @@ static void i2s_config(void)
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edma_double_buffer_mode_init(EDMA_STREAM2, (uint32_t)i2s3_buffer2_tx, EDMA_MEMORY_0);
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edma_double_buffer_mode_init(EDMA_STREAM2, (uint32_t)i2s3_buffer2_tx, EDMA_MEMORY_0);
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edma_double_buffer_mode_enable(EDMA_STREAM2, TRUE);
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edma_double_buffer_mode_enable(EDMA_STREAM2, TRUE);
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/* enable transfer full data intterrupt */
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/* enable transfer full data interrupt */
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edma_interrupt_enable(EDMA_STREAM1, EDMA_FDT_INT, TRUE);
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edma_interrupt_enable(EDMA_STREAM1, EDMA_FDT_INT, TRUE);
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/* edma stream1 interrupt nvic init */
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/* edma stream1 interrupt nvic init */
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@ -112,7 +112,7 @@ int main(void)
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edmamux_enable(TRUE);
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edmamux_enable(TRUE);
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edmamux_init(EDMAMUX_CHANNEL1, EDMAMUX_DMAREQ_ID_USART1_TX);
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edmamux_init(EDMAMUX_CHANNEL1, EDMAMUX_DMAREQ_ID_USART1_TX);
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/* enable transfer full data intterrupt */
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/* enable transfer full data interrupt */
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edma_interrupt_enable(EDMA_STREAM1, EDMA_FDT_INT, TRUE);
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edma_interrupt_enable(EDMA_STREAM1, EDMA_FDT_INT, TRUE);
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/* edma stream1 interrupt nvic init */
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/* edma stream1 interrupt nvic init */
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@ -99,7 +99,7 @@ int main(void)
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edma_init_struct.loop_mode_enable = FALSE;
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edma_init_struct.loop_mode_enable = FALSE;
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edma_init(EDMA_STREAM1, &edma_init_struct);
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edma_init(EDMA_STREAM1, &edma_init_struct);
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/* enable transfer full data intterrupt */
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/* enable transfer full data interrupt */
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edma_interrupt_enable(EDMA_STREAM1, EDMA_FDT_INT, TRUE);
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edma_interrupt_enable(EDMA_STREAM1, EDMA_FDT_INT, TRUE);
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/* edma stream1 interrupt nvic init */
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/* edma stream1 interrupt nvic init */
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@ -126,7 +126,7 @@ void dma_configuration(void)
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dma_init_struct.loop_mode_enable = FALSE;
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dma_init_struct.loop_mode_enable = FALSE;
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dma_init(DMA1_CHANNEL1, &dma_init_struct);
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dma_init(DMA1_CHANNEL1, &dma_init_struct);
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/* enable transfer full data intterrupt */
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/* enable transfer full data interrupt */
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dma_interrupt_enable(DMA1_CHANNEL1, DMA_FDT_INT, TRUE);
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dma_interrupt_enable(DMA1_CHANNEL1, DMA_FDT_INT, TRUE);
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/* dma1 channel1 interrupt nvic init */
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/* dma1 channel1 interrupt nvic init */
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@ -151,7 +151,7 @@ void dma_configuration(void)
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dma_init_struct.loop_mode_enable = FALSE;
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dma_init_struct.loop_mode_enable = FALSE;
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dma_init(DMA1_CHANNEL2, &dma_init_struct);
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dma_init(DMA1_CHANNEL2, &dma_init_struct);
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/* enable transfer full data intterrupt */
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/* enable transfer full data interrupt */
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dma_interrupt_enable(DMA1_CHANNEL2, DMA_FDT_INT, TRUE);
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dma_interrupt_enable(DMA1_CHANNEL2, DMA_FDT_INT, TRUE);
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/* dma1 channel2 interrupt nvic init */
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/* dma1 channel2 interrupt nvic init */
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@ -175,7 +175,7 @@ void dma_configuration(void)
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dma_init_struct.loop_mode_enable = FALSE;
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dma_init_struct.loop_mode_enable = FALSE;
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dma_init(DMA1_CHANNEL3, &dma_init_struct);
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dma_init(DMA1_CHANNEL3, &dma_init_struct);
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/* enable transfer full data intterrupt */
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/* enable transfer full data interrupt */
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dma_interrupt_enable(DMA1_CHANNEL3, DMA_FDT_INT, TRUE);
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dma_interrupt_enable(DMA1_CHANNEL3, DMA_FDT_INT, TRUE);
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/* dma1 channel3 interrupt nvic init */
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/* dma1 channel3 interrupt nvic init */
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@ -199,7 +199,7 @@ void dma_configuration(void)
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dma_init_struct.loop_mode_enable = FALSE;
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dma_init_struct.loop_mode_enable = FALSE;
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dma_init(DMA1_CHANNEL4, &dma_init_struct);
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dma_init(DMA1_CHANNEL4, &dma_init_struct);
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/* enable transfer full data intterrupt */
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/* enable transfer full data interrupt */
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dma_interrupt_enable(DMA1_CHANNEL4, DMA_FDT_INT, TRUE);
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dma_interrupt_enable(DMA1_CHANNEL4, DMA_FDT_INT, TRUE);
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/* dma1 channel4 interrupt nvic init */
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/* dma1 channel4 interrupt nvic init */
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@ -98,7 +98,7 @@ static void edma_config(void)
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edmamux_enable(TRUE);
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edmamux_enable(TRUE);
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edmamux_init(EDMAMUX_CHANNEL1, EDMAMUX_DMAREQ_ID_ADC1);
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edmamux_init(EDMAMUX_CHANNEL1, EDMAMUX_DMAREQ_ID_ADC1);
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/* enable edma full data transfer intterrupt */
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/* enable edma full data transfer interrupt */
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edma_interrupt_enable(EDMA_STREAM1, EDMA_FDT_INT, TRUE);
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edma_interrupt_enable(EDMA_STREAM1, EDMA_FDT_INT, TRUE);
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edma_stream_enable(EDMA_STREAM1, TRUE);
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edma_stream_enable(EDMA_STREAM1, TRUE);
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}
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}
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@ -100,7 +100,7 @@ static void edma_config(void)
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/* enable the double memory mode */
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/* enable the double memory mode */
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edma_double_buffer_mode_enable(EDMA_STREAM1, TRUE);
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edma_double_buffer_mode_enable(EDMA_STREAM1, TRUE);
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/* enable edma full data transfer intterrupt */
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/* enable edma full data transfer interrupt */
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edma_interrupt_enable(EDMA_STREAM1, EDMA_FDT_INT, TRUE);
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edma_interrupt_enable(EDMA_STREAM1, EDMA_FDT_INT, TRUE);
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edma_stream_enable(EDMA_STREAM1, TRUE);
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edma_stream_enable(EDMA_STREAM1, TRUE);
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}
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}
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@ -86,7 +86,7 @@ int main(void)
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dma_init_struct.loop_mode_enable = FALSE;
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dma_init_struct.loop_mode_enable = FALSE;
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dma_init(DMA2_CHANNEL1, &dma_init_struct);
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dma_init(DMA2_CHANNEL1, &dma_init_struct);
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/* enable transfer full data intterrupt */
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/* enable transfer full data interrupt */
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dma_interrupt_enable(DMA2_CHANNEL1, DMA_FDT_INT, TRUE);
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dma_interrupt_enable(DMA2_CHANNEL1, DMA_FDT_INT, TRUE);
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/* dma2 channel1 interrupt nvic init */
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/* dma2 channel1 interrupt nvic init */
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@ -116,7 +116,7 @@ int main(void)
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dmamux_gen_init_struct.gen_enable = TRUE;
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dmamux_gen_init_struct.gen_enable = TRUE;
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dmamux_generator_config(DMA2MUX_GENERATOR1, &dmamux_gen_init_struct);
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dmamux_generator_config(DMA2MUX_GENERATOR1, &dmamux_gen_init_struct);
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/* enable transfer full data intterrupt */
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/* enable transfer full data interrupt */
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dma_interrupt_enable(DMA2_CHANNEL4, DMA_FDT_INT, TRUE);
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dma_interrupt_enable(DMA2_CHANNEL4, DMA_FDT_INT, TRUE);
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/* dma2 channel4 interrupt nvic init */
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/* dma2 channel4 interrupt nvic init */
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@ -118,7 +118,7 @@ int main(void)
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dmamux_sync_init_struct.sync_enable = TRUE;
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dmamux_sync_init_struct.sync_enable = TRUE;
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dmamux_sync_config(DMA2MUX_CHANNEL4, &dmamux_sync_init_struct);
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dmamux_sync_config(DMA2MUX_CHANNEL4, &dmamux_sync_init_struct);
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/* enable transfer full data intterrupt */
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/* enable transfer full data interrupt */
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dma_interrupt_enable(DMA2_CHANNEL4, DMA_FDT_INT, TRUE);
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dma_interrupt_enable(DMA2_CHANNEL4, DMA_FDT_INT, TRUE);
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/* dma2 channel4 interrupt nvic init */
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/* dma2 channel4 interrupt nvic init */
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@ -102,7 +102,7 @@ int main(void)
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dma_init_struct.loop_mode_enable = FALSE;
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dma_init_struct.loop_mode_enable = FALSE;
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dma_init(DMA1_CHANNEL1, &dma_init_struct);
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dma_init(DMA1_CHANNEL1, &dma_init_struct);
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/* enable transfer full data intterrupt */
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/* enable transfer full data interrupt */
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dma_interrupt_enable(DMA1_CHANNEL1, DMA_FDT_INT, TRUE);
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dma_interrupt_enable(DMA1_CHANNEL1, DMA_FDT_INT, TRUE);
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/* dma1 channel1 interrupt nvic init */
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/* dma1 channel1 interrupt nvic init */
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@ -136,7 +136,7 @@ int main(void)
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dmamux_gen_init_struct.gen_enable = TRUE;
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dmamux_gen_init_struct.gen_enable = TRUE;
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edmamux_generator_config(EDMAMUX_GENERATOR1, &dmamux_gen_init_struct);
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edmamux_generator_config(EDMAMUX_GENERATOR1, &dmamux_gen_init_struct);
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/* enable transfer full data intterrupt */
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/* enable transfer full data interrupt */
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edma_interrupt_enable(EDMA_STREAM4, EDMA_FDT_INT, TRUE);
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edma_interrupt_enable(EDMA_STREAM4, EDMA_FDT_INT, TRUE);
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/* edma stream4 interrupt nvic init */
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/* edma stream4 interrupt nvic init */
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@ -138,7 +138,7 @@ int main(void)
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edmamux_sync_init_struct.sync_signal_sel = EDMAMUX_SYNC_ID_EXINT1;
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edmamux_sync_init_struct.sync_signal_sel = EDMAMUX_SYNC_ID_EXINT1;
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edmamux_sync_config(EDMAMUX_CHANNEL4, &edmamux_sync_init_struct);
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edmamux_sync_config(EDMAMUX_CHANNEL4, &edmamux_sync_init_struct);
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/* enable transfer full data intterrupt */
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/* enable transfer full data interrupt */
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edma_interrupt_enable(EDMA_STREAM4, EDMA_FDT_INT, TRUE);
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edma_interrupt_enable(EDMA_STREAM4, EDMA_FDT_INT, TRUE);
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/* edma stream4 interrupt nvic init */
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/* edma stream4 interrupt nvic init */
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@ -119,7 +119,7 @@ int main(void)
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edma_init_struct.loop_mode_enable = FALSE;
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edma_init_struct.loop_mode_enable = FALSE;
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edma_init(EDMA_STREAM1, &edma_init_struct);
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edma_init(EDMA_STREAM1, &edma_init_struct);
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/* enable transfer full data intterrupt */
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/* enable transfer full data interrupt */
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edma_interrupt_enable(EDMA_STREAM1, EDMA_FDT_INT, TRUE);
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edma_interrupt_enable(EDMA_STREAM1, EDMA_FDT_INT, TRUE);
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/* edma stream1 interrupt nvic init */
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/* edma stream1 interrupt nvic init */
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@ -165,7 +165,7 @@ static void i2s_config(void)
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edma_double_buffer_mode_init(EDMA_STREAM2, (uint32_t)i2s3_buffer2_tx, EDMA_MEMORY_0);
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edma_double_buffer_mode_init(EDMA_STREAM2, (uint32_t)i2s3_buffer2_tx, EDMA_MEMORY_0);
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edma_double_buffer_mode_enable(EDMA_STREAM2, TRUE);
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edma_double_buffer_mode_enable(EDMA_STREAM2, TRUE);
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/* enable transfer full data intterrupt */
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/* enable transfer full data interrupt */
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edma_interrupt_enable(EDMA_STREAM1, EDMA_FDT_INT, TRUE);
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edma_interrupt_enable(EDMA_STREAM1, EDMA_FDT_INT, TRUE);
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/* edma stream1 interrupt nvic init */
|
/* edma stream1 interrupt nvic init */
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||||||
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|
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@ -112,7 +112,7 @@ int main(void)
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||||||
edmamux_enable(TRUE);
|
edmamux_enable(TRUE);
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||||||
edmamux_init(EDMAMUX_CHANNEL1, EDMAMUX_DMAREQ_ID_USART1_TX);
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edmamux_init(EDMAMUX_CHANNEL1, EDMAMUX_DMAREQ_ID_USART1_TX);
|
||||||
|
|
||||||
/* enable transfer full data intterrupt */
|
/* enable transfer full data interrupt */
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||||||
edma_interrupt_enable(EDMA_STREAM1, EDMA_FDT_INT, TRUE);
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edma_interrupt_enable(EDMA_STREAM1, EDMA_FDT_INT, TRUE);
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||||||
|
|
||||||
/* edma stream1 interrupt nvic init */
|
/* edma stream1 interrupt nvic init */
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||||||
|
|
|
@ -99,7 +99,7 @@ int main(void)
|
||||||
edma_init_struct.loop_mode_enable = FALSE;
|
edma_init_struct.loop_mode_enable = FALSE;
|
||||||
edma_init(EDMA_STREAM1, &edma_init_struct);
|
edma_init(EDMA_STREAM1, &edma_init_struct);
|
||||||
|
|
||||||
/* enable transfer full data intterrupt */
|
/* enable transfer full data interrupt */
|
||||||
edma_interrupt_enable(EDMA_STREAM1, EDMA_FDT_INT, TRUE);
|
edma_interrupt_enable(EDMA_STREAM1, EDMA_FDT_INT, TRUE);
|
||||||
|
|
||||||
/* edma stream1 interrupt nvic init */
|
/* edma stream1 interrupt nvic init */
|
||||||
|
|
|
@ -126,7 +126,7 @@ void dma_configuration(void)
|
||||||
dma_init_struct.loop_mode_enable = FALSE;
|
dma_init_struct.loop_mode_enable = FALSE;
|
||||||
dma_init(DMA1_CHANNEL1, &dma_init_struct);
|
dma_init(DMA1_CHANNEL1, &dma_init_struct);
|
||||||
|
|
||||||
/* enable transfer full data intterrupt */
|
/* enable transfer full data interrupt */
|
||||||
dma_interrupt_enable(DMA1_CHANNEL1, DMA_FDT_INT, TRUE);
|
dma_interrupt_enable(DMA1_CHANNEL1, DMA_FDT_INT, TRUE);
|
||||||
|
|
||||||
/* dma1 channel1 interrupt nvic init */
|
/* dma1 channel1 interrupt nvic init */
|
||||||
|
@ -151,7 +151,7 @@ void dma_configuration(void)
|
||||||
dma_init_struct.loop_mode_enable = FALSE;
|
dma_init_struct.loop_mode_enable = FALSE;
|
||||||
dma_init(DMA1_CHANNEL2, &dma_init_struct);
|
dma_init(DMA1_CHANNEL2, &dma_init_struct);
|
||||||
|
|
||||||
/* enable transfer full data intterrupt */
|
/* enable transfer full data interrupt */
|
||||||
dma_interrupt_enable(DMA1_CHANNEL2, DMA_FDT_INT, TRUE);
|
dma_interrupt_enable(DMA1_CHANNEL2, DMA_FDT_INT, TRUE);
|
||||||
|
|
||||||
/* dma1 channel2 interrupt nvic init */
|
/* dma1 channel2 interrupt nvic init */
|
||||||
|
@ -175,7 +175,7 @@ void dma_configuration(void)
|
||||||
dma_init_struct.loop_mode_enable = FALSE;
|
dma_init_struct.loop_mode_enable = FALSE;
|
||||||
dma_init(DMA1_CHANNEL3, &dma_init_struct);
|
dma_init(DMA1_CHANNEL3, &dma_init_struct);
|
||||||
|
|
||||||
/* enable transfer full data intterrupt */
|
/* enable transfer full data interrupt */
|
||||||
dma_interrupt_enable(DMA1_CHANNEL3, DMA_FDT_INT, TRUE);
|
dma_interrupt_enable(DMA1_CHANNEL3, DMA_FDT_INT, TRUE);
|
||||||
|
|
||||||
/* dma1 channel3 interrupt nvic init */
|
/* dma1 channel3 interrupt nvic init */
|
||||||
|
@ -199,7 +199,7 @@ void dma_configuration(void)
|
||||||
dma_init_struct.loop_mode_enable = FALSE;
|
dma_init_struct.loop_mode_enable = FALSE;
|
||||||
dma_init(DMA1_CHANNEL4, &dma_init_struct);
|
dma_init(DMA1_CHANNEL4, &dma_init_struct);
|
||||||
|
|
||||||
/* enable transfer full data intterrupt */
|
/* enable transfer full data interrupt */
|
||||||
dma_interrupt_enable(DMA1_CHANNEL4, DMA_FDT_INT, TRUE);
|
dma_interrupt_enable(DMA1_CHANNEL4, DMA_FDT_INT, TRUE);
|
||||||
|
|
||||||
/* dma1 channel4 interrupt nvic init */
|
/* dma1 channel4 interrupt nvic init */
|
||||||
|
|
Loading…
Reference in New Issue