rusefi
/
AT32F435_437_Firmware_Library
mirror of https://github.com/rusefi/AT32F435_437_Firmware_Library.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

update version to v2.1.2

This commit is contained in:
Artery-MCU 2023-02-28 11:07:11 +08:00
parent 66089830a3
commit cc0d895282
1815 changed files with 21458 additions and 6073 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

BIN
document/AT32F435_437固件库BSP&Pack应用指南.pdf
View File

Binary file not shown.

BIN
document/ReleaseNotes_AT32F435_437_Firmware_Library.pdf
View File

Binary file not shown.

2
libraries/cmsis/cm4/device_support/at32f435_437.h
View File

@ -134,7 +134,7 @@ extern "C" {
*/
#define __AT32F435_437_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */
#define __AT32F435_437_LIBRARY_VERSION_MIDDLE (0x01) /*!< [23:16] middle version */
#define __AT32F435_437_LIBRARY_VERSION_MINOR (0x01) /*!< [15:8] minor version */
#define __AT32F435_437_LIBRARY_VERSION_MINOR (0x02) /*!< [15:8] minor version */
#define __AT32F435_437_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __AT32F435_437_LIBRARY_VERSION ((__AT32F435_437_LIBRARY_VERSION_MAJOR << 24) | \
(__AT32F435_437_LIBRARY_VERSION_MIDDLE << 16) | \

3
libraries/cmsis/cm4/device_support/at32f435_437_conf_template.h
View File

@ -45,8 +45,9 @@ extern "C" {
* @brief in the following line adjust the high speed exernal crystal (hext) startup
* timeout value
*/
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */
/* module define -------------------------------------------------------------*/
#define CRM_MODULE_ENABLED

2
libraries/cmsis/cm4/device_support/system_at32f435_437.c
View File

@ -35,7 +35,7 @@
/** @addtogroup AT32F435_437_system_private_defines
* @{
*/
#define VECT_TAB_OFFSET 0x0 /*!< vector table base offset field. this value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET 0x0 /*!< vector table base offset field. this value must be a multiple of 0x400. */
/**
* @}
*/

BIN
libraries/drivers/ReleaseNotes_AT32F435_437_Firmware_Library_Drivers.pdf
View File

Binary file not shown.

8
libraries/drivers/inc/at32f435_437_crm.h
View File

@ -402,10 +402,6 @@ typedef enum
CRM_EDMA_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 21), /*!< edma sleep mode periph clock */
CRM_DMA1_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 22), /*!< dma1 sleep mode periph clock */
CRM_DMA2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 24), /*!< dma2 sleep mode periph clock */
CRM_EMAC_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 25), /*!< emac sleep mode periph clock */
CRM_EMACTX_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 26), /*!< emac tx sleep mode periph clock */
CRM_EMACRX_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 27), /*!< emac rx sleep mode periph clock */
CRM_EMACPTP_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 28), /*!< emac ptp sleep mode periph clock */
CRM_OTGFS2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 29), /*!< otgfs2 sleep mode periph clock */
/* ahb periph2 */
CRM_DVP_PERIPH_LOWPOWER = MAKE_VALUE(0x54, 0), /*!< dvp sleep mode periph clock */
@ -477,6 +473,10 @@ typedef enum
CRM_EDMA_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 21), /*!< edma sleep mode periph clock */
CRM_DMA1_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 22), /*!< dma1 sleep mode periph clock */
CRM_DMA2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 24), /*!< dma2 sleep mode periph clock */
CRM_EMAC_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 25), /*!< emac sleep mode periph clock */
CRM_EMACTX_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 26), /*!< emac tx sleep mode periph clock */
CRM_EMACRX_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 27), /*!< emac rx sleep mode periph clock */
CRM_EMACPTP_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 28), /*!< emac ptp sleep mode periph clock */
CRM_OTGFS2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 29), /*!< otgfs2 sleep mode periph clock */
/* ahb periph2 */
CRM_DVP_PERIPH_LOWPOWER = MAKE_VALUE(0x54, 0), /*!< dvp sleep mode periph clock */

2
libraries/drivers/inc/at32f435_437_tmr.h
View File

@ -238,7 +238,7 @@ typedef enum
{
TMR_CC_CHANNEL_MAPPED_DIRECT = 0x01, /*!< channel is configured as input, mapped direct */
TMR_CC_CHANNEL_MAPPED_INDIRECT = 0x02, /*!< channel is configured as input, mapped indirect */
TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped trc */
TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped sti */
} tmr_input_direction_mapped_type;
/**

10
libraries/drivers/src/at32f435_437_ertc.c
View File

@ -320,7 +320,7 @@ error_status ertc_date_set(uint8_t year, uint8_t month, uint8_t date, uint8_t we
return ERROR;
}
/* Set the ertc_DR register */
/* set the ertc_date register */
ERTC->date = reg.date;
/* exit init mode */
@ -395,8 +395,6 @@ void ertc_calendar_get(ertc_time_type* time)
ertc_reg_time_type reg_tm;
ertc_reg_date_type reg_dt;
UNUSED(ERTC->sts);
reg_tm.time = ERTC->time;
reg_dt.date = ERTC->date;
@ -1516,13 +1514,7 @@ void ertc_bpr_data_write(ertc_dt_type dt, uint32_t data)
reg = ERTC_BASE + 0x50 + (dt * 4);
/* disable write protection */
ertc_write_protect_disable();
*(__IO uint32_t *)reg = data;
/* enable write protection */
ertc_write_protect_enable();
}
/**

97
middlewares/3rd_party/lwip_2.1.2/port/arch/cc.h vendored
View File

@ -32,81 +32,44 @@
#ifndef LWIP_ARCH_CC_H
#define LWIP_ARCH_CC_H
#ifdef _MSC_VER
#pragma warning (disable: 4127) /* conditional expression is constant */
#pragma warning (disable: 4996) /* 'strncpy' was declared deprecated */
#pragma warning (disable: 4103) /* structure packing changed by including file */
#pragma warning (disable: 4820) /* 'x' bytes padding added after data member 'y' */
#pragma warning (disable: 4711) /* The compiler performed inlining on the given function, although it was not marked for inlining */
#endif
#ifdef _MSC_VER
#if _MSC_VER >= 1910
#include <errno.h> /* use MSVC errno for >= 2017 */
#else
#define LWIP_PROVIDE_ERRNO /* provide errno for MSVC pre-2017 */
#endif
#else /* _MSC_VER */
#define LWIP_PROVIDE_ERRNO /* provide errno for non-MSVC */
#endif /* _MSC_VER */
/* Define platform endianness (might already be defined) */
#ifndef BYTE_ORDER
#define BYTE_ORDER LITTLE_ENDIAN
#endif /* BYTE_ORDER */
typedef int sys_prot_t;
#ifdef _MSC_VER
/* define _INTPTR for Win32 MSVC stdint.h */
#define _INTPTR 2
/* Define random number generator function */
#define LWIP_RAND() ((u32_t)rand())
/* Do not use lwIP default definitions for format strings
* because these do not work with MSVC 2010 compiler (no inttypes.h)
*/
#define LWIP_NO_INTTYPES_H 1
/* define compiler specific symbols */
#if defined (__ICCARM__)
/* Define (sn)printf formatters for these lwIP types */
#define X8_F "02x"
#define U16_F "hu"
#define U32_F "lu"
#define S32_F "ld"
#define X32_F "lx"
#define S16_F "hd"
#define X16_F "hx"
#define SZT_F "lu"
#endif /* _MSC_VER */
/* Compiler hints for packing structures */
#define PACK_STRUCT_BEGIN
#define PACK_STRUCT_STRUCT
#define PACK_STRUCT_END
#define PACK_STRUCT_FIELD(x) x
#define PACK_STRUCT_USE_INCLUDES
#define LWIP_ERROR(message, expression, handler) do { if (!(expression)) { \
printf("Assertion \"%s\" failed at line %d in %s\n", message, __LINE__, __FILE__); \
fflush(NULL);handler;} } while(0)
#elif defined (__GNUC__)
#define PACK_STRUCT_BEGIN
#define PACK_STRUCT_STRUCT __attribute__ ((__packed__))
#define PACK_STRUCT_END
#define PACK_STRUCT_FIELD(x) x
#elif defined (__CC_ARM)
#define PACK_STRUCT_BEGIN __packed
#define PACK_STRUCT_STRUCT
#define PACK_STRUCT_END
#define PACK_STRUCT_FIELD(x) x
#elif defined (__TASKING__)
#define PACK_STRUCT_BEGIN
#define PACK_STRUCT_STRUCT
#define PACK_STRUCT_END
#define PACK_STRUCT_FIELD(x) x
#ifdef _MSC_VER
/* C runtime functions redefined */
#if _MSC_VER < 1910
#define snprintf _snprintf
#endif
#define strdup _strdup
#endif
/* Define an example for LWIP_PLATFORM_DIAG: since this uses varargs and the old
* C standard lwIP targets does not support this in macros, we have extra brackets
* around the arguments, which are left out in the following macro definition:
*/
#if !defined(LWIP_TESTMODE) || !LWIP_TESTMODE
void lwip_win32_platform_diag(const char *format, ...);
#define LWIP_PLATFORM_DIAG(x) lwip_win32_platform_diag x
#endif
//#ifndef LWIP_NORAND
//extern unsigned int sys_win_rand(void);
//#define LWIP_RAND() (sys_win_rand())
//#endif
#define PPP_INCLUDE_SETTINGS_HEADER
#define LWIP_PLATFORM_ASSERT(x) do {printf("Assertion \"%s\" failed at line %d in %s\n", \
x, __LINE__, __FILE__); } while(0)
#endif /* LWIP_ARCH_CC_H */

335
middlewares/3rd_party/lwip_2.1.2/port/ethernetif.c vendored
View File

@ -94,14 +94,19 @@ extern emac_dma_desc_type *dma_tx_desc_to_set;
extern emac_dma_desc_type *dma_rx_desc_to_get;
typedef struct{
u32 length;
u32 buffer;
emac_dma_desc_type *descriptor;
u32 length;
u32 buffer;
emac_dma_desc_type *descriptor;
emac_dma_desc_type *rx_fs_desc;
emac_dma_desc_type *rx_ls_desc;
uint32_t g_seg_count;
}FrameTypeDef;
FrameTypeDef emac_rxpkt_chainmode(void);
FrameTypeDef rx_frame;
error_status emac_rxpkt_chainmode(void);
u32 emac_getcurrenttxbuffer(void);
error_status emac_txpkt_chainmode(u16 FrameLength);
error_status emac_txpkt_chainmode(uint32_t FrameLength);
/**
@ -133,6 +138,8 @@ void lwip_set_mac_address(uint8_t* macadd)
static void
low_level_init(struct netif *netif)
{
uint32_t index = 0;
/* set MAC hardware address length */
netif->hwaddr_len = ETHARP_HWADDR_LEN;
@ -149,7 +156,7 @@ low_level_init(struct netif *netif)
/* device capabilities */
/* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */
netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP;
netif->flags |= NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP;
/* Initialize Tx Descriptors list: Chain Mode */
emac_dma_descriptor_list_address_set(EMAC_DMA_TRANSMIT, DMATxDscrTab, &Tx_Buff[0][0], EMAC_TXBUFNB);
@ -157,18 +164,19 @@ low_level_init(struct netif *netif)
emac_dma_descriptor_list_address_set(EMAC_DMA_RECEIVE, DMARxDscrTab, &Rx_Buff[0][0], EMAC_RXBUFNB);
/* Enable Ethernet Rx interrrupt */
{ int i;
for(i=0; i < EMAC_RXBUFNB; i++)
{
emac_dma_rx_desc_interrupt_config(&DMARxDscrTab[i], TRUE);
}
#ifdef CHECKSUM_BY_HARDWARE
for(i=0; i < EMAC_TXBUFNB; i++)
{
DMATxDscrTab[i].status |= EMAC_DMATXDESC_CIC_TUI_FULL;
}
#endif
for(index = 0; index < EMAC_RXBUFNB; index ++)
{
emac_dma_rx_desc_interrupt_config(&DMARxDscrTab[index], TRUE);
}
#ifdef CHECKSUM_BY_HARDWARE
for(index = 0; index < EMAC_TXBUFNB; index ++)
{
DMATxDscrTab[index].status |= EMAC_DMATXDESC_CIC_TUI_FULL;
}
#endif
rx_frame.g_seg_count = 0;
/* Enable MAC and DMA transmission and reception */
emac_start();
@ -195,21 +203,66 @@ static err_t
low_level_output(struct netif *netif, struct pbuf *p)
{
struct pbuf *q;
int l = 0;
u8 *buffer = (u8 *)emac_getcurrenttxbuffer();
err_t errno;
emac_dma_desc_type *dma_tx_desc;
uint8_t *buffer;
uint32_t length = 0;
uint32_t buffer_offset = 0, payload_offset = 0, copy_count = 0;
dma_tx_desc = dma_tx_desc_to_set;
buffer = (uint8_t *)emac_getcurrenttxbuffer();
/* copy data to buffer */
for(q = p; q != NULL; q = q->next)
{
memcpy((u8_t*)&buffer[l], q->payload, q->len);
l = l + q->len;
if((dma_tx_desc->status & EMAC_DMATXDESC_OWN) != RESET)
{
errno = ERR_USE;
goto out_error;
}
copy_count = q->len;
payload_offset = 0;
while((copy_count + buffer_offset) > EMAC_MAX_PACKET_LENGTH)
{
memcpy(buffer + buffer_offset, (uint8_t *)q->payload + payload_offset, (EMAC_MAX_PACKET_LENGTH - buffer_offset));
dma_tx_desc = (emac_dma_desc_type*)dma_tx_desc->buf2nextdescaddr;
if((dma_tx_desc->status & EMAC_DMATXDESC_OWN) != RESET)
{
errno = ERR_USE;
goto out_error;
}
buffer = (uint8_t *)dma_tx_desc->buf1addr;
copy_count = copy_count - (EMAC_MAX_PACKET_LENGTH - buffer_offset);
payload_offset = payload_offset + (EMAC_MAX_PACKET_LENGTH - buffer_offset);
length = length + (EMAC_MAX_PACKET_LENGTH - buffer_offset);
buffer_offset = 0;
}
memcpy(buffer + buffer_offset, (uint8_t *)q->payload + payload_offset, copy_count);
buffer_offset = buffer_offset + copy_count;
length = length + copy_count;
}
if(emac_txpkt_chainmode(l) == ERROR)
emac_txpkt_chainmode(length);
errno = ERR_OK;
out_error:
/* When Tx Buffer unavailable flag is set: clear it and resume transmission */
if(emac_dma_flag_get(EMAC_DMA_TBU_FLAG))
{
return ERR_MEM;
/* Clear TBUS ETHERNET DMA flag */
emac_dma_flag_clear(EMAC_DMA_TBU_FLAG);
/* Resume DMA transmission*/
EMAC_DMA->tpd_bit.tpd = 0;
}
return ERR_OK;
return errno;
}
/**
@ -224,35 +277,69 @@ static struct pbuf *
low_level_input(struct netif *netif)
{
struct pbuf *p, *q;
u16_t len;
int l =0;
FrameTypeDef frame;
u8 *buffer;
uint32_t len = 0;
emac_dma_desc_type *dma_rx_desc;
uint8_t *buffer;
uint32_t buffer_offset, payload_offset = 0, copy_count = 0;
uint32_t index = 0;
p = NULL;
frame = emac_rxpkt_chainmode();
if(emac_rxpkt_chainmode() != SUCCESS)
{
return NULL;
}
/* Obtain the size of the packet and put it into the "len"
variable. */
len = frame.length;
buffer = (u8 *)frame.buffer;
len = rx_frame.length;
buffer = (uint8_t *)rx_frame.buffer;
/* We allocate a pbuf chain of pbufs from the pool. */
p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
if (p != NULL)
if(len > 0)
{
p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
}
if(p != NULL)
{
dma_rx_desc = rx_frame.rx_fs_desc;
buffer_offset = 0;
for (q = p; q != NULL; q = q->next)
{
memcpy((u8_t*)q->payload, (u8_t*)&buffer[l], q->len);
l = l + q->len;
copy_count = q->len;
payload_offset = 0;
while( (copy_count + buffer_offset) > EMAC_MAX_PACKET_LENGTH )
{
/* copy data to pbuf */
memcpy((uint8_t*)q->payload + payload_offset, buffer + buffer_offset, (EMAC_MAX_PACKET_LENGTH - buffer_offset));
/* point to next descriptor */
dma_rx_desc = (emac_dma_desc_type *)(dma_rx_desc->buf2nextdescaddr);
buffer = (uint8_t *)(dma_rx_desc->buf1addr);
copy_count = copy_count - (EMAC_MAX_PACKET_LENGTH - buffer_offset);
payload_offset = payload_offset + (EMAC_MAX_PACKET_LENGTH - buffer_offset);
buffer_offset = 0;
}
memcpy((uint8_t*)q->payload + payload_offset, (uint8_t*)buffer + buffer_offset, copy_count);
buffer_offset = buffer_offset + copy_count;
}
}
/* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */
frame.descriptor->status |= EMAC_DMARXDESC_OWN;
dma_rx_desc = rx_frame.rx_fs_desc;
for(index = 0; index < rx_frame.g_seg_count; index ++)
{
dma_rx_desc->status |= EMAC_DMARXDESC_OWN;
dma_rx_desc = (emac_dma_desc_type*) (dma_rx_desc->buf2nextdescaddr);
}
rx_frame.g_seg_count = 0;
/* When Rx Buffer unavailable flag is set: clear it and resume reception */
if(emac_dma_flag_get(EMAC_DMA_RBU_FLAG))
{
@ -261,8 +348,7 @@ low_level_input(struct netif *netif)
/* Resume DMA reception */
EMAC_DMA->rpd_bit.rpd = FALSE;
}
return p;
}
@ -359,55 +445,47 @@ ethernetif_init(struct netif *netif)
* Description : Receives a packet.
* Input : None
* Output : None
* Return : frame: farme size and location
* Return : ERROR: in case of Tx desc owned by DMA
* SUCCESS: for correct transmission
*******************************************************************************/
FrameTypeDef emac_rxpkt_chainmode(void)
error_status emac_rxpkt_chainmode(void)
{
u32 framelength = 0;
FrameTypeDef frame = {0,0};
/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
if((dma_rx_desc_to_get->status & EMAC_DMARXDESC_OWN) != (u32)RESET)
{
frame.length = FALSE;
if(emac_dma_flag_get(EMAC_DMA_RBU_FLAG))
{
/* Clear RBUS ETHERNET DMA flag */
emac_dma_flag_clear(EMAC_DMA_RBU_FLAG);
/* Resume DMA reception */
EMAC_DMA->rpd_bit.rpd = FALSE;
}
/* Return error: OWN bit set */
return frame;
{
/* return error: own bit set */
return ERROR;
}
if(((dma_rx_desc_to_get->status & EMAC_DMATXDESC_ES) == (u32)RESET) &&
((dma_rx_desc_to_get->status & EMAC_DMARXDESC_LS) != (u32)RESET) &&
((dma_rx_desc_to_get->status & EMAC_DMARXDESC_FS) != (u32)RESET))
if((dma_rx_desc_to_get->status & EMAC_DMARXDESC_LS) != (u32)RESET)
{
/* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
framelength = ((dma_rx_desc_to_get->status & EMAC_DMARXDESC_FL) >> EMAC_DMARxDesc_FrameLengthShift) - 4;
/* Get the addrees of the actual buffer */
frame.buffer = dma_rx_desc_to_get->buf1addr;
rx_frame.g_seg_count ++;
if(rx_frame.g_seg_count == 1)
{
rx_frame.rx_fs_desc = dma_rx_desc_to_get;
}
rx_frame.rx_ls_desc = dma_rx_desc_to_get;
rx_frame.length = ((dma_rx_desc_to_get->status & EMAC_DMARXDESC_FL) >> EMAC_DMARxDesc_FrameLengthShift) - 4;
rx_frame.buffer = rx_frame.rx_fs_desc->buf1addr;
/* Selects the next DMA Rx descriptor list for next buffer to read */
dma_rx_desc_to_get = (emac_dma_desc_type*) (dma_rx_desc_to_get->buf2nextdescaddr);
return SUCCESS;
}
else if((dma_rx_desc_to_get->status & EMAC_DMARXDESC_FS) != (u32)RESET)
{
rx_frame.g_seg_count = 1;
rx_frame.rx_fs_desc = dma_rx_desc_to_get;
rx_frame.rx_ls_desc = NULL;
dma_rx_desc_to_get = (emac_dma_desc_type*) (dma_rx_desc_to_get->buf2nextdescaddr);
}
else
{
/* Return ERROR */
framelength = FALSE;
rx_frame.g_seg_count ++;
dma_rx_desc_to_get = (emac_dma_desc_type*) (dma_rx_desc_to_get->buf2nextdescaddr);
}
frame.length = framelength;
frame.descriptor = dma_rx_desc_to_get;
/* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */
/* Chained Mode */
/* Selects the next DMA Rx descriptor list for next buffer to read */
dma_rx_desc_to_get = (emac_dma_desc_type*) (dma_rx_desc_to_get->buf2nextdescaddr);
/* Return Frame */
return (frame);
return ERROR;
}
/*******************************************************************************
@ -418,23 +496,81 @@ FrameTypeDef emac_rxpkt_chainmode(void)
* Return : ERROR: in case of Tx desc owned by DMA
* SUCCESS: for correct transmission
*******************************************************************************/
error_status emac_txpkt_chainmode(u16 FrameLength)
error_status emac_txpkt_chainmode(uint32_t FrameLength)
{
uint32_t buf_cnt = 0, index = 0;
/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
if((dma_tx_desc_to_set->status & EMAC_DMATXDESC_OWN) != (u32)RESET)
{
/* Return ERROR: OWN bit set */
return ERROR;
}
/* Setting the Frame Length: bits[12:0] */
dma_tx_desc_to_set->controlsize = (FrameLength & EMAC_DMATXDESC_TBS1);
/* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */
dma_tx_desc_to_set->status |= EMAC_DMATXDESC_LS | EMAC_DMATXDESC_FS;
/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
dma_tx_desc_to_set->status |= EMAC_DMATXDESC_OWN;
if(FrameLength == 0)
{
return ERROR;
}
if(FrameLength > EMAC_MAX_PACKET_LENGTH)
{
buf_cnt = FrameLength / EMAC_MAX_PACKET_LENGTH;
if(FrameLength % EMAC_MAX_PACKET_LENGTH)
{
buf_cnt += 1;
}
}
else
{
buf_cnt = 1;
}
if(buf_cnt == 1)
{
/* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */
dma_tx_desc_to_set->status |= EMAC_DMATXDESC_LS | EMAC_DMATXDESC_FS;
/* Setting the Frame Length: bits[12:0] */
dma_tx_desc_to_set->controlsize = (FrameLength & EMAC_DMATXDESC_TBS1);
/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
dma_tx_desc_to_set->status |= EMAC_DMATXDESC_OWN;
/* Selects the next DMA Tx descriptor list for next buffer to send */
dma_tx_desc_to_set = (emac_dma_desc_type*) (dma_tx_desc_to_set->buf2nextdescaddr);
}
else
{
for(index = 0; index < buf_cnt; index ++)
{
/* clear first and last segments */
dma_tx_desc_to_set->status &= ~(EMAC_DMATXDESC_LS | EMAC_DMATXDESC_FS);
/* set first segments */
if(index == 0)
{
dma_tx_desc_to_set->status |= EMAC_DMATXDESC_FS;
}
/* set size */
dma_tx_desc_to_set->controlsize = (EMAC_MAX_PACKET_LENGTH & EMAC_DMATXDESC_TBS1);
/* set last segments */
if(index == (buf_cnt - 1))
{
dma_tx_desc_to_set->status |= EMAC_DMATXDESC_LS;
dma_tx_desc_to_set->controlsize = ((FrameLength - ((buf_cnt-1) * EMAC_MAX_PACKET_LENGTH)) & EMAC_DMATXDESC_TBS1);
}
/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
dma_tx_desc_to_set->status |= EMAC_DMATXDESC_OWN;
/* Selects the next DMA Tx descriptor list for next buffer to send */
dma_tx_desc_to_set = (emac_dma_desc_type*) (dma_tx_desc_to_set->buf2nextdescaddr);
}
}
/* When Tx Buffer unavailable flag is set: clear it and resume transmission */
if(emac_dma_flag_get(EMAC_DMA_TBU_FLAG))
{
@ -443,12 +579,7 @@ error_status emac_txpkt_chainmode(u16 FrameLength)
/* Resume DMA transmission*/
EMAC_DMA->tpd_bit.tpd = 0;
}
/* Update the ETHERNET DMA global Tx descriptor with next Tx decriptor */
/* Chained Mode */
/* Selects the next DMA Tx descriptor list for next buffer to send */
dma_tx_desc_to_set = (emac_dma_desc_type*) (dma_tx_desc_to_set->buf2nextdescaddr);
/* Return SUCCESS */
return SUCCESS;
}

2
middlewares/3rd_party/lwip_2.1.2/src/include/lwip/arch.h vendored
View File

@ -45,7 +45,7 @@
#define BIG_ENDIAN 4321
#endif
//#include "arch/cc.h"
#include "arch/cc.h"
/**
* @defgroup compiler_abstraction Compiler/platform abstraction

1
middlewares/3rd_party/lwip_2.1.2/src/include/lwip/debug.h vendored
View File

@ -111,7 +111,6 @@
/**
* @}
*/
#define LWIP_NOASSERT
#ifndef LWIP_NOASSERT
#define LWIP_ASSERT(message, assertion) do { if (!(assertion)) { \

1
middlewares/freertos/source/include/portable.h
View File

@ -50,7 +50,6 @@
#ifndef portENTER_CRITICAL
#include "portmacro.h"
#endif
#if portBYTE_ALIGNMENT == 32
#define portBYTE_ALIGNMENT_MASK ( 0x001f )
#endif

1
middlewares/usb_drivers/src/usbd_sdr.c
View File

@ -156,6 +156,7 @@ static usb_sts_type usbd_set_address(usbd_core_type *udev)
else
{
udev->device_addr = dev_addr;
usbd_set_device_addr(udev, udev->device_addr);
if(dev_addr != 0)
{

32
middlewares/usb_drivers/src/usbh_ctrl.c
View File

@ -159,6 +159,7 @@ usb_sts_type usbh_ctrl_setup_wait_handler(usbh_core_type *uhost, uint32_t *timeo
uhost->ctrl.state = CONTROL_STATUS_IN;
}
}
uhost->ctrl.timer = uhost->timer;
status = USB_OK;
}
else if(urb_state == URB_ERROR || urb_state == URB_NOTREADY)
@ -279,15 +280,13 @@ usb_sts_type usbh_ctrl_data_out_wait_handler(usbh_core_type *uhost, uint32_t tim
{
uhost->ctrl.state = CONTROL_DATA_OUT;
}
else
/* wait nak timeout 5s*/
if((uhost->timer - uhost->ctrl.timer > CTRL_TIMEOUT) && (urb_state == URB_NOTREADY))
{
/* wait nak timeout 5s*/
if(uhost->timer - uhost->ctrl.timer > CTRL_TIMEOUT)
{
uhost->ctrl.state = CONTROL_ERROR;
uhost->ctrl.sts = CTRL_XACTERR;
status = USB_ERROR;
}
uhost->ctrl.state = CONTROL_ERROR;
uhost->ctrl.sts = CTRL_XACTERR;
status = USB_ERROR;
}
return status;
}
@ -388,15 +387,12 @@ usb_sts_type usbh_ctrl_status_out_wait_handler(usbh_core_type *uhost, uint32_t t
{
uhost->ctrl.state = CONTROL_STATUS_OUT;
}
else
/* wait nak timeout 5s*/
if((uhost->timer - uhost->ctrl.timer > CTRL_TIMEOUT) && (urb_state == URB_NOTREADY))
{
/* wait nak timeout 5s*/
if(uhost->timer - uhost->ctrl.timer > CTRL_TIMEOUT)
{
uhost->ctrl.state = CONTROL_ERROR;
uhost->ctrl.sts = CTRL_XACTERR;
status = USB_ERROR;
}
uhost->ctrl.state = CONTROL_ERROR;
uhost->ctrl.sts = CTRL_XACTERR;
status = USB_ERROR;
}
return status;
}
@ -468,7 +464,6 @@ usb_sts_type usbh_ctrl_transfer_loop(usbh_core_type *uhost)
case CONTROL_DATA_IN:
usbh_ctrl_data_in_handler(uhost);
uhost->ctrl.timer = uhost->timer;
break;
case CONTROL_DATA_IN_WAIT:
@ -477,7 +472,6 @@ usb_sts_type usbh_ctrl_transfer_loop(usbh_core_type *uhost)
case CONTROL_DATA_OUT:
usbh_ctrl_data_out_handler(uhost);
uhost->ctrl.timer = uhost->timer;
break;
case CONTROL_DATA_OUT_WAIT:
@ -486,7 +480,6 @@ usb_sts_type usbh_ctrl_transfer_loop(usbh_core_type *uhost)
case CONTROL_STATUS_IN:
usbh_ctrl_status_in_handler(uhost);
uhost->ctrl.timer = uhost->timer;
break;
case CONTROL_STATUS_IN_WAIT:
@ -495,7 +488,6 @@ usb_sts_type usbh_ctrl_transfer_loop(usbh_core_type *uhost)
case CONTROL_STATUS_OUT:
usbh_ctrl_status_out_handler(uhost);
uhost->ctrl.timer = uhost->timer;
break;
case CONTROL_STATUS_OUT_WAIT:

3
project/at_start_f435/examples/acc/calibration/inc/at32f435_437_conf.h
View File

@ -46,8 +46,9 @@ extern "C" {
* @brief in the following line adjust the high speed exernal crystal (hext) startup
* timeout value
*/
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */
/* module define -------------------------------------------------------------*/
#define CRM_MODULE_ENABLED

2
project/at_start_f435/examples/acc/calibration/inc/usb_conf.h
View File

@ -116,7 +116,7 @@ extern "C" {
#define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13
#define OTG_PIN_ID GPIO_PINS_12
#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10
#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12
#define OTG_PIN_SOF_GPIO GPIOA
#define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK

4
project/at_start_f435/examples/acc/calibration/mdk_v5/calibration.uvoptx
View File

@ -10,9 +10,9 @@
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp; *.cc; *.cxx</CppX>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>

17
project/at_start_f435/examples/acc/calibration/mdk_v5/calibration.uvprojx
View File

@ -16,7 +16,7 @@
<TargetCommonOption>
<Device>-AT32F435ZMT7</Device>
<Vendor>ArteryTek</Vendor>
<PackID>ArteryTek.AT32F435_437_DFP.2.1.0</PackID>
<PackID>ArteryTek.AT32F435_437_DFP.2.0.1</PackID>
<Cpu>IRAM(0x20000000,0x60000) IROM(0x08000000,0x400000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
@ -629,4 +629,19 @@
<files/>
</RTE>
<LayerInfo>
<Layers>
<Layer>
<LayName>&lt;Project Info&gt;</LayName>
<LayDesc></LayDesc>
<LayUrl></LayUrl>
<LayKeys></LayKeys>
<LayCat></LayCat>
<LayLic></LayLic>
<LayTarg>0</LayTarg>
<LayPrjMark>1</LayPrjMark>
</Layer>
</Layers>
</LayerInfo>
</Project>

6
project/at_start_f435/examples/acc/calibration/src/at32f435_437_clock.c
View File

@ -45,6 +45,9 @@
*/
void system_clock_config(void)
{
/* reset crm */
crm_reset();
/* enable pwc periph clock */
crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE);
@ -54,9 +57,6 @@ void system_clock_config(void)
/* set the flash clock divider */
flash_clock_divider_set(FLASH_CLOCK_DIV_3);
/* reset crm */
crm_reset();
/* enable hick */
crm_clock_source_enable(CRM_CLOCK_SOURCE_HICK, TRUE);

2
project/at_start_f435/examples/acc/calibration/src/main.c
View File

@ -83,7 +83,7 @@ void usb_gpio_config(void)
crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE);
gpio_init_struct.gpio_pins = OTG_PIN_SOF;
gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct);
gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX);
gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX);
#endif
/* otgfs use vbus pin */

3
project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma3/inc/at32f435_437_conf.h
View File

@ -46,8 +46,9 @@ extern "C" {
* @brief in the following line adjust the high speed exernal crystal (hext) startup
* timeout value
*/
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */
/* module define -------------------------------------------------------------*/
#define CRM_MODULE_ENABLED

4
project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma3/mdk_v5/combine_mode_ordinary_shift_twoslave_dma3.uvoptx
View File

@ -10,9 +10,9 @@
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp; *.cc; *.cxx</CppX>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>

7
project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma3/mdk_v5/combine_mode_ordinary_shift_twoslave_dma3.uvprojx
View File

@ -16,7 +16,7 @@
<TargetCommonOption>
<Device>-AT32F435ZMT7</Device>
<Vendor>ArteryTek</Vendor>
<PackID>ArteryTek.AT32F435_437_DFP.2.1.0</PackID>
<PackID>ArteryTek.AT32F435_437_DFP.2.0.1</PackID>
<Cpu>IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
@ -488,6 +488,11 @@
<Layers>
<Layer>
<LayName>&lt;Project Info&gt;</LayName>
<LayDesc></LayDesc>
<LayUrl></LayUrl>
<LayKeys></LayKeys>
<LayCat></LayCat>
<LayLic></LayLic>
<LayTarg>0</LayTarg>
<LayPrjMark>1</LayPrjMark>
</Layer>

6
project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma3/src/at32f435_437_clock.c
View File

@ -46,6 +46,9 @@
*/
void system_clock_config(void)
{
/* reset crm */
crm_reset();
/* enable pwc periph clock */
crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE);
@ -55,9 +58,6 @@ void system_clock_config(void)
/* set the flash clock divider */
flash_clock_divider_set(FLASH_CLOCK_DIV_3);
/* reset crm */
crm_reset();
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
/* wait till hext is ready */

3
project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma4/inc/at32f435_437_conf.h
View File

@ -46,8 +46,9 @@ extern "C" {
* @brief in the following line adjust the high speed exernal crystal (hext) startup
* timeout value
*/
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */
/* module define -------------------------------------------------------------*/
#define CRM_MODULE_ENABLED

4
project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma4/mdk_v5/combine_mode_ordinary_shift_twoslave_dma4.uvoptx
View File

@ -10,9 +10,9 @@
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp; *.cc; *.cxx</CppX>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>

7
project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma4/mdk_v5/combine_mode_ordinary_shift_twoslave_dma4.uvprojx
View File

@ -16,7 +16,7 @@
<TargetCommonOption>
<Device>-AT32F435ZMT7</Device>
<Vendor>ArteryTek</Vendor>
<PackID>ArteryTek.AT32F435_437_DFP.2.1.0</PackID>
<PackID>ArteryTek.AT32F435_437_DFP.2.0.1</PackID>
<Cpu>IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
@ -488,6 +488,11 @@
<Layers>
<Layer>
<LayName>&lt;Project Info&gt;</LayName>
<LayDesc></LayDesc>
<LayUrl></LayUrl>
<LayKeys></LayKeys>
<LayCat></LayCat>
<LayLic></LayLic>
<LayTarg>0</LayTarg>
<LayPrjMark>1</LayPrjMark>
</Layer>

6
project/at_start_f435/examples/adc/combine_mode_ordinary_shift_twoslave_dma4/src/at32f435_437_clock.c
View File

@ -46,6 +46,9 @@
*/
void system_clock_config(void)
{
/* reset crm */
crm_reset();
/* enable pwc periph clock */
crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE);
@ -55,9 +58,6 @@ void system_clock_config(void)
/* set the flash clock divider */
flash_clock_divider_set(FLASH_CLOCK_DIV_3);
/* reset crm */
crm_reset();
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
/* wait till hext is ready */

3
project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_dma2/inc/at32f435_437_conf.h
View File

@ -46,8 +46,9 @@ extern "C" {
* @brief in the following line adjust the high speed exernal crystal (hext) startup
* timeout value
*/
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */
/* module define -------------------------------------------------------------*/
#define CRM_MODULE_ENABLED

4
project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_dma2/mdk_v5/combine_mode_ordinary_smlt_oneslave_dma2.uvoptx
View File

@ -10,9 +10,9 @@
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp; *.cc; *.cxx</CppX>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>

7
project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_dma2/mdk_v5/combine_mode_ordinary_smlt_oneslave_dma2.uvprojx
View File

@ -16,7 +16,7 @@
<TargetCommonOption>
<Device>-AT32F435ZMT7</Device>
<Vendor>ArteryTek</Vendor>
<PackID>ArteryTek.AT32F435_437_DFP.2.1.0</PackID>
<PackID>ArteryTek.AT32F435_437_DFP.2.0.1</PackID>
<Cpu>IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
@ -483,6 +483,11 @@
<Layers>
<Layer>
<LayName>&lt;Project Info&gt;</LayName>
<LayDesc></LayDesc>
<LayUrl></LayUrl>
<LayKeys></LayKeys>
<LayCat></LayCat>
<LayLic></LayLic>
<LayTarg>0</LayTarg>
<LayPrjMark>1</LayPrjMark>
</Layer>

6
project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_dma2/src/at32f435_437_clock.c
View File

@ -46,6 +46,9 @@
*/
void system_clock_config(void)
{
/* reset crm */
crm_reset();
/* enable pwc periph clock */
crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE);
@ -55,9 +58,6 @@ void system_clock_config(void)
/* set the flash clock divider */
flash_clock_divider_set(FLASH_CLOCK_DIV_3);
/* reset crm */
crm_reset();
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
/* wait till hext is ready */

3
project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_edma/inc/at32f435_437_conf.h
View File

@ -46,8 +46,9 @@ extern "C" {
* @brief in the following line adjust the high speed exernal crystal (hext) startup
* timeout value
*/
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */
/* module define -------------------------------------------------------------*/
#define CRM_MODULE_ENABLED

4
project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_edma/mdk_v5/combine_mode_ordinary_smlt_oneslave_edma.uvoptx
View File

@ -10,9 +10,9 @@
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp; *.cc; *.cxx</CppX>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>

7
project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_edma/mdk_v5/combine_mode_ordinary_smlt_oneslave_edma.uvprojx
View File

@ -16,7 +16,7 @@
<TargetCommonOption>
<Device>-AT32F435ZMT7</Device>
<Vendor>ArteryTek</Vendor>
<PackID>ArteryTek.AT32F435_437_DFP.2.1.0</PackID>
<PackID>ArteryTek.AT32F435_437_DFP.2.0.1</PackID>
<Cpu>IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
@ -483,6 +483,11 @@
<Layers>
<Layer>
<LayName>&lt;Project Info&gt;</LayName>
<LayDesc></LayDesc>
<LayUrl></LayUrl>
<LayKeys></LayKeys>
<LayCat></LayCat>
<LayLic></LayLic>
<LayTarg>0</LayTarg>
<LayPrjMark>1</LayPrjMark>
</Layer>

6
project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_oneslave_edma/src/at32f435_437_clock.c
View File

@ -46,6 +46,9 @@
*/
void system_clock_config(void)
{
/* reset crm */
crm_reset();
/* enable pwc periph clock */
crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE);
@ -55,9 +58,6 @@ void system_clock_config(void)
/* set the flash clock divider */
flash_clock_divider_set(FLASH_CLOCK_DIV_3);
/* reset crm */
crm_reset();
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
/* wait till hext is ready */

3
project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma1/inc/at32f435_437_conf.h
View File

@ -46,8 +46,9 @@ extern "C" {
* @brief in the following line adjust the high speed exernal crystal (hext) startup
* timeout value
*/
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */
/* module define -------------------------------------------------------------*/
#define CRM_MODULE_ENABLED

4
project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma1/mdk_v5/combine_mode_ordinary_smlt_twoslave_dma1.uvoptx
View File

@ -10,9 +10,9 @@
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp; *.cc; *.cxx</CppX>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>

7
project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma1/mdk_v5/combine_mode_ordinary_smlt_twoslave_dma1.uvprojx
View File

@ -16,7 +16,7 @@
<TargetCommonOption>
<Device>-AT32F435ZMT7</Device>
<Vendor>ArteryTek</Vendor>
<PackID>ArteryTek.AT32F435_437_DFP.2.1.0</PackID>
<PackID>ArteryTek.AT32F435_437_DFP.2.0.1</PackID>
<Cpu>IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
@ -488,6 +488,11 @@
<Layers>
<Layer>
<LayName>&lt;Project Info&gt;</LayName>
<LayDesc></LayDesc>
<LayUrl></LayUrl>
<LayKeys></LayKeys>
<LayCat></LayCat>
<LayLic></LayLic>
<LayTarg>0</LayTarg>
<LayPrjMark>1</LayPrjMark>
</Layer>

6
project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma1/src/at32f435_437_clock.c
View File

@ -46,6 +46,9 @@
*/
void system_clock_config(void)
{
/* reset crm */
crm_reset();
/* enable pwc periph clock */
crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE);
@ -55,9 +58,6 @@ void system_clock_config(void)
/* set the flash clock divider */
flash_clock_divider_set(FLASH_CLOCK_DIV_3);
/* reset crm */
crm_reset();
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
/* wait till hext is ready */

3
project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma5/inc/at32f435_437_conf.h
View File

@ -46,8 +46,9 @@ extern "C" {
* @brief in the following line adjust the high speed exernal crystal (hext) startup
* timeout value
*/
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */
/* module define -------------------------------------------------------------*/
#define CRM_MODULE_ENABLED

4
project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma5/mdk_v5/combine_mode_ordinary_smlt_twoslave_dma5.uvoptx
View File

@ -10,9 +10,9 @@
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp; *.cc; *.cxx</CppX>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>

7
project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma5/mdk_v5/combine_mode_ordinary_smlt_twoslave_dma5.uvprojx
View File

@ -16,7 +16,7 @@
<TargetCommonOption>
<Device>-AT32F435ZMT7</Device>
<Vendor>ArteryTek</Vendor>
<PackID>ArteryTek.AT32F435_437_DFP.2.1.0</PackID>
<PackID>ArteryTek.AT32F435_437_DFP.2.0.1</PackID>
<Cpu>IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
@ -488,6 +488,11 @@
<Layers>
<Layer>
<LayName>&lt;Project Info&gt;</LayName>
<LayDesc></LayDesc>
<LayUrl></LayUrl>
<LayKeys></LayKeys>
<LayCat></LayCat>
<LayLic></LayLic>
<LayTarg>0</LayTarg>
<LayPrjMark>1</LayPrjMark>
</Layer>

6
project/at_start_f435/examples/adc/combine_mode_ordinary_smlt_twoslave_dma5/src/at32f435_437_clock.c
View File

@ -46,6 +46,9 @@
*/
void system_clock_config(void)
{
/* reset crm */
crm_reset();
/* enable pwc periph clock */
crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE);
@ -55,9 +58,6 @@ void system_clock_config(void)
/* set the flash clock divider */
flash_clock_divider_set(FLASH_CLOCK_DIV_3);
/* reset crm */
crm_reset();
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
/* wait till hext is ready */

3
project/at_start_f435/examples/adc/combine_mode_preempt_interltrig_twoslave/inc/at32f435_437_conf.h
View File

@ -46,8 +46,9 @@ extern "C" {
* @brief in the following line adjust the high speed exernal crystal (hext) startup
* timeout value
*/
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */
/* module define -------------------------------------------------------------*/
#define CRM_MODULE_ENABLED

4
project/at_start_f435/examples/adc/combine_mode_preempt_interltrig_twoslave/mdk_v5/combine_mode_preempt_interltrig_twoslave.uvoptx
View File

@ -10,9 +10,9 @@
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp; *.cc; *.cxx</CppX>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>

7
project/at_start_f435/examples/adc/combine_mode_preempt_interltrig_twoslave/mdk_v5/combine_mode_preempt_interltrig_twoslave.uvprojx
View File

@ -16,7 +16,7 @@
<TargetCommonOption>
<Device>-AT32F435ZMT7</Device>
<Vendor>ArteryTek</Vendor>
<PackID>ArteryTek.AT32F435_437_DFP.2.1.0</PackID>
<PackID>ArteryTek.AT32F435_437_DFP.2.0.1</PackID>
<Cpu>IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
@ -478,6 +478,11 @@
<Layers>
<Layer>
<LayName>&lt;Project Info&gt;</LayName>
<LayDesc></LayDesc>
<LayUrl></LayUrl>
<LayKeys></LayKeys>
<LayCat></LayCat>
<LayLic></LayLic>
<LayTarg>0</LayTarg>
<LayPrjMark>1</LayPrjMark>
</Layer>

6
project/at_start_f435/examples/adc/combine_mode_preempt_interltrig_twoslave/src/at32f435_437_clock.c
View File

@ -46,6 +46,9 @@
*/
void system_clock_config(void)
{
/* reset crm */
crm_reset();
/* enable pwc periph clock */
crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE);
@ -55,9 +58,6 @@ void system_clock_config(void)
/* set the flash clock divider */
flash_clock_divider_set(FLASH_CLOCK_DIV_3);
/* reset crm */
crm_reset();
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
/* wait till hext is ready */

3
project/at_start_f435/examples/adc/conversion_abort/inc/at32f435_437_conf.h
View File

@ -46,8 +46,9 @@ extern "C" {
* @brief in the following line adjust the high speed exernal crystal (hext) startup
* timeout value
*/
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */
/* module define -------------------------------------------------------------*/
#define CRM_MODULE_ENABLED

4
project/at_start_f435/examples/adc/conversion_abort/mdk_v5/conversion_abort.uvoptx
View File

@ -10,9 +10,9 @@
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp; *.cc; *.cxx</CppX>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>

7
project/at_start_f435/examples/adc/conversion_abort/mdk_v5/conversion_abort.uvprojx
View File

@ -16,7 +16,7 @@
<TargetCommonOption>
<Device>-AT32F435ZMT7</Device>
<Vendor>ArteryTek</Vendor>
<PackID>ArteryTek.AT32F435_437_DFP.2.1.0</PackID>
<PackID>ArteryTek.AT32F435_437_DFP.2.0.1</PackID>
<Cpu>IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
@ -483,6 +483,11 @@
<Layers>
<Layer>
<LayName>&lt;Project Info&gt;</LayName>
<LayDesc></LayDesc>
<LayUrl></LayUrl>
<LayKeys></LayKeys>
<LayCat></LayCat>
<LayLic></LayLic>
<LayTarg>0</LayTarg>
<LayPrjMark>1</LayPrjMark>
</Layer>

6
project/at_start_f435/examples/adc/conversion_abort/src/at32f435_437_clock.c
View File

@ -46,6 +46,9 @@
*/
void system_clock_config(void)
{
/* reset crm */
crm_reset();
/* enable pwc periph clock */
crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE);
@ -55,9 +58,6 @@ void system_clock_config(void)
/* set the flash clock divider */
flash_clock_divider_set(FLASH_CLOCK_DIV_3);
/* reset crm */
crm_reset();
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
/* wait till hext is ready */

3
project/at_start_f435/examples/adc/current_vref_value_check/inc/at32f435_437_conf.h
View File

@ -46,8 +46,9 @@ extern "C" {
* @brief in the following line adjust the high speed exernal crystal (hext) startup
* timeout value
*/
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */
/* module define -------------------------------------------------------------*/
#define CRM_MODULE_ENABLED

4
project/at_start_f435/examples/adc/current_vref_value_check/mdk_v5/current_vref_value_check.uvoptx
View File

@ -10,9 +10,9 @@
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp; *.cc; *.cxx</CppX>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>

7
project/at_start_f435/examples/adc/current_vref_value_check/mdk_v5/current_vref_value_check.uvprojx
View File

@ -16,7 +16,7 @@
<TargetCommonOption>
<Device>-AT32F435ZMT7</Device>
<Vendor>ArteryTek</Vendor>
<PackID>ArteryTek.AT32F435_437_DFP.2.1.0</PackID>
<PackID>ArteryTek.AT32F435_437_DFP.2.0.1</PackID>
<Cpu>IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
@ -483,6 +483,11 @@
<Layers>
<Layer>
<LayName>&lt;Project Info&gt;</LayName>
<LayDesc></LayDesc>
<LayUrl></LayUrl>
<LayKeys></LayKeys>
<LayCat></LayCat>
<LayLic></LayLic>
<LayTarg>0</LayTarg>
<LayPrjMark>1</LayPrjMark>
</Layer>

6
project/at_start_f435/examples/adc/current_vref_value_check/src/at32f435_437_clock.c
View File

@ -46,6 +46,9 @@
*/
void system_clock_config(void)
{
/* reset crm */
crm_reset();
/* enable pwc periph clock */
crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE);
@ -55,9 +58,6 @@ void system_clock_config(void)
/* set the flash clock divider */
flash_clock_divider_set(FLASH_CLOCK_DIV_3);
/* reset crm */
crm_reset();
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
/* wait till hext is ready */

3
project/at_start_f435/examples/adc/edma_double_buffer/inc/at32f435_437_conf.h
View File

@ -46,8 +46,9 @@ extern "C" {
* @brief in the following line adjust the high speed exernal crystal (hext) startup
* timeout value
*/
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */
/* module define -------------------------------------------------------------*/
#define CRM_MODULE_ENABLED

4
project/at_start_f435/examples/adc/edma_double_buffer/mdk_v5/edma_double_buffer.uvoptx
View File

@ -10,9 +10,9 @@
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp; *.cc; *.cxx</CppX>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>

7
project/at_start_f435/examples/adc/edma_double_buffer/mdk_v5/edma_double_buffer.uvprojx
View File

@ -16,7 +16,7 @@
<TargetCommonOption>
<Device>-AT32F435ZMT7</Device>
<Vendor>ArteryTek</Vendor>
<PackID>ArteryTek.AT32F435_437_DFP.2.1.0</PackID>
<PackID>ArteryTek.AT32F435_437_DFP.2.0.1</PackID>
<Cpu>IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
@ -483,6 +483,11 @@
<Layers>
<Layer>
<LayName>&lt;Project Info&gt;</LayName>
<LayDesc></LayDesc>
<LayUrl></LayUrl>
<LayKeys></LayKeys>
<LayCat></LayCat>
<LayLic></LayLic>
<LayTarg>0</LayTarg>
<LayPrjMark>1</LayPrjMark>
</Layer>

6
project/at_start_f435/examples/adc/edma_double_buffer/src/at32f435_437_clock.c
View File

@ -46,6 +46,9 @@
*/
void system_clock_config(void)
{
/* reset crm */
crm_reset();
/* enable pwc periph clock */
crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE);
@ -55,9 +58,6 @@ void system_clock_config(void)
/* set the flash clock divider */
flash_clock_divider_set(FLASH_CLOCK_DIV_3);
/* reset crm */
crm_reset();
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
/* wait till hext is ready */

3
project/at_start_f435/examples/adc/exint_trigger_partitioned/inc/at32f435_437_conf.h
View File

@ -46,8 +46,9 @@ extern "C" {
* @brief in the following line adjust the high speed exernal crystal (hext) startup
* timeout value
*/
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */
/* module define -------------------------------------------------------------*/
#define CRM_MODULE_ENABLED

4
project/at_start_f435/examples/adc/exint_trigger_partitioned/mdk_v5/exint_trigger_partitioned.uvoptx
View File

@ -10,9 +10,9 @@
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp; *.cc; *.cxx</CppX>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>

7
project/at_start_f435/examples/adc/exint_trigger_partitioned/mdk_v5/exint_trigger_partitioned.uvprojx
View File

@ -16,7 +16,7 @@
<TargetCommonOption>
<Device>-AT32F435ZMT7</Device>
<Vendor>ArteryTek</Vendor>
<PackID>ArteryTek.AT32F435_437_DFP.2.1.0</PackID>
<PackID>ArteryTek.AT32F435_437_DFP.2.0.1</PackID>
<Cpu>IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
@ -493,6 +493,11 @@
<Layers>
<Layer>
<LayName>&lt;Project Info&gt;</LayName>
<LayDesc></LayDesc>
<LayUrl></LayUrl>
<LayKeys></LayKeys>
<LayCat></LayCat>
<LayLic></LayLic>
<LayTarg>0</LayTarg>
<LayPrjMark>1</LayPrjMark>
</Layer>

6
project/at_start_f435/examples/adc/exint_trigger_partitioned/src/at32f435_437_clock.c
View File

@ -46,6 +46,9 @@
*/
void system_clock_config(void)
{
/* reset crm */
crm_reset();
/* enable pwc periph clock */
crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE);
@ -55,9 +58,6 @@ void system_clock_config(void)
/* set the flash clock divider */
flash_clock_divider_set(FLASH_CLOCK_DIV_3);
/* reset crm */
crm_reset();
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
/* wait till hext is ready */

3
project/at_start_f435/examples/adc/internal_temperature_sensor/inc/at32f435_437_conf.h
View File

@ -46,8 +46,9 @@ extern "C" {
* @brief in the following line adjust the high speed exernal crystal (hext) startup
* timeout value
*/
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */
/* module define -------------------------------------------------------------*/
#define CRM_MODULE_ENABLED

4
project/at_start_f435/examples/adc/internal_temperature_sensor/mdk_v5/internal_temperature_sensor.uvoptx
View File

@ -10,9 +10,9 @@
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp; *.cc; *.cxx</CppX>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>

7
project/at_start_f435/examples/adc/internal_temperature_sensor/mdk_v5/internal_temperature_sensor.uvprojx
View File

@ -16,7 +16,7 @@
<TargetCommonOption>
<Device>-AT32F435ZMT7</Device>
<Vendor>ArteryTek</Vendor>
<PackID>ArteryTek.AT32F435_437_DFP.2.1.0</PackID>
<PackID>ArteryTek.AT32F435_437_DFP.2.0.1</PackID>
<Cpu>IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
@ -483,6 +483,11 @@
<Layers>
<Layer>
<LayName>&lt;Project Info&gt;</LayName>
<LayDesc></LayDesc>
<LayUrl></LayUrl>
<LayKeys></LayKeys>
<LayCat></LayCat>
<LayLic></LayLic>
<LayTarg>0</LayTarg>
<LayPrjMark>1</LayPrjMark>
</Layer>

6
project/at_start_f435/examples/adc/internal_temperature_sensor/src/at32f435_437_clock.c
View File

@ -46,6 +46,9 @@
*/
void system_clock_config(void)
{
/* reset crm */
crm_reset();
/* enable pwc periph clock */
crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE);
@ -55,9 +58,6 @@ void system_clock_config(void)
/* set the flash clock divider */
flash_clock_divider_set(FLASH_CLOCK_DIV_3);
/* reset crm */
crm_reset();
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
/* wait till hext is ready */

3
project/at_start_f435/examples/adc/ordinary_preempt_oversampling/inc/at32f435_437_conf.h
View File

@ -46,8 +46,9 @@ extern "C" {
* @brief in the following line adjust the high speed exernal crystal (hext) startup
* timeout value
*/
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */
/* module define -------------------------------------------------------------*/
#define CRM_MODULE_ENABLED

4
project/at_start_f435/examples/adc/ordinary_preempt_oversampling/mdk_v5/ordinary_preempt_oversampling.uvoptx
View File

@ -10,9 +10,9 @@
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp; *.cc; *.cxx</CppX>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>

7
project/at_start_f435/examples/adc/ordinary_preempt_oversampling/mdk_v5/ordinary_preempt_oversampling.uvprojx
View File

@ -16,7 +16,7 @@
<TargetCommonOption>
<Device>-AT32F435ZMT7</Device>
<Vendor>ArteryTek</Vendor>
<PackID>ArteryTek.AT32F435_437_DFP.2.1.0</PackID>
<PackID>ArteryTek.AT32F435_437_DFP.2.0.1</PackID>
<Cpu>IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
@ -483,6 +483,11 @@
<Layers>
<Layer>
<LayName>&lt;Project Info&gt;</LayName>
<LayDesc></LayDesc>
<LayUrl></LayUrl>
<LayKeys></LayKeys>
<LayCat></LayCat>
<LayLic></LayLic>
<LayTarg>0</LayTarg>
<LayPrjMark>1</LayPrjMark>
</Layer>

6
project/at_start_f435/examples/adc/ordinary_preempt_oversampling/src/at32f435_437_clock.c
View File

@ -46,6 +46,9 @@
*/
void system_clock_config(void)
{
/* reset crm */
crm_reset();
/* enable pwc periph clock */
crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE);
@ -55,9 +58,6 @@ void system_clock_config(void)
/* set the flash clock divider */
flash_clock_divider_set(FLASH_CLOCK_DIV_3);
/* reset crm */
crm_reset();
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
/* wait till hext is ready */

3
project/at_start_f435/examples/adc/repeat_conversion_loop_transfer/inc/at32f435_437_conf.h
View File

@ -46,8 +46,9 @@ extern "C" {
* @brief in the following line adjust the high speed exernal crystal (hext) startup
* timeout value
*/
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */
/* module define -------------------------------------------------------------*/
#define CRM_MODULE_ENABLED

4
project/at_start_f435/examples/adc/repeat_conversion_loop_transfer/mdk_v5/repeat_conversion_loop_transfer.uvoptx
View File

@ -10,9 +10,9 @@
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp; *.cc; *.cxx</CppX>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>

7
project/at_start_f435/examples/adc/repeat_conversion_loop_transfer/mdk_v5/repeat_conversion_loop_transfer.uvprojx
View File

@ -16,7 +16,7 @@
<TargetCommonOption>
<Device>-AT32F435ZMT7</Device>
<Vendor>ArteryTek</Vendor>
<PackID>ArteryTek.AT32F435_437_DFP.2.1.0</PackID>
<PackID>ArteryTek.AT32F435_437_DFP.2.0.1</PackID>
<Cpu>IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
@ -483,6 +483,11 @@
<Layers>
<Layer>
<LayName>&lt;Project Info&gt;</LayName>
<LayDesc></LayDesc>
<LayUrl></LayUrl>
<LayKeys></LayKeys>
<LayCat></LayCat>
<LayLic></LayLic>
<LayTarg>0</LayTarg>
<LayPrjMark>1</LayPrjMark>
</Layer>

6
project/at_start_f435/examples/adc/repeat_conversion_loop_transfer/src/at32f435_437_clock.c
View File

@ -46,6 +46,9 @@
*/
void system_clock_config(void)
{
/* reset crm */
crm_reset();
/* enable pwc periph clock */
crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE);
@ -55,9 +58,6 @@ void system_clock_config(void)
/* set the flash clock divider */
flash_clock_divider_set(FLASH_CLOCK_DIV_3);
/* reset crm */
crm_reset();
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
/* wait till hext is ready */

3
project/at_start_f435/examples/adc/resolution_6bit/inc/at32f435_437_conf.h
View File

@ -46,8 +46,9 @@ extern "C" {
* @brief in the following line adjust the high speed exernal crystal (hext) startup
* timeout value
*/
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */
/* module define -------------------------------------------------------------*/
#define CRM_MODULE_ENABLED

4
project/at_start_f435/examples/adc/resolution_6bit/mdk_v5/resolution_6bit.uvoptx
View File

@ -10,9 +10,9 @@
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp; *.cc; *.cxx</CppX>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>

7
project/at_start_f435/examples/adc/resolution_6bit/mdk_v5/resolution_6bit.uvprojx
View File

@ -16,7 +16,7 @@
<TargetCommonOption>
<Device>-AT32F435ZMT7</Device>
<Vendor>ArteryTek</Vendor>
<PackID>ArteryTek.AT32F435_437_DFP.2.1.0</PackID>
<PackID>ArteryTek.AT32F435_437_DFP.2.0.1</PackID>
<Cpu>IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
@ -483,6 +483,11 @@
<Layers>
<Layer>
<LayName>&lt;Project Info&gt;</LayName>
<LayDesc></LayDesc>
<LayUrl></LayUrl>
<LayKeys></LayKeys>
<LayCat></LayCat>
<LayLic></LayLic>
<LayTarg>0</LayTarg>
<LayPrjMark>1</LayPrjMark>
</Layer>

6
project/at_start_f435/examples/adc/resolution_6bit/src/at32f435_437_clock.c
View File

@ -46,6 +46,9 @@
*/
void system_clock_config(void)
{
/* reset crm */
crm_reset();
/* enable pwc periph clock */
crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE);
@ -55,9 +58,6 @@ void system_clock_config(void)
/* set the flash clock divider */
flash_clock_divider_set(FLASH_CLOCK_DIV_3);
/* reset crm */
crm_reset();
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
/* wait till hext is ready */

3
project/at_start_f435/examples/adc/software_trigger_repeat/inc/at32f435_437_conf.h
View File

@ -46,8 +46,9 @@ extern "C" {
* @brief in the following line adjust the high speed exernal crystal (hext) startup
* timeout value
*/
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */
/* module define -------------------------------------------------------------*/
#define CRM_MODULE_ENABLED

4
project/at_start_f435/examples/adc/software_trigger_repeat/mdk_v5/software_trigger_repeat.uvoptx
View File

@ -10,9 +10,9 @@
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp; *.cc; *.cxx</CppX>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>

7
project/at_start_f435/examples/adc/software_trigger_repeat/mdk_v5/software_trigger_repeat.uvprojx
View File

@ -16,7 +16,7 @@
<TargetCommonOption>
<Device>-AT32F435ZMT7</Device>
<Vendor>ArteryTek</Vendor>
<PackID>ArteryTek.AT32F435_437_DFP.2.1.0</PackID>
<PackID>ArteryTek.AT32F435_437_DFP.2.0.1</PackID>
<Cpu>IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
@ -483,6 +483,11 @@
<Layers>
<Layer>
<LayName>&lt;Project Info&gt;</LayName>
<LayDesc></LayDesc>
<LayUrl></LayUrl>
<LayKeys></LayKeys>
<LayCat></LayCat>
<LayLic></LayLic>
<LayTarg>0</LayTarg>
<LayPrjMark>1</LayPrjMark>
</Layer>

6
project/at_start_f435/examples/adc/software_trigger_repeat/src/at32f435_437_clock.c
View File

@ -46,6 +46,9 @@
*/
void system_clock_config(void)
{
/* reset crm */
crm_reset();
/* enable pwc periph clock */
crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE);
@ -55,9 +58,6 @@ void system_clock_config(void)
/* set the flash clock divider */
flash_clock_divider_set(FLASH_CLOCK_DIV_3);
/* reset crm */
crm_reset();
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
/* wait till hext is ready */

3
project/at_start_f435/examples/adc/tmr_trigger_automatic_preempted/inc/at32f435_437_conf.h
View File

@ -46,8 +46,9 @@ extern "C" {
* @brief in the following line adjust the high speed exernal crystal (hext) startup
* timeout value
*/
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */
/* module define -------------------------------------------------------------*/
#define CRM_MODULE_ENABLED

4
project/at_start_f435/examples/adc/tmr_trigger_automatic_preempted/mdk_v5/tmr_trigger_automatic_preempted.uvoptx
View File

@ -10,9 +10,9 @@
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp; *.cc; *.cxx</CppX>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>

7
project/at_start_f435/examples/adc/tmr_trigger_automatic_preempted/mdk_v5/tmr_trigger_automatic_preempted.uvprojx
View File

@ -16,7 +16,7 @@
<TargetCommonOption>
<Device>-AT32F435ZMT7</Device>
<Vendor>ArteryTek</Vendor>
<PackID>ArteryTek.AT32F435_437_DFP.2.1.0</PackID>
<PackID>ArteryTek.AT32F435_437_DFP.2.0.1</PackID>
<Cpu>IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
@ -493,6 +493,11 @@
<Layers>
<Layer>
<LayName>&lt;Project Info&gt;</LayName>
<LayDesc></LayDesc>
<LayUrl></LayUrl>
<LayKeys></LayKeys>
<LayCat></LayCat>
<LayLic></LayLic>
<LayTarg>0</LayTarg>
<LayPrjMark>1</LayPrjMark>
</Layer>

6
project/at_start_f435/examples/adc/tmr_trigger_automatic_preempted/src/at32f435_437_clock.c
View File

@ -46,6 +46,9 @@
*/
void system_clock_config(void)
{
/* reset crm */
crm_reset();
/* enable pwc periph clock */
crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE);
@ -55,9 +58,6 @@ void system_clock_config(void)
/* set the flash clock divider */
flash_clock_divider_set(FLASH_CLOCK_DIV_3);
/* reset crm */
crm_reset();
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
/* wait till hext is ready */

3
project/at_start_f435/examples/adc/use_polling_get_conversion_data/inc/at32f435_437_conf.h
View File

@ -46,8 +46,9 @@ extern "C" {
* @brief in the following line adjust the high speed exernal crystal (hext) startup
* timeout value
*/
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */
/* module define -------------------------------------------------------------*/
#define CRM_MODULE_ENABLED

4
project/at_start_f435/examples/adc/use_polling_get_conversion_data/mdk_v5/use_polling_get_conversion_data.uvoptx
View File

@ -10,9 +10,9 @@
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp; *.cc; *.cxx</CppX>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>

7
project/at_start_f435/examples/adc/use_polling_get_conversion_data/mdk_v5/use_polling_get_conversion_data.uvprojx
View File

@ -16,7 +16,7 @@
<TargetCommonOption>
<Device>-AT32F435ZMT7</Device>
<Vendor>ArteryTek</Vendor>
<PackID>ArteryTek.AT32F435_437_DFP.2.1.0</PackID>
<PackID>ArteryTek.AT32F435_437_DFP.2.0.1</PackID>
<Cpu>IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
@ -493,6 +493,11 @@
<Layers>
<Layer>
<LayName>&lt;Project Info&gt;</LayName>
<LayDesc></LayDesc>
<LayUrl></LayUrl>
<LayKeys></LayKeys>
<LayCat></LayCat>
<LayLic></LayLic>
<LayTarg>0</LayTarg>
<LayPrjMark>1</LayPrjMark>
</Layer>

6
project/at_start_f435/examples/adc/use_polling_get_conversion_data/src/at32f435_437_clock.c
View File

@ -46,6 +46,9 @@
*/
void system_clock_config(void)
{
/* reset crm */
crm_reset();
/* enable pwc periph clock */
crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE);
@ -55,9 +58,6 @@ void system_clock_config(void)
/* set the flash clock divider */
flash_clock_divider_set(FLASH_CLOCK_DIV_3);
/* reset crm */
crm_reset();
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
/* wait till hext is ready */

3
project/at_start_f435/examples/adc/vbat_monitor/inc/at32f435_437_conf.h
View File

@ -46,8 +46,9 @@ extern "C" {
* @brief in the following line adjust the high speed exernal crystal (hext) startup
* timeout value
*/
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */
/* module define -------------------------------------------------------------*/
#define CRM_MODULE_ENABLED

4
project/at_start_f435/examples/adc/vbat_monitor/mdk_v5/vbat_monitor.uvoptx
View File

@ -10,9 +10,9 @@
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp; *.cc; *.cxx</CppX>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>

7
project/at_start_f435/examples/adc/vbat_monitor/mdk_v5/vbat_monitor.uvprojx
View File

@ -16,7 +16,7 @@
<TargetCommonOption>
<Device>-AT32F435ZMT7</Device>
<Vendor>ArteryTek</Vendor>
<PackID>ArteryTek.AT32F435_437_DFP.2.1.0</PackID>
<PackID>ArteryTek.AT32F435_437_DFP.2.0.1</PackID>
<Cpu>IRAM(0x20000000,0x60000) IROM(0x08000000,0x3F0000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
@ -483,6 +483,11 @@
<Layers>
<Layer>
<LayName>&lt;Project Info&gt;</LayName>
<LayDesc></LayDesc>
<LayUrl></LayUrl>
<LayKeys></LayKeys>
<LayCat></LayCat>
<LayLic></LayLic>
<LayTarg>0</LayTarg>
<LayPrjMark>1</LayPrjMark>
</Layer>

6
project/at_start_f435/examples/adc/vbat_monitor/src/at32f435_437_clock.c
View File

@ -46,6 +46,9 @@
*/
void system_clock_config(void)
{
/* reset crm */
crm_reset();
/* enable pwc periph clock */
crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE);
@ -55,9 +58,6 @@ void system_clock_config(void)
/* set the flash clock divider */
flash_clock_divider_set(FLASH_CLOCK_DIV_3);
/* reset crm */
crm_reset();
crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
/* wait till hext is ready */

3
project/at_start_f435/examples/adc/voltage_monitoring/inc/at32f435_437_conf.h
View File

@ -46,8 +46,9 @@ extern "C" {
* @brief in the following line adjust the high speed exernal crystal (hext) startup
* timeout value
*/
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed exernal clock in hz */
/* module define -------------------------------------------------------------*/
#define CRM_MODULE_ENABLED

4
project/at_start_f435/examples/adc/voltage_monitoring/mdk_v5/voltage_monitoring.uvoptx
View File

@ -10,9 +10,9 @@
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc; *.md</tExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp; *.cc; *.cxx</CppX>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>

Some files were not shown because too many files have changed in this diff Show More