I've got build failure when enable CRC module on STM32. The reason is SW CRC header is included by default but not by compiler if ChibiOS-Contrib/os/various/ is not included into search path.
The fix includes only requested LL header.
By default B4 has the JTAG NJRST signal with a pull up enabled. On the longan Nano
this PIN is broken out as a regular pin. So we just disable NJRST by default
and make it available as a regular GPIO.
Without this change, the ChibiOS shell prompt does not show up reliably on
Linux, and possibly other operating systems.
For a detailed walk-through covering the individual problems and causes, see:
https://michael.stapelberg.ch/posts/2021-04-27-linux-usb-virtual-serial-cdc-acm/
I verified that this approach works with:
1. Linux 5.10
2. Windows 10
3. macOS Big Sur on a MacBook Air M1
An oversight when arrangeing the code according to the nucleisys docs,
t0 was overriden with the value of msubm and never actually restored. To
fix the issue we restore the csrs after the general purpose registers.
The offical docs want it the other way around but this should be fine as
well, as the interrupts are still globaly disabled at this point.
The first attempt to solve illegal instruction expections was made in commit
b875108cd0
It seemed as this "fixed" the issue, but merely added delays in the code
which prevented the error to appear in lucky circumstances. Interesting that this code worked in the first place.
Root cause for the expections where write attempts to mstatus in
user privilege mode which raised the illegal instruction exception which
is in spec with the risc-v privileged isa and documented in the
bumbleebee core architecture manual by nucleisys. The solution is
to never enter user mode by forceing mcause.mpp to 0x3
before calling mret when exiting the interrupt handler
for context switching.
Fast subsequent reads and writes to the mstatus csr lead to
illegal instruction exceptions on the nucleisys bumblee core
of the gd32vf103. This behavior only occurred in high load
situations e.g. interrupt frequency of 5khz but reliably let
to these errors. Adding the instruction and memory barriers solved
the problem. There is some negligible performance impact.
a_p_u_r_o
Alex Lewontin
Stefan Kerkmann
Fabien Poussin
snazarkin
José Simões
andru
Andrey Gusakov
andru
fauxpark
Michael Stapelberg