- Fix return value on succesfull scsi_requestsense.
- Fix calls to LL SMT32 API for OTG2.
- Port changes from ChibiOS fatfs_diskio.
- Rework checks to allow simultaneous use of SD Card and USB MSD.
Signed-off-by: José Simões <jose.simoes@eclo.solutions>
This was removed in commit
ae7a4d40b84d8afc999691577210696f16e682f6#diff-7ddaa5ecc31109f41b7801dea2660b47
But I think is still necessary as the underlying rccEnableAHB macros
take parameter 'lp'. It seems to work for the F0xx series, because its
rccEnableAHB ignores the 'lp'. It is required when I tried to use the
CRC driver on a family that does require the 'lp' parameter in the lower
level macros.
list_for_each_entry_safe is only safe when the current entry is being removed.
If other entries in the list could potentially be removed it can result in an infinite loop.
Because usbh_lld_ep_close blocks on each urb during iteration, it may give up its lock on
the system and allow an interrupt to remove a different urb from the list,
resulting in an infinite loop when the thread resumes.
RCC API changed in 01/2018 so apply the changes.
Note that ae7a4d40b8 partially fixed the changes in QEI module but some were missing.
So update the other modules too.
RCC API changed in 01/2018 so apply the changes.
Note that ae7a4d40b8 partially fixed the changes in QEI module but some were missing.
So update the other modules too.
- general cleanup
- implemented workaround to undocumented erratum (the OTG core may
report successful enabling of port when connecting a low-speed device,
but really it generates no traffic and remains in a "dumb" state)
- improved handling of disconnection of devices (avoid submitting URBs
if the port is disabled)
- Cleaned up alignment macros for GCC & IAR
- Corrected EP halt and Clear halt behaviours
- Initialization of class drivers by USB Host main driver
- Minor cosmetic fixes
- Updated USB_HOST testhal app
1) Control registers writes reordered in init sequence to eliminate
incorrect output clock frequnency in short period after CCLKEN bit
set and B(W)TR registers set.
2) Added reset of CCLEN bit in stop procedure.