Rename paltatech naming to Axiom.
For safety set Axiom default max input voltage to 0.0V so it can not run a
motor without mc_conf being explicitly configured by the user.
Signed-off-by: Marcos Chaparro <mchaparro@powerdesigns.ca>
2 failure modes added:
* On boot, when calculating DC offsets generate a fault if the offset is beyond
HW_MAX_CURRENT_OFFSET. Fault code reports which sensor is having issues (1, 2 or 3).
Most likely cause is a disconnected sensor, if hw has fault-detecting pullups.
* On runtime, in setups with 3 in-line phase current sensors, checks that the sum
of the currents is below MCCONF_MAX_CURRENT_UNBALANCE, with a configurable low pass
filter. If unbalanced current is high, it means a fault to ground, or a disconnected
sensor (this works at 0 Amp if hw has pullups in the sensor input to detect the
failure).
Signed-off-by: Marcos Chaparro <mchaparro@powerdesigns.ca>
Ensures the memory addresses used for flash memory integrity check
are initially 0xFFFFFFFF, so the application can write a new CRC in the
first boot.
Signed-off-by: Marcos Chaparro <mchaparro@powerdesigns.ca>
Create a new, low priority thread that checks that the CRC of the
flash memory matches the CRC stored in flash.
8kB chunks are computed every 50 milliseconds. A reset is invoked if
CRC does not match.
Signed-off-by: Marcos Chaparro <mchaparro@powerdesigns.ca>
Only unlock when it is necessary to write it. This prevents memory
corruptions caused by software or EMI glitches.
Signed-off-by: Marcos Chaparro <mchaparro@powerdesigns.ca>
The check only covers address 0x08008000 to 0x805FFFF, where application
code is stored. It excludes virtual eeprom area (first 0x8000 bytes)
because it is modified on runtime with user configurations.
After a fresh flash programming the CRC is read as 0xFFFFFFFF and firmware
computes and stores the new CRC and a reset is invoked.
After reset the CRC will be available for checking code integrity.
Linker file had a wrong flash2 size, it was set to 480kB, thus allowing
the linking of binaries larger than 393216 (x3 128kB sectors).
The bootloader won't program binaries that span more than 3 sectors.
Now flash2 length is set as (393216 - 8) to ensure that the last 8 bytes
are left blank (0xFFFF) and reserved for CRC information.
Signed-off-by: Marcos Chaparro <mchaparro@powerdesigns.ca>