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Merge pull request #317 from SonixQMK/sn32_master_2.11 

Sonix SN32 series support
This commit is contained in:
Fabien Poussin 2022-04-18 12:52:20 +02:00 committed by GitHub
parent 934631adbd e201116e61
commit e775cbbc88
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GPG Key ID: 4AEE18F83AFDEB23
162 changed files with 48271 additions and 0 deletions
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os/common/ext/SONiX/SN32F2xx/SN32F200_Def.h Normal file
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#ifndef __SN32F200_DEF_H
#define __SN32F200_DEF_H
/*_____ I N C L U D E S ____________________________________________________*/
/*_____ D E F I N I T I O N S ______________________________________________*/
//Ture or False
// #define TRUE 0x1
// #define FALSE 0x0
//Enable or Disable
#define ENABLE 0x1
#define DISABLE 0x0
//Error Status
#define OK 0x0
#define FAIL 0x1
//Null
// #define NULL 0
//Interrupt Flag Parsing Method
#define POLLING_METHOD 0x0
#define INTERRUPT_METHOD 0x1
//;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
//SN32F230_PKG
#define SN32F239 0
#define SN32F238 1
#define SN32F237 2
#define SN32F236 3
#define SN32F235 4
//SN32F240_PKG
#define SN32F249 0
#define SN32F248 1
#define SN32F247 2
#define SN32F246 3
#define SN32F245 4
//SN32F240B_PKG
#define SN32F248B 0
#define SN32F247B 1
#define SN32F246B 2
#define SN32F2451B 3
//SN32F260_PKG
#define SN32F268 0
#define SN32F267 1
#define SN32F265 2
#define SN32F2641 3
#define SN32F264 4
#define SN32F263 5
//;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
/*_____ M A C R O S ________________________________________________________*/
/*_____ D E C L A R A T I O N S ____________________________________________*/
#endif /*__SN32F200_DEF_H*/

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os/common/ext/SONiX/SN32F2xx/SN32F240.h Normal file
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os/common/ext/SONiX/SN32F2xx/SN32F240B.h Normal file
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os/common/ext/SONiX/SN32F2xx/SN32F260.h Normal file
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os/common/ext/SONiX/SN32F2xx/SN32F260_defines.h Normal file
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os/common/ext/SONiX/SN32F2xx/SN32F2xx.h Normal file
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#ifndef __SN32F2xx_H
#define __SN32F2xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Library_configuration_section
* @{
*/
/**
* @brief SN32 Family
*/
#if !defined (SN32F2)
#define SN32F2
#endif /* SN32F2 */
/* Uncomment the line below according to the target SN32 device used in your
application
*/
#if !defined (SN32F240) && !defined (SN32F240B) && !defined (SN32F260) \
&& !defined (SN32F280) && !defined (SN32F290)
/* #define SN32F230 */ /*!< SN32F239, SN32F238, SN32F237, SN32F236,and SN32F235 Devices */
/* #define SN32F240 */ /*!< SN32F249, SN32F248, SN32F247, SN32F246 and SN32F245 Devices */
/* #define SN32F240B */ /*!< SN32F248B, SN32F247B, SN32F246B and SN32F2451B Devices */
/* #define SN32F260 */ /*!< SN32F268, SN32F267, SN32F265, SN32F2641,
SN32F264 and SN32F263 Devices */
/* #define SN32F280 */ /*!< SN32F289, SN32F288 and SN32F287 Devices */
/* #define SN32F290 */ /*!< SN32F299. SN32F298 and SN32F297 Devices */
#include "board.h"
#endif
/** @addtogroup Device_Included
* @{
*/
#if defined(SN32F240)
#include "SN32F240.h"
#elif defined(SN32F240B)
#include "SN32F240B.h"
#elif defined(SN32F260)
#include "SN32F260.h"
#elif defined(SN32F280)
#include "SN32F280.h"
#elif defined(SN32F290)
#include "SN32F290.h"
#else
#error "Please select first the target SN32F2xx device used in your application (in SN32F2xx.h file)"
#endif
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /*__SN32F2xx_H*/

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os/common/ext/SONiX/SN32F2xx/system_SN32F240.c Normal file
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/******************************************************************************
* @file system_SN32F240.c
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File
* for the SONIX SN32F240 Devices
* @version V1.1.1
* @date 2015/08/21
*
* @note
* Copyright (C) 2009-2013 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
#include <system_SN32F2xx.h>
#include <mcuconf.h>
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*--------------------- Clock Configuration ----------------------------------
//
//<e> System Clock Configuration
// <o1.0..2> SYSCLKSEL (SYS0_CLKCFG)
// <0=> IHRC
// <1=> ILRC
// <2=> EHS X'TAL
// <3=> ELS X'TAL
// <4=> PLL
//
// <o2> EHS Source Frequency (MHz)
// <10-25>
//
// <h> PLL Control Register (SYS0_PLLCTRL)
// <i> F_CLKOUT = F_VCO / P = (F_CLKIN / F * M) / P
// <i> 10 MHz <= F_CLKIN <= 25 MHz
// <i> 156 MHz <= (F_CLKIN / F * M) <= 320 MHz
// <o3> MSEL
// <3-31>
// <o4> PSEL
// <3=> P = 6
// <4=> P = 8
// <5=> P = 10
// <6=> P = 12
// <7=> P = 14
// <o5> FSEL
// <0=> F = 1
// <1=> F = 2
// <o6> PLL CLKIN Source selection
// <0=> IHRC
// <1=> EHS X'TAL
// <o7> PLL Enable selection
// <0=> Disable
// <1=> Enable
// </h>
//
// <o8> AHB Clock Prescaler Register (SYS0_AHBCP)
// <0=> SYSCLK/1
// <1=> SYSCLK/2
// <2=> SYSCLK/4
// <3=> SYSCLK/8
// <4=> SYSCLK/16
// <5=> SYSCLK/32
// <6=> SYSCLK/64
// <7=> SYSCLK/128
// <8=> SYSCLK/256
// <9=> SYSCLK/512
//
// <o9> CLKOUT selection
// <0=> Disable
// <1=> ILRC
// <2=> ELS X'TAL
// <4=> HCLK
// <5=> IHRC
// <6=> EHS X'TAL
// <7=> PLL
//</e>
*/
#ifndef SYS_CLOCK_SETUP
#define SYS_CLOCK_SETUP 1
#endif
#ifndef SYS0_CLKCFG_VAL
#define SYS0_CLKCFG_VAL 0
#endif
#ifndef EHS_FREQ
#define EHS_FREQ 10
#endif
#ifndef PLL_MSEL
#define PLL_MSEL 12
#endif
#ifndef PLL_PSEL
#define PLL_PSEL 3
#endif
#ifndef PLL_FSEL
#define PLL_FSEL 0
#endif
#ifndef PLL_CLKIN
#define PLL_CLKIN 1
#endif
#ifndef PLL_ENABLE
#define PLL_ENABLE 0
#endif
#ifndef AHB_PRESCALAR
#define AHB_PRESCALAR 0x0
#endif
#ifndef CLKOUT_SEL_VAL
#define CLKOUT_SEL_VAL 0x0
#endif
/*
//-------- <<< end of configuration section >>> ------------------------------
*/
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
#ifndef IHRC
#define IHRC 0
#endif
#ifndef ILRC
#define ILRC 1
#endif
#ifndef EHSXTAL
#define EHSXTAL 2
#endif
#ifndef ELSXTAL
#define ELSXTAL 3
#endif
#ifndef PLL
#define PLL 4
#endif
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define __IHRC_FREQ (12000000UL)
#define __ILRC_FREQ (32000UL)
#define __ELS_XTAL_FREQ (32768UL)
#if (SYS_CLOCK_SETUP)
#define SYS0_PLLCTRL_VAL (PLL_ENABLE<<15) | (PLL_CLKIN<<12) | (PLL_FSEL<<8) | (PLL_PSEL<<5) | PLL_MSEL
#endif
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
uint32_t AHB_prescaler = 0;
uint32_t F;
switch (SN_SYS0->CLKCFG_b.SYSCLKST)
{
case 0: //IHRC
SystemCoreClock = __IHRC_FREQ;
break;
case 1: //ILRC
SystemCoreClock = __ILRC_FREQ;
break;
case 2: //EHS X'TAL
#if (SYS_CLOCK_SETUP)
SystemCoreClock = EHS_FREQ * 1000000;
#else
//TODO: User had to assign EHS X'TAL frequency.
SystemCoreClock = 10000000UL / AHB_prescaler;
#endif
break;
case 3: //ELS X'TAL
SystemCoreClock = __ELS_XTAL_FREQ;
break;
case 4: //PLL
#if (SYS_CLOCK_SETUP)
if (PLL_FSEL == 0)
F = 1;
else
F = 2;
if (PLL_CLKIN == 0x0) //IHRC as F_CLKIN
SystemCoreClock = __IHRC_FREQ / F * PLL_MSEL / PLL_PSEL /2;
else
SystemCoreClock = EHS_FREQ * 1000000 / F * PLL_MSEL / PLL_PSEL /2;
#else
//TODO: User had to assign PLL output frequency.
SystemCoreClock = 50000000UL;
#endif
break;
default:
break;
}
switch (SN_SYS0->AHBCP)
{
case 0: AHB_prescaler = 1; break;
case 1: AHB_prescaler = 2; break;
case 2: AHB_prescaler = 4; break;
case 3: AHB_prescaler = 8; break;
case 4: AHB_prescaler = 16; break;
case 5: AHB_prescaler = 32; break;
case 6: AHB_prescaler = 64; break;
case 7: AHB_prescaler = 128;break;
case 8: AHB_prescaler = 256;break;
case 9: AHB_prescaler = 512;break;
default: break;
}
SystemCoreClock /= AHB_prescaler;
return;
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
#if (SYS_CLOCK_SETUP)
#if SYS0_CLKCFG_VAL == IHRC //IHRC
#endif
#if SYS0_CLKCFG_VAL == ILRC //ILRC
SN_SYS0->CLKCFG = 0x1;
while ((SN_SYS0->CLKCFG & 0x70) != 0x10);
#endif
#if (SYS0_CLKCFG_VAL == EHSXTAL) //EHS XTAL
#if (EHS_FREQ > 12)
SN_SYS0->ANBCTRL |= (1<<5);
#else
SN_SYS0->ANBCTRL &=~(1<<5);
#endif
SN_SYS0->ANBCTRL |= (1<<4);
while ((SN_SYS0->CSST & 0x10) != 0x10);
SN_SYS0->CLKCFG = 0x2;
while ((SN_SYS0->CLKCFG & 0x70) != 0x20);
#endif
#if (SYS0_CLKCFG_VAL == ELSXTAL) //ELS XTAL
SN_SYS0->ANBCTRL |=0x04;
while((SN_SYS0->CSST & 0x4) != 0x4);
SN_SYS0->CLKCFG = 0x3;
while ((SN_SYS0->CLKCFG & 0x70) != 0x30);
#endif
#if (SYS0_CLKCFG_VAL == PLL) //PLL
SN_SYS0->PLLCTRL = SYS0_PLLCTRL_VAL;
if (PLL_CLKIN == 0x1) //EHS XTAL as F_CLKIN
{
//Enable EHS
#if (EHS_FREQ > 12)
SN_SYS0->ANBCTRL |= (1<<5);
#else
SN_SYS0->ANBCTRL &=~(1<<5);
#endif
SN_SYS0->ANBCTRL |= (1<<4);
while ((SN_SYS0->CSST & 0x10) != 0x10);
}
while ((SN_SYS0->CSST & 0x40) != 0x40);
SN_SYS0->CLKCFG = 0x4;
while ((SN_SYS0->CLKCFG & 0x70) != 0x40);
#endif
SN_SYS0->AHBCP = AHB_PRESCALAR;
#if (CLKOUT_SEL_VAL > 0) //CLKOUT
SN_SYS1->AHBCLKEN_b.CLKOUTSEL = CLKOUT_SEL_VAL;
#endif
#endif //(SYS_CLOCK_SETUP)
}

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os/common/ext/SONiX/SN32F2xx/system_SN32F240B.c Normal file
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/******************************************************************************
* @file system_SN32F240B.c
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File
* for the SONIX SN32F240B Devices
* @version V1.0.3
* @date 2018/09/18
*
* @note
* Copyright (C) 2014-2018 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
#include <system_SN32F2xx.h>
#include <mcuconf.h>
#include <sn32_sys1.h>
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*--------------------- Clock Configuration ----------------------------------
//
//<e> System Clock Configuration
// <o1> SYSCLKSEL (SYS0_CLKCFG)
// <0=> IHRC=48MHz
// <1=> ILRC
//
// <o2> AHB Clock Prescaler Register (SYS0_AHBCP)
// <0=> SYSCLK/1
// <1=> SYSCLK/2
// <2=> SYSCLK/4
// <3=> SYSCLK/8
// <4=> SYSCLK/16
// <5=> SYSCLK/32
// <6=> SYSCLK/64
// <7=> SYSCLK/128
//
// <o3> CLKOUT selection
// <0=> Disable
// <1=> ILRC
// <4=> HCLK
// <5=> IHRC
//
// <o4> CLKOUT Prescaler Register (SYS1_APBCP1)
// <0=> CLKOUT/1
// <1=> CLKOUT/2
// <2=> CLKOUT/4
// <3=> CLKOUT/8
// <4=> CLKOUT/16
// <5=> CLKOUT/32
// <6=> CLKOUT/64
// <7=> CLKOUT/128
//</e>
*/
#ifndef SYS_CLOCK_SETUP
#define SYS_CLOCK_SETUP 1
#endif
#ifndef SYS0_CLKCFG_VAL
#define SYS0_CLKCFG_VAL 0
#endif
#ifndef AHB_PRESCALAR
#define AHB_PRESCALAR 0x0
#endif
#ifndef CLKOUT_SEL_VAL
#define CLKOUT_SEL_VAL 0x0
#endif
#ifndef CLKOUT_PRESCALAR
#define CLKOUT_PRESCALAR 0x0
#endif
/*
//-------- <<< end of configuration section >>> ------------------------------
*/
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
#ifndef IHRC48
#define IHRC48 0
#endif
#ifndef ILRC
#define ILRC 1
#endif
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define __IHRC48_FREQ (48000000UL)
#define __ILRC_FREQ (32000UL)
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
uint32_t AHB_prescaler = 0;
switch (SN_SYS0->CLKCFG_b.SYSCLKST)
{
case 0: //IHRC
if(SN_SYS0->ANBCTRL == 1)
SystemCoreClock = __IHRC48_FREQ;
break;
case 1: //ILRC
SystemCoreClock = __ILRC_FREQ;
break;
default:
break;
}
switch (SN_SYS0->AHBCP_b.AHBPRE)
{
case 0: AHB_prescaler = 1; break;
case 1: AHB_prescaler = 2; break;
case 2: AHB_prescaler = 4; break;
case 3: AHB_prescaler = 8; break;
case 4: AHB_prescaler = 16; break;
case 5: AHB_prescaler = 32; break;
case 6: AHB_prescaler = 64; break;
case 7: AHB_prescaler = 128;break;
default: break;
}
SystemCoreClock /= AHB_prescaler;
}
/**
* Initialize the Flash controller
*
* @param none
* @return none
*
* @brief Update the Flash power control.
*/
void FlashClockUpdate (void)
{
//;;;;;;;;; Need for SN32F240B Begin
if (SystemCoreClock > 24000000)
SN_FLASH->LPCTRL = 0x5AFA0005;
else if (SystemCoreClock > 12000000)
SN_FLASH->LPCTRL = 0x5AFA0003;
else if (SystemCoreClock > 8000)
SN_FLASH->LPCTRL = 0x5AFA0000;
else //Slow mode required for SystemCoreClock <= 8000
SlowModeSwitch();
//;;;;;;;;; Need for SN32F240B End
}
/**
* Switch System to Slow Mode
* @param none
* @return none
*
* @brief Special init required for SystemCoreClock <= 8000
*/
void SlowModeSwitch (void)
{
SN_SYS0->CLKCFG_b.SYSCLKSEL = 1; //Switch to ILRC
SN_SYS0->AHBCP_b.AHBPRE =0x2; //8kHz only for now
SystemCoreClockUpdate();
SN_FLASH->LPCTRL = 0x5AFA0002;
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
#if (SYS_CLOCK_SETUP)
#if SYS0_CLKCFG_VAL == IHRC48 //IHRC=48MHz
SN_FLASH->LPCTRL = 0x5AFA0005;
SN_SYS0->ANBCTRL = 0x1;
while ((SN_SYS0->CSST & 0x1) != 0x1);
SN_SYS0->CLKCFG = 0x0;
while ((SN_SYS0->CLKCFG & 0x70) != 0x0);
#endif
#if SYS0_CLKCFG_VAL == ILRC //ILRC ON
SN_FLASH->LPCTRL = 0x5AFA0000;
SN_SYS0->CLKCFG = 0x1;
while ((SN_SYS0->CLKCFG & 0x70) != 0x10);
#endif
SN_SYS0->AHBCP_b.AHBPRE = AHB_PRESCALAR;
sys1EnableCLKOUT(CLKOUT_SEL_VAL);
sys1SelectCLKOUTPRE(CLKOUT_PRESCALAR);
#endif //(SYS_CLOCK_SETUP)
}

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/******************************************************************************
* @file system_SN32F260.c
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File
* for the SONIX SN32F260 Devices
* @version V1.0.3
* @date 2016/01/21
*
* @note
* Copyright (C) 2014-2015 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
#include <system_SN32F2xx.h>
#include <mcuconf.h>
#include <sn32_sys1.h>
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*--------------------- Clock Configuration ----------------------------------
//
//<e> System Clock Configuration
// <o1> SYSCLKSEL (SYS0_CLKCFG)
// <0=> IHRC
// <1=> ILRC
//
// <o2> AHB Clock Prescaler Register (SYS0_AHBCP)
// <0=> SYSCLK/1
// <1=> SYSCLK/2
// <2=> SYSCLK/4
// <3=> SYSCLK/8
// <4=> SYSCLK/16
// <5=> SYSCLK/32
// <6=> SYSCLK/64
// <7=> SYSCLK/128
//
// <o3> CLKOUT selection
// <0=> Disable
// <1=> ILRC
// <4=> HCLK
// <5=> IHRC
//</e>
*/
#ifndef SYS_CLOCK_SETUP
#define SYS_CLOCK_SETUP 1
#endif
#ifndef SYS0_CLKCFG_VAL
#define SYS0_CLKCFG_VAL 0
#endif
#ifndef AHB_PRESCALAR
#define AHB_PRESCALAR 0x0
#endif
#ifndef CLKOUT_SEL_VAL
#define CLKOUT_SEL_VAL 0x0
#endif
/*
//-------- <<< end of configuration section >>> ------------------------------
*/
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
#ifndef IHRC
#define IHRC 0
#endif
#ifndef ILRC
#define ILRC 1
#endif
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define __IHRC_FREQ (48000000UL)
#define __ILRC_FREQ (32000UL)
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
uint32_t AHB_prescaler;
switch ((SN_SYS0->CLKCFG >> 4) & 0x07)
{
case 0: //IHRC
SystemCoreClock = __IHRC_FREQ;
break;
case 1: //ILRC
SystemCoreClock = __ILRC_FREQ;
break;
default:
break;
}
switch (AHB_PRESCALAR)
{
case 0: AHB_prescaler = 1; break;
case 1: AHB_prescaler = 2; break;
case 2: AHB_prescaler = 4; break;
case 3: AHB_prescaler = 8; break;
case 4: AHB_prescaler = 16; break;
case 5: AHB_prescaler = 32; break;
case 6: AHB_prescaler = 64; break;
case 7: AHB_prescaler = 128;break;
default: break;
}
SystemCoreClock /= AHB_prescaler;
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
#if (SYS_CLOCK_SETUP)
#if SYS0_CLKCFG_VAL == IHRC //IHRC
#if (AHB_PRESCALAR == 0 | AHB_PRESCALAR == 1)
SN_FLASH->LPCTRL = 0x5AFA0005;
#else
SN_FLASH->LPCTRL = 0x5AFA0000;
#endif
SN_SYS0->AHBCP = AHB_PRESCALAR;
SN_SYS0->CLKCFG = 0x0;
while ((SN_SYS0->CLKCFG & 0x70) != 0x0);
#endif
#if SYS0_CLKCFG_VAL == ILRC //ILRC
SN_FLASH->LPCTRL = 0x5AFA0000;
SN_SYS0->CLKCFG = 0x1;
while ((SN_SYS0->CLKCFG & 0x70) != 0x10);
SN_SYS0->AHBCP = AHB_PRESCALAR;
#endif
sys1EnableCLKOUT(CLKOUT_SEL_VAL);
#endif //(SYS_CLOCK_SETUP)
}

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/******************************************************************************
* @file system_SN32F280.c
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File
* for the SONIX SN32F790 Devices
* @version V0.0.5
* @date 2018/06/14
*
* @note
* Copyright (C) 2016-2017 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
#include <system_SN32F2xx.h>
#include <mcuconf.h>
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*--------------------- Clock Configuration ----------------------------------
//
// <o0.0..2> SYSCLKSEL (SYS0_CLKCFG)
// <0=> IHRC
// <1=> ILRC
// <2=> EHS X'TAL
// <3=> ELS X'TAL
// <4=> PLL
//
// <o1> EHS Source Frequency (MHz)
// <10-25>
//
//<e2> PLL ENABLE
// <h> PLL Control Register (SYS0_PLLCTRL)
// <i> F_CLKOUT = F_VCO / P = (F_CLKIN * M) / P
// <i> 10 MHz <= F_CLKIN <= 25 MHz
// <i> 96 MHz <= (F_CLKIN * M) <= 144 MHz
// <o3> MSEL
// <0=> M = 4
// <1=> M = 6
// <2=> M = 8
// <3=> M = 10
// <4=> M = 12
// <o4> PSEL
// <0=> P = 2
// <1=> P = 4
// <o5> PLL CLKIN Source selection
// <0=> IHRC
// <1=> EHS X'TAL
// </h>
//</e>
// <o6> AHB Clock Prescaler Register (SYS0_AHBCP)
// <0=> SYSCLK/1
// <1=> SYSCLK/2
// <2=> SYSCLK/4
// <3=> SYSCLK/8
// <4=> SYSCLK/16
// <5=> SYSCLK/32
// <6=> SYSCLK/64
// <7=> SYSCLK/128
// <o7> SYSCLK prescaler Register (SYS0_AHBCP)
// <0=> SYSCLK/1
// <1=> SYSCLK/1.5
// <o8> CLKOUT selection
// <0=> Disable
// <1=> ILRC
// <2=> ELS X'TAL
// <4=> HCLK
// <5=> IHRC
// <6=> EHS X'TAL
// <7=> PLL
// <o9> CLKOUT Prescaler Register (SYS1_APBCP1)
// <0=> CLKOUT selection/1
// <1=> CLKOUT selection/2
// <2=> CLKOUT selection/4
// <3=> CLKOUT selection/8
// <4=> CLKOUT selection/16
// <5=> CLKOUT selection/32
// <6=> CLKOUT selection/64
// <7=> CLKOUT selection/128
*/
#ifndef SYS0_CLKCFG_VAL
#define SYS0_CLKCFG_VAL 0
#endif
#ifndef EHS_FREQ
#define EHS_FREQ 16
#endif
#ifndef PLL_ENABLE
#define PLL_ENABLE 0
#endif
#ifndef PLL_MSEL
#define PLL_MSEL 1
#endif
#ifndef PLL_PSEL
#define PLL_PSEL 0
#endif
#ifndef PLL_CLKIN
#define PLL_CLKIN 0
#endif
#ifndef AHB_PRESCALAR
#define AHB_PRESCALAR 0x0
#endif
#ifndef AHB_1P5PRESCALAR
#define AHB_1P5PRESCALAR 0x0
#endif
#ifndef CLKOUT_SEL_VAL
#define CLKOUT_SEL_VAL 0x0
#endif
#ifndef CLKOUT_PRESCALAR
#define CLKOUT_PRESCALAR 0x0
#endif
/*
//-------- <<< end of configuration section >>> ------------------------------
*/
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
#ifndef IHRC
#define IHRC 0
#endif
#ifndef ILRC
#define ILRC 1
#endif
#ifndef EHSXTAL
#define EHSXTAL 2
#endif
#ifndef ELSXTAL
#define ELSXTAL 3
#endif
#ifndef PLL
#define PLL 4
#endif
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define __IHRC_FREQ (12000000UL)
#define __ILRC_FREQ (32000UL)
#define __ELS_XTAL_FREQ (32768UL)
#define SYS0_PLLCTRL_VAL (PLL_ENABLE<<15) | (PLL_CLKIN<<12) | (PLL_PSEL<<5) | PLL_MSEL
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
uint32_t AHB_prescaler;
switch (SN_SYS0->CLKCFG_b.SYSCLKST)
{
case 0: //IHRC
SystemCoreClock = __IHRC_FREQ;
break;
case 1: //ILRC
SystemCoreClock = __ILRC_FREQ;
break;
case 2: //EHS X'TAL
SystemCoreClock = EHS_FREQ * 1000000;
break;
case 3: //ELS X'TAL
SystemCoreClock = __ELS_XTAL_FREQ;
break;
case 4: //PLL
if (PLL_CLKIN == 0x0) //IHRC as F_CLKIN
SystemCoreClock = __IHRC_FREQ * (PLL_MSEL+2) / (PLL_PSEL+1);
else
SystemCoreClock = EHS_FREQ * 1000000 * (PLL_MSEL+2) / (PLL_PSEL+1);
break;
default:
break;
}
switch (SN_SYS0->AHBCP)
{
case 0: AHB_prescaler = 1; break;
case 1: AHB_prescaler = 2; break;
case 2: AHB_prescaler = 4; break;
case 3: AHB_prescaler = 8; break;
case 4: AHB_prescaler = 16; break;
case 5: AHB_prescaler = 32; break;
case 6: AHB_prescaler = 64; break;
case 7: AHB_prescaler = 128;break;
default: break;
}
SystemCoreClock /= AHB_prescaler;
if (SN_SYS0->AHBCP_b.DIV1P5 == 1)
SystemCoreClock = SystemCoreClock*2/3;
//;;;;;;;;; Need for SN32F780 Begin ;;;;;;;;;
if (SystemCoreClock > 48000000)
SN_FLASH->LPCTRL = 0x5AFA0031;
else if (SystemCoreClock > 24000000)
SN_FLASH->LPCTRL = 0x5AFA0011;
else
SN_FLASH->LPCTRL = 0x5AFA0000;
//;;;;;;;;; Need for SN32F780 End ;;;;;;;;;
return;
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
#if SYS0_CLKCFG_VAL == IHRC //IHRC
SN_SYS0->CLKCFG = 0x0;
while ((SN_SYS0->CLKCFG & 0x70) != 0x0);
#endif
#if SYS0_CLKCFG_VAL == ILRC //ILRC
SN_SYS0->CLKCFG = 0x1;
while ((SN_SYS0->CLKCFG & 0x70) != 0x10);
#endif
#if (SYS0_CLKCFG_VAL == EHSXTAL) //EHS XTAL
#if (EHS_FREQ > 12)
SN_SYS0->ANBCTRL_b.EHSFREQ = 1;
SN_FLASH->LPCTRL = 0x5AFA0011;
#else
SN_SYS0->ANBCTRL_b.EHSFREQ = 0;
#endif
SN_SYS0->ANBCTRL_b.EHSEN = 1;
while ((SN_SYS0->CSST & 0x10) != 0x10);
SN_SYS0->CLKCFG = 0x2;
while ((SN_SYS0->CLKCFG & 0x70) != 0x20);
#endif
#if (SYS0_CLKCFG_VAL == ELSXTAL) //ELS XTAL
SN_SYS0->ANBCTRL_b.ELSEN = 1;
while((SN_SYS0->CSST & 0x4) != 0x4);
SN_SYS0->CLKCFG = 0x3;
while ((SN_SYS0->CLKCFG & 0x70) != 0x30);
#endif
#if (PLL_ENABLE == 1)
SN_SYS0->PLLCTRL = SYS0_PLLCTRL_VAL;
if (PLL_CLKIN == 0x1) //EHS XTAL as F_CLKIN
{
//Enable EHS
#if (EHS_FREQ > 12)
SN_SYS0->ANBCTRL_b.EHSFREQ = 1;
#else
SN_SYS0->ANBCTRL_b.EHSFREQ = 0;
#endif
SN_SYS0->ANBCTRL_b.EHSEN = 1;
while ((SN_SYS0->CSST & 0x10) != 0x10);
}
while ((SN_SYS0->CSST & 0x40) != 0x40);
#if (SYS0_CLKCFG_VAL == PLL) //PLL
SN_FLASH->LPCTRL = 0x5AFA0031;
SN_SYS0->CLKCFG = 0x4;
while ((SN_SYS0->CLKCFG & 0x70) != 0x40);
#endif
#endif
SN_SYS0->AHBCP = AHB_PRESCALAR;
SN_SYS0->AHBCP_b.DIV1P5 = AHB_1P5PRESCALAR;
#if (CLKOUT_SEL_VAL > 0) //CLKOUT
SN_SYS1->AHBCLKEN_b.CLKOUTSEL = CLKOUT_SEL_VAL;
SN_SYS1->APBCP1_b.CLKOUTPRE = CLKOUT_PRESCALAR;
#endif
}

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/******************************************************************************
* @file system_SN32F290.c
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File
* for the SONIX SN32F790 Devices
* @version V0.0.5
* @date 2018/06/14
*
* @note
* Copyright (C) 2016-2017 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
#include <system_SN32F2xx.h>
#include <mcuconf.h>
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*--------------------- Clock Configuration ----------------------------------
//
// <o0.0..2> SYSCLKSEL (SYS0_CLKCFG)
// <0=> IHRC
// <1=> ILRC
// <2=> EHS X'TAL
// <3=> ELS X'TAL
// <4=> PLL
//
// <o1> EHS Source Frequency (MHz)
// <10-25>
//
//<e2> PLL ENABLE
// <h> PLL Control Register (SYS0_PLLCTRL)
// <i> F_CLKOUT = F_VCO / P = (F_CLKIN * M) / P
// <i> 10 MHz <= F_CLKIN <= 25 MHz
// <i> 96 MHz <= (F_CLKIN * M) <= 144 MHz
// <o3> MSEL
// <0=> M = 4
// <1=> M = 6
// <2=> M = 8
// <3=> M = 10
// <4=> M = 12
// <o4> PSEL
// <0=> P = 2
// <1=> P = 4
// <o5> PLL CLKIN Source selection
// <0=> IHRC
// <1=> EHS X'TAL
// </h>
//</e>
// <o6> AHB Clock Prescaler Register (SYS0_AHBCP)
// <0=> SYSCLK/1
// <1=> SYSCLK/2
// <2=> SYSCLK/4
// <3=> SYSCLK/8
// <4=> SYSCLK/16
// <5=> SYSCLK/32
// <6=> SYSCLK/64
// <7=> SYSCLK/128
// <o7> SYSCLK prescaler Register (SYS0_AHBCP)
// <0=> SYSCLK/1
// <1=> SYSCLK/1.5
// <o8> CLKOUT selection
// <0=> Disable
// <1=> ILRC
// <2=> ELS X'TAL
// <4=> HCLK
// <5=> IHRC
// <6=> EHS X'TAL
// <7=> PLL
// <o9> CLKOUT Prescaler Register (SYS1_APBCP1)
// <0=> CLKOUT selection/1
// <1=> CLKOUT selection/2
// <2=> CLKOUT selection/4
// <3=> CLKOUT selection/8
// <4=> CLKOUT selection/16
// <5=> CLKOUT selection/32
// <6=> CLKOUT selection/64
// <7=> CLKOUT selection/128
*/
#ifndef SYS0_CLKCFG_VAL
#define SYS0_CLKCFG_VAL 0
#endif
#ifndef EHS_FREQ
#define EHS_FREQ 16
#endif
#ifndef PLL_ENABLE
#define PLL_ENABLE 0
#endif
#ifndef PLL_MSEL
#define PLL_MSEL 1
#endif
#ifndef PLL_PSEL
#define PLL_PSEL 0
#endif
#ifndef PLL_CLKIN
#define PLL_CLKIN 0
#endif
#ifndef AHB_PRESCALAR
#define AHB_PRESCALAR 0x0
#endif
#ifndef AHB_1P5PRESCALAR
#define AHB_1P5PRESCALAR 0x0
#endif
#ifndef CLKOUT_SEL_VAL
#define CLKOUT_SEL_VAL 0x0
#endif
#ifndef CLKOUT_PRESCALAR
#define CLKOUT_PRESCALAR 0x0
#endif
/*
//-------- <<< end of configuration section >>> ------------------------------
*/
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
#ifndef IHRC
#define IHRC 0
#endif
#ifndef ILRC
#define ILRC 1
#endif
#ifndef EHSXTAL
#define EHSXTAL 2
#endif
#ifndef ELSXTAL
#define ELSXTAL 3
#endif
#ifndef PLL
#define PLL 4
#endif
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define __IHRC_FREQ (12000000UL)
#define __ILRC_FREQ (32000UL)
#define __ELS_XTAL_FREQ (32768UL)
#define SYS0_PLLCTRL_VAL (PLL_ENABLE<<15) | (PLL_CLKIN<<12) | (PLL_PSEL<<5) | PLL_MSEL
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
uint32_t AHB_prescaler;
switch (SN_SYS0->CLKCFG_b.SYSCLKST)
{
case 0: //IHRC
SystemCoreClock = __IHRC_FREQ;
break;
case 1: //ILRC
SystemCoreClock = __ILRC_FREQ;
break;
case 2: //EHS X'TAL
SystemCoreClock = EHS_FREQ * 1000000;
break;
case 3: //ELS X'TAL
SystemCoreClock = __ELS_XTAL_FREQ;
break;
case 4: //PLL
if (PLL_CLKIN == 0x0) //IHRC as F_CLKIN
SystemCoreClock = __IHRC_FREQ * (PLL_MSEL+2) / (PLL_PSEL+1);
else
SystemCoreClock = EHS_FREQ * 1000000 * (PLL_MSEL+2) / (PLL_PSEL+1);
break;
default:
break;
}
switch (SN_SYS0->AHBCP)
{
case 0: AHB_prescaler = 1; break;
case 1: AHB_prescaler = 2; break;
case 2: AHB_prescaler = 4; break;
case 3: AHB_prescaler = 8; break;
case 4: AHB_prescaler = 16; break;
case 5: AHB_prescaler = 32; break;
case 6: AHB_prescaler = 64; break;
case 7: AHB_prescaler = 128;break;
default: break;
}
SystemCoreClock /= AHB_prescaler;
if (SN_SYS0->AHBCP_b.DIV1P5 == 1)
SystemCoreClock = SystemCoreClock*2/3;
//;;;;;;;;; Need for SN32F780 Begin ;;;;;;;;;
if (SystemCoreClock > 48000000)
SN_FLASH->LPCTRL = 0x5AFA0031;
else if (SystemCoreClock > 24000000)
SN_FLASH->LPCTRL = 0x5AFA0011;
else
SN_FLASH->LPCTRL = 0x5AFA0000;
//;;;;;;;;; Need for SN32F780 End ;;;;;;;;;
return;
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
#if SYS0_CLKCFG_VAL == IHRC //IHRC
SN_SYS0->CLKCFG = 0x0;
while ((SN_SYS0->CLKCFG & 0x70) != 0x0);
#endif
#if SYS0_CLKCFG_VAL == ILRC //ILRC
SN_SYS0->CLKCFG = 0x1;
while ((SN_SYS0->CLKCFG & 0x70) != 0x10);
#endif
#if (SYS0_CLKCFG_VAL == EHSXTAL) //EHS XTAL
#if (EHS_FREQ > 12)
SN_SYS0->ANBCTRL_b.EHSFREQ = 1;
SN_FLASH->LPCTRL = 0x5AFA0011;
#else
SN_SYS0->ANBCTRL_b.EHSFREQ = 0;
#endif
SN_SYS0->ANBCTRL_b.EHSEN = 1;
while ((SN_SYS0->CSST & 0x10) != 0x10);
SN_SYS0->CLKCFG = 0x2;
while ((SN_SYS0->CLKCFG & 0x70) != 0x20);
#endif
#if (SYS0_CLKCFG_VAL == ELSXTAL) //ELS XTAL
SN_SYS0->ANBCTRL_b.ELSEN = 1;
while((SN_SYS0->CSST & 0x4) != 0x4);
SN_SYS0->CLKCFG = 0x3;
while ((SN_SYS0->CLKCFG & 0x70) != 0x30);
#endif
#if (PLL_ENABLE == 1)
SN_SYS0->PLLCTRL = SYS0_PLLCTRL_VAL;
if (PLL_CLKIN == 0x1) //EHS XTAL as F_CLKIN
{
//Enable EHS
#if (EHS_FREQ > 12)
SN_SYS0->ANBCTRL_b.EHSFREQ = 1;
#else
SN_SYS0->ANBCTRL_b.EHSFREQ = 0;
#endif
SN_SYS0->ANBCTRL_b.EHSEN = 1;
while ((SN_SYS0->CSST & 0x10) != 0x10);
}
while ((SN_SYS0->CSST & 0x40) != 0x40);
#if (SYS0_CLKCFG_VAL == PLL) //PLL
SN_FLASH->LPCTRL = 0x5AFA0031;
SN_SYS0->CLKCFG = 0x4;
while ((SN_SYS0->CLKCFG & 0x70) != 0x40);
#endif
#endif
SN_SYS0->AHBCP = AHB_PRESCALAR;
SN_SYS0->AHBCP_b.DIV1P5 = AHB_1P5PRESCALAR;
#if (CLKOUT_SEL_VAL > 0) //CLKOUT
SN_SYS1->AHBCLKEN_b.CLKOUTSEL = CLKOUT_SEL_VAL;
SN_SYS1->APBCP1_b.CLKOUTPRE = CLKOUT_PRESCALAR;
#endif
}

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/**************************************************************************//**
* @file system_SN32F240B.h
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File
* for the SONIX SN32F240B Device
* @version V1.1
* @date Jul 2017
*
* @note
* Copyright (C) 2009-2017 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __SYSTEM_SN32F2xx_H
#define __SYSTEM_SN32F2xx_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include "SN32F2xx.h"
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#if defined(SN32F240B)
/**
* Initialize the Flash controller
*
* @param none
* @return none
*
* @brief Update the Flash power control.
*/
extern void FlashClockUpdate (void);
/**
* Switch System to Slow Mode
* @param none
* @return none
*
* @brief Special init required for SystemCoreClock <= 8000
*/
extern void SlowModeSwitch (void);
#endif /* defined(SN32F240B) */
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_SN32F2xx_H */

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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* SN32F240 memory setup.
*/
MEMORY
{
flash0 (rx) : org = 0x00000000, len = 64k
flash1 (rx) : org = 0x00000000, len = 0
flash2 (rx) : org = 0x00000000, len = 0
flash3 (rx) : org = 0x00000000, len = 0
flash4 (rx) : org = 0x00000000, len = 0
flash5 (rx) : org = 0x00000000, len = 0
flash6 (rx) : org = 0x00000000, len = 0
flash7 (rx) : org = 0x00000000, len = 0
ram0 (wx) : org = 0x20000000, len = 8k
ram1 (wx) : org = 0x00000000, len = 0
ram2 (wx) : org = 0x00000000, len = 0
ram3 (wx) : org = 0x00000000, len = 0
ram4 (wx) : org = 0x00000000, len = 0
ram5 (wx) : org = 0x00000000, len = 0
ram6 (wx) : org = 0x00000000, len = 0
ram7 (wx) : org = 0x00000000, len = 0
}
/* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/
/* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash0);
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
/* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash0);
REGION_ALIAS("XTORS_FLASH_LMA", flash0);
/* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash0);
REGION_ALIAS("TEXT_FLASH_LMA", flash0);
/* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH", flash0);
REGION_ALIAS("RODATA_FLASH_LMA", flash0);
/* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash0);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
/* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram0);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash0);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);
/* Generic rules inclusion.*/
INCLUDE rules.ld
_flag_start = 0xFFFC;
SECTIONS
{
.flag _flag_start :
{
KEEP(*(.flag)) ;
} > flash0
}

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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* SN32F240B memory setup.
*/
MEMORY
{
flash0 (rx) : org = 0x00000000, len = 64k
flash1 (rx) : org = 0x00000000, len = 0
flash2 (rx) : org = 0x00000000, len = 0
flash3 (rx) : org = 0x00000000, len = 0
flash4 (rx) : org = 0x00000000, len = 0
flash5 (rx) : org = 0x00000000, len = 0
flash6 (rx) : org = 0x00000000, len = 0
flash7 (rx) : org = 0x00000000, len = 0
ram0 (wx) : org = 0x20000000, len = 8k
ram1 (wx) : org = 0x00000000, len = 0
ram2 (wx) : org = 0x00000000, len = 0
ram3 (wx) : org = 0x00000000, len = 0
ram4 (wx) : org = 0x00000000, len = 0
ram5 (wx) : org = 0x00000000, len = 0
ram6 (wx) : org = 0x00000000, len = 0
ram7 (wx) : org = 0x00000000, len = 0
}
/* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/
/* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash0);
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
/* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash0);
REGION_ALIAS("XTORS_FLASH_LMA", flash0);
/* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash0);
REGION_ALIAS("TEXT_FLASH_LMA", flash0);
/* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH", flash0);
REGION_ALIAS("RODATA_FLASH_LMA", flash0);
/* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash0);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
/* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram0);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash0);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);
/* Generic rules inclusion.*/
INCLUDE rules.ld
_flag_start = 0xFFFC;
SECTIONS
{
.flag _flag_start :
{
KEEP(*(.flag)) ;
} > flash0
}

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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* SN32F240B memory setup.
* 0x200 entry point bootloader
*/
MEMORY
{
flash0 (rx) : org = 0x00000200, len = 30208
flash1 (rx) : org = 0x00000000, len = 0
flash2 (rx) : org = 0x00000000, len = 0
flash3 (rx) : org = 0x00000000, len = 0
flash4 (rx) : org = 0x00000000, len = 0
flash5 (rx) : org = 0x00000000, len = 0
flash6 (rx) : org = 0x00000000, len = 0
flash7 (rx) : org = 0x00000000, len = 0
ram0 (wx) : org = 0x20000000, len = 2k
ram1 (wx) : org = 0x00000000, len = 0
ram2 (wx) : org = 0x00000000, len = 0
ram3 (wx) : org = 0x00000000, len = 0
ram4 (wx) : org = 0x00000000, len = 0
ram5 (wx) : org = 0x00000000, len = 0
ram6 (wx) : org = 0x00000000, len = 0
ram7 (wx) : org = 0x00000000, len = 0
}
/* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/
/* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash0);
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
/* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash0);
REGION_ALIAS("XTORS_FLASH_LMA", flash0);
/* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash0);
REGION_ALIAS("TEXT_FLASH_LMA", flash0);
/* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH", flash0);
REGION_ALIAS("RODATA_FLASH_LMA", flash0);
/* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash0);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
/* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram0);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash0);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);
/* Custom vectors section with 512 byte alignment.
The default ChibiOS linker script aligns to 1024 bytes, because that is the worse
case alignment requirement for STM32 chips.
See https://forum.chibios.org/viewtopic.php?t=5554
However the sonix-keyboard-bootloader expects the ISR vector table to be at 0x200.
This is not possible if the alignment is 1024 bytes.
By adding this custom section with 512 byte alignment before the inclusion of
the rules.ld defaults, the linker will use this section for .vectors objects. */
SECTIONS
{
.vectors_512_aligned : ALIGN(512)
{
KEEP(*(.vectors))
} > VECTORS_FLASH AT > VECTORS_FLASH_LMA
}
/* Generic rules inclusion.*/
INCLUDE rules.ld

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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* SN32F280 memory setup.
*/
MEMORY
{
flash0 (rx) : org = 0x00000000, len = 128k
flash1 (rx) : org = 0x00000000, len = 0
flash2 (rx) : org = 0x00000000, len = 0
flash3 (rx) : org = 0x00000000, len = 0
flash4 (rx) : org = 0x00000000, len = 0
flash5 (rx) : org = 0x00000000, len = 0
flash6 (rx) : org = 0x00000000, len = 0
flash7 (rx) : org = 0x00000000, len = 0
ram0 (wx) : org = 0x20000000, len = 32k
ram1 (wx) : org = 0x00000000, len = 0
ram2 (wx) : org = 0x00000000, len = 0
ram3 (wx) : org = 0x00000000, len = 0
ram4 (wx) : org = 0x00000000, len = 0
ram5 (wx) : org = 0x00000000, len = 0
ram6 (wx) : org = 0x00000000, len = 0
ram7 (wx) : org = 0x00000000, len = 0
}
/* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/
/* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash0);
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
/* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash0);
REGION_ALIAS("XTORS_FLASH_LMA", flash0);
/* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash0);
REGION_ALIAS("TEXT_FLASH_LMA", flash0);
/* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH", flash0);
REGION_ALIAS("RODATA_FLASH_LMA", flash0);
/* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash0);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
/* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram0);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash0);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);
/* Generic rules inclusion.*/
INCLUDE rules.ld
_flag_start = 0xFFFC;
SECTIONS
{
.flag _flag_start :
{
KEEP(*(.flag)) ;
} > flash0
}

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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* SN32F290 memory setup.
*/
MEMORY
{
flash0 (rx) : org = 0x00000000, len = 256k
flash1 (rx) : org = 0x00000000, len = 0
flash2 (rx) : org = 0x00000000, len = 0
flash3 (rx) : org = 0x00000000, len = 0
flash4 (rx) : org = 0x00000000, len = 0
flash5 (rx) : org = 0x00000000, len = 0
flash6 (rx) : org = 0x00000000, len = 0
flash7 (rx) : org = 0x00000000, len = 0
ram0 (wx) : org = 0x20000000, len = 32k
ram1 (wx) : org = 0x00000000, len = 0
ram2 (wx) : org = 0x00000000, len = 0
ram3 (wx) : org = 0x00000000, len = 0
ram4 (wx) : org = 0x00000000, len = 0
ram5 (wx) : org = 0x00000000, len = 0
ram6 (wx) : org = 0x00000000, len = 0
ram7 (wx) : org = 0x00000000, len = 0
}
/* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/
/* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash0);
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
/* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash0);
REGION_ALIAS("XTORS_FLASH_LMA", flash0);
/* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash0);
REGION_ALIAS("TEXT_FLASH_LMA", flash0);
/* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH", flash0);
REGION_ALIAS("RODATA_FLASH_LMA", flash0);
/* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash0);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
/* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram0);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram0);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash0);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);
/* Generic rules inclusion.*/
INCLUDE rules.ld
_flag_start = 0xFFFC;
SECTIONS
{
.flag _flag_start :
{
KEEP(*(.flag)) ;
} > flash0
}

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# List of the ChibiOS generic SN32F24x startup and CMSIS files.
STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
$(CHIBIOS_CONTRIB)/os/common/ext/SONiX/SN32F2xx/system_SN32F240.c
STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S \
$(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
$(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld \
$(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/SN32F24x \
$(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
$(CHIBIOS_CONTRIB)/os/common/ext/SONiX/SN32F2xx
STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
STARTUPLD_CONTRIB = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
# Shared variables
ALLXASMSRC += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

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# List of the ChibiOS generic SN32F24xB startup and CMSIS files.
STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
$(CHIBIOS_CONTRIB)/os/common/ext/SONiX/SN32F2xx/system_SN32F240B.c
STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S \
$(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
$(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld \
$(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/SN32F24xB \
$(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
$(CHIBIOS_CONTRIB)/os/common/ext/SONiX/SN32F2xx
STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
STARTUPLD_CONTRIB = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
# Shared variables
ALLXASMSRC += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

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# List of the ChibiOS generic SN32F26x startup and CMSIS files.
STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
$(CHIBIOS_CONTRIB)/os/common/ext/SONiX/SN32F2xx/system_SN32F260.c
STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S \
$(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
$(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld \
$(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/SN32F26x \
$(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
$(CHIBIOS_CONTRIB)/os/common/ext/SONiX/SN32F2xx
STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
STARTUPLD_CONTRIB = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
# Shared variables
ALLXASMSRC += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

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# List of the ChibiOS generic SN32F28x startup and CMSIS files.
STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
$(CHIBIOS_CONTRIB)/os/common/ext/SONiX/SN32F2xx/system_SN32F280.c
STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S \
$(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
$(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld \
$(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/SN32F28x \
$(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
$(CHIBIOS_CONTRIB)/os/common/ext/SONiX/SN32F2xx
STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
STARTUPLD_CONTRIB = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
# Shared variables
ALLXASMSRC += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

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# List of the ChibiOS generic SN32F29x startup and CMSIS files.
STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
$(CHIBIOS_CONTRIB)/os/common/ext/SONiX/SN32F2xx/system_SN32F290.c
STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S \
$(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
$(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld \
$(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/SN32F29x \
$(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
$(CHIBIOS_CONTRIB)/os/common/ext/SONiX/SN32F2xx
STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
STARTUPLD_CONTRIB = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
# Shared variables
ALLXASMSRC += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file SN32F24x/cmparams.h
* @brief ARM Cortex-M0 parameters for the SN32F24x.
*
* @defgroup ARMCMx_SN32F24x SN32F24x Specific Parameters
* @ingroup ARMCMx_SPECIFIC
* @details This file contains the Cortex-M0 specific parameters for the
* SN32F24x platform.
* @{
*/
#ifndef CMPARAMS_H
#define CMPARAMS_H
/**
* @brief Cortex core model.
*/
#define CORTEX_MODEL 0
/**
* @brief Floating Point unit presence.
*/
#define CORTEX_HAS_FPU 0
/**
* @brief Number of bits in priority masks.
*/
#define CORTEX_PRIORITY_BITS 2
/**
* @brief Number of interrupt vectors.
* @note This number does not include the 16 system vectors and must be
* rounded to a multiple of 8.
*/
#define CORTEX_NUM_VECTORS 32
/* The following code is not processed when the file is included from an
asm module.*/
#if !defined(_FROM_ASM_)
#include "board.h"
/* Including the device CMSIS header. Note, we are not using the definitions
from this header because we need this file to be usable also from
assembler source files. We verify that the info matches instead.*/
#include "SN32F240.h"
/*lint -save -e9029 [10.4] Signedness comes from external files, it is
unpredictable but gives no problems.*/
#if CORTEX_MODEL != __CORTEX_M
#error "CMSIS __CORTEX_M mismatch"
#endif
#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
#error "CMSIS __NVIC_PRIO_BITS mismatch"
#endif
/*lint -restore*/
#endif /* !defined(_FROM_ASM_) */
#endif /* CMPARAMS_H */
/** @} */

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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file SN32F24x/cmparams.h
* @brief ARM Cortex-M0 parameters for the SN32F24x.
*
* @defgroup ARMCMx_SN32F24x SN32F24x Specific Parameters
* @ingroup ARMCMx_SPECIFIC
* @details This file contains the Cortex-M0 specific parameters for the
* SN32F24x platform.
* @{
*/
#ifndef CMPARAMS_H
#define CMPARAMS_H
/**
* @brief Cortex core model.
*/
#define CORTEX_MODEL 0
/**
* @brief Floating Point unit presence.
*/
#define CORTEX_HAS_FPU 0
/**
* @brief Number of bits in priority masks.
*/
#define CORTEX_PRIORITY_BITS 2
/**
* @brief Number of interrupt vectors.
* @note This number does not include the 16 system vectors and must be
* rounded to a multiple of 8.
*/
#define CORTEX_NUM_VECTORS 32
/* The following code is not processed when the file is included from an
asm module.*/
#if !defined(_FROM_ASM_)
#include "board.h"
/* Including the device CMSIS header. Note, we are not using the definitions
from this header because we need this file to be usable also from
assembler source files. We verify that the info matches instead.*/
#include "SN32F240B.h"
/*lint -save -e9029 [10.4] Signedness comes from external files, it is
unpredictable but gives no problems.*/
#if CORTEX_MODEL != __CORTEX_M
#error "CMSIS __CORTEX_M mismatch"
#endif
#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
#error "CMSIS __NVIC_PRIO_BITS mismatch"
#endif
/*lint -restore*/
#endif /* !defined(_FROM_ASM_) */
#endif /* CMPARAMS_H */
/** @} */

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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file SN32F26x/cmparams.h
* @brief ARM Cortex-M0 parameters for the SN32F26x.
*
* @defgroup ARMCMx_SN32F26x SN32F26x Specific Parameters
* @ingroup ARMCMx_SPECIFIC
* @details This file contains the Cortex-M0 specific parameters for the
* SN32F26x platform.
* @{
*/
#ifndef CMPARAMS_H
#define CMPARAMS_H
/**
* @brief Cortex core model.
*/
#define CORTEX_MODEL 0
/**
* @brief Floating Point unit presence.
*/
#define CORTEX_HAS_FPU 0
/**
* @brief Number of bits in priority masks.
*/
#define CORTEX_PRIORITY_BITS 2
/**
* @brief Number of interrupt vectors.
* @note This number does not include the 16 system vectors and must be
* rounded to a multiple of 8.
*/
#define CORTEX_NUM_VECTORS 32
/* The following code is not processed when the file is included from an
asm module.*/
#if !defined(_FROM_ASM_)
#include "board.h"
/* Including the device CMSIS header. Note, we are not using the definitions
from this header because we need this file to be usable also from
assembler source files. We verify that the info matches instead.*/
#include "SN32F260.h"
/*lint -save -e9029 [10.4] Signedness comes from external files, it is
unpredictable but gives no problems.*/
#if CORTEX_MODEL != __CORTEX_M
#error "CMSIS __CORTEX_M mismatch"
#endif
#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
#error "CMSIS __NVIC_PRIO_BITS mismatch"
#endif
/*lint -restore*/
#endif /* !defined(_FROM_ASM_) */
#endif /* CMPARAMS_H */
/** @} */

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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file SN32F28x/cmparams.h
* @brief ARM Cortex-M0 parameters for the SN32F28x.
*
* @defgroup ARMCMx_SN32F28x SN32F28x Specific Parameters
* @ingroup ARMCMx_SPECIFIC
* @details This file contains the Cortex-M0 specific parameters for the
* SN32F28x platform.
* @{
*/
#ifndef CMPARAMS_H
#define CMPARAMS_H
/**
* @brief Cortex core model.
*/
#define CORTEX_MODEL 0
/**
* @brief Floating Point unit presence.
*/
#define CORTEX_HAS_FPU 0
/**
* @brief Number of bits in priority masks.
*/
#define CORTEX_PRIORITY_BITS 2
/**
* @brief Number of interrupt vectors.
* @note This number does not include the 16 system vectors and must be
* rounded to a multiple of 8.
*/
#define CORTEX_NUM_VECTORS 32
/* The following code is not processed when the file is included from an
asm module.*/
#if !defined(_FROM_ASM_)
#include "board.h"
/* Including the device CMSIS header. Note, we are not using the definitions
from this header because we need this file to be usable also from
assembler source files. We verify that the info matches instead.*/
#include "SN32F280.h"
/*lint -save -e9029 [10.4] Signedness comes from external files, it is
unpredictable but gives no problems.*/
#if CORTEX_MODEL != __CORTEX_M
#error "CMSIS __CORTEX_M mismatch"
#endif
#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
#error "CMSIS __NVIC_PRIO_BITS mismatch"
#endif
/*lint -restore*/
#endif /* !defined(_FROM_ASM_) */
#endif /* CMPARAMS_H */
/** @} */

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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file SN32F29x/cmparams.h
* @brief ARM Cortex-M0 parameters for the SN32F29x.
*
* @defgroup ARMCMx_SN32F29x SN32F29x Specific Parameters
* @ingroup ARMCMx_SPECIFIC
* @details This file contains the Cortex-M0 specific parameters for the
* SN32F29x platform.
* @{
*/
#ifndef CMPARAMS_H
#define CMPARAMS_H
/**
* @brief Cortex core model.
*/
#define CORTEX_MODEL 0
/**
* @brief Floating Point unit presence.
*/
#define CORTEX_HAS_FPU 0
/**
* @brief Number of bits in priority masks.
*/
#define CORTEX_PRIORITY_BITS 2
/**
* @brief Number of interrupt vectors.
* @note This number does not include the 16 system vectors and must be
* rounded to a multiple of 8.
*/
#define CORTEX_NUM_VECTORS 32
/* The following code is not processed when the file is included from an
asm module.*/
#if !defined(_FROM_ASM_)
#include "board.h"
/* Including the device CMSIS header. Note, we are not using the definitions
from this header because we need this file to be usable also from
assembler source files. We verify that the info matches instead.*/
#include "SN32F290.h"
/*lint -save -e9029 [10.4] Signedness comes from external files, it is
unpredictable but gives no problems.*/
#if CORTEX_MODEL != __CORTEX_M
#error "CMSIS __CORTEX_M mismatch"
#endif
#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
#error "CMSIS __NVIC_PRIO_BITS mismatch"
#endif
/*lint -restore*/
#endif /* !defined(_FROM_ASM_) */
#endif /* CMPARAMS_H */
/** @} */

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/*
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* This file has been automatically generated using ChibiStudio board
* generator plugin. Do not edit manually.
*/
#include "hal.h"
#if HAL_USE_PAL || defined(__DOXYGEN__)
/**
* @brief PAL setup.
* @details Digital I/O ports static configuration as defined in @p board.h.
* This variable is used by the HAL when initializing the PAL driver.
*/
const PALConfig pal_default_config = {
#if SN32_HAS_GPIOA
{.mode = VAL_GPIOA_MODE, .cfg = VAL_GPIOA_CFG},
#endif
#if SN32_HAS_GPIOB
{.mode = VAL_GPIOB_MODE, .cfg = VAL_GPIOB_CFG},
#endif
#if SN32_HAS_GPIOC
{.mode = VAL_GPIOC_MODE, .cfg = VAL_GPIOC_CFG},
#endif
#if SN32_HAS_GPIOD
{.mode = VAL_GPIOD_MODE, .cfg = VAL_GPIOD_CFG},
#endif
};
#endif
static int flag __attribute__((section(".flag"))) __attribute__((__used__)) = 0xAAAA5555;
extern void enter_bootloader_mode_if_requested(void);
/**
* @brief Early initialization code.
* @details This initialization must be performed just after stack setup
* and before any other initialization.
*/
void __early_init(void) {
enter_bootloader_mode_if_requested();
sn32_clock_init();
}
/**
* @brief Board-specific initialization code.
* @todo Add your board-specific code, if any.
*/
void boardInit(void) {
SN_SYS0->EXRSTCTRL_b.RESETDIS = 1; // Disable RESET
SN_SYS0->SWDCTRL_b.SWDDIS = 1; // Disable SWD
}
void restart_usb_driver(USBDriver *usbp) {
// Do nothing. Restarting the USB driver on these boards breaks it.
}

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/*
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef _BOARD_H_
#define _BOARD_H_
/*
* Setup for Generic SN32F240 Board
*/
/*
* Board identifier.
*/
#define BOARD_GENERIC_SN32_F240
#define BOARD_NAME "SN32F240"
/*
* MCU type as defined in the SN32 header.
*/
#define SN32F240
/*
* IO pins assignments.
*/
#define GPIOA_PIN0 0U
#define GPIOA_PIN1 1U
#define GPIOA_PIN2 2U
#define GPIOA_PIN3 3U
#define GPIOA_PIN4 4U
#define GPIOA_PIN5 5U
#define GPIOA_PIN6 6U
#define GPIOA_PIN7 7U
#define GPIOA_PIN8 8U
#define GPIOA_PIN9 9U
#define GPIOA_PIN10 10U
#define GPIOA_PIN11 11U
#define GPIOA_PIN12 12U
#define GPIOA_PIN13 13U
#define GPIOA_PIN14 14U
#define GPIOA_PIN15 15U
#define GPIOB_PIN0 0U
#define GPIOB_PIN1 1U
#define GPIOB_PIN2 2U
#define GPIOB_PIN3 3U
#define GPIOB_PIN4 4U
#define GPIOB_PIN5 5U
#define GPIOB_PIN6 6U
#define GPIOB_PIN7 7U
#define GPIOB_PIN8 8U
#define GPIOB_PIN9 9U
#define GPIOB_PIN10 10U
#define GPIOB_PIN11 11U
#define GPIOB_PIN12 12U
#define GPIOB_PIN13 13U
#define GPIOB_PIN14 14U
#define GPIOB_PIN15 15U
#define GPIOC_PIN0 0U
#define GPIOC_PIN1 1U
#define GPIOC_PIN2 2U
#define GPIOC_PIN3 3U
#define GPIOC_PIN4 4U
#define GPIOC_PIN5 5U
#define GPIOC_PIN6 6U
#define GPIOC_PIN7 7U
#define GPIOC_PIN8 8U
#define GPIOC_PIN9 9U
#define GPIOC_PIN10 10U
#define GPIOC_PIN11 11U
#define GPIOC_PIN12 12U
#define GPIOC_PIN13 13U
#define GPIOC_PIN14 14U
#define GPIOC_PIN15 15U
#define GPIOD_PIN3 3U
#define GPIOD_PIN4 4U
#define GPIOD_PIN5 5U
#define GPIOD_PIN6 6U
#define GPIOD_PIN7 7U
#define GPIOD_PIN8 8U
#define GPIOD_PIN9 9U
#define GPIOD_PIN10 10U
#define GPIOD_PIN11 11U
#define GPIOD_PIN12 12U
#define GPIOD_PIN13 13U
#define GPIOD_PIN14 14U
#define GPIOD_PIN15 15U
/*
* I/O ports initial setup, this configuration is established soon after reset
* in the initialization code.
* Please refer to the SN32 Reference Manual for details.
*/
#define PIN_MODE_INPUT(n) (0U << ((n)))
#define PIN_MODE_OUTPUT(n) (1U << ((n)))
#define PIN_CFG_PULLUP(n) (0U << ((n*2))) // Pull-up
#define PIN_CFG_SCHMITT_EN(n) (2U << ((n*2))) // Floating
#define PIN_CFG_SCHMITT_DIS(n) (3U << ((n*2))) // Input buffer disconnected, alway read as zero.
// Define GPIO register values used by pal_default_config.
// The following values match the chip reset values, all GPIO pins as floating inputs.
#define VAL_GPIOA_MODE \
( PIN_MODE_INPUT(GPIOA_PIN0) \
| PIN_MODE_INPUT(GPIOA_PIN1) \
| PIN_MODE_INPUT(GPIOA_PIN2) \
| PIN_MODE_INPUT(GPIOA_PIN3) \
| PIN_MODE_INPUT(GPIOA_PIN4) \
| PIN_MODE_INPUT(GPIOA_PIN5) \
| PIN_MODE_INPUT(GPIOA_PIN6) \
| PIN_MODE_INPUT(GPIOA_PIN7) \
| PIN_MODE_INPUT(GPIOA_PIN8) \
| PIN_MODE_INPUT(GPIOA_PIN9) \
| PIN_MODE_INPUT(GPIOA_PIN10) \
| PIN_MODE_INPUT(GPIOA_PIN11) \
| PIN_MODE_INPUT(GPIOA_PIN12) \
| PIN_MODE_INPUT(GPIOA_PIN13) \
| PIN_MODE_INPUT(GPIOA_PIN14) \
| PIN_MODE_INPUT(GPIOA_PIN15) )
#define VAL_GPIOA_CFG \
( PIN_CFG_SCHMITT_EN(GPIOA_PIN0) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN1) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN2) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN3) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN4) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN5) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN6) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN7) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN8) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN9) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN10) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN11) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN12) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN13) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN14) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN15) )
#define VAL_GPIOB_MODE \
( PIN_MODE_INPUT(GPIOB_PIN0) \
| PIN_MODE_INPUT(GPIOB_PIN1) \
| PIN_MODE_INPUT(GPIOB_PIN2) \
| PIN_MODE_INPUT(GPIOB_PIN3) \
| PIN_MODE_INPUT(GPIOB_PIN4) \
| PIN_MODE_INPUT(GPIOB_PIN5) \
| PIN_MODE_INPUT(GPIOB_PIN6) \
| PIN_MODE_INPUT(GPIOB_PIN7) \
| PIN_MODE_INPUT(GPIOB_PIN8) \
| PIN_MODE_INPUT(GPIOB_PIN9) \
| PIN_MODE_INPUT(GPIOB_PIN10) \
| PIN_MODE_INPUT(GPIOB_PIN11) \
| PIN_MODE_INPUT(GPIOB_PIN12) \
| PIN_MODE_INPUT(GPIOB_PIN13) \
| PIN_MODE_INPUT(GPIOB_PIN14) \
| PIN_MODE_INPUT(GPIOB_PIN15) )
#define VAL_GPIOB_CFG \
( PIN_CFG_SCHMITT_EN(GPIOB_PIN0) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN1) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN2) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN3) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN4) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN5) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN6) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN7) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN8) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN9) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN10) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN11) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN12) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN13) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN14) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN15) )
#define VAL_GPIOC_MODE \
( PIN_MODE_INPUT(GPIOC_PIN0) \
| PIN_MODE_INPUT(GPIOC_PIN1) \
| PIN_MODE_INPUT(GPIOC_PIN2) \
| PIN_MODE_INPUT(GPIOC_PIN3) \
| PIN_MODE_INPUT(GPIOC_PIN4) \
| PIN_MODE_INPUT(GPIOC_PIN5) \
| PIN_MODE_INPUT(GPIOC_PIN6) \
| PIN_MODE_INPUT(GPIOC_PIN7) \
| PIN_MODE_INPUT(GPIOC_PIN8) \
| PIN_MODE_INPUT(GPIOC_PIN9) \
| PIN_MODE_INPUT(GPIOC_PIN10) \
| PIN_MODE_INPUT(GPIOC_PIN11) \
| PIN_MODE_INPUT(GPIOC_PIN12) \
| PIN_MODE_INPUT(GPIOC_PIN13) \
| PIN_MODE_INPUT(GPIOC_PIN14) \
| PIN_MODE_INPUT(GPIOC_PIN15) )
#define VAL_GPIOC_CFG \
( PIN_CFG_SCHMITT_EN(GPIOC_PIN0) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN1) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN2) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN3) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN4) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN5) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN6) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN7) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN8) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN9) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN10) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN11) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN12) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN13) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN14) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN15) )
#define VAL_GPIOD_MODE \
( PIN_MODE_INPUT(GPIOD_PIN3) \
| PIN_MODE_INPUT(GPIOD_PIN4) \
| PIN_MODE_INPUT(GPIOD_PIN5) \
| PIN_MODE_INPUT(GPIOD_PIN6) \
| PIN_MODE_INPUT(GPIOD_PIN7) \
| PIN_MODE_INPUT(GPIOD_PIN8) \
| PIN_MODE_INPUT(GPIOD_PIN9) \
| PIN_MODE_INPUT(GPIOD_PIN10) \
| PIN_MODE_INPUT(GPIOD_PIN11) \
| PIN_MODE_INPUT(GPIOD_PIN12) \
| PIN_MODE_INPUT(GPIOD_PIN13) \
| PIN_MODE_INPUT(GPIOD_PIN14) \
| PIN_MODE_INPUT(GPIOD_PIN15) )
#define VAL_GPIOD_CFG \
( PIN_CFG_SCHMITT_EN(GPIOD_PIN3) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN4) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN5) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN6) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN7) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN8) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN9) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN10) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN11) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN12) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN13) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN14) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN15) )
#if !defined(_FROM_ASM_)
# ifdef __cplusplus
extern "C" {
# endif
void boardInit(void);
# ifdef __cplusplus
}
# endif
#endif /* _FROM_ASM_ */
#endif /* _BOARD_H_ */

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# List of all the board related files.
BOARDSRC = $(CHIBIOS_CONTRIB)/os/hal/boards/SN_SN32F240B/board.c
# Required include directories
BOARDINC = $(CHIBIOS_CONTRIB)/os/hal/boards/SN_SN32F240B
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

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/*
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* This file has been automatically generated using ChibiStudio board
* generator plugin. Do not edit manually.
*/
#include "hal.h"
#if HAL_USE_PAL || defined(__DOXYGEN__)
/**
* @brief PAL setup.
* @details Digital I/O ports static configuration as defined in @p board.h.
* This variable is used by the HAL when initializing the PAL driver.
*/
const PALConfig pal_default_config = {
#if SN32_HAS_GPIOA
{.mode = VAL_GPIOA_MODE, .cfg = VAL_GPIOA_CFG},
#endif
#if SN32_HAS_GPIOB
{.mode = VAL_GPIOB_MODE, .cfg = VAL_GPIOB_CFG},
#endif
#if SN32_HAS_GPIOC
{.mode = VAL_GPIOC_MODE, .cfg = VAL_GPIOC_CFG},
#endif
#if SN32_HAS_GPIOD
{.mode = VAL_GPIOD_MODE, .cfg = VAL_GPIOD_CFG},
#endif
};
#endif
static int flag __attribute__((section(".flag"))) __attribute__((__used__)) = 0xAAAA5555;
extern void enter_bootloader_mode_if_requested(void);
/**
* @brief Early initialization code.
* @details This initialization must be performed just after stack setup
* and before any other initialization.
*/
void __early_init(void) {
enter_bootloader_mode_if_requested();
sn32_clock_init();
}
/**
* @brief Board-specific initialization code.
* @todo Add your board-specific code, if any.
*/
void boardInit(void) {
SN_SYS0->EXRSTCTRL_b.RESETDIS = 1; // Disable RESET
SN_SYS0->SWDCTRL_b.SWDDIS = 1; // Disable SWD
}

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/*
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef _BOARD_H_
#define _BOARD_H_
/*
* Setup for Generic SN32F240B Board
*/
/*
* Board identifier.
*/
#define BOARD_GENERIC_SN32_F240B
#define BOARD_NAME "SN32F240B"
/*
* MCU type as defined in the SN32 header.
*/
#define SN32F240B
/*
* IO pins assignments.
*/
#define GPIOA_PIN0 0U
#define GPIOA_PIN1 1U
#define GPIOA_PIN2 2U
#define GPIOA_PIN3 3U
#define GPIOA_PIN4 4U
#define GPIOA_PIN5 5U
#define GPIOA_PIN6 6U
#define GPIOA_PIN7 7U
#define GPIOA_PIN8 8U
#define GPIOA_PIN9 9U
#define GPIOA_PIN10 10U
#define GPIOA_PIN11 11U
#define GPIOA_PIN12 12U
#define GPIOA_PIN13 13U
#define GPIOA_PIN14 14U
#define GPIOA_PIN15 15U
#define GPIOB_PIN0 0U
#define GPIOB_PIN1 1U
#define GPIOB_PIN2 2U
#define GPIOB_PIN3 3U
#define GPIOB_PIN4 4U
#define GPIOB_PIN5 5U
#define GPIOB_PIN6 6U
#define GPIOB_PIN7 7U
#define GPIOB_PIN8 8U
#define GPIOB_PIN9 9U
#define GPIOB_PIN10 10U
#define GPIOB_PIN11 11U
#define GPIOB_PIN12 12U
#define GPIOB_PIN13 13U
#define GPIOB_PIN14 14U
#define GPIOB_PIN15 15U
#define GPIOC_PIN0 0U
#define GPIOC_PIN1 1U
#define GPIOC_PIN2 2U
#define GPIOC_PIN3 3U
#define GPIOC_PIN4 4U
#define GPIOC_PIN5 5U
#define GPIOC_PIN6 6U
#define GPIOC_PIN7 7U
#define GPIOC_PIN8 8U
#define GPIOC_PIN9 9U
#define GPIOC_PIN10 10U
#define GPIOC_PIN11 11U
#define GPIOC_PIN12 12U
#define GPIOC_PIN13 13U
#define GPIOC_PIN14 14U
#define GPIOC_PIN15 15U
#define GPIOD_PIN3 3U
#define GPIOD_PIN4 4U
#define GPIOD_PIN5 5U
#define GPIOD_PIN6 6U
#define GPIOD_PIN7 7U
#define GPIOD_PIN8 8U
#define GPIOD_PIN9 9U
#define GPIOD_PIN10 10U
#define GPIOD_PIN11 11U
/*
* I/O ports initial setup, this configuration is established soon after reset
* in the initialization code.
* Please refer to the SN32 Reference Manual for details.
*/
#define PIN_MODE_INPUT(n) (0U << ((n)))
#define PIN_MODE_OUTPUT(n) (1U << ((n)))
#define PIN_CFG_PULLUP(n) (0U << ((n*2))) // Pull-up
#define PIN_CFG_SCHMITT_EN(n) (2U << ((n*2))) // Floating
#define PIN_CFG_SCHMITT_DIS(n) (3U << ((n*2))) // Input buffer disconnected, alway read as zero.
// Define GPIO register values used by pal_default_config.
// The following values match the chip reset values, all GPIO pins as floating inputs.
#define VAL_GPIOA_MODE \
( PIN_MODE_INPUT(GPIOA_PIN0) \
| PIN_MODE_INPUT(GPIOA_PIN1) \
| PIN_MODE_INPUT(GPIOA_PIN2) \
| PIN_MODE_INPUT(GPIOA_PIN3) \
| PIN_MODE_INPUT(GPIOA_PIN4) \
| PIN_MODE_INPUT(GPIOA_PIN5) \
| PIN_MODE_INPUT(GPIOA_PIN6) \
| PIN_MODE_INPUT(GPIOA_PIN7) \
| PIN_MODE_INPUT(GPIOA_PIN8) \
| PIN_MODE_INPUT(GPIOA_PIN9) \
| PIN_MODE_INPUT(GPIOA_PIN10) \
| PIN_MODE_INPUT(GPIOA_PIN11) \
| PIN_MODE_INPUT(GPIOA_PIN12) \
| PIN_MODE_INPUT(GPIOA_PIN13) \
| PIN_MODE_INPUT(GPIOA_PIN14) \
| PIN_MODE_INPUT(GPIOA_PIN15) )
#define VAL_GPIOA_CFG \
( PIN_CFG_SCHMITT_EN(GPIOA_PIN0) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN1) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN2) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN3) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN4) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN5) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN6) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN7) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN8) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN9) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN10) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN11) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN12) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN13) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN14) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN15) )
#define VAL_GPIOB_MODE \
( PIN_MODE_INPUT(GPIOB_PIN0) \
| PIN_MODE_INPUT(GPIOB_PIN1) \
| PIN_MODE_INPUT(GPIOB_PIN2) \
| PIN_MODE_INPUT(GPIOB_PIN3) \
| PIN_MODE_INPUT(GPIOB_PIN4) \
| PIN_MODE_INPUT(GPIOB_PIN5) \
| PIN_MODE_INPUT(GPIOB_PIN6) \
| PIN_MODE_INPUT(GPIOB_PIN7) \
| PIN_MODE_INPUT(GPIOB_PIN8) \
| PIN_MODE_INPUT(GPIOB_PIN9) \
| PIN_MODE_INPUT(GPIOB_PIN10) \
| PIN_MODE_INPUT(GPIOB_PIN11) \
| PIN_MODE_INPUT(GPIOB_PIN12) \
| PIN_MODE_INPUT(GPIOB_PIN13) \
| PIN_MODE_INPUT(GPIOB_PIN14) \
| PIN_MODE_INPUT(GPIOB_PIN15) )
#define VAL_GPIOB_CFG \
( PIN_CFG_SCHMITT_EN(GPIOB_PIN0) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN1) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN2) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN3) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN4) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN5) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN6) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN7) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN8) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN9) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN10) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN11) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN12) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN13) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN14) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN15) )
#define VAL_GPIOC_MODE \
( PIN_MODE_INPUT(GPIOC_PIN0) \
| PIN_MODE_INPUT(GPIOC_PIN1) \
| PIN_MODE_INPUT(GPIOC_PIN2) \
| PIN_MODE_INPUT(GPIOC_PIN3) \
| PIN_MODE_INPUT(GPIOC_PIN4) \
| PIN_MODE_INPUT(GPIOC_PIN5) \
| PIN_MODE_INPUT(GPIOC_PIN6) \
| PIN_MODE_INPUT(GPIOC_PIN7) \
| PIN_MODE_INPUT(GPIOC_PIN8) \
| PIN_MODE_INPUT(GPIOC_PIN9) \
| PIN_MODE_INPUT(GPIOC_PIN10) \
| PIN_MODE_INPUT(GPIOC_PIN11) \
| PIN_MODE_INPUT(GPIOC_PIN12) \
| PIN_MODE_INPUT(GPIOC_PIN13) \
| PIN_MODE_INPUT(GPIOC_PIN14) \
| PIN_MODE_INPUT(GPIOC_PIN15) )
#define VAL_GPIOC_CFG \
( PIN_CFG_SCHMITT_EN(GPIOC_PIN0) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN1) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN2) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN3) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN4) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN5) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN6) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN7) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN8) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN9) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN10) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN11) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN12) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN13) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN14) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN15) )
#define VAL_GPIOD_MODE \
( PIN_MODE_INPUT(GPIOD_PIN3) \
| PIN_MODE_INPUT(GPIOD_PIN4) \
| PIN_MODE_INPUT(GPIOD_PIN5) \
| PIN_MODE_INPUT(GPIOD_PIN6) \
| PIN_MODE_INPUT(GPIOD_PIN7) \
| PIN_MODE_INPUT(GPIOD_PIN8) \
| PIN_MODE_INPUT(GPIOD_PIN9) \
| PIN_MODE_INPUT(GPIOD_PIN10) \
| PIN_MODE_INPUT(GPIOD_PIN11) )
#define VAL_GPIOD_CFG \
( PIN_CFG_SCHMITT_EN(GPIOD_PIN3) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN4) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN5) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN6) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN7) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN8) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN9) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN10) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN11) )
#if !defined(_FROM_ASM_)
# ifdef __cplusplus
extern "C" {
# endif
void boardInit(void);
# ifdef __cplusplus
}
# endif
#endif /* _FROM_ASM_ */
#endif /* _BOARD_H_ */

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# List of all the board related files.
BOARDSRC = $(CHIBIOS_CONTRIB)/os/hal/boards/SN_SN32F240B/board.c
# Required include directories
BOARDINC = $(CHIBIOS_CONTRIB)/os/hal/boards/SN_SN32F240B
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

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/*
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* This file has been automatically generated using ChibiStudio board
* generator plugin. Do not edit manually.
*/
#include "hal.h"
#if HAL_USE_PAL || defined(__DOXYGEN__)
/**
* @brief PAL setup.
* @details Digital I/O ports static configuration as defined in @p board.h.
* This variable is used by the HAL when initializing the PAL driver.
*/
const PALConfig pal_default_config = {
#if SN32_HAS_GPIOA
{.mode = VAL_GPIOA_MODE, .cfg = VAL_GPIOA_CFG},
#endif
#if SN32_HAS_GPIOB
{.mode = VAL_GPIOB_MODE, .cfg = VAL_GPIOB_CFG},
#endif
#if SN32_HAS_GPIOC
{.mode = VAL_GPIOC_MODE, .cfg = VAL_GPIOC_CFG},
#endif
#if SN32_HAS_GPIOD
{.mode = VAL_GPIOD_MODE, .cfg = VAL_GPIOD_CFG},
#endif
};
#endif
/**
* @brief Early initialization code.
* @details This initialization must be performed just after stack setup
* and before any other initialization.
*/
void __early_init(void) {
sn32_clock_init();
}
/**
* @brief Board-specific initialization code.
*/
void boardInit(void) {
SN_SYS0->SWDCTRL_b.SWDDIS = 1; // Disable SWD
}

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/*
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef _BOARD_H_
#define _BOARD_H_
/*
* Setup for Generic SN32F260 Board
*/
/*
* Board identifier.
*/
#define BOARD_GENERIC_SN32_F260
#define BOARD_NAME "SN32F260"
/*
* MCU type as defined in the SN32 header.
*/
#define SN32F260
/*
* IO pins assignments.
*/
#define GPIOA_PIN0 0U
#define GPIOA_PIN1 1U
#define GPIOA_PIN2 2U
#define GPIOA_PIN3 3U
#define GPIOA_PIN4 4U
#define GPIOA_PIN5 5U
#define GPIOA_PIN6 6U
#define GPIOA_PIN7 7U
#define GPIOA_PIN8 8U
#define GPIOA_PIN9 9U
#define GPIOA_PIN10 10U
#define GPIOA_PIN11 11U
#define GPIOA_PIN12 12U
#define GPIOA_PIN13 13U
#define GPIOA_PIN14 14U
#define GPIOA_PIN15 15U
#define GPIOB_PIN0 0U
#define GPIOB_PIN1 1U
#define GPIOB_PIN2 2U
#define GPIOB_PIN3 3U
#define GPIOB_PIN4 4U
#define GPIOB_PIN5 5U
#define GPIOC_PIN0 0U
#define GPIOC_PIN1 1U
#define GPIOC_PIN2 2U
#define GPIOC_PIN3 3U
#define GPIOC_PIN4 4U
#define GPIOC_PIN5 5U
#define GPIOC_PIN6 6U
#define GPIOC_PIN7 7U
#define GPIOC_PIN8 8U
#define GPIOC_PIN9 9U
#define GPIOC_PIN10 10U
#define GPIOD_PIN0 0U
#define GPIOD_PIN1 1U
#define GPIOD_PIN2 2U
#define GPIOD_PIN3 3U
#define GPIOD_PIN4 4U
#define GPIOD_PIN5 5U
#define GPIOD_PIN6 6U
#define GPIOD_PIN7 7U
#define GPIOD_PIN8 8U
/*
* I/O ports initial setup, this configuration is established soon after reset
* in the initialization code.
* Please refer to the SN32 Reference Manual for details.
*/
#define PIN_MODE_INPUT(n) (0U << ((n)))
#define PIN_MODE_OUTPUT(n) (1U << ((n)))
#define PIN_CFG_PULLUP(n) (0U << ((n*2))) // Pull-up
#define PIN_CFG_SCHMITT_EN(n) (2U << ((n*2))) // Floating
#define PIN_CFG_SCHMITT_DIS(n) (3U << ((n*2))) // Input buffer disconnected, alway read as zero.
// Define GPIO register values used by pal_default_config.
// The following values match the chip reset values, all GPIO pins as floating inputs.
#define VAL_GPIOA_MODE \
( PIN_MODE_INPUT(GPIOA_PIN0) \
| PIN_MODE_INPUT(GPIOA_PIN1) \
| PIN_MODE_INPUT(GPIOA_PIN2) \
| PIN_MODE_INPUT(GPIOA_PIN3) \
| PIN_MODE_INPUT(GPIOA_PIN4) \
| PIN_MODE_INPUT(GPIOA_PIN5) \
| PIN_MODE_INPUT(GPIOA_PIN6) \
| PIN_MODE_INPUT(GPIOA_PIN7) \
| PIN_MODE_INPUT(GPIOA_PIN8) \
| PIN_MODE_INPUT(GPIOA_PIN9) \
| PIN_MODE_INPUT(GPIOA_PIN10) \
| PIN_MODE_INPUT(GPIOA_PIN11) \
| PIN_MODE_INPUT(GPIOA_PIN12) \
| PIN_MODE_INPUT(GPIOA_PIN13) \
| PIN_MODE_INPUT(GPIOA_PIN14) \
| PIN_MODE_INPUT(GPIOA_PIN15) )
#define VAL_GPIOA_CFG \
( PIN_CFG_SCHMITT_EN(GPIOA_PIN0) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN1) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN2) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN3) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN4) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN5) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN6) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN7) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN8) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN9) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN10) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN11) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN12) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN13) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN14) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN15) )
#define VAL_GPIOB_MODE \
( PIN_MODE_INPUT(GPIOB_PIN0) \
| PIN_MODE_INPUT(GPIOB_PIN1) \
| PIN_MODE_INPUT(GPIOB_PIN2) \
| PIN_MODE_INPUT(GPIOB_PIN3) \
| PIN_MODE_INPUT(GPIOB_PIN4) \
| PIN_MODE_INPUT(GPIOB_PIN5) )
#define VAL_GPIOB_CFG \
( PIN_CFG_SCHMITT_EN(GPIOB_PIN0) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN1) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN2) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN3) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN4) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN5) )
#define VAL_GPIOC_MODE \
( PIN_MODE_INPUT(GPIOC_PIN0) \
| PIN_MODE_INPUT(GPIOC_PIN1) \
| PIN_MODE_INPUT(GPIOC_PIN2) \
| PIN_MODE_INPUT(GPIOC_PIN3) \
| PIN_MODE_INPUT(GPIOC_PIN4) \
| PIN_MODE_INPUT(GPIOC_PIN5) \
| PIN_MODE_INPUT(GPIOC_PIN6) \
| PIN_MODE_INPUT(GPIOC_PIN7) \
| PIN_MODE_INPUT(GPIOC_PIN8) \
| PIN_MODE_INPUT(GPIOC_PIN9) \
| PIN_MODE_INPUT(GPIOC_PIN10) )
#define VAL_GPIOC_CFG \
( PIN_CFG_SCHMITT_EN(GPIOC_PIN0) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN1) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN2) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN3) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN4) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN5) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN6) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN7) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN8) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN9) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN10) )
#define VAL_GPIOD_MODE \
( PIN_MODE_INPUT(GPIOD_PIN0) \
| PIN_MODE_INPUT(GPIOD_PIN1) \
| PIN_MODE_INPUT(GPIOD_PIN2) \
| PIN_MODE_INPUT(GPIOD_PIN3) \
| PIN_MODE_INPUT(GPIOD_PIN4) \
| PIN_MODE_INPUT(GPIOD_PIN5) \
| PIN_MODE_INPUT(GPIOD_PIN6) \
| PIN_MODE_INPUT(GPIOD_PIN7) \
| PIN_MODE_INPUT(GPIOD_PIN8) )
#define VAL_GPIOD_CFG \
( PIN_CFG_SCHMITT_EN(GPIOD_PIN0) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN1) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN2) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN3) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN4) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN5) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN6) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN7) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN8) )
#if !defined(_FROM_ASM_)
# ifdef __cplusplus
extern "C" {
# endif
void boardInit(void);
# ifdef __cplusplus
}
# endif
#endif /* _FROM_ASM_ */
#endif /* _BOARD_H_ */

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# List of all the board related files.
BOARDSRC = $(CHIBIOS_CONTRIB)/os/hal/boards/SN_SN32F260/board.c
# Required include directories
BOARDINC = $(CHIBIOS_CONTRIB)/os/hal/boards/SN_SN32F260
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

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os/hal/boards/SN_SN32F280/board.c Normal file
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/*
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* This file has been automatically generated using ChibiStudio board
* generator plugin. Do not edit manually.
*/
#include "hal.h"
#if HAL_USE_PAL || defined(__DOXYGEN__)
/**
* @brief PAL setup.
* @details Digital I/O ports static configuration as defined in @p board.h.
* This variable is used by the HAL when initializing the PAL driver.
*/
const PALConfig pal_default_config = {
#if SN32_HAS_GPIOA
{.mode = VAL_GPIOA_MODE, .cfg = VAL_GPIOA_CFG},
#endif
#if SN32_HAS_GPIOB
{.mode = VAL_GPIOB_MODE, .cfg = VAL_GPIOB_CFG},
#endif
#if SN32_HAS_GPIOC
{.mode = VAL_GPIOC_MODE, .cfg = VAL_GPIOC_CFG},
#endif
#if SN32_HAS_GPIOD
{.mode = VAL_GPIOD_MODE, .cfg = VAL_GPIOD_CFG},
#endif
};
#endif
static int flag __attribute__((section(".flag"))) __attribute__((__used__)) = 0xAAAA5555;
extern void enter_bootloader_mode_if_requested(void);
/**
* @brief Early initialization code.
* @details This initialization must be performed just after stack setup
* and before any other initialization.
*/
void __early_init(void) {
enter_bootloader_mode_if_requested();
sn32_clock_init();
}
/**
* @brief Board-specific initialization code.
* @todo Add your board-specific code, if any.
*/
void boardInit(void) {
SN_SYS0->EXRSTCTRL_b.RESETDIS = 1; // Disable RESET
SN_SYS0->SWDCTRL_b.SWDDIS = 1; // Disable SWD
}

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/*
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef _BOARD_H_
#define _BOARD_H_
/*
* Setup for Generic SN32F280 Board
*/
/*
* Board identifier.
*/
#define BOARD_GENERIC_SN32_F240
#define BOARD_NAME "SN32F280"
/*
* MCU type as defined in the SN32 header.
*/
#define SN32F280
/*
* IO pins assignments.
*/
#define GPIOA_PIN0 0U
#define GPIOA_PIN1 1U
#define GPIOA_PIN2 2U
#define GPIOA_PIN3 3U
#define GPIOA_PIN4 4U
#define GPIOA_PIN5 5U
#define GPIOA_PIN6 6U
#define GPIOA_PIN7 7U
#define GPIOA_PIN8 8U
#define GPIOA_PIN9 9U
#define GPIOA_PIN10 10U
#define GPIOA_PIN11 11U
#define GPIOA_PIN12 12U
#define GPIOA_PIN13 13U
#define GPIOA_PIN14 14U
#define GPIOA_PIN15 15U
#define GPIOA_PIN16 16U
#define GPIOA_PIN17 17U
#define GPIOA_PIN18 18U
#define GPIOA_PIN19 19U
#define GPIOB_PIN0 0U
#define GPIOB_PIN1 1U
#define GPIOB_PIN2 2U
#define GPIOB_PIN3 3U
#define GPIOB_PIN4 4U
#define GPIOB_PIN5 5U
#define GPIOB_PIN6 6U
#define GPIOB_PIN7 7U
#define GPIOB_PIN8 8U
#define GPIOB_PIN9 9U
#define GPIOB_PIN10 10U
#define GPIOB_PIN11 11U
#define GPIOB_PIN12 12U
#define GPIOB_PIN13 13U
#define GPIOB_PIN14 14U
#define GPIOB_PIN15 15U
#define GPIOB_PIN16 16U
#define GPIOB_PIN17 17U
#define GPIOB_PIN18 18U
#define GPIOB_PIN19 19U
#define GPIOC_PIN0 0U
#define GPIOC_PIN1 1U
#define GPIOC_PIN2 2U
#define GPIOC_PIN5 5U
#define GPIOC_PIN6 6U
#define GPIOC_PIN7 7U
#define GPIOC_PIN8 8U
#define GPIOC_PIN9 9U
#define GPIOC_PIN10 10U
#define GPIOC_PIN11 11U
#define GPIOC_PIN12 12U
#define GPIOC_PIN13 13U
#define GPIOC_PIN14 14U
#define GPIOC_PIN15 15U
#define GPIOD_PIN3 3U
#define GPIOD_PIN4 4U
#define GPIOD_PIN5 5U
#define GPIOD_PIN6 6U
#define GPIOD_PIN7 7U
#define GPIOD_PIN8 8U
#define GPIOD_PIN9 9U
#define GPIOD_PIN10 10U
#define GPIOD_PIN11 11U
#define GPIOD_PIN12 12U
#define GPIOD_PIN13 13U
#define GPIOD_PIN14 14U
#define GPIOD_PIN15 15U
#define GPIOD_PIN16 16U
#define GPIOD_PIN17 17U
#define GPIOD_PIN18 18U
#define GPIOD_PIN19 19U
/*
* I/O ports initial setup, this configuration is established soon after reset
* in the initialization code.
* Please refer to the SN32 Reference Manual for details.
*/
#define PIN_MODE_INPUT(n) (0U << ((n)))
#define PIN_MODE_OUTPUT(n) (1U << ((n)))
#define PIN_CFG_PULLUP(n) (0U << ((n*2))) // Pull-up
#define PIN_CFG_SCHMITT_EN(n) (2U << ((n*2))) // Floating
#define PIN_CFG_SCHMITT_DIS(n) (3U << ((n*2))) // Input buffer disconnected, alway read as zero.
// Define GPIO register values used by pal_default_config.
// The following values match the chip reset values, all GPIO pins as floating inputs.
#define VAL_GPIOA_MODE \
( PIN_MODE_INPUT(GPIOA_PIN0) \
| PIN_MODE_INPUT(GPIOA_PIN1) \
| PIN_MODE_INPUT(GPIOA_PIN2) \
| PIN_MODE_INPUT(GPIOA_PIN3) \
| PIN_MODE_INPUT(GPIOA_PIN4) \
| PIN_MODE_INPUT(GPIOA_PIN5) \
| PIN_MODE_INPUT(GPIOA_PIN6) \
| PIN_MODE_INPUT(GPIOA_PIN7) \
| PIN_MODE_INPUT(GPIOA_PIN8) \
| PIN_MODE_INPUT(GPIOA_PIN9) \
| PIN_MODE_INPUT(GPIOA_PIN10) \
| PIN_MODE_INPUT(GPIOA_PIN11) \
| PIN_MODE_INPUT(GPIOA_PIN12) \
| PIN_MODE_INPUT(GPIOA_PIN13) \
| PIN_MODE_INPUT(GPIOA_PIN14) \
| PIN_MODE_INPUT(GPIOA_PIN15) \
| PIN_MODE_INPUT(GPIOA_PIN16) \
| PIN_MODE_INPUT(GPIOA_PIN17) \
| PIN_MODE_INPUT(GPIOA_PIN18) \
| PIN_MODE_INPUT(GPIOA_PIN19) )
#define VAL_GPIOA_CFG \
( PIN_CFG_SCHMITT_EN(GPIOA_PIN0) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN1) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN2) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN3) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN4) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN5) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN6) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN7) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN8) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN9) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN10) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN11) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN12) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN13) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN14) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN15) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN16) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN17) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN18) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN19) )
#define VAL_GPIOB_MODE \
( PIN_MODE_INPUT(GPIOB_PIN0) \
| PIN_MODE_INPUT(GPIOB_PIN1) \
| PIN_MODE_INPUT(GPIOB_PIN2) \
| PIN_MODE_INPUT(GPIOB_PIN3) \
| PIN_MODE_INPUT(GPIOB_PIN4) \
| PIN_MODE_INPUT(GPIOB_PIN5) \
| PIN_MODE_INPUT(GPIOB_PIN6) \
| PIN_MODE_INPUT(GPIOB_PIN7) \
| PIN_MODE_INPUT(GPIOB_PIN8) \
| PIN_MODE_INPUT(GPIOB_PIN9) \
| PIN_MODE_INPUT(GPIOB_PIN10) \
| PIN_MODE_INPUT(GPIOB_PIN11) \
| PIN_MODE_INPUT(GPIOB_PIN12) \
| PIN_MODE_INPUT(GPIOB_PIN13) \
| PIN_MODE_INPUT(GPIOB_PIN14) \
| PIN_MODE_INPUT(GPIOB_PIN15) \
| PIN_MODE_INPUT(GPIOB_PIN16) \
| PIN_MODE_INPUT(GPIOB_PIN17) \
| PIN_MODE_INPUT(GPIOB_PIN18) \
| PIN_MODE_INPUT(GPIOB_PIN19) )
#define VAL_GPIOB_CFG \
( PIN_CFG_SCHMITT_EN(GPIOB_PIN0) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN1) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN2) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN3) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN4) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN5) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN6) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN7) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN8) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN9) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN10) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN11) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN12) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN13) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN14) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN15) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN16) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN17) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN18) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN19) )
#define VAL_GPIOC_MODE \
( PIN_MODE_INPUT(GPIOC_PIN0) \
| PIN_MODE_INPUT(GPIOC_PIN1) \
| PIN_MODE_INPUT(GPIOC_PIN2) \
| PIN_MODE_INPUT(GPIOC_PIN3) \
| PIN_MODE_INPUT(GPIOC_PIN4) \
| PIN_MODE_INPUT(GPIOC_PIN5) \
| PIN_MODE_INPUT(GPIOC_PIN6) \
| PIN_MODE_INPUT(GPIOC_PIN7) \
| PIN_MODE_INPUT(GPIOC_PIN8) \
| PIN_MODE_INPUT(GPIOC_PIN9) \
| PIN_MODE_INPUT(GPIOC_PIN10) \
| PIN_MODE_INPUT(GPIOC_PIN11) \
| PIN_MODE_INPUT(GPIOC_PIN12) \
| PIN_MODE_INPUT(GPIOC_PIN13) \
| PIN_MODE_INPUT(GPIOC_PIN14) \
| PIN_MODE_INPUT(GPIOC_PIN15) )
#define VAL_GPIOC_CFG \
( PIN_CFG_SCHMITT_EN(GPIOC_PIN0) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN1) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN2) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN3) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN4) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN5) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN6) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN7) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN8) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN9) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN10) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN11) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN12) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN13) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN14) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN15) )
#define VAL_GPIOD_MODE \
( PIN_MODE_INPUT(GPIOD_PIN3) \
| PIN_MODE_INPUT(GPIOD_PIN4) \
| PIN_MODE_INPUT(GPIOD_PIN5) \
| PIN_MODE_INPUT(GPIOD_PIN6) \
| PIN_MODE_INPUT(GPIOD_PIN7) \
| PIN_MODE_INPUT(GPIOD_PIN8) \
| PIN_MODE_INPUT(GPIOD_PIN9) \
| PIN_MODE_INPUT(GPIOD_PIN10) \
| PIN_MODE_INPUT(GPIOD_PIN11) \
| PIN_MODE_INPUT(GPIOD_PIN12) \
| PIN_MODE_INPUT(GPIOD_PIN13) \
| PIN_MODE_INPUT(GPIOD_PIN14) \
| PIN_MODE_INPUT(GPIOD_PIN15) \
| PIN_MODE_INPUT(GPIOD_PIN16) \
| PIN_MODE_INPUT(GPIOD_PIN17) \
| PIN_MODE_INPUT(GPIOD_PIN18) \
| PIN_MODE_INPUT(GPIOD_PIN19) )
#define VAL_GPIOD_CFG \
( PIN_CFG_SCHMITT_EN(GPIOD_PIN3) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN4) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN5) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN6) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN7) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN8) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN9) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN10) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN11) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN12) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN13) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN14) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN15) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN16) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN17) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN18) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN19) )
#if !defined(_FROM_ASM_)
# ifdef __cplusplus
extern "C" {
# endif
void boardInit(void);
# ifdef __cplusplus
}
# endif
#endif /* _FROM_ASM_ */
#endif /* _BOARD_H_ */

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# List of all the board related files.
BOARDSRC = $(CHIBIOS_CONTRIB)/os/hal/boards/SN_SN32F280/board.c
# Required include directories
BOARDINC = $(CHIBIOS_CONTRIB)/os/hal/boards/SN_SN32F280
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

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/*
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* This file has been automatically generated using ChibiStudio board
* generator plugin. Do not edit manually.
*/
#include "hal.h"
#if HAL_USE_PAL || defined(__DOXYGEN__)
/**
* @brief PAL setup.
* @details Digital I/O ports static configuration as defined in @p board.h.
* This variable is used by the HAL when initializing the PAL driver.
*/
const PALConfig pal_default_config = {
#if SN32_HAS_GPIOA
{.mode = VAL_GPIOA_MODE, .cfg = VAL_GPIOA_CFG},
#endif
#if SN32_HAS_GPIOB
{.mode = VAL_GPIOB_MODE, .cfg = VAL_GPIOB_CFG},
#endif
#if SN32_HAS_GPIOC
{.mode = VAL_GPIOC_MODE, .cfg = VAL_GPIOC_CFG},
#endif
#if SN32_HAS_GPIOD
{.mode = VAL_GPIOD_MODE, .cfg = VAL_GPIOD_CFG},
#endif
};
#endif
static int flag __attribute__((section(".flag"))) __attribute__((__used__)) = 0xAAAA5555;
extern void enter_bootloader_mode_if_requested(void);
/**
* @brief Early initialization code.
* @details This initialization must be performed just after stack setup
* and before any other initialization.
*/
void __early_init(void) {
enter_bootloader_mode_if_requested();
sn32_clock_init();
}
/**
* @brief Board-specific initialization code.
* @todo Add your board-specific code, if any.
*/
void boardInit(void) {
SN_SYS0->EXRSTCTRL_b.RESETDIS = 1; // Disable RESET
SN_SYS0->SWDCTRL_b.SWDDIS = 1; // Disable SWD
}

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/*
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef _BOARD_H_
#define _BOARD_H_
/*
* Setup for Generic SN32F290 Board
*/
/*
* Board identifier.
*/
#define BOARD_GENERIC_SN32_F240
#define BOARD_NAME "SN32F290"
/*
* MCU type as defined in the SN32 header.
*/
#define SN32F290
/*
* IO pins assignments.
*/
#define GPIOA_PIN0 0U
#define GPIOA_PIN1 1U
#define GPIOA_PIN2 2U
#define GPIOA_PIN3 3U
#define GPIOA_PIN4 4U
#define GPIOA_PIN5 5U
#define GPIOA_PIN6 6U
#define GPIOA_PIN7 7U
#define GPIOA_PIN8 8U
#define GPIOA_PIN9 9U
#define GPIOA_PIN10 10U
#define GPIOA_PIN11 11U
#define GPIOA_PIN12 12U
#define GPIOA_PIN13 13U
#define GPIOA_PIN14 14U
#define GPIOA_PIN15 15U
#define GPIOA_PIN16 16U
#define GPIOA_PIN17 17U
#define GPIOA_PIN18 18U
#define GPIOA_PIN19 19U
#define GPIOB_PIN0 0U
#define GPIOB_PIN1 1U
#define GPIOB_PIN2 2U
#define GPIOB_PIN3 3U
#define GPIOB_PIN4 4U
#define GPIOB_PIN5 5U
#define GPIOB_PIN6 6U
#define GPIOB_PIN7 7U
#define GPIOB_PIN8 8U
#define GPIOB_PIN9 9U
#define GPIOB_PIN10 10U
#define GPIOB_PIN11 11U
#define GPIOB_PIN12 12U
#define GPIOB_PIN13 13U
#define GPIOB_PIN14 14U
#define GPIOB_PIN15 15U
#define GPIOB_PIN16 16U
#define GPIOB_PIN17 17U
#define GPIOB_PIN18 18U
#define GPIOB_PIN19 19U
#define GPIOC_PIN0 0U
#define GPIOC_PIN1 1U
#define GPIOC_PIN2 2U
#define GPIOC_PIN5 5U
#define GPIOC_PIN6 6U
#define GPIOC_PIN7 7U
#define GPIOC_PIN8 8U
#define GPIOC_PIN9 9U
#define GPIOC_PIN10 10U
#define GPIOC_PIN11 11U
#define GPIOC_PIN12 12U
#define GPIOC_PIN13 13U
#define GPIOC_PIN14 14U
#define GPIOC_PIN15 15U
#define GPIOD_PIN3 3U
#define GPIOD_PIN4 4U
#define GPIOD_PIN5 5U
#define GPIOD_PIN6 6U
#define GPIOD_PIN7 7U
#define GPIOD_PIN8 8U
#define GPIOD_PIN9 9U
#define GPIOD_PIN10 10U
#define GPIOD_PIN11 11U
#define GPIOD_PIN12 12U
#define GPIOD_PIN13 13U
#define GPIOD_PIN14 14U
#define GPIOD_PIN15 15U
#define GPIOD_PIN16 16U
#define GPIOD_PIN17 17U
#define GPIOD_PIN18 18U
#define GPIOD_PIN19 19U
/*
* I/O ports initial setup, this configuration is established soon after reset
* in the initialization code.
* Please refer to the SN32 Reference Manual for details.
*/
#define PIN_MODE_INPUT(n) (0U << ((n)))
#define PIN_MODE_OUTPUT(n) (1U << ((n)))
#define PIN_CFG_PULLUP(n) (0U << ((n*2))) // Pull-up
#define PIN_CFG_SCHMITT_EN(n) (2U << ((n*2))) // Floating
#define PIN_CFG_SCHMITT_DIS(n) (3U << ((n*2))) // Input buffer disconnected, alway read as zero.
// Define GPIO register values used by pal_default_config.
// The following values match the chip reset values, all GPIO pins as floating inputs.
#define VAL_GPIOA_MODE \
( PIN_MODE_INPUT(GPIOA_PIN0) \
| PIN_MODE_INPUT(GPIOA_PIN1) \
| PIN_MODE_INPUT(GPIOA_PIN2) \
| PIN_MODE_INPUT(GPIOA_PIN3) \
| PIN_MODE_INPUT(GPIOA_PIN4) \
| PIN_MODE_INPUT(GPIOA_PIN5) \
| PIN_MODE_INPUT(GPIOA_PIN6) \
| PIN_MODE_INPUT(GPIOA_PIN7) \
| PIN_MODE_INPUT(GPIOA_PIN8) \
| PIN_MODE_INPUT(GPIOA_PIN9) \
| PIN_MODE_INPUT(GPIOA_PIN10) \
| PIN_MODE_INPUT(GPIOA_PIN11) \
| PIN_MODE_INPUT(GPIOA_PIN12) \
| PIN_MODE_INPUT(GPIOA_PIN13) \
| PIN_MODE_INPUT(GPIOA_PIN14) \
| PIN_MODE_INPUT(GPIOA_PIN15) \
| PIN_MODE_INPUT(GPIOA_PIN16) \
| PIN_MODE_INPUT(GPIOA_PIN17) \
| PIN_MODE_INPUT(GPIOA_PIN18) \
| PIN_MODE_INPUT(GPIOA_PIN19) )
#define VAL_GPIOA_CFG \
( PIN_CFG_SCHMITT_EN(GPIOA_PIN0) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN1) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN2) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN3) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN4) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN5) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN6) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN7) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN8) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN9) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN10) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN11) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN12) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN13) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN14) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN15) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN16) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN17) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN18) \
| PIN_CFG_SCHMITT_EN(GPIOA_PIN19) )
#define VAL_GPIOB_MODE \
( PIN_MODE_INPUT(GPIOB_PIN0) \
| PIN_MODE_INPUT(GPIOB_PIN1) \
| PIN_MODE_INPUT(GPIOB_PIN2) \
| PIN_MODE_INPUT(GPIOB_PIN3) \
| PIN_MODE_INPUT(GPIOB_PIN4) \
| PIN_MODE_INPUT(GPIOB_PIN5) \
| PIN_MODE_INPUT(GPIOB_PIN6) \
| PIN_MODE_INPUT(GPIOB_PIN7) \
| PIN_MODE_INPUT(GPIOB_PIN8) \
| PIN_MODE_INPUT(GPIOB_PIN9) \
| PIN_MODE_INPUT(GPIOB_PIN10) \
| PIN_MODE_INPUT(GPIOB_PIN11) \
| PIN_MODE_INPUT(GPIOB_PIN12) \
| PIN_MODE_INPUT(GPIOB_PIN13) \
| PIN_MODE_INPUT(GPIOB_PIN14) \
| PIN_MODE_INPUT(GPIOB_PIN15) \
| PIN_MODE_INPUT(GPIOB_PIN16) \
| PIN_MODE_INPUT(GPIOB_PIN17) \
| PIN_MODE_INPUT(GPIOB_PIN18) \
| PIN_MODE_INPUT(GPIOB_PIN19) )
#define VAL_GPIOB_CFG \
( PIN_CFG_SCHMITT_EN(GPIOB_PIN0) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN1) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN2) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN3) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN4) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN5) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN6) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN7) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN8) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN9) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN10) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN11) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN12) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN13) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN14) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN15) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN16) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN17) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN18) \
| PIN_CFG_SCHMITT_EN(GPIOB_PIN19) )
#define VAL_GPIOC_MODE \
( PIN_MODE_INPUT(GPIOC_PIN0) \
| PIN_MODE_INPUT(GPIOC_PIN1) \
| PIN_MODE_INPUT(GPIOC_PIN2) \
| PIN_MODE_INPUT(GPIOC_PIN3) \
| PIN_MODE_INPUT(GPIOC_PIN4) \
| PIN_MODE_INPUT(GPIOC_PIN5) \
| PIN_MODE_INPUT(GPIOC_PIN6) \
| PIN_MODE_INPUT(GPIOC_PIN7) \
| PIN_MODE_INPUT(GPIOC_PIN8) \
| PIN_MODE_INPUT(GPIOC_PIN9) \
| PIN_MODE_INPUT(GPIOC_PIN10) \
| PIN_MODE_INPUT(GPIOC_PIN11) \
| PIN_MODE_INPUT(GPIOC_PIN12) \
| PIN_MODE_INPUT(GPIOC_PIN13) \
| PIN_MODE_INPUT(GPIOC_PIN14) \
| PIN_MODE_INPUT(GPIOC_PIN15) )
#define VAL_GPIOC_CFG \
( PIN_CFG_SCHMITT_EN(GPIOC_PIN0) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN1) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN2) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN3) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN4) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN5) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN6) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN7) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN8) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN9) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN10) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN11) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN12) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN13) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN14) \
| PIN_CFG_SCHMITT_EN(GPIOC_PIN15) )
#define VAL_GPIOD_MODE \
( PIN_MODE_INPUT(GPIOD_PIN3) \
| PIN_MODE_INPUT(GPIOD_PIN4) \
| PIN_MODE_INPUT(GPIOD_PIN5) \
| PIN_MODE_INPUT(GPIOD_PIN6) \
| PIN_MODE_INPUT(GPIOD_PIN7) \
| PIN_MODE_INPUT(GPIOD_PIN8) \
| PIN_MODE_INPUT(GPIOD_PIN9) \
| PIN_MODE_INPUT(GPIOD_PIN10) \
| PIN_MODE_INPUT(GPIOD_PIN11) \
| PIN_MODE_INPUT(GPIOD_PIN12) \
| PIN_MODE_INPUT(GPIOD_PIN13) \
| PIN_MODE_INPUT(GPIOD_PIN14) \
| PIN_MODE_INPUT(GPIOD_PIN15) \
| PIN_MODE_INPUT(GPIOD_PIN16) \
| PIN_MODE_INPUT(GPIOD_PIN17) \
| PIN_MODE_INPUT(GPIOD_PIN18) \
| PIN_MODE_INPUT(GPIOD_PIN19) )
#define VAL_GPIOD_CFG \
( PIN_CFG_SCHMITT_EN(GPIOD_PIN3) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN4) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN5) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN6) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN7) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN8) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN9) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN10) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN11) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN12) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN13) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN14) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN15) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN16) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN17) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN18) \
| PIN_CFG_SCHMITT_EN(GPIOD_PIN19) )
#if !defined(_FROM_ASM_)
# ifdef __cplusplus
extern "C" {
# endif
void boardInit(void);
# ifdef __cplusplus
}
# endif
#endif /* _FROM_ASM_ */
#endif /* _BOARD_H_ */

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# List of all the board related files.
BOARDSRC = $(CHIBIOS_CONTRIB)/os/hal/boards/SN_SN32F290/board.c
# Required include directories
BOARDINC = $(CHIBIOS_CONTRIB)/os/hal/boards/SN_SN32F290
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

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/******************** (C) COPYRIGHT 2013 SONiX *******************************
* COMPANY: SONiX
* DATE: 2013/12
* AUTHOR: SA1
* IC: SN32F240/230/220
* DESCRIPTION: ADC related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2013/12/17 SA1 First release
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240.h>
#include <SN32F200_Def.h>
#include "ADC.h"
#include "..\..\Utility\Utility.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
uint8_t bADC_StartConv;
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
/*****************************************************************************
* Function : ADC_Init
* Description : Initialization of ADC
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void ADC_Init(void)
{
SN_SYS1->AHBCLKEN |= (0x01 << 11); //Enables HCLK for ADC
//Set ADC PCLK
SN_SYS1->APBCP0 |= (0x00 << 16); //ADC PCLK = HCLK/1
//SN_SYS1->APBCP0 |= (0x01 << 16); //ADC PCLK = HCLK/2
//SN_SYS1->APBCP0 |= (0x02 << 16); //ADC PCLK = HCLK/4
//SN_SYS1->APBCP0 |= (0x03 << 16); //ADC PCLK = HCLK/8
//SN_SYS1->APBCP0 |= (0x04 << 16); //ADC PCLK = HCLK/16
SN_ADC->ADM_b.ADENB = ADC_ADENB_EN; //Enable ADC
UT_DelayNx10us(10); //Delay 100us
SN_ADC->ADM_b.AVREFHSEL = ADC_AVREFHSEL_INTERNAL; //Set ADC high reference voltage source from internal VDD
SN_ADC->ADM_b.GCHS = ADC_GCHS_EN; //Enable ADC global channel
SN_ADC->ADM_b.ADLEN = ADC_ADLEN_12BIT; //Set ADC resolution = 12-bit
SN_ADC->ADM_b.ADCKS = ADC_ADCKS_DIV32; //ADC_CLK = ADC_PCLK/32
#if ADC_FUNCTION_TYPE == ADC_TYPE
SN_ADC->ADM_b.CHS = ADC_CHS_AIN1; //Set P2.1 as ADC input channel
SN_ADC->IE |= ADC_IE_AIN1; //Enable ADC channel P2.1 interrupt
#endif
#if ADC_FUNCTION_TYPE == TS_TYPE
SN_ADC->ADM_b.TSENB = ADC_TSENB_EN; //Enable Temperature Sensor
SN_ADC->ADM_b.CHS = ADC_CHS_TS; //Set P2.14 as Temperature Sensor channel
SN_ADC->IE |= ADC_IE_TS; //Enable Temperature Sensor interrupt
#endif
ADC_NvicEnable(); //Enable ADC NVIC interrupt
}
/*****************************************************************************
* Function : ADC_Read
* Description : Read ADC converted data
* Input : None
* Output : None
* Return : Data in ADB register
* Note : None
*****************************************************************************/
uint16_t ADC_Read(void)
{
return SN_ADC->ADB;
}
/*****************************************************************************
* Function : ADC_IRQHandler
* Description : ISR of ADC interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
__irq void ADC_IRQHandler(void)
{
bADC_StartConv = 0;
SN_ADC->RIS = 0x0; //clear interrupt flag
}
/*****************************************************************************
* Function : ADC_NvicEnable
* Description : Enable ADC interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void ADC_NvicEnable(void)
{
NVIC_ClearPendingIRQ(ADC_IRQn);
NVIC_EnableIRQ(ADC_IRQn);
NVIC_SetPriority(ADC_IRQn,0); // Set interrupt priority (default)
}
/*****************************************************************************
* Function : ADC_NvicDisable
* Description : Disable ADC interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void ADC_NvicDisable(void)
{
NVIC_DisableIRQ(ADC_IRQn);
}

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#ifndef __SN32F240_ADC_H
#define __SN32F240_ADC_H
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240.h>
/*_____ D E F I N I T I O N S ______________________________________________*/
//ADC function Type
#define ADC_FUNCTION_TYPE ADC_TYPE //ADC_TYPE, TS_TYPE
#define ADC_TYPE 0 //ADC function
#define TS_TYPE 1 //Temperature Sensor function
//Temperature sensor enable bit
#define ADC_TSENB_DIS 0x0
#define ADC_TSENB_EN 0x1
//ADC high reference voltage source select bit
#define ADC_AVREFHSEL_INTERNAL 0x0
#define ADC_AVREFHSEL_EXTERNAL 0x1
//ADC Enable bit
#define ADC_ADENB_DIS 0x0
#define ADC_ADENB_EN 0x1
//ADC Clock source divider
#define ADC_ADCKS_DIV1 0x0
#define ADC_ADCKS_DIV2 0x1
#define ADC_ADCKS_DIV4 0x2
#define ADC_ADCKS_DIV8 0x3
#define ADC_ADCKS_DIV16 0x5
#define ADC_ADCKS_DIV32 0x6
//ADC resolution control bit
#define ADC_ADLEN_8BIT 0x0
#define ADC_ADLEN_12BIT 0x1
//ADC start control bit
#define ADC_ADS_STOP 0x0
#define ADC_ADS_START 0x1
//ADC global channel select bit
#define ADC_GCHS_DIS 0x0
#define ADC_GCHS_EN 0x1
//ADC input channels select bit
#define ADC_CHS_AIN0 0x0 //P2.0
#define ADC_CHS_AIN1 0x1 //P2.1
#define ADC_CHS_AIN2 0x2 //P2.2
#define ADC_CHS_AIN3 0x3 //P2.3
#define ADC_CHS_AIN4 0x4 //P2.4
#define ADC_CHS_AIN5 0x5 //P2.5
#define ADC_CHS_AIN6 0x6 //P2.6
#define ADC_CHS_AIN7 0x7 //P2.7
#define ADC_CHS_AIN8 0x8 //P2.8
#define ADC_CHS_AIN9 0x9 //P2.9
#define ADC_CHS_AIN10 0xA //P2.10
#define ADC_CHS_AIN11 0xB //P2.11
#define ADC_CHS_AIN12 0xC //P2.12
#define ADC_CHS_AIN13 0xD //P2.13
#define ADC_CHS_TS 0xE //Temperature Sensor
//ADC Interrupt Enable register(ADC_IE)
#define ADC_IE_AIN0 0x0001
#define ADC_IE_AIN1 0x0002
#define ADC_IE_AIN2 0x0004
#define ADC_IE_AIN3 0x0008
#define ADC_IE_AIN4 0x0010
#define ADC_IE_AIN5 0x0020
#define ADC_IE_AIN6 0x0040
#define ADC_IE_AIN7 0x0080
#define ADC_IE_AIN8 0x0100
#define ADC_IE_AIN9 0x0200
#define ADC_IE_AIN10 0x0400
#define ADC_IE_AIN11 0x0800
#define ADC_IE_AIN12 0x1000
#define ADC_IE_AIN13 0x2000
#define ADC_IE_TS 0x4000
//ADC Raw Interrupt Status register(ADC_RIS)
#define mskADC_IF_AIN0 (0x1<<0) //P2.0
#define mskADC_IF_AIN1 (0x1<<1) //P2.1
#define mskADC_IF_AIN2 (0x1<<2) //P2.2
#define mskADC_IF_AIN3 (0x1<<3) //P2.3
#define mskADC_IF_AIN4 (0x1<<4) //P2.4
#define mskADC_IF_AIN5 (0x1<<5) //P2.5
#define mskADC_IF_AIN6 (0x1<<6) //P2.6
#define mskADC_IF_AIN7 (0x1<<7) //P2.7
#define mskADC_IF_AIN8 (0x1<<8) //P2.8
#define mskADC_IF_AIN9 (0x1<<9) //P2.9
#define mskADC_IF_AIN10 (0x1<<10) //P2.10
#define mskADC_IF_AIN11 (0x1<<11) //P2.11
#define mskADC_IF_AIN12 (0x1<<12) //P2.12
#define mskADC_IF_AIN13 (0x1<<13) //P2.13
#define mskADC_IF_TS (0x1<<14) //Temperature Sensor
/*_____ M A C R O S ________________________________________________________*/
/*_____ D E C L A R A T I O N S ____________________________________________*/
extern uint8_t bADC_StartConv;
void ADC_Init(void);
uint16_t ADC_Read(void);
void ADC_NvicEnable(void);
void ADC_NvicDisable(void);
#endif /*__SN32F240_ADC_H*/

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#ifndef __SN32F240_CT16_H
#define __SN32F240_CT16_H
/*_____ I N C L U D E S ____________________________________________________*/
/*_____ D E F I N I T I O N S ______________________________________________*/
/*
Base Address: 0x4000 0000 (CT16B0)
0x4000 2000 (CT16B1)
0x4000 4000 (CT16B2)
*/
/* CT16Bn Timer Control register <CT16Bn_TMRCTRL> (0x00) */
#define CT16_CEN_DIS 0 //[0:0] CT16Bn enable bit
#define CT16_CEN_EN 1
#define mskCT16_CEN_DIS (CT16_CEN_DIS<<0)
#define mskCT16_CEN_EN (CT16_CEN_EN<<0)
#define CT16_CRST 1 //[1:1] CT16Bn counter reset bit
#define mskCT16_CRST (CT16_CRST<<1)
//[6:4] CT16Bn counting mode selection
#define CT16_CM_EDGE_UP 0 //Edge-aligned Up-counting mode
#define CT16_CM_EDGE_DOWN 1 //Edge-aligned Down-counting mode
#define CT16_CM_CENTER_UP 2 //Center-aligned mode 1. Match interrupt is set during up-counting period
#define CT16_CM_CENTER_DOWN 4 //Center-aligned mode 2. Match interrupt is set during down-counting period
#define CT16_CM_CENTER_BOTH 6 //Center-aligned mode 3. Match interrupt is set during both up and down period.
#define mskCT16_CM_EDGE_UP (CT16_CM_EDGE_UP<<4)
#define mskCT16_CM_EDGE_DOWN (CT16_CM_EDGE_DOWN<<4)
#define mskCT16_CM_CENTER_UP (CT16_CM_CENTER_UP<<4)
#define mskCT16_CM_CENTER_DOWN (CT16_CM_CENTER_DOWN<<4)
#define mskCT16_CM_CENTER_BOTH (CT16_CM_CENTER_BOTH<<4)
/* CT16Bn Count Control register <CT16Bn_CNTCTRL> (0x10) */
//[1:0] Count/Timer Mode selection.
#define CT16_CTM_TIMER 0 //Timer mode: Every rising PCLK edge.
#define CT16_CTM_CNTER_RISING 1 //Counter mode: TC increments on rising edge of CAP input.
#define CT16_CTM_CNTER_FALLING 2 //Counter mode: TC increments on falling edge of CAP input.
#define CT16_CTM_CNTER_BOTH 3 //Counter mode: TC increments on both edge of CAP input.
#define mskCT16_CTM_TIMER (CT16_CTM_TIMER<<0)
#define mskCT16_CTM_CNTER_RISING (CT16_CTM_CNTER_RISING<<0)
#define mskCT16_CTM_CNTER_FALLING (CT16_CTM_CNTER_FALLING<<0)
#define mskCT16_CTM_CNTER_BOTH (CT16_CTM_CNTER_BOTH<<0)
#define CT16_CIS 0 //[3:2] Count Input Select
#define mskCT16_CIS (CT16_CIS<<2)
/* CT16Bn Match Control register <CT16Bn_MCTRL> (0x14) */
#define CT16_MR0IE_EN 1 //[0:0] Enable MR0 match interrupt
#define CT16_MR0IE_DIS 0
#define mskCT16_MR0IE_EN (CT16_MR0IE_EN<<0)
#define mskCT16_MR0IE_DIS (CT16_MR0IE_DIS<<0)
#define CT16_MR0RST_EN 1 //[1:1] Enable reset TC when MR0 matches TC.
#define CT16_MR0RST_DIS 0
#define mskCT16_MR0RST_EN (CT16_MR0RST_EN<<1)
#define mskCT16_MR0RST_DIS (CT16_MR0RST_DIS<<1)
#define CT16_MR0STOP_EN 1 //[2:2] Enable stop TC and clear CEN when MR0 matches TC.
#define CT16_MR0STOP_DIS 0
#define mskCT16_MR0STOP_EN (CT16_MR0STOP_EN<<2)
#define mskCT16_MR0STOP_DIS (CT16_MR0STOP_DIS<<2)
#define CT16_MR1IE_EN 1 //[3:3] Enable MR1 match interrupt
#define CT16_MR1IE_DIS 0
#define mskCT16_MR1IE_EN (CT16_MR1IE_EN<<3)
#define mskCT16_MR1IE_DIS (CT16_MR1IE_DIS<<3)
#define CT16_MR1RST_EN 1 //[4:4] Enable reset TC when MR1 matches TC.
#define CT16_MR1RST_DIS 0
#define mskCT16_MR1RST_EN (CT16_MR1RST_EN<<4)
#define mskCT16_MR1RST_DIS (CT16_MR1RST_DIS<<4)
#define CT16_MR1STOP_EN 1 //[5:5] Enable stop TC and clear CEN when MR1 matches TC.
#define CT16_MR1STOP_DIS 0
#define mskCT16_MR1STOP_EN (CT16_MR1STOP_EN<<5)
#define mskCT16_MR1STOP_DIS (CT16_MR1STOP_DIS<<5)
#define CT16_MR2IE_EN 1 //[6:6] Enable MR2 match interrupt
#define CT16_MR2IE_DIS 0
#define mskCT16_MR2IE_EN (CT16_MR2IE_EN<<6)
#define mskCT16_MR2IE_DIS (CT16_MR2IE_DIS<<6)
#define CT16_MR2RST_EN 1 //[7:7] Enable reset TC when MR2 matches TC.
#define CT16_MR2RST_DIS 0
#define mskCT16_MR2RST_EN (CT16_MR2RST_EN<<7)
#define mskCT16_MR2RST_DIS (CT16_MR2RST_DIS<<7)
#define CT16_MR2STOP_EN 1 //[8:8] Enable stop TC and clear CEN when MR2 matches TC.
#define CT16_MR2STOP_DIS 0
#define mskCT16_MR2STOP_EN (CT16_MR2STOP_EN<<8)
#define mskCT16_MR2STOP_DIS (CT16_MR2STOP_DIS<<8)
#define CT16_MR3IE_EN 1 //[9:9] Enable MR3 match interrupt
#define CT16_MR3IE_DIS 0
#define mskCT16_MR3IE_EN (CT16_MR3IE_EN<<9)
#define mskCT16_MR3IE_DIS (CT16_MR3IE_DIS<<9)
#define CT16_MR3RST_EN 1 //[10:10] Enable reset TC when MR3 matches TC.
#define CT16_MR3RST_DIS 0
#define mskCT16_MR3RST_EN (CT16_MR3RST_EN<<10)
#define mskCT16_MR3RST_DIS (CT16_MR3RST_DIS<<10)
#define CT16_MR3STOP_EN 1 //[11:11] Enable stop TC and clear CEN when MR3 matches TC.
#define CT16_MR3STOP_DIS 0
#define mskCT16_MR3STOP_EN (CT16_MR3STOP_EN<<11)
#define mskCT16_MR3STOP_DIS (CT16_MR3STOP_DIS<<11)
/* CT16Bn Capture Control register <CT16Bn_CAPCTRL> (0x28) */
#define CT16_CAP0RE_EN 1 //[0:0] Enable CAP0 capture on rising edge.
#define CT16_CAP0RE_DIS 0
#define mskCT16_CAP0RE_EN (CT16_CAP0RE_EN<<0)
#define mskCT16_CAP0RE_DIS (CT16_CAP0RE_DIS<<0)
#define CT16_CAP0FE_EN 1 //[1:1] Enable CAP0 capture on fallng edge.
#define CT16_CAP0FE_DIS 0
#define mskCT16_CAP0FE_EN (CT16_CAP0FE_EN<<1)
#define mskCT16_CAP0FE_DIS (CT16_CAP0FE_DIS<<1)
#define CT16_CAP0IE_EN 1 //[2:2] Enable CAP0 interrupt.
#define CT16_CAP0IE_DIS 0
#define mskCT16_CAP0IE_EN (CT16_CAP0IE_EN<<2)
#define mskCT16_CAP0IE_DIS (CT16_CAP0IE_DIS<<2)
#define CT16_CAP0EN_EN 1 //[3:3] Enable CAP0 function.
#define CT16_CAP0EN_DIS 0
#define mskCT16_CAP0EN_EN (CT16_CAP0EN_EN<<3)
#define mskCT16_CAP0EN_DIS (CT16_CAP0EN_DIS<<3)
/* CT16Bn External Match register <CT16Bn_EM> (0x30) */
#define CT16_EM0 1 //[0:0] CT16Bn PWM0 drive state
#define mskCT16_EM0 (CT16_EM0<<0)
#define CT16_EM1 1 //[1:1] CT16Bn PWM1 drive state
#define mskCT16_EM1 (CT16_EM1<<1)
#define CT16_EM2 1 //[2:2] CT16Bn PWM2 drive state
#define mskCT16_EM2 (CT16_EM2<<2)
//[5:4] CT16Bn PWM0 functionality
#define CT16_EMC0_DO_NOTHING 0 //Do nothing.
#define CT16_EMC0_LOW 1 //CT16Bn PWM0 pin is low.
#define CT16_EMC0_HIGH 2 //CT16Bn PWM0 pin is high.
#define CT16_EMC0_TOGGLE 3 //Toggle CT16Bn PWM0 pin.
#define mskCT16_EMC0_DO_NOTHING (CT16_EMC0_LOW<<4)
#define mskCT16_EMC0_LOW (CT16_EMC0_LOW<<4)
#define mskCT16_EMC0_HIGH (CT16_EMC0_HIGH<<4)
#define mskCT16_EMC0_TOGGLE (CT16_EMC0_TOGGLE<<4)
//[7:6] CT16Bn PWM1 functionality
#define CT16_EMC1_DO_NOTHING 0 //Do nothing.
#define CT16_EMC1_LOW 1 //CT16Bn PWM1 pin is low.
#define CT16_EMC1_HIGH 2 //CT16Bn PWM1 pin is high.
#define CT16_EMC1_TOGGLE 3 //Toggle CT16Bn PWM1 pin.
#define mskCT16_EMC1_DO_NOTHING (CT16_EMC1_LOW<<6)
#define mskCT16_EMC1_LOW (CT16_EMC1_LOW<<6)
#define mskCT16_EMC1_HIGH (CT16_EMC1_HIGH<<6)
#define mskCT16_EMC1_TOGGLE (CT16_EMC1_TOGGLE<<6)
//[9:8] CT16Bn PWM2 functionality
#define CT16_EMC2_DO_NOTHING 0 //Do nothing.
#define CT16_EMC2_LOW 1 //CT16Bn PWM2 pin is low.
#define CT16_EMC2_HIGH 2 //CT16Bn PWM2 pin is high.
#define CT16_EMC2_TOGGLE 3 //Toggle CT16Bn PWM2 pin.
#define mskCT16_EMC2_DO_NOTHING (CT16_EMC2_LOW<<8)
#define mskCT16_EMC2_LOW (CT16_EMC2_LOW<<8)
#define mskCT16_EMC2_HIGH (CT16_EMC2_HIGH<<8)
#define mskCT16_EMC2_TOGGLE (CT16_EMC2_TOGGLE<<8)
/* CT16Bn PWM Control register <CT16Bn_PWMCTRL> (0x34) */
//[0:0] CT16Bn PWM0 enable.
#define CT16_PWM0EN_EN 1 // CT16Bn PWM0 is enabled for PWM mode.
#define CT16_PWM0EN_EM0 0 // CT16Bn PWM0 is controlled by EM0.
#define mskCT16_PWM0EN_EN (CT16_PWM0EN_EN<<0)
#define mskCT16_PWM0EN_EM0 (CT16_PWM0EN_EM0<<0)
//[1:1] CT16Bn PWM1 enable.
#define CT16_PWM1EN_EN 1 // CT16Bn PWM1 is enabled for PWM mode.
#define CT16_PWM1EN_EM1 0 // CT16Bn PWM1 is controlled by EM1.
#define mskCT16_PWM1EN_EN (CT16_PWM1EN_EN<<1)
#define mskCT16_PWM1EN_EM1 (CT16_PWM1EN_EM1<<1)
//[2:2] CT16Bn PWM2 enable.
#define CT16_PWM2EN_EN 1 // CT16Bn PWM2 is enabled for PWM mode.
#define CT16_PWM2EN_EM2 0 // CT16Bn PWM2 is controlled by EM2.
#define mskCT16_PWM2EN_EN (CT16_PWM2EN_EN<<2)
#define mskCT16_PWM2EN_EM2 (CT16_PWM2EN_EM2<<2)
//[5:4] CT16Bn PWM0 output mode.
#define CT16_PWM0MODE_1 0 // PWM mode 1.
#define CT16_PWM0MODE_2 1 // PWM mode 2.
#define CT16_PWM0MODE_FORCE_0 2 // Force 0.
#define CT16_PWM0MODE_FORCE_1 3 // Force 1.
#define mskCT16_PWM0MODE_1 (CT16_PWM0MODE_1<<4)
#define mskCT16_PWM0MODE_2 (CT16_PWM0MODE_2<<4)
#define mskCT16_PWM0MODE_FORCE_0 (CT16_PWM0MODE_FORCE_0<<4)
#define mskCT16_PWM0MODE_FORCE_1 (CT16_PWM0MODE_FORCE_1<<4)
//[7:6] CT16Bn PWM1 output mode.
#define CT16_PWM1MODE_1 0 // PWM mode 1.
#define CT16_PWM1MODE_2 1 // PWM mode 2.
#define CT16_PWM1MODE_FORCE_0 2 // Force 0.
#define CT16_PWM1MODE_FORCE_1 3 // Force 1.
#define mskCT16_PWM1MODE_1 (CT16_PWM1MODE_1<<6)
#define mskCT16_PWM1MODE_2 (CT16_PWM1MODE_2<<6)
#define mskCT16_PWM1MODE_FORCE_0 (CT16_PWM1MODE_FORCE_0<<6)
#define mskCT16_PWM1MODE_FORCE_1 (CT16_PWM1MODE_FORCE_1<<6)
//[9:8] CT16Bn PWM2 output mode.
#define CT16_PWM2MODE_1 0 // PWM mode 1.
#define CT16_PWM2MODE_2 1 // PWM mode 2.
#define CT16_PWM2MODE_FORCE_0 2 // Force 0.
#define CT16_PWM2MODE_FORCE_1 3 // Force 1.
#define mskCT16_PWM2MODE_1 (CT16_PWM2MODE_1<<8)
#define mskCT16_PWM2MODE_2 (CT16_PWM2MODE_2<<8)
#define mskCT16_PWM2MODE_FORCE_0 (CT16_PWM2MODE_FORCE_0<<8)
#define mskCT16_PWM2MODE_FORCE_1 (CT16_PWM2MODE_FORCE_1<<8)
//[20:20] CT16Bn PWM0 IO selection.
#define CT16_PWM0IOEN_EN 1 // PWM 0 pin acts as match output.
#define CT16_PWM0IOEN_DIS 0 // PWM 0 pin acts as GPIO.
#define mskCT16_PWM0IOEN_EN (CT16_PWM0IOEN_EN<<20)
#define mskCT16_PWM0IOEN_DIS (CT16_PWM0IOEN_DIS<<20)
//[21:21] CT16Bn PWM1 IO selection.
#define CT16_PWM1IOEN_EN 1 // PWM 1 pin acts as match output.
#define CT16_PWM1IOEN_DIS 0 // PWM 1 pin acts as GPIO.
#define mskCT16_PWM1IOEN_EN (CT16_PWM1IOEN_EN<<21)
#define mskCT16_PWM1IOEN_DIS (CT16_PWM1IOEN_DIS<<21)
//[22:22] CT16Bn PWM2 IO selection.
#define CT16_PWM2IOEN_EN 1 // PWM 2 pin acts as match output.
#define CT16_PWM2IOEN_DIS 0 // PWM 2 pin acts as GPIO.
#define mskCT16_PWM2IOEN_EN (CT16_PWM2IOEN_EN<<22)
#define mskCT16_PWM2IOEN_DIS (CT16_PWM2IOEN_DIS<<22)
/* CT16Bn Timer Raw Interrupt Status register <CT16Bn_RIS> (0x38) */
/* CT16Bn Timer Interrupt Clear register <CT16Bn_IC> (0x3C) */
/* The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS*/
#define mskCT16_MR0IF (0x1<<0) //[0:0] Interrupt flag for match channel 0
#define mskCT16_MR0IC mskCT16_MR0IF
#define mskCT16_MR1IF (0x1<<1) //[1:1] Interrupt flag for match channel 1
#define mskCT16_MR1IC mskCT16_MR1IF
#define mskCT16_MR2IF (0x1<<2) //[2:2] Interrupt flag for match channel 2
#define mskCT16_MR2IC mskCT16_MR2IF
#define mskCT16_MR3IF (0x1<<3) //[3:3] Interrupt flag for match channel 3
#define mskCT16_MR3IC mskCT16_MR3IF
#define mskCT16_CAP0IF (0x1<<4) //[4:4] Interrupt flag for capture channel 0
#define mskCT16_CAP0IC mskCT16_CAP0IF
/*_____ M A C R O S ________________________________________________________*/
/*_____ D E C L A R A T I O N S ____________________________________________*/
#endif /*__SN32F240_CT16_H*/

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/******************** (C) COPYRIGHT 2013 SONiX *******************************
* COMPANY: SONiX
* DATE: 2013/12
* AUTHOR: SA1
* IC: SN32F240/230/220
* DESCRIPTION: CT16B0 related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2013/12/17 SA1 First release
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240.h>
#include "CT16.h"
#include "CT16B0.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
volatile uint32_t iwCT16B0_IrqEvent = 0x00; //The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS
void CT16B0_Init (void);
void CT16B0_NvicEnable (void);
void CT16B0_NvicDisable (void);
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
/*****************************************************************************
* Function : CT16B0_Init
* Description : Initialization of CT16B0 timer
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void CT16B0_Init (void)
{
//Enable P_CLOCK for CT16B0.
__CT16B0_ENABLE;
//CT16B0 PCLK prescalar setting
SN_SYS1->APBCP0_b.CT16B0PRE = 0x00; //PCLK = HCLK/1
//SN_SYS1->APBCP0_b.CT16B0PRE = 0x01; //PCLK = HCLK/2
//SN_SYS1->APBCP0_b.CT16B0PRE = 0x02; //PCLK = HCLK/4
//SN_SYS1->APBCP0_b.CT16B0PRE = 0x03; //PCLK = HCLK/8
//SN_SYS1->APBCP0_b.CT16B0PRE = 0x04; //PCLK = HCLK/16
}
/*****************************************************************************
* Function : CT16B0_NvicEnable
* Description : Enable CT16B0 timer interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void CT16B0_NvicEnable (void)
{
NVIC_ClearPendingIRQ(CT16B0_IRQn);
NVIC_EnableIRQ(CT16B0_IRQn);
//NVIC_SetPriority(CT16B0_IRQn,0); // Set interrupt priority (default)
}
/*****************************************************************************
* Function : CT16B0_NvicEnable
* Description : Disable CT16B0 timer interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void CT16B0_NvicDisable (void)
{
NVIC_DisableIRQ(CT16B0_IRQn);
}
/*****************************************************************************
* Function : CT16B0_IRQHandler
* Description : ISR of CT16B0 interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void CT16B0_IRQHandler(void)
{
uint32_t iwRisStatus;
iwRisStatus = SN_CT16B0->RIS; //Save the interrupt status.
//Before checking the status, always re-check the interrupt enable register first.
//In practice, user might use only one or two timer interrupt source.
//Ex: Enable only MR0IE and MR3IE ==> No check on MR1IE, MR2IE, and CAP0IE is necessary.
//User can add the directive pair of "#if 0" and "#endif" pair
//to COMMENT the un-used parts to reduce ISR overheads and ROM usage.
//Check the status in oder.
//MR0
if (SN_CT16B0->MCTRL_b.MR0IE) //Check if MR0 IE enables?
{
if(iwRisStatus & mskCT16_MR0IF)
{
iwCT16B0_IrqEvent |= mskCT16_MR0IF;
SN_CT16B0->IC = mskCT16_MR0IC; //Clear MR0 match interrupt status
}
}
//MR1
if (SN_CT16B0->MCTRL_b.MR1IE) //Check if MR1 IE enables?
{
if(iwRisStatus & mskCT16_MR1IF)
{
iwCT16B0_IrqEvent |= mskCT16_MR1IF;
SN_CT16B0->IC = mskCT16_MR1IC; //Clear MR1 match interrupt status
}
}
//MR2
if (SN_CT16B0->MCTRL_b.MR2IE) //Check if MR2 IE enables?
{
if(iwRisStatus & mskCT16_MR2IF)
{
iwCT16B0_IrqEvent |= mskCT16_MR2IF;
SN_CT16B0->IC = mskCT16_MR2IC; //Clear MR2 match interrupt status
}
}
//MR3
if (SN_CT16B0->MCTRL_b.MR3IE) //Check if MR3 IE enables?
{
if(iwRisStatus & mskCT16_MR3IF)
{
iwCT16B0_IrqEvent |= mskCT16_MR3IF;
SN_CT16B0->IC = mskCT16_MR3IC; //Clear MR3 match interrupt status
}
}
//CAP0
if (SN_CT16B0->CAPCTRL_b.CAP0IE) //Check if CAP0 IE enables?
{
if(iwRisStatus & mskCT16_CAP0IF) //CAP0
{
iwCT16B0_IrqEvent |= mskCT16_CAP0IF;
SN_CT16B0->IC = mskCT16_CAP0IC; //Clear CAP0 interrupt status
}
}
}

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#ifndef __SN32F240_CT16B0_H
#define __SN32F240_CT16B0_H
/*_____ I N C L U D E S ____________________________________________________*/
#include <stdint.h>
#include <SN32F200_Def.h>
/*_____ D E F I N I T I O N S ______________________________________________*/
#define CT16B0_IRQ INTERRUPT_METHOD //INTERRUPT_METHOD: Enable CT16B0 timer and interrupt
//POLLING_METHOD: Enable CT16B0 timer ONLY
/*_____ M A C R O S ________________________________________________________*/
// Enable CT16B0 PCLK
#define __CT16B0_ENABLE SN_SYS1->AHBCLKEN_b.CT16B0CLKEN = ENABLE
// Disable CT16B0 PCLK
#define __CT16B0_DISABLE SN_SYS1->AHBCLKEN_b.CT16B0CLKEN = DISABLE
/*_____ D E C L A R A T I O N S ____________________________________________*/
extern volatile uint32_t iwCT16B0_IrqEvent; //The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS
extern void CT16B0_Init(void);
extern void CT16B0_NvicEnable(void);
extern void CT16B0_NvicDisable(void);
extern void CT16B0_IRQHandler(void);
#endif /*__SN32F240_CT16B0_H*/

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/******************** (C) COPYRIGHT 2013 SONiX *******************************
* COMPANY: SONiX
* DATE: 2013/12
* AUTHOR: SA1
* IC: SN32F240/230/220
* DESCRIPTION: CT16B1 related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2013/12/17 SA1 First release
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240.h>
#include "CT16.h"
#include "CT16B1.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
volatile uint32_t iwCT16B1_IrqEvent = 0x00; //The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS
void CT16B1_Init (void);
void CT16B1_NvicEnable (void);
void CT16B1_NvicDisable (void);
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
/*****************************************************************************
* Function : CT16B1_Init
* Description : Initialization of CT16B1 timer
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void CT16B1_Init (void)
{
//Enable P_CLOCK for CT16B1.
__CT16B1_ENABLE;
//CT16B1 PCLK prescalar setting
SN_SYS1->APBCP0_b.CT16B1PRE = 0x00; //PCLK = HCLK/1
//SN_SYS1->APBCP0_b.CT16B1PRE = 0x01; //PCLK = HCLK/2
//SN_SYS1->APBCP0_b.CT16B1PRE = 0x02; //PCLK = HCLK/4
//SN_SYS1->APBCP0_b.CT16B1PRE = 0x03; //PCLK = HCLK/8
//SN_SYS1->APBCP0_b.CT16B1PRE = 0x04; //PCLK = HCLK/16
}
/*****************************************************************************
* Function : CT16B1_NvicEnable
* Description : Enable CT16B1 timer interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void CT16B1_NvicEnable (void)
{
NVIC_ClearPendingIRQ(CT16B1_IRQn);
NVIC_EnableIRQ(CT16B1_IRQn);
//NVIC_SetPriority(CT16B1_IRQn,0); // Set interrupt priority (default)
}
/*****************************************************************************
* Function : CT16B1_NvicDisable
* Description : Enable CT16B1 timer interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void CT16B1_NvicDisable (void)
{
NVIC_DisableIRQ(CT16B1_IRQn);
}
/*****************************************************************************
* Function : CT16B1_IRQHandler
* Description : ISR of CT16B1 interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void CT16B1_IRQHandler(void)
{
uint32_t iwRisStatus;
iwRisStatus = SN_CT16B1->RIS; //Save the interrupt status.
//Before checking the status, always re-check the interrupt enable register first.
//In practice, user might use only one or two timer interrupt source.
//Ex: Enable only MR0IE and MR3IE ==> No check on MR1IE, MR2IE, and CAP0IE is necessary.
//User can add the directive pair of "#if 0" and "#endif" pair
//to COMMENT the un-used parts to reduce ISR overheads and ROM usage.
//Check the status in oder.
//MR0
if (SN_CT16B1->MCTRL_b.MR0IE) //Check if MR0 IE enables?
{
if(iwRisStatus & mskCT16_MR0IF)
{
iwCT16B1_IrqEvent |= mskCT16_MR0IF;
SN_CT16B1->IC = mskCT16_MR0IC; //Clear MR0 match interrupt status
}
}
//MR1
if (SN_CT16B1->MCTRL_b.MR1IE) //Check if MR1 IE enables?
{
if(iwRisStatus & mskCT16_MR1IF)
{
iwCT16B1_IrqEvent |= mskCT16_MR1IF;
SN_CT16B1->IC = mskCT16_MR1IC; //Clear MR1 match interrupt status
}
}
//MR2
if (SN_CT16B1->MCTRL_b.MR2IE) //Check if MR2 IE enables?
{
if(iwRisStatus & mskCT16_MR2IF)
{
iwCT16B1_IrqEvent |= mskCT16_MR2IF;
SN_CT16B1->IC = mskCT16_MR2IC; //Clear MR2 match interrupt status
}
}
//MR3
if (SN_CT16B1->MCTRL_b.MR3IE) //Check if MR3 IE enables?
{
if(iwRisStatus & mskCT16_MR3IF)
{
iwCT16B1_IrqEvent |= mskCT16_MR3IF;
SN_CT16B1->IC = mskCT16_MR3IC; //Clear MR3 match interrupt status
}
}
//CAP0
if (SN_CT16B1->CAPCTRL_b.CAP0IE) //Check if CAP0 IE enables?
{
if(iwRisStatus & mskCT16_CAP0IF) //CAP0
{
iwCT16B1_IrqEvent |= mskCT16_CAP0IF;
SN_CT16B1->IC = mskCT16_CAP0IC; //Clear CAP0 interrupt status
}
}
}

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#ifndef __SN32F240_CT16B1_H
#define __SN32F240_CT16B1_H
/*_____ I N C L U D E S ____________________________________________________*/
#include <stdint.h>
#include <SN32F200_Def.h>
/*_____ D E F I N I T I O N S ______________________________________________*/
#define CT16B1_IRQ INTERRUPT_METHOD //INTERRUPT_METHOD: Enable CT16B1 timer and interrupt
//POLLING_METHOD: Enable CT16B1 timer ONLY
/*_____ M A C R O S ________________________________________________________*/
// Enable CT16B1 PCLK
#define __CT16B1_ENABLE SN_SYS1->AHBCLKEN_b.CT16B1CLKEN = ENABLE
// Disable CT16B1 PCLK
#define __CT16B1_DISABLE SN_SYS1->AHBCLKEN_b.CT16B1CLKEN = DISABLE
/*_____ D E C L A R A T I O N S ____________________________________________*/
extern volatile uint32_t iwCT16B1_IrqEvent; //The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS
extern void CT16B1_Init(void);
extern void CT16B1_NvicEnable(void);
extern void CT16B1_NvicDisable(void);
extern void CT16B1_IRQHandler(void);
#endif /*__SN32F240_CT16B1_H*/

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/******************** (C) COPYRIGHT 2013 SONiX *******************************
* COMPANY: SONiX
* DATE: 2013/12
* AUTHOR: SA1
* IC: SN32F240/230/220
* DESCRIPTION: CT16B2 related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2013/12/17 SA1 First release
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240.h>
#include "CT16.h"
#include "CT16B2.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
volatile uint32_t iwCT16B2_IrqEvent = 0x00; //The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS
void CT16B2_Init (void);
void CT16B2_NvicEnable (void);
void CT16B2_NvicDisable (void);
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
/*****************************************************************************
* Function : CT16B2_Init
* Description : Initialization of CT16B2 timer
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void CT16B2_Init (void)
{
//Enable P_CLOCK for CT16B2.
__CT16B2_ENABLE;
//CT16B2 PCLK prescalar setting
SN_SYS1->APBCP1_b.CT16B2PRE = 0x00; //PCLK = HCLK/1
//SN_SYS1->APBCP1_b.CT16B2PRE = 0x01; //PCLK = HCLK/2
//SN_SYS1->APBCP1_b.CT16B2PRE = 0x02; //PCLK = HCLK/4
//SN_SYS1->APBCP1_b.CT16B2PRE = 0x03; //PCLK = HCLK/8
//SN_SYS1->APBCP1_b.CT16B2PRE = 0x04; //PCLK = HCLK/16
}
/*****************************************************************************
* Function : CT16B2_NvicEnable
* Description : Enable CT16B2 timer interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void CT16B2_NvicEnable (void)
{
NVIC_ClearPendingIRQ(CT16B2_IRQn);
NVIC_EnableIRQ(CT16B2_IRQn);
NVIC_SetPriority(CT16B2_IRQn,0); // Set interrupt priority (default)
}
/*****************************************************************************
* Function : CT16B2_NvicDisable
* Description : Disable CT16B2 timer interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void CT16B2_NvicDisable (void)
{
NVIC_DisableIRQ(CT16B2_IRQn);
}
/*****************************************************************************
* Function : CT16B2_IRQHandler
* Description : ISR of CT16B2 interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void CT16B2_IRQHandler(void)
{
uint32_t iwRisStatus;
iwRisStatus = SN_CT16B2->RIS; // Save the interrupt status.
//Before checking the status, always re-check the interrupt enable register first.
//In practice, user might use only one or two timer interrupt source.
//Ex: Enable only MR0IE and MR3IE ==> No check on MR1IE, MR2IE, and CAP0IE is necessary.
//User can add the directive pair of "#if 0" and "#endif" pair
//to COMMENT the un-used parts to reduce ISR overheads and ROM usage.
//Check the status in oder.
//MR0
if (SN_CT16B2->MCTRL_b.MR0IE) //Check if MR0 IE enables?
{
if(iwRisStatus & mskCT16_MR0IF)
{
iwCT16B2_IrqEvent |= mskCT16_MR0IF;
SN_CT16B2->IC = mskCT16_MR0IC; //Clear MR0 match interrupt status
}
}
//MR1
if (SN_CT16B2->MCTRL_b.MR1IE) //Check if MR1 IE enables?
{
if(iwRisStatus & mskCT16_MR1IF)
{
iwCT16B2_IrqEvent |= mskCT16_MR1IF;
SN_CT16B2->IC = mskCT16_MR1IC; //Clear MR1 match interrupt status
}
}
//MR2
if (SN_CT16B2->MCTRL_b.MR2IE) //Check if MR2 IE enables?
{
if(iwRisStatus & mskCT16_MR2IF)
{
iwCT16B2_IrqEvent |= mskCT16_MR2IF;
SN_CT16B2->IC = mskCT16_MR2IC; //Clear MR2 match interrupt status
}
}
//MR3
if (SN_CT16B2->MCTRL_b.MR3IE) //Check if MR3 IE enables?
{
if(iwRisStatus & mskCT16_MR3IF)
{
iwCT16B2_IrqEvent |= mskCT16_MR3IF;
SN_CT16B2->IC = mskCT16_MR3IC; //Clear MR3 match interrupt status
}
}
//CAP0
if (SN_CT16B2->CAPCTRL_b.CAP0IE) //Check if CAP0 IE enables?
{
if(iwRisStatus & mskCT16_CAP0IF) //CAP0
{
iwCT16B2_IrqEvent |= mskCT16_CAP0IF;
SN_CT16B2->IC = mskCT16_CAP0IC; //Clear CAP0 interrupt status
}
}
}

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#ifndef __SN32F240_CT16B2_H
#define __SN32F240_CT16B2_H
/*_____ I N C L U D E S ____________________________________________________*/
#include <stdint.h>
#include <SN32F200_Def.h>
/*_____ D E F I N I T I O N S ______________________________________________*/
#define CT16B2_IRQ INTERRUPT_METHOD //INTERRUPT_METHOD: Enable CT16B2 timer and interrupt
//POLLING_METHOD: Enable CT16B2 timer ONLY
/*_____ M A C R O S ________________________________________________________*/
// Enable CT16B2 PCLK
#define __CT16B2_ENABLE SN_SYS1->AHBCLKEN_b.CT16B2CLKEN = ENABLE
// Disable CT16B1 PCLK
#define __CT16B2_DISABLE SN_SYS1->AHBCLKEN_b.CT16B2CLKEN = DISABLE
/*_____ D E C L A R A T I O N S ____________________________________________*/
extern volatile uint32_t iwCT16B2_IrqEvent; //The bitmask usage of iwCT16Bn_IrqEvent is the same with CT16Bn_RIS
extern void CT16B2_Init(void);
extern void CT16B2_NvicEnable(void);
extern void CT16B2_NvicDisable(void);
extern void CT16B2_IRQHandler(void);
#endif /*__SN32F240_CT16B2_H*/

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#ifndef __SN32F240_CT32_H
#define __SN32F240_CT32_H
/*_____ I N C L U D E S ____________________________________________________*/
/*_____ D E F I N I T I O N S ______________________________________________*/
/*
Base Address: 0x4000 6000 (CT32B0)
0x4000 8000 (CT32B1)
0x4000 A000 (CT32B2)
*/
/* CT32Bn Timer Control register <CT32Bn_TMRCTRL> (0x00) */
#define CT32_CEN_DIS 0 //[0:0] CT32Bn enable bit
#define CT32_CEN_EN 1
#define mskCT32_CEN_DIS (CT32_CEN_DIS<<0)
#define mskCT32_CEN_EN (CT32_CEN_EN<<0)
#define CT32_CRST 1 //[1:1] CT32Bn counter reset bit
#define mskCT32_CRST (CT32_CRST<<1)
//[6:4] CT32Bn counting mode selection
#define CT32_CM_EDGE_UP 0 //Edge-aligned Up-counting mode
#define CT32_CM_EDGE_DOWN 1 //Edge-aligned Down-counting mode
#define CT32_CM_CENTER_UP 2 //Center-aligned mode 1. Match interrupt is set during up-counting period
#define CT32_CM_CENTER_DOWN 4 //Center-aligned mode 2. Match interrupt is set during down-counting period
#define CT32_CM_CENTER_BOTH 6 //Center-aligned mode 3. Match interrupt is set during both up and down period.
#define mskCT32_CM_EDGE_UP (CT32_CM_EDGE_UP<<4)
#define mskCT32_CM_EDGE_DOWN (CT32_CM_EDGE_DOWN<<4)
#define mskCT32_CM_CENTER_UP (CT32_CM_CENTER_UP<<4)
#define mskCT32_CM_CENTER_DOWN (CT32_CM_CENTER_DOWN<<4)
#define mskCT32_CM_CENTER_BOTH (CT32_CM_CENTER_BOTH<<4)
/* CT32Bn Count Control register <CT32Bn_CNTCTRL> (0x10) */
//[1:0] Count/Timer Mode selection.
#define CT32_CTM_TIMER 0 //Timer mode: Every rising PCLK edge.
#define CT32_CTM_CNTER_RISING 1 //Counter mode: TC increments on rising edge of CAP input.
#define CT32_CTM_CNTER_FALLING 2 //Counter mode: TC increments on falling edge of CAP input.
#define CT32_CTM_CNTER_BOTH 3 //Counter mode: TC increments on both edge of CAP input.
#define mskCT32_CTM_TIMER (CT32_CTM_TIMER<<0)
#define mskCT32_CTM_CNTER_RISING (CT32_CTM_CNTER_RISING<<0)
#define mskCT32_CTM_CNTER_FALLING (CT32_CTM_CNTER_FALLING<<0)
#define mskCT32_CTM_CNTER_BOTH (CT32_CTM_CNTER_BOTH<<0)
#define CT32_CIS 0 //[3:2] Count Input Select
#define mskCT32_CIS (CT32_CIS<<2)
/* CT32Bn Match Control register <CT32Bn_MCTRL> (0x14) */
#define CT32_MR0IE_EN 1 //[0:0] Enable MR0 match interrupt
#define CT32_MR0IE_DIS 0
#define mskCT32_MR0IE_EN (CT32_MR0IE_EN<<0)
#define mskCT32_MR0IE_DIS (CT32_MR0IE_DIS<<0)
#define CT32_MR0RST_EN 1 //[1:1] Enable reset TC when MR0 matches TC.
#define CT32_MR0RST_DIS 0
#define mskCT32_MR0RST_EN (CT32_MR0RST_EN<<1)
#define mskCT32_MR0RST_DIS (CT32_MR0RST_DIS<<1)
#define CT32_MR0STOP_EN 1 //[2:2] Enable stop TC and clear CEN when MR0 matches TC.
#define CT32_MR0STOP_DIS 0
#define mskCT32_MR0STOP_EN (CT32_MR0STOP_EN<<2)
#define mskCT32_MR0STOP_DIS (CT32_MR0STOP_DIS<<2)
#define CT32_MR1IE_EN 1 //[3:3] Enable MR1 match interrupt
#define CT32_MR1IE_DIS 0
#define mskCT32_MR1IE_EN (CT32_MR1IE_EN<<3)
#define mskCT32_MR1IE_DIS (CT32_MR1IE_DIS<<3)
#define CT32_MR1RST_EN 1 //[4:4] Enable reset TC when MR1 matches TC.
#define CT32_MR1RST_DIS 0
#define mskCT32_MR1RST_EN (CT32_MR1RST_EN<<4)
#define mskCT32_MR1RST_DIS (CT32_MR1RST_DIS<<4)
#define CT32_MR1STOP_EN 1 //[5:5] Enable stop TC and clear CEN when MR1 matches TC.
#define CT32_MR1STOP_DIS 0
#define mskCT32_MR1STOP_EN (CT32_MR1STOP_EN<<5)
#define mskCT32_MR1STOP_DIS (CT32_MR1STOP_DIS<<5)
#define CT32_MR2IE_EN 1 //[6:6] Enable MR2 match interrupt
#define CT32_MR2IE_DIS 0
#define mskCT32_MR2IE_EN (CT32_MR2IE_EN<<6)
#define mskCT32_MR2IE_DIS (CT32_MR2IE_DIS<<6)
#define CT32_MR2RST_EN 1 //[7:7] Enable reset TC when MR2 matches TC.
#define CT32_MR2RST_DIS 0
#define mskCT32_MR2RST_EN (CT32_MR2RST_EN<<7)
#define mskCT32_MR2RST_DIS (CT32_MR2RST_DIS<<7)
#define CT32_MR2STOP_EN 1 //[8:8] Enable stop TC and clear CEN when MR2 matches TC.
#define CT32_MR2STOP_DIS 0
#define mskCT32_MR2STOP_EN (CT32_MR2STOP_EN<<8)
#define mskCT32_MR2STOP_DIS (CT32_MR2STOP_DIS<<8)
#define CT32_MR3IE_EN 1 //[9:9] Enable MR3 match interrupt
#define CT32_MR3IE_DIS 0
#define mskCT32_MR3IE_EN (CT32_MR3IE_EN<<9)
#define mskCT32_MR3IE_DIS (CT32_MR3IE_DIS<<9)
#define CT32_MR3RST_EN 1 //[10:10] Enable reset TC when MR3 matches TC.
#define CT32_MR3RST_DIS 0
#define mskCT32_MR3RST_EN (CT32_MR3RST_EN<<10)
#define mskCT32_MR3RST_DIS (CT32_MR3RST_DIS<<10)
#define CT32_MR3STOP_EN 1 //[11:11] Enable stop TC and clear CEN when MR3 matches TC.
#define CT32_MR3STOP_DIS 0
#define mskCT32_MR3STOP_EN (CT32_MR3STOP_EN<<11)
#define mskCT32_MR3STOP_DIS (CT32_MR3STOP_DIS<<11)
/* CT32Bn Capture Control register <CT32Bn_CAPCTRL> (0x28) */
#define CT32_CAP0RE_EN 1 //[0:0] Enable CAP0 capture on rising edge.
#define CT32_CAP0RE_DIS 0
#define mskCT32_CAP0RE_EN (CT32_CAP0RE_EN<<0)
#define mskCT32_CAP0RE_DIS (CT32_CAP0RE_DIS<<0)
#define CT32_CAP0FE_EN 1 //[1:1] Enable CAP0 capture on fallng edge.
#define CT32_CAP0FE_DIS 0
#define mskCT32_CAP0FE_EN (CT32_CAP0FE_EN<<1)
#define mskCT32_CAP0FE_DIS (CT32_CAP0FE_DIS<<1)
#define CT32_CAP0IE_EN 1 //[2:2] Enable CAP0 interrupt.
#define CT32_CAP0IE_DIS 0
#define mskCT32_CAP0IE_EN (CT32_CAP0IE_EN<<2)
#define mskCT32_CAP0IE_DIS (CT32_CAP0IE_DIS<<2)
#define CT32_CAP0EN_EN 1 //[3:3] Enable CAP0 function.
#define CT32_CAP0EN_DIS 0
#define mskCT32_CAP0EN_EN (CT32_CAP0EN_EN<<3)
#define mskCT32_CAP0EN_DIS (CT32_CAP0EN_DIS<<3)
/* CT32Bn External Match register <CT32Bn_EM> (0x30) */
#define CT32_EM0 1 //[0:0] CT32Bn PWM0 drive state
#define mskCT32_EM0 (CT32_EM0<<0)
#define CT32_EM1 1 //[1:1] CT32Bn PWM1 drive state
#define mskCT32_EM1 (CT32_EM1<<1)
#define CT32_EM2 1 //[2:2] CT32Bn PWM2 drive state
#define mskCT32_EM2 (CT32_EM2<<2)
#define CT32_EM3 1 //[3:3] CT32Bn PWM3 drive state
#define mskCT32_EM3 (CT32_EM3<<3)
//[5:4] CT32Bn PWM0 functionality
#define CT32_EMC0_DO_NOTHING 0 //Do nothing.
#define CT32_EMC0_LOW 1 //CT32Bn PWM0 pin is low.
#define CT32_EMC0_HIGH 2 //CT32Bn PWM0 pin is high.
#define CT32_EMC0_TOGGLE 3 //Toggle CT32Bn PWM0 pin.
#define mskCT32_EMC0_DO_NOTHING (CT32_EMC0_LOW<<4)
#define mskCT32_EMC0_LOW (CT32_EMC0_LOW<<4)
#define mskCT32_EMC0_HIGH (CT32_EMC0_HIGH<<4)
#define mskCT32_EMC0_TOGGLE (CT32_EMC0_TOGGLE<<4)
//[7:6] CT32Bn PWM1 functionality
#define CT32_EMC1_DO_NOTHING 0 //Do nothing.
#define CT32_EMC1_LOW 1 //CT32Bn PWM1 pin is low.
#define CT32_EMC1_HIGH 2 //CT32Bn PWM1 pin is high.
#define CT32_EMC1_TOGGLE 3 //Toggle CT32Bn PWM1 pin.
#define mskCT32_EMC1_DO_NOTHING (CT32_EMC1_LOW<<6)
#define mskCT32_EMC1_LOW (CT32_EMC1_LOW<<6)
#define mskCT32_EMC1_HIGH (CT32_EMC1_HIGH<<6)
#define mskCT32_EMC1_TOGGLE (CT32_EMC1_TOGGLE<<6)
//[9:8] CT32Bn PWM2 functionality
#define CT32_EMC2_DO_NOTHING 0 //Do nothing.
#define CT32_EMC2_LOW 1 //CT32Bn PWM2 pin is low.
#define CT32_EMC2_HIGH 2 //CT32Bn PWM2 pin is high.
#define CT32_EMC2_TOGGLE 3 //Toggle CT32Bn PWM2 pin.
#define mskCT32_EMC2_DO_NOTHING (CT32_EMC2_LOW<<8)
#define mskCT32_EMC2_LOW (CT32_EMC2_LOW<<8)
#define mskCT32_EMC2_HIGH (CT32_EMC2_HIGH<<8)
#define mskCT32_EMC2_TOGGLE (CT32_EMC2_TOGGLE<<8)
//[11:10] CT32Bn PWM3 functionality
#define CT32_EMC3_DO_NOTHING 0 //Do nothing.
#define CT32_EMC3_LOW 1 //CT32Bn PWM3 pin is low.
#define CT32_EMC3_HIGH 2 //CT32Bn PWM3 pin is high.
#define CT32_EMC3_TOGGLE 3 //Toggle CT32Bn PWM3 pin.
#define mskCT32_EMC3_DO_NOTHING (CT32_EMC2_LOW<<10)
#define mskCT32_EMC3_LOW (CT32_EMC2_LOW<<10)
#define mskCT32_EMC3_HIGH (CT32_EMC2_HIGH<<10)
#define mskCT32_EMC3_TOGGLE (CT32_EMC2_TOGGLE<<10)
/* CT32Bn PWM Control register <CT32Bn_PWMCTRL> (0x34) */
//[0:0] CT32Bn PWM0 enable.
#define CT32_PWM0EN_EN 1 // CT32Bn PWM0 is enabled for PWM mode.
#define CT32_PWM0EN_EM0 0 // CT32Bn PWM0 is controlled by EM0.
#define mskCT32_PWM0EN_EN (CT32_PWM0EN_EN<<0)
#define mskCT32_PWM0EN_EM0 (CT32_PWM0EN_EM0<<0)
//[1:1] CT32Bn PWM1 enable.
#define CT32_PWM1EN_EN 1 // CT32Bn PWM1 is enabled for PWM mode.
#define CT32_PWM1EN_EM1 0 // CT32Bn PWM1 is controlled by EM1.
#define mskCT32_PWM1EN_EN (CT32_PWM1EN_EN<<1)
#define mskCT32_PWM1EN_EM1 (CT32_PWM1EN_EM1<<1)
//[2:2] CT32Bn PWM2 enable.
#define CT32_PWM2EN_EN 1 // CT32Bn PWM2 is enabled for PWM mode.
#define CT32_PWM2EN_EM2 0 // CT32Bn PWM2 is controlled by EM2.
#define mskCT32_PWM2EN_EN (CT32_PWM2EN_EN<<2)
#define mskCT32_PWM2EN_EM2 (CT32_PWM2EN_EM2<<2)
//[3:3] CT32Bn PWM3 enable.
#define CT32_PWM3EN_EN 1 // CT32Bn PWM3 is enabled for PWM mode.
#define CT32_PWM3EN_EM3 0 // CT32Bn PWM3 is controlled by EM3.
#define mskCT32_PWM3EN_EN (CT32_PWM3EN_EN<<3)
#define mskCT32_PWM3EN_EM3 (CT32_PWM3EN_EM3<<3)
//[5:4] CT32Bn PWM0 output mode.
#define CT32_PWM0MODE_1 0 // PWM mode 1.
#define CT32_PWM0MODE_2 1 // PWM mode 2.
#define CT32_PWM0MODE_FORCE_0 2 // Force 0.
#define CT32_PWM0MODE_FORCE_1 3 // Force 1.
#define mskCT32_PWM0MODE_1 (CT32_PWM0MODE_1<<4)
#define mskCT32_PWM0MODE_2 (CT32_PWM0MODE_2<<4)
#define mskCT32_PWM0MODE_FORCE_0 (CT32_PWM0MODE_FORCE_0<<4)
#define mskCT32_PWM0MODE_FORCE_1 (CT32_PWM0MODE_FORCE_1<<4)
//[7:6] CT32Bn PWM1 output mode.
#define CT32_PWM1MODE_1 0 // PWM mode 1.
#define CT32_PWM1MODE_2 1 // PWM mode 2.
#define CT32_PWM1MODE_FORCE_0 2 // Force 0.
#define CT32_PWM1MODE_FORCE_1 3 // Force 1.
#define mskCT32_PWM1MODE_1 (CT32_PWM1MODE_1<<6)
#define mskCT32_PWM1MODE_2 (CT32_PWM1MODE_2<<6)
#define mskCT32_PWM1MODE_FORCE_0 (CT32_PWM1MODE_FORCE_0<<6)
#define mskCT32_PWM1MODE_FORCE_1 (CT32_PWM1MODE_FORCE_1<<6)
//[9:8] CT32Bn PWM2 output mode.
#define CT32_PWM2MODE_1 0 // PWM mode 1.
#define CT32_PWM2MODE_2 1 // PWM mode 2.
#define CT32_PWM2MODE_FORCE_0 2 // Force 0.
#define CT32_PWM2MODE_FORCE_1 3 // Force 1.
#define mskCT32_PWM2MODE_1 (CT32_PWM2MODE_1<<8)
#define mskCT32_PWM2MODE_2 (CT32_PWM2MODE_2<<8)
#define mskCT32_PWM2MODE_FORCE_0 (CT32_PWM2MODE_FORCE_0<<8)
#define mskCT32_PWM2MODE_FORCE_1 (CT32_PWM2MODE_FORCE_1<<8)
//[20:20] CT32Bn PWM0 IO selection.
#define CT32_PWM0IOEN_EN 1 // PWM 0 pin acts as match output.
#define CT32_PWM0IOEN_DIS 0 // PWM 0 pin acts as GPIO.
#define mskCT32_PWM0IOEN_EN (CT32_PWM0IOEN_EN<<20)
#define mskCT32_PWM0IOEN_DIS (CT32_PWM0IOEN_DIS<<20)
//[21:21] CT32Bn PWM1 IO selection.
#define CT32_PWM1IOEN_EN 1 // PWM 1 pin acts as match output.
#define CT32_PWM1IOEN_DIS 0 // PWM 1 pin acts as GPIO.
#define mskCT32_PWM1IOEN_EN (CT32_PWM1IOEN_EN<<21)
#define mskCT32_PWM1IOEN_DIS (CT32_PWM1IOEN_DIS<<21)
//[22:22] CT32Bn PWM2 IO selection.
#define CT32_PWM2IOEN_EN 1 // PWM 2 pin acts as match output.
#define CT32_PWM2IOEN_DIS 0 // PWM 2 pin acts as GPIO.
#define mskCT32_PWM2IOEN_EN (CT32_PWM2IOEN_EN<<22)
#define mskCT32_PWM2IOEN_DIS (CT32_PWM2IOEN_DIS<<22)
//[23:23] CT32Bn PWM3 IO selection.
#define CT32_PWM3IOEN_EN 1 // PWM 3 pin acts as match output.
#define CT32_PWM3IOEN_DIS 0 // PWM 3 pin acts as GPIO.
#define mskCT32_PWM3IOEN_EN (CT32_PWM3IOEN_EN<<23)
#define mskCT32_PWM3IOEN_DIS (CT32_PWM3IOEN_DIS<<23)
/* CT32Bn Timer Raw Interrupt Status register <CT32Bn_RIS> (0x38) */
/* CT32Bn Timer Interrupt Clear register <CT32Bn_IC> (0x3C) */
/* The bitmask usage of iwCT32Bn_IrqEvent is the same with CT32Bn_RIS*/
#define mskCT32_MR0IF (0x1<<0) //[0:0] Interrupt flag for match channel 0
#define mskCT32_MR0IC mskCT32_MR0IF
#define mskCT32_MR1IF (0x1<<1) //[1:1] Interrupt flag for match channel 1
#define mskCT32_MR1IC mskCT32_MR1IF
#define mskCT32_MR2IF (0x1<<2) //[2:2] Interrupt flag for match channel 2
#define mskCT32_MR2IC mskCT32_MR2IF
#define mskCT32_MR3IF (0x1<<3) //[3:3] Interrupt flag for match channel 3
#define mskCT32_MR3IC mskCT32_MR3IF
#define mskCT32_CAP0IF (0x1<<4) //[4:4] Interrupt flag for capture channel 0
#define mskCT32_CAP0IC mskCT32_CAP0IF
/*_____ M A C R O S ________________________________________________________*/
/*_____ D E C L A R A T I O N S ____________________________________________*/
#endif /*__SN32F240_CT32_H*/

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/******************** (C) COPYRIGHT 2013 SONiX *******************************
* COMPANY: SONiX
* DATE: 2013/12
* AUTHOR: SA1
* IC: SN32F240/230/220
* DESCRIPTION: CT32B0 related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2013/12/17 SA1 First release
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240.h>
#include "CT32.h"
#include "CT32B0.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
volatile uint32_t iwCT32B0_IrqEvent = 0x00; //The bitmask usage of iwCT32Bn_IrqEvent is the same with CT32Bn_RIS
void CT32B0_Init (void);
void CT32B0_NvicEnable (void);
void CT32B0_NvicDisable (void);
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
/*****************************************************************************
* Function : CT32B0_Init
* Description : Initialization of CT32B0 timer
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void CT32B0_Init (void)
{
//Enable P_CLOCK for CT32B0.
__CT32B0_ENABLE;
//CT32B0 PCLK prescalar setting
SN_SYS1->APBCP0_b.CT32B0PRE = 0x00; //PCLK = HCLK/1
//SN_SYS1->APBCP0_b.CT32B0PRE = 0x01; //PCLK = HCLK/2
//SN_SYS1->APBCP0_b.CT32B0PRE = 0x02; //PCLK = HCLK/4
//SN_SYS1->APBCP0_b.CT32B0PRE = 0x03; //PCLK = HCLK/8
//SN_SYS1->APBCP0_b.CT32B0PRE = 0x04; //PCLK = HCLK/16
}
/*****************************************************************************
* Function : CT32B0_NvicEnable
* Description : Enable CT32B0 timer interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void CT32B0_NvicEnable (void)
{
NVIC_ClearPendingIRQ(CT32B0_IRQn);
NVIC_EnableIRQ(CT32B0_IRQn);
//NVIC_SetPriority(CT32B0_IRQn,0); //Set interrupt priority (default)
}
/*****************************************************************************
* Function : CT32B0_NvicDisable
* Description : Disable CT32B0 timer interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void CT32B0_NvicDisable (void)
{
NVIC_DisableIRQ(CT32B0_IRQn);
}
/*****************************************************************************
* Function : TIMER32_0_IRQHandler
* Description : ISR of CT32B0 interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void CT32B0_IRQHandler(void)
{
uint32_t iwRisStatus;
iwRisStatus = SN_CT32B0->RIS; // Save the interrupt status.
//Before checking the status, always re-check the interrupt enable register first.
//In practice, user might use only one or two timer interrupt source.
//Ex: Enable only MR0IE and MR3IE ==> No check on MR1IE, MR2IE, and CAP0IE is necessary.
//User can add the directive pair of "#if 0" and "#endif" pair
//to COMMENT the un-used parts to reduce ISR overheads and ROM usage.
//Check the status in oder.
//MR0
if (SN_CT32B0->MCTRL_b.MR0IE) //Check if MR0 IE enables?
{
if(iwRisStatus & mskCT32_MR0IF)
{
iwCT32B0_IrqEvent |= mskCT32_MR0IF;
SN_CT32B0->IC = mskCT32_MR0IC; //Clear MR0 match interrupt status
}
}
//MR1
if (SN_CT32B0->MCTRL_b.MR1IE) //Check if MR1 IE enables?
{
if(iwRisStatus & mskCT32_MR1IF)
{
iwCT32B0_IrqEvent |= mskCT32_MR1IF;
SN_CT32B0->IC = mskCT32_MR1IC; //Clear MR1 match interrupt status
}
}
//MR2
if (SN_CT32B0->MCTRL_b.MR2IE) //Check if MR2 IE enables?
{
if(iwRisStatus & mskCT32_MR2IF)
{
iwCT32B0_IrqEvent |= mskCT32_MR2IF;
SN_CT32B0->IC = mskCT32_MR2IC; //Clear MR2 match interrupt status
}
}
//MR3
if (SN_CT32B0->MCTRL_b.MR3IE) //Check if MR3 IE enables?
{
if(iwRisStatus & mskCT32_MR3IF)
{
iwCT32B0_IrqEvent |= mskCT32_MR3IF;
SN_CT32B0->IC = mskCT32_MR3IC; //Clear MR3 match interrupt status
}
}
//CAP0
if (SN_CT32B0->CAPCTRL_b.CAP0IE) //Check if CAP0 IE enables?
{
if(iwRisStatus & mskCT32_CAP0IF) //CAP0
{
iwCT32B0_IrqEvent |= mskCT32_CAP0IF;
SN_CT32B0->IC = mskCT32_CAP0IC; //Clear CAP0 interrupt status
}
}
}

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#ifndef __SN32F240_CT32B0_H
#define __SN32F240_CT32B0_H
/*_____ I N C L U D E S ____________________________________________________*/
#include <stdint.h>
#include <SN32F200_Def.h>
/*_____ D E F I N I T I O N S ______________________________________________*/
#define CT32B0_IRQ INTERRUPT_METHOD //INTERRUPT_METHOD: Enable CT32B0 timer and interrupt
//POLLING_METHOD: Enable CT32B0 timer ONLY
/*_____ M A C R O S ________________________________________________________*/
// Enable CT32B0 PCLK
#define __CT32B0_ENABLE SN_SYS1->AHBCLKEN_b.CT32B0CLKEN = ENABLE
// Disable CT32B0 PCLK
#define __CT32B0_DISABLE SN_SYS1->AHBCLKEN_b.CT32B0CLKEN = DISABLE
/*_____ D E C L A R A T I O N S ____________________________________________*/
extern volatile uint32_t iwCT32B0_IrqEvent; //The bitmask usage of iwCT32Bn_IrqEvent is the same with CT32Bn_RIS
extern void CT32B0_Init(void);
extern void CT32B0_NvicEnable(void);
extern void CT32B0_NvicDisable(void);
extern void CT32B0_IRQHandler(void);
#endif /*__SN32F240_CT32B0_H*/

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/******************** (C) COPYRIGHT 2013 SONiX *******************************
* COMPANY: SONiX
* DATE: 2013/12
* AUTHOR: SA1
* IC: SN32F240/230/220
* DESCRIPTION: CT32B1 related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2013/12/17 SA1 First release
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240.h>
#include "CT32.h"
#include "CT32B1.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
volatile uint32_t iwCT32B1_IrqEvent = 0x00; //The bitmask usage of iwCT32Bn_IrqEvent is the same with CT32Bn_RIS
void CT32B1_Init (void);
void CT32B1_NvicEnable (void);
void CT32B1_NvicDisable (void);
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
/*****************************************************************************
* Function : CT32B1_Init
* Description : Initialization of CT32B1 timer
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void CT32B1_Init (void)
{
//Enable P_CLOCK for CT32B1.
__CT32B1_ENABLE;
//CT32B1 PCLK prescalar setting
SN_SYS1->APBCP0_b.CT32B1PRE = 0x00; //PCLK = HCLK/1
//SN_SYS1->APBCP0_b.CT32B1PRE = 0x01; //PCLK = HCLK/2
//SN_SYS1->APBCP0_b.CT32B1PRE = 0x02; //PCLK = HCLK/4
//SN_SYS1->APBCP0_b.CT32B1PRE = 0x03; //PCLK = HCLK/8
//SN_SYS1->APBCP0_b.CT32B1PRE = 0x04; //PCLK = HCLK/16
}
/*****************************************************************************
* Function : CT32B1_NvicEnable
* Description : Enable CT32B1 timer interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void CT32B1_NvicEnable (void)
{
NVIC_ClearPendingIRQ(CT32B1_IRQn);
NVIC_EnableIRQ(CT32B1_IRQn);
//NVIC_SetPriority(CT32B1_IRQn,0); //Set interrupt priority (default)
}
/*****************************************************************************
* Function : CT32B1_NvicDisable
* Description : Disable CT32B1 timer interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void CT32B1_NvicDisable (void)
{
NVIC_DisableIRQ(CT32B1_IRQn);
}
/*****************************************************************************
* Function : TIMER32_0_IRQHandler
* Description : ISR of CT32B1 interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void CT32B1_IRQHandler(void)
{
uint32_t iwRisStatus;
iwRisStatus = SN_CT32B1->RIS; // Save the interrupt status.
//Before checking the status, always re-check the interrupt enable register first.
//In practice, user might use only one or two timer interrupt source.
//Ex: Enable only MR0IE and MR3IE ==> No check on MR1IE, MR2IE, and CAP0IE is necessary.
//User can add the directive pair of "#if 0" and "#endif" pair
//to COMMENT the un-used parts to reduce ISR overheads and ROM usage.
//Check the status in oder.
//MR0
if (SN_CT32B1->MCTRL_b.MR0IE) //Check if MR0 IE enables?
{
if(iwRisStatus & mskCT32_MR0IF)
{
iwCT32B1_IrqEvent |= mskCT32_MR0IF;
SN_CT32B1->IC = mskCT32_MR0IC; //Clear MR0 match interrupt status
}
}
//MR1
if (SN_CT32B1->MCTRL_b.MR1IE) //Check if MR1 IE enables?
{
if(iwRisStatus & mskCT32_MR1IF)
{
iwCT32B1_IrqEvent |= mskCT32_MR1IF;
SN_CT32B1->IC = mskCT32_MR1IC; //Clear MR1 match interrupt status
}
}
//MR2
if (SN_CT32B1->MCTRL_b.MR2IE) //Check if MR2 IE enables?
{
if(iwRisStatus & mskCT32_MR2IF)
{
iwCT32B1_IrqEvent |= mskCT32_MR2IF;
SN_CT32B1->IC = mskCT32_MR2IC; //Clear MR2 match interrupt status
}
}
//MR3
if (SN_CT32B1->MCTRL_b.MR3IE) //Check if MR3 IE enables?
{
if(iwRisStatus & mskCT32_MR3IF)
{
iwCT32B1_IrqEvent |= mskCT32_MR3IF;
SN_CT32B1->IC = mskCT32_MR3IC; //Clear MR3 match interrupt status
}
}
//CAP0
if (SN_CT32B1->CAPCTRL_b.CAP0IE) //Check if CAP0 IE enables?
{
if(iwRisStatus & mskCT32_CAP0IF) //CAP0
{
iwCT32B1_IrqEvent |= mskCT32_CAP0IF;
SN_CT32B1->IC = mskCT32_CAP0IC; //Clear CAP0 interrupt status
}
}
}

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#ifndef __SN32F240_CT32B1_H
#define __SN32F240_CT32B1_H
/*_____ I N C L U D E S ____________________________________________________*/
#include <stdint.h>
#include <SN32F200_Def.h>
/*_____ D E F I N I T I O N S ______________________________________________*/
#define CT32B1_IRQ INTERRUPT_METHOD //INTERRUPT_METHOD: Enable CT32B1 timer and interrupt
//POLLING_METHOD: Enable CT32B1 timer ONLY
/*_____ M A C R O S ________________________________________________________*/
// Enable CT32B1 PCLK
#define __CT32B1_ENABLE SN_SYS1->AHBCLKEN_b.CT32B1CLKEN = ENABLE
// Disable CT32B1 PCLK
#define __CT32B1_DISABLE SN_SYS1->AHBCLKEN_b.CT32B1CLKEN = DISABLE
/*_____ D E C L A R A T I O N S ____________________________________________*/
extern volatile uint32_t iwCT32B1_IrqEvent; //The bitmask usage of iwCT32Bn_IrqEvent is the same with CT32Bn_RIS
extern void CT32B1_Init(void);
extern void CT32B1_NvicEnable(void);
extern void CT32B1_NvicDisable(void);
extern void CT32B1_IRQHandler(void);
#endif /*__SN32F240_CT32B1_H*/

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os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B2.c Normal file
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/******************** (C) COPYRIGHT 2013 SONiX *******************************
* COMPANY: SONiX
* DATE: 2013/12
* AUTHOR: SA1
* IC: SN32F240/230/220
* DESCRIPTION: CT32B2 related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2013/12/17 SA1 First release
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240.h>
#include "CT32.h"
#include "CT32B2.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
volatile uint32_t iwCT32B2_IrqEvent = 0x00; //The bitmask usage of iwCT32Bn_IrqEvent is the same with CT32Bn_RIS
void CT32B2_Init (void);
void CT32B2_NvicEnable (void);
void CT32B2_NvicDisable (void);
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
/*****************************************************************************
* Function : CT32B2_Init
* Description : Initialization of CT32B2 timer
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void CT32B2_Init (void)
{
//Enable P_CLOCK for CT32B2.
__CT32B2_ENABLE;
//CT32B2 PCLK prescalar setting
SN_SYS1->APBCP0_b.CT32B2PRE = 0x00; //PCLK = HCLK/1
//SN_SYS1->APBCP0_b.CT32B2PRE = 0x01; //PCLK = HCLK/2
//SN_SYS1->APBCP0_b.CT32B2PRE = 0x02; //PCLK = HCLK/4
//SN_SYS1->APBCP0_b.CT32B2PRE = 0x03; //PCLK = HCLK/8
//SN_SYS1->APBCP0_b.CT32B2PRE = 0x04; //PCLK = HCLK/16
}
/*****************************************************************************
* Function : CT32B2_NvicEnable
* Description : Enable CT32B2 timer interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void CT32B2_NvicEnable (void)
{
NVIC_ClearPendingIRQ(CT32B2_IRQn);
NVIC_EnableIRQ(CT32B2_IRQn);
//NVIC_SetPriority(CT32B2_IRQn,0); //Set interrupt priority (default)
}
/*****************************************************************************
* Function : CT32B2_NvicDisable
* Description : Disable CT32B2 timer interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void CT32B2_NvicDisable (void)
{
NVIC_DisableIRQ(CT32B2_IRQn);
}
/*****************************************************************************
* Function : TIMER32_0_IRQHandler
* Description : ISR of CT32B2 interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void CT32B2_IRQHandler(void)
{
uint32_t iwRisStatus;
iwRisStatus = SN_CT32B2->RIS; // Save the interrupt status.
//Before checking the status, always re-check the interrupt enable register first.
//In practice, user might use only one or two timer interrupt source.
//Ex: Enable only MR0IE and MR3IE ==> No check on MR1IE, MR2IE, and CAP0IE is necessary.
//User can add the directive pair of "#if 0" and "#endif" pair
//to COMMENT the un-used parts to reduce ISR overheads and ROM usage.
//Check the status in oder.
//MR0
if (SN_CT32B2->MCTRL_b.MR0IE) //Check if MR0 IE enables?
{
if(iwRisStatus & mskCT32_MR0IF)
{
iwCT32B2_IrqEvent |= mskCT32_MR0IF;
SN_CT32B2->IC = mskCT32_MR0IC; //Clear MR0 match interrupt status
}
}
//MR1
if (SN_CT32B2->MCTRL_b.MR1IE) //Check if MR1 IE enables?
{
if(iwRisStatus & mskCT32_MR1IF)
{
iwCT32B2_IrqEvent |= mskCT32_MR1IF;
SN_CT32B2->IC = mskCT32_MR1IC; //Clear MR1 match interrupt status
}
}
//MR2
if (SN_CT32B2->MCTRL_b.MR2IE) //Check if MR2 IE enables?
{
if(iwRisStatus & mskCT32_MR2IF)
{
iwCT32B2_IrqEvent |= mskCT32_MR2IF;
SN_CT32B2->IC = mskCT32_MR2IC; //Clear MR2 match interrupt status
}
}
//MR3
if (SN_CT32B2->MCTRL_b.MR3IE) //Check if MR3 IE enables?
{
if(iwRisStatus & mskCT32_MR3IF)
{
iwCT32B2_IrqEvent |= mskCT32_MR3IF;
SN_CT32B2->IC = mskCT32_MR3IC; //Clear MR3 match interrupt status
}
}
//CAP0
if (SN_CT32B2->CAPCTRL_b.CAP0IE) //Check if CAP0 IE enables?
{
if(iwRisStatus & mskCT32_CAP0IF) //CAP0
{
iwCT32B2_IrqEvent |= mskCT32_CAP0IF;
SN_CT32B2->IC = mskCT32_CAP0IC; //Clear CAP0 interrupt status
}
}
}

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os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B2.h Normal file
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#ifndef __SN32F240_CT32B2_H
#define __SN32F240_CT32B2_H
/*_____ I N C L U D E S ____________________________________________________*/
#include <stdint.h>
#include <SN32F200_Def.h>
/*_____ D E F I N I T I O N S ______________________________________________*/
#define CT32B2_IRQ INTERRUPT_METHOD //INTERRUPT_METHOD: Enable CT32B2 timer and interrupt
//POLLING_METHOD: Enable CT32B2 timer ONLY
/*_____ M A C R O S ________________________________________________________*/
// Enable CT32B2 PCLK
#define __CT32B2_ENABLE SN_SYS1->AHBCLKEN_b.CT32B2CLKEN = ENABLE
// Disable CT32B2 PCLK
#define __CT32B2_DISABLE SN_SYS1->AHBCLKEN_b.CT32B2CLKEN = DISABLE
/*_____ D E C L A R A T I O N S ____________________________________________*/
extern volatile uint32_t iwCT32B2_IrqEvent; //The bitmask usage of iwCT32Bn_IrqEvent is the same with CT32Bn_RIS
extern void CT32B2_Init(void);
extern void CT32B2_NvicEnable(void);
extern void CT32B2_NvicDisable(void);
extern void CT32B2_IRQHandler(void);
#endif /*__SN32F240_CT32B2_H*/

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os/hal/ports/SN32/LLD/SN32F24x/CT/driver.mk Normal file
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ifeq ($(USE_SMART_BUILD),yes)
ifneq ($(findstring HAL_USE_CT TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/CT/hal_st_lld.c
endif
else
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/CT/hal_st_lld.c
endif
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B0.c
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B1.c
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/CT/CT16B2.c
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B0.c
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B1.c
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/CT/CT32B2.c
PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/CT

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os/hal/ports/SN32/LLD/SN32F24x/CT/hal_st_lld.c Normal file
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/*
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file hal_st_lld.c
* @brief PLATFORM ST subsystem low level driver source.
*
* @addtogroup ST
* @{
*/
#include "hal.h"
#include "CT16.h"
#include "CT16B0.h"
#include "CT16B1.h"
#include "CT16B2.h"
#include "CT32.h"
#include "CT32B0.h"
#include "CT32B1.h"
#include "CT32B2.h"
#include "SN32F240.h"
#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
#define IHRC_CLOCK 12000000
#define ILRC_CLOCK 32000
#define ELS_XTAL_CLOCK 32768
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
OSAL_IRQ_HANDLER(SysTick_Handler) {
OSAL_IRQ_PROLOGUE();
osalSysLockFromISR();
osalOsTimerHandlerI();
osalSysUnlockFromISR();
OSAL_IRQ_EPILOGUE();
}
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Low level ST driver initialization.
*
* @notapi
*/
void st_lld_init(void) {
/* Periodic systick mode, the Cortex-Mx internal systick timer is used
in this mode.*/
SysTick->LOAD = ((IHRC_CLOCK >> SN_SYS0->AHBCP) / OSAL_ST_FREQUENCY) - 1;
SysTick->VAL = 0;
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk |
SysTick_CTRL_TICKINT_Msk;
/* IRQ enabled.*/
nvicSetSystemHandlerPriority(HANDLER_SYSTICK, 8);
}
#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */
/** @} */

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os/hal/ports/SN32/LLD/SN32F24x/CT/hal_st_lld.h Normal file
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/*
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file hal_st_lld.h
* @brief PLATFORM ST subsystem low level driver header.
* @details This header is designed to be include-able without having to
* include other files from the HAL.
*
* @addtogroup ST
* @{
*/
#ifndef HAL_ST_LLD_H
#define HAL_ST_LLD_H
#include "CT16B0.h"
#include "CT16B1.h"
#include "CT16B2.h"
#include "CT32B0.h"
#include "CT32B1.h"
#include "CT32B2.h"
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
#ifdef __cplusplus
extern "C" {
#endif
void st_lld_init(void);
#ifdef __cplusplus
}
#endif
/*===========================================================================*/
/* Driver inline functions. */
/*===========================================================================*/
/**
* @brief Returns the time counter value.
*
* @return The counter value.
*
* @notapi
*/
static inline systime_t st_lld_get_counter(void) {
return (systime_t)0;
}
/**
* @brief Starts the alarm.
* @note Makes sure that no spurious alarms are triggered after
* this call.
*
* @param[in] abstime the time to be set for the first alarm
*
* @notapi
*/
static inline void st_lld_start_alarm(systime_t abstime) {
(void)abstime;
}
/**
* @brief Stops the alarm interrupt.
*
* @notapi
*/
static inline void st_lld_stop_alarm(void) {
}
/**
* @brief Sets the alarm time.
*
* @param[in] abstime the time to be set for the next alarm
*
* @notapi
*/
static inline void st_lld_set_alarm(systime_t abstime) {
(void)abstime;
}
/**
* @brief Returns the current alarm time.
*
* @return The currently set alarm time.
*
* @notapi
*/
static inline systime_t st_lld_get_alarm(void) {
return (systime_t)0;
}
/**
* @brief Determines if the alarm is active.
*
* @return The alarm status.
* @retval false if the alarm is not active.
* @retval true is the alarm is active
*
* @notapi
*/
static inline bool st_lld_is_alarm_active(void) {
return false;
}
#endif /* HAL_ST_LLD_H */
/** @} */

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os/hal/ports/SN32/LLD/SN32F24x/FLASH/Flash.c Normal file
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/******************** (C) COPYRIGHT 2013 SONiX *******************************
* COMPANY: SONiX
* DATE: 2013/12
* AUTHOR: SA1
* IC: SN32F240/230/220
* DESCRIPTION: Flash related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2013/12/17 SA1 First release
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include "Flash.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
uint32_t wFLASH_PGRAM[2];
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
/*****************************************************************************
* Function : FLASH_EraseSector
* Description : Erase assigned sector address in Flash ROM
* Input : adr - Sector start address
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void FLASH_EraseSector (uint32_t adr)
{
SN_FLASH->CTRL = FLASH_PER; // Page Erase Enabled
SN_FLASH->ADDR = adr; // Page Address
SN_FLASH->CTRL |= FLASH_STARTE; // Start Erase
while ((SN_FLASH->STATUS & FLASH_BUSY) == FLASH_BUSY);
}
/*****************************************************************************
* Function : Flash_ProgramPage
* Description : Program assigned page in Flash ROM
* Input : adr - Page start address (word-alignment) of Flash
* sz - Content size to be programmed (Bytes)
* pBuf - pointer to the Source data
* Output : None
* Return : OK or FAIL
* Note : None
*****************************************************************************/
uint32_t FLASH_ProgramPage (uint32_t adr, uint32_t sz, uint8_t *pBuf)
{
while (sz){
SN_FLASH->CTRL = FLASH_PG; // Programming Enabled
SN_FLASH->ADDR = adr;
SN_FLASH->DATA = *((uint32_t *)pBuf);
__nop();__nop();__nop();__nop();__nop();__nop(); //Must add to avoid Hard Fault!!!!!!
while ((SN_FLASH->STATUS & FLASH_BUSY) == FLASH_BUSY);
// Check for Errors
if ((SN_FLASH->STATUS & FLASH_PGERR) == FLASH_PGERR) {
SN_FLASH->STATUS &= ~FLASH_PGERR;
return (FAIL);
}
// Go to next Word
adr += 4;
pBuf += 4;
sz -= 4;
}
return (OK);
}

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#ifndef __SN32F240_FLASH_H
#define __SN32F240_FLASH_H
/*_____ I N C L U D E S ____________________________________________________*/
#include "SN32F240.h"
#include "SN32F200_Def.h"
/*_____ D E F I N I T I O N S ______________________________________________*/
//FLASH HW
#define FLASH_PAGE_SIZE 1024
#define FLASH_F240_MAX_ROM_SIZE 0xFFFF
#define FLASH_F230_MAX_ROM_SIZE 0x7FFF
#define FLASH_F220_MAX_ROM_SIZE 0x3FFF
// Flash Control Register definitions
#define FLASH_PG 0x00000001
#define FLASH_PER 0x00000002
#define FLASH_STARTE 0x00000040
// Flash Status Register definitions
#define FLASH_BUSY 0x00000001
#define FLASH_PGERR 0x00000004
/*_____ M A C R O S ________________________________________________________*/
//Flash Low Power Mode
#define __FLASH_LPM_DISABLE SN_FLASH->LPCTRL = 0x5AFA0000
#define __FLASH_LPM_SLOW_MODE SN_FLASH->LPCTRL = 0x5AFA0002
//Flash Status
#define __FLASH_CLEAR_ERROR_STATUS SN_FLASH->STATUS &= ~FLASH_PGERR
/*_____ D E C L A R A T I O N S ____________________________________________*/
extern uint32_t wFLASH_PGRAM[2];
void FLASH_EraseSector (uint32_t);
uint32_t FLASH_ProgramPage (uint32_t, uint32_t, uint8_t *);
#endif /* __SN32F240_FLASH_H */

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os/hal/ports/SN32/LLD/SN32F24x/GPIO/GPIO.c Normal file
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/******************** (C) COPYRIGHT 2014 SONiX *******************************
* COMPANY: SONiX
* DATE: 2014/02
* AUTHOR: SA1
* IC: SN32F240/230/220
* DESCRIPTION: GPIO related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2013/12/17 SA1 1. First release
* 1.1 2014/02/27 SA1 1. Fix error in GPIO_Interrupt.
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include "GPIO.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
/*****************************************************************************
* Function : GPIO_Init
* Description : GPIO Init
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void GPIO_Init (void)
{
//P2.0 as Input Pull-down
GPIO_Mode (GPIO_PORT2, GPIO_PIN0, GPIO_MODE_INPUT);
GPIO_Config (GPIO_PORT2, GPIO_PIN0, GPIO_CFG_PULL_DOWN);
//P2.0 as rising edge
GPIO_P2Trigger(GPIO_PIN0, GPIO_IS_EDGE, GPIO_IBS_EDGE_TRIGGER, GPIO_IEV_RISING_EDGE);
GPIO_Interrupt(GPIO_PORT2, GPIO_PIN0, GPIO_IE_EN);
//P2.1 as Input Pull-up
GPIO_Mode (GPIO_PORT2, GPIO_PIN1, GPIO_MODE_INPUT);
GPIO_Config (GPIO_PORT2, GPIO_PIN1, GPIO_CFG_PULL_UP);
//P2.1 as falling edge
GPIO_P2Trigger(GPIO_PIN1, GPIO_IS_EDGE, GPIO_IBS_EDGE_TRIGGER, GPIO_IEV_FALLING_EDGE);
GPIO_Interrupt(GPIO_PORT2, GPIO_PIN1, GPIO_IE_EN);
//P2.2 as Input Repeater-mode
GPIO_Mode (GPIO_PORT2, GPIO_PIN2, GPIO_MODE_INPUT);
GPIO_Config (GPIO_PORT2, GPIO_PIN2, GPIO_CFG_REPEATER_MODE);
//P2.2 as both edge
GPIO_P2Trigger(GPIO_PIN2, GPIO_IS_EDGE, GPIO_IBS_BOTH_EDGE_TRIGGER, GPIO_IEV_RISING_EDGE);
GPIO_Interrupt(GPIO_PORT2, GPIO_PIN2, GPIO_IE_EN);
//P2.3 as Input Pull-down
GPIO_Mode (GPIO_PORT2, GPIO_PIN3, GPIO_MODE_INPUT);
GPIO_Config (GPIO_PORT2, GPIO_PIN3, GPIO_CFG_PULL_DOWN);
//P2.3 as high level
GPIO_P2Trigger(GPIO_PIN3, GPIO_IS_EVENT, GPIO_IBS_EDGE_TRIGGER, GPIO_IEV_RISING_EDGE);
GPIO_Interrupt(GPIO_PORT2, GPIO_PIN3, GPIO_IE_EN);
//P2.4 as Input Pullup
GPIO_Mode (GPIO_PORT2, GPIO_PIN4, GPIO_MODE_INPUT);
GPIO_Config (GPIO_PORT2, GPIO_PIN4, GPIO_CFG_PULL_UP);
//P2.4 as low level trigger
GPIO_P2Trigger(GPIO_PIN4, GPIO_IS_EVENT, GPIO_IBS_EDGE_TRIGGER, GPIO_IEV_FALLING_EDGE);
GPIO_Interrupt(GPIO_PORT2, GPIO_PIN4, GPIO_IE_EN);
//P2.5 as Output Low
GPIO_Mode (GPIO_PORT2, GPIO_PIN5, GPIO_MODE_OUTPUT);
GPIO_Clr (GPIO_PORT2, GPIO_PIN5);
}
/*****************************************************************************
* Function : GPIO_Mode
* Description : set GPIO as input or output
* Input : port_number - GPIO0, GPIO1, GPIO2, GPIO3
pin_number - GPIO_PIN0, 1, 2, ...,15
mode - 0 as Input
1 as output
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void GPIO_Mode(uint32_t port_number, uint32_t pin_number, uint32_t mode)
{
uint32_t wGpiomode=0;
switch(port_number){
case 0:
wGpiomode=(uint32_t)SN_GPIO0->MODE;
wGpiomode&=~(1<<(uint32_t) pin_number);
wGpiomode|=(mode<<(uint32_t) pin_number);
SN_GPIO0->MODE=wGpiomode;
wGpiomode=SN_GPIO0->MODE; //for checlk
break;
case 1:
wGpiomode=(uint32_t)SN_GPIO1->MODE;
wGpiomode&=~(1<<(uint32_t) pin_number);
wGpiomode|=(mode<<(uint32_t) pin_number);
SN_GPIO1->MODE=wGpiomode;
wGpiomode=SN_GPIO1->MODE; //for checlk
break;
case 2:
wGpiomode=(uint32_t)SN_GPIO2->MODE;
wGpiomode&=~(1<<(uint32_t) pin_number);
wGpiomode|=(mode<<(uint32_t) pin_number);
SN_GPIO2->MODE=wGpiomode;
wGpiomode=SN_GPIO2->MODE; //for checlk
break;
case 3:
wGpiomode=(uint32_t)SN_GPIO3->MODE;
wGpiomode&=~(1<<(uint32_t) pin_number);
wGpiomode|=(mode<<(uint32_t) pin_number);
SN_GPIO3->MODE=wGpiomode;
wGpiomode=SN_GPIO3->MODE; //for checlk
break;
default:
break;
}
return;
}
/*****************************************************************************
* Function : GPIO_Set
* Description : set GPIO high
* Input : port_number - GPIO0, GPIO1, GPIO2, GPIO3
pin_number - GPIO_PIN0, 1, 2, ...,15
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void GPIO_Set(uint32_t port_number, uint32_t pin_number)
{
switch(port_number){
case 0:
SN_GPIO0->BSET|=(1<<pin_number);
break;
case 1:
SN_GPIO1->BSET|=(1<<pin_number);
break;
case 2:
SN_GPIO2->BSET|=(1<<pin_number);
break;
case 3:
SN_GPIO3->BSET|=(1<<pin_number);
break;
default:
break;
}
return;
}
/*****************************************************************************
* Function : GPIO_Clr
* Description : set GPIO low
* Input : port_number - GPIO0, GPIO1, GPIO2, GPIO3
pin_number - GPIO_PIN0, 1, 2, ...,15
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void GPIO_Clr(uint32_t port_number, uint32_t pin_number)
{
switch(port_number){
case 0:
SN_GPIO0->BCLR|=(1<<pin_number);
break;
case 1:
SN_GPIO1->BCLR|=(1<<pin_number);
break;
case 2:
SN_GPIO2->BCLR|=(1<<pin_number);
break;
case 3:
SN_GPIO3->BCLR|=(1<<pin_number);
break;
default:
break;
}
return;
}
/*****************************************************************************
* Function : GPIO_P0Trigger
* Description : set GPIO as edge or level trigger
* Input : port_number - GPIO0, GPIO1, GPIO2, GPIO3
pin_number - GPIO_PIN0, 1, 2, ...,15
is - 0: edge sensitive
1: event sensitive
ibs - 0: edge trigger
1: both edge trigger
iev - 0: Rising edges or HIGH level trigger
1: Falling edges or LOW level trigger
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void GPIO_P0Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev)
{
uint32_t wGpiovalue=0;
wGpiovalue=SN_GPIO0->IS;
wGpiovalue&=~(1<<pin_number);
wGpiovalue|=(is<<pin_number);
SN_GPIO0->IS=wGpiovalue;
wGpiovalue=SN_GPIO0->IBS;
wGpiovalue&=~(1<<pin_number);
wGpiovalue|=(ibs<<pin_number);
SN_GPIO0->IBS=wGpiovalue;
wGpiovalue=SN_GPIO0->IEV;
wGpiovalue&=~(1<<pin_number);
wGpiovalue|=(iev<<pin_number);
SN_GPIO0->IEV=wGpiovalue;
}
/*****************************************************************************
* Function : GPIO_P1Trigger
* Description : set GPIO as edge or level trigger
* Input : port_number - GPIO0, GPIO1, GPIO2, GPIO3
pin_number - GPIO_PIN0, 1, 2, ...,15
is - 0: edge sensitive
1: event sensitive
ibs - 0: edge trigger
1: both edge trigger
iev - 0: Rising edges or HIGH level trigger
1: Falling edges or LOW level trigger
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void GPIO_P1Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev)
{
uint32_t wGpiovalue=0;
wGpiovalue=SN_GPIO1->IS;
wGpiovalue&=~(1<<pin_number);
wGpiovalue|=(is<<pin_number);
SN_GPIO1->IS=wGpiovalue;
wGpiovalue=SN_GPIO1->IBS;
wGpiovalue&=~(1<<pin_number);
wGpiovalue|=(ibs<<pin_number);
SN_GPIO1->IBS=wGpiovalue;
wGpiovalue=SN_GPIO1->IEV;
wGpiovalue&=~(1<<pin_number);
wGpiovalue|=(iev<<pin_number);
SN_GPIO1->IEV=wGpiovalue;
}
/*****************************************************************************
* Function : GPIO_P2Trigger
* Description : set GPIO as edge or level trigger
* Input : port_number - GPIO0, GPIO1, GPIO2, GPIO3
pin_number - GPIO_PIN0, 1, 2, ...,15
is - 0: edge sensitive
1: event sensitive
ibs - 0: edge trigger
1: both edge trigger
iev - 0: Rising edges or HIGH level trigger
1: Falling edges or LOW level trigger
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void GPIO_P2Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev)
{
uint32_t wGpiovalue=0;
wGpiovalue=SN_GPIO2->IS;
wGpiovalue&=~(1<<pin_number);
wGpiovalue|=(is<<pin_number);
SN_GPIO2->IS=wGpiovalue;
wGpiovalue=SN_GPIO2->IBS;
wGpiovalue&=~(1<<pin_number);
wGpiovalue|=(ibs<<pin_number);
SN_GPIO2->IBS=wGpiovalue;
wGpiovalue=SN_GPIO2->IEV;
wGpiovalue&=~(1<<pin_number);
wGpiovalue|=(iev<<pin_number);
SN_GPIO2->IEV=wGpiovalue;
}
/*****************************************************************************
* Function : GPIO_P3Trigger
* Description : set GPIO as edge or level trigger
* Input : port_number - GPIO0, GPIO1, GPIO2, GPIO3
pin_number - GPIO_PIN0, 1, 2, ...,15
is - 0: edge sensitive
1: event sensitive
ibs - 0: edge trigger
1: both edge trigger
iev - 0: Rising edges or HIGH level trigger
1: Falling edges or LOW level trigger
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void GPIO_P3Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev)
{
uint32_t wGpiovalue=0;
wGpiovalue=SN_GPIO3->IS;
wGpiovalue&=~(1<<pin_number);
wGpiovalue|=(is<<pin_number);
SN_GPIO3->IS=wGpiovalue;
wGpiovalue=SN_GPIO3->IBS;
wGpiovalue&=~(1<<pin_number);
wGpiovalue|=(ibs<<pin_number);
SN_GPIO3->IBS=wGpiovalue;
wGpiovalue=SN_GPIO3->IEV;
wGpiovalue&=~(1<<pin_number);
wGpiovalue|=(iev<<pin_number);
SN_GPIO3->IEV=wGpiovalue;
}
/*****************************************************************************
* Function : GPIO_Interrupt
* Description : set GPIO interrupt and NVIC
* Input : port_number - GPIO0, GPIO1, GPIO2, GPIO3
pin_number - GPIO_PIN0, 1, 2, ...,15
enable - 0 as disable
1 as enable
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void GPIO_Interrupt(uint32_t port_number, uint32_t pin_number, uint32_t enable)
{
switch(port_number){
case 0:
//check SWD pin
if ((pin_number == GPIO_PIN8) || (pin_number == GPIO_PIN9)){
if(SN_SYS0->SWDCTRL!=0x1) return;
}
SN_GPIO0->IC=0xFFFF;
SN_GPIO0->IE&=~(1<<pin_number);
SN_GPIO0->IE|=(enable<<pin_number);
NVIC_ClearPendingIRQ(P0_IRQn);
NVIC_EnableIRQ(P0_IRQn);
break;
case 1:
SN_GPIO1->IE&=~(1<<pin_number);
SN_GPIO1->IE|=(enable<<pin_number);
SN_GPIO1->IC=0xFFFF;
NVIC_ClearPendingIRQ(P1_IRQn);
NVIC_EnableIRQ(P1_IRQn);
break;
case 2:
SN_GPIO2->IC=0xFFFF;
SN_GPIO2->IE&=~(1<<pin_number);
SN_GPIO2->IE|=(enable<<pin_number);
NVIC_ClearPendingIRQ(P2_IRQn);
NVIC_EnableIRQ(P2_IRQn);
break;
case 3:
//check external Reset pin
if (pin_number == GPIO_PIN10){
if(SN_SYS0->EXRSTCTRL!=1) return;
}
SN_GPIO3->IC=0xFFFF;
SN_GPIO3->IE&=~(1<<pin_number);
SN_GPIO3->IE|=(enable<<pin_number);
NVIC_ClearPendingIRQ(P3_IRQn);
NVIC_EnableIRQ(P3_IRQn);
break;
default:
break;
}
return;
}
/*****************************************************************************
* Function : GPIO_int_clr
* Description : set clear interrupt
* Input : port_number - GPIO0, GPIO1, GPIO2, GPIO3
pin_number - GPIO_PIN0, 1, 2, ...,15
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void GPIO_IntClr(uint32_t port_number, uint32_t pin_number)
{
switch(port_number){
case 0:
SN_GPIO0->IC=(1<<pin_number);
break;
case 1:
SN_GPIO1->IC=(1<<pin_number);
break;
case 2:
SN_GPIO2->IC=(1<<pin_number);
break;
case 3:
SN_GPIO3->IC=(1<<pin_number);
break;
default:
break;
}
}
/*****************************************************************************
* Function : GPIO_Config
* Description : set GPIO as pull-up, pull-down, inactive or repeater
* Input : port_number - GPIO0, GPIO1, GPIO2, GPIO3
pin_number - GPIO_PIN0, 1, 2, ...,15
value - 0: Pull-up enable
1: Pull-down enable
2: Inactive
3: Repeate mode
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void GPIO_Config(uint32_t port_number, uint32_t pin_number, uint32_t value)
{
uint32_t wTemp=0;
wTemp=pin_number*2;
switch(port_number){
case 0:
SN_GPIO0->CFG&=~(3<<wTemp);
SN_GPIO0->CFG|=(value<<wTemp);
break;
case 1:
SN_GPIO1->CFG&=~(3<<wTemp);
SN_GPIO1->CFG|=(value<<wTemp);
break;
case 2:
SN_GPIO2->CFG&=~(3<<wTemp);
SN_GPIO2->CFG|=(value<<wTemp);
break;
case 3:
SN_GPIO3->CFG&=~(3<<wTemp);
SN_GPIO3->CFG|=(value<<wTemp);
break;
default:
break;
}
return;
}
/*****************************************************************************
* Function : GPIO_OpenDrain
* Description : set Open drain
* Input : port_number - GPIO0, GPIO1, GPIO2, GPIO3
pin_number - GPIO_PIN0, 1, 2, ...,15
value - 0: disable
1: enable
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void GPIO_OpenDrain(uint32_t port_number, uint32_t pin_number, uint32_t value)
{
switch(port_number)
{
case 0:
SN_GPIO0->ODCTRL&=~(1<<pin_number);
SN_GPIO0->ODCTRL|=(value<<pin_number);
break;
case 1:
SN_GPIO1->ODCTRL=~(1<<pin_number);
SN_GPIO1->ODCTRL|=(value<<pin_number);
break;
case 2:
SN_GPIO2->ODCTRL=~(1<<pin_number);
SN_GPIO2->ODCTRL|=(value<<pin_number);
break;
case 3:
SN_GPIO3->ODCTRL=~(1<<pin_number);
SN_GPIO3->ODCTRL|=(value<<pin_number);
break;
default:
break;
}
}
/*****************************************************************************
* Function : GPIO_IntStatus
* Description : Check GPIO interrupt status
* Input : port_number - GPIO0, GPIO1, GPIO2, GPIO3
pin_number - GPIO_PIN0, 1, 2, ...,15
* Output : None
* Return : 0 or 1
* Note : None
*****************************************************************************/
uint32_t GPIO_IntStatus(uint32_t port_number, uint32_t pin_number)
{
uint32_t wreturn_value=0;
switch(port_number)
{
case 0:
wreturn_value=(SN_GPIO0->RIS >>pin_number);
break;
case 1:
wreturn_value=(SN_GPIO1->RIS >>pin_number);
break;
case 2:
wreturn_value=(SN_GPIO2->RIS >>pin_number);
break;
case 3:
wreturn_value=(SN_GPIO3->RIS >>pin_number);
break;
default:
break;
}
wreturn_value&=0x01;
return wreturn_value;
}
/*****************************************************************************
* Function : P0_IRQHandler
* Description : Set GPIO P0 IRQ
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
__irq void P0_IRQHandler(void)
{
if (GPIO_IntStatus(GPIO_PORT0,GPIO_PIN0)==1)
{
GPIO_IntClr(GPIO_PORT0,GPIO_PIN0);
}
else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN1)==1)
{
GPIO_IntClr(GPIO_PORT0,GPIO_PIN1);
}
else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN2)==1)
{
GPIO_IntClr(GPIO_PORT0,GPIO_PIN2);
}
else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN3)==1)
{
GPIO_IntClr(GPIO_PORT0,GPIO_PIN3);
}
else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN4)==1)
{
GPIO_IntClr(GPIO_PORT0,GPIO_PIN4);
}
else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN5)==1)
{
GPIO_IntClr(GPIO_PORT0,GPIO_PIN5);
}
else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN6)==1)
{
GPIO_IntClr(GPIO_PORT0,GPIO_PIN6);
}
else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN7)==1)
{
GPIO_IntClr(GPIO_PORT0,GPIO_PIN7);
}
else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN8)==1)
{
GPIO_IntClr(GPIO_PORT0,GPIO_PIN8);
}
else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN9)==1)
{
GPIO_IntClr(GPIO_PORT0,GPIO_PIN9);
}
else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN10)==1)
{
GPIO_IntClr(GPIO_PORT0,GPIO_PIN10);
}
else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN11)==1)
{
GPIO_IntClr(GPIO_PORT0,GPIO_PIN11);
}
else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN12)==1)
{
GPIO_IntClr(GPIO_PORT0,GPIO_PIN12);
}
else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN13)==1)
{
GPIO_IntClr(GPIO_PORT0,GPIO_PIN13);
}
else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN14)==1)
{
GPIO_IntClr(GPIO_PORT0,GPIO_PIN14);
}
else if(GPIO_IntStatus(GPIO_PORT0,GPIO_PIN15)==1)
{
GPIO_IntClr(GPIO_PORT0,GPIO_PIN15);
}
}
/*****************************************************************************
* Function : P1_IRQHandler
* Description : Set GPIO P1 IRQ
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
__irq void P1_IRQHandler(void)
{
if (GPIO_IntStatus(GPIO_PORT1,GPIO_PIN0)==1)
{
GPIO_IntClr(GPIO_PORT1,GPIO_PIN0);
}
else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN1)==1)
{
GPIO_IntClr(GPIO_PORT1,GPIO_PIN1);
}
else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN2)==1)
{
GPIO_IntClr(GPIO_PORT1,GPIO_PIN2);
}
else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN3)==1)
{
GPIO_IntClr(GPIO_PORT1,GPIO_PIN3);
}
else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN4)==1)
{
GPIO_IntClr(GPIO_PORT1,GPIO_PIN4);
}
else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN5)==1)
{
GPIO_IntClr(GPIO_PORT1,GPIO_PIN5);
}
else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN6)==1)
{
GPIO_IntClr(GPIO_PORT1,GPIO_PIN6);
}
else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN7)==1)
{
GPIO_IntClr(GPIO_PORT1,GPIO_PIN7);
}
else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN8)==1)
{
GPIO_IntClr(GPIO_PORT1,GPIO_PIN8);
}
else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN9)==1)
{
GPIO_IntClr(GPIO_PORT1,GPIO_PIN9);
}
else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN10)==1)
{
GPIO_IntClr(GPIO_PORT1,GPIO_PIN10);
}
else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN11)==1)
{
GPIO_IntClr(GPIO_PORT1,GPIO_PIN11);
}
else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN12)==1)
{
GPIO_IntClr(GPIO_PORT1,GPIO_PIN12);
}
else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN13)==1)
{
GPIO_IntClr(GPIO_PORT1,GPIO_PIN13);
}
else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN14)==1)
{
GPIO_IntClr(GPIO_PORT1,GPIO_PIN14);
}
else if(GPIO_IntStatus(GPIO_PORT1,GPIO_PIN15)==1)
{
GPIO_IntClr(GPIO_PORT1,GPIO_PIN15);
}
}
/*****************************************************************************
* Function : P2_IRQHandler
* Description : Set GPIO P2 IRQ
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
__irq void P2_IRQHandler(void)
{
if (GPIO_IntStatus(GPIO_PORT2,GPIO_PIN0)==1)
{
GPIO_IntClr(GPIO_PORT2,GPIO_PIN0);
}
else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN1)==1)
{
GPIO_IntClr(GPIO_PORT2,GPIO_PIN1);
}
else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN2)==1)
{
GPIO_IntClr(GPIO_PORT2,GPIO_PIN2);
}
else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN3)==1)
{
GPIO_IntClr(GPIO_PORT2,GPIO_PIN3);
}
else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN4)==1)
{
GPIO_IntClr(GPIO_PORT2,GPIO_PIN4);
}
else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN5)==1)
{
GPIO_IntClr(GPIO_PORT2,GPIO_PIN5);
}
else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN6)==1)
{
GPIO_IntClr(GPIO_PORT2,GPIO_PIN6);
}
else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN7)==1)
{
GPIO_IntClr(GPIO_PORT2,GPIO_PIN7);
}
else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN8)==1)
{
GPIO_IntClr(GPIO_PORT2,GPIO_PIN8);
}
else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN9)==1)
{
GPIO_IntClr(GPIO_PORT2,GPIO_PIN9);
}
else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN10)==1)
{
GPIO_IntClr(GPIO_PORT2,GPIO_PIN10);
}
else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN11)==1)
{
GPIO_IntClr(GPIO_PORT2,GPIO_PIN11);
}
else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN12)==1)
{
GPIO_IntClr(GPIO_PORT2,GPIO_PIN12);
}
else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN13)==1)
{
GPIO_IntClr(GPIO_PORT2,GPIO_PIN13);
}
else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN14)==1)
{
GPIO_IntClr(GPIO_PORT2,GPIO_PIN14);
}
else if(GPIO_IntStatus(GPIO_PORT2,GPIO_PIN15)==1)
{
GPIO_IntClr(GPIO_PORT2,GPIO_PIN15);
}
}
/*****************************************************************************
* Function : P3_IRQHandler
* Description : Set GPIO P3 IRQ
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
__irq void P3_IRQHandler(void)
{
if (GPIO_IntStatus(GPIO_PORT3,GPIO_PIN0)==1)
{
GPIO_IntClr(GPIO_PORT3,GPIO_PIN0);
}
else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN1)==1)
{
GPIO_IntClr(GPIO_PORT3,GPIO_PIN1);
}
else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN2)==1)
{
GPIO_IntClr(GPIO_PORT3,GPIO_PIN2);
}
else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN3)==1)
{
GPIO_IntClr(GPIO_PORT3,GPIO_PIN3);
}
else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN4)==1)
{
GPIO_IntClr(GPIO_PORT3,GPIO_PIN4);
}
else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN5)==1)
{
GPIO_IntClr(GPIO_PORT3,GPIO_PIN5);
}
else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN6)==1)
{
GPIO_IntClr(GPIO_PORT3,GPIO_PIN6);
}
else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN7)==1)
{
GPIO_IntClr(GPIO_PORT3,GPIO_PIN7);
}
else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN8)==1)
{
GPIO_IntClr(GPIO_PORT3,GPIO_PIN8);
}
else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN9)==1)
{
GPIO_IntClr(GPIO_PORT3,GPIO_PIN9);
}
else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN10)==1)
{
GPIO_IntClr(GPIO_PORT3,GPIO_PIN10);
}
else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN11)==1)
{
GPIO_IntClr(GPIO_PORT3,GPIO_PIN11);
}
else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN12)==1)
{
GPIO_IntClr(GPIO_PORT3,GPIO_PIN12);
}
else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN13)==1)
{
GPIO_IntClr(GPIO_PORT3,GPIO_PIN13);
}
else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN14)==1)
{
GPIO_IntClr(GPIO_PORT3,GPIO_PIN14);
}
else if(GPIO_IntStatus(GPIO_PORT3,GPIO_PIN15)==1)
{
GPIO_IntClr(GPIO_PORT3,GPIO_PIN15);
}
}

114
os/hal/ports/SN32/LLD/SN32F24x/GPIO/GPIO.h Normal file
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#ifndef __SN32F240_GPIO_H
#define __SN32F240_GPIO_H
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240.h>
/*_____ D E F I N I T I O N S ______________________________________________*/
/*
Base Address: 0x4004 4000 (GPIO 0)
0x4004 6000 (GPIO 1)
0x4004 8000 (GPIO 2)
0x4004 A000 (GPIO 3)
*/
/* GPIO Port n Data register <GPIOn_DATA> (0x00) */
/* GPIO Port n Mode register <GPIOn_MODE> (0x04) */
#define GPIO_MODE_INPUT 0
#define GPIO_MODE_OUTPUT 1
#define GPIO_CURRENT_10MA 0
#define GPIO_CURRENT_20MA 1
/* GPIO Port n Configuration register <GPIOn_CFG> (0x08) */
#define GPIO_CFG_PULL_UP 0
#define GPIO_CFG_PULL_DOWN 1
#define GPIO_CFG_PULL_INACTIVE 2
#define GPIO_CFG_REPEATER_MODE 3
/* GPIO Port n Interrupt Sense register <GPIOn_IS> (0x0C) */
#define GPIO_IS_EDGE 0
#define GPIO_IS_EVENT 1
/* GPIO Port n Interrupt Both-edge Sense registe <GPIOn_IBS> (0x10) */
#define GPIO_IBS_EDGE_TRIGGER 0
#define GPIO_IBS_BOTH_EDGE_TRIGGER 1
/* GPIO Port n Interrupt Event register <GPIOn_IEV> (0x14) */
#define GPIO_IEV_RISING_EDGE 0
#define GPIO_IEV_FALLING_EDGE 1
/* GPIO Port n Interrupt Enable register <GPIOn_IE> (0x18) */
#define GPIO_IE_DIS 0
#define GPIO_IE_EN 1
/* GPIO Port n Raw Interrupt Status register <GPIOn_RIS/GPIOn_IC> (0x1C/0x20) */
#define mskPIN0IF (0x1<<0)
#define mskPIN1IF (0x1<<1)
#define mskPIN2IF (0x1<<2)
#define mskPIN3IF (0x1<<3)
#define mskPIN4IF (0x1<<4)
#define mskPIN5IF (0x1<<5)
#define mskPIN6IF (0x1<<6)
#define mskPIN7IF (0x1<<7)
#define mskPIN8IF (0x1<<8)
#define mskPIN9IF (0x1<<9)
#define mskPIN10IF (0x1<<10)
#define mskPIN11IF (0x1<<11)
#define mskPIN12IF (0x1<<12)
#define mskPIN13IF (0x1<<13)
#define mskPIN14IF (0x1<<14)
#define mskPIN15IF (0x1<<15)
/* GPIO Port Name Define */
//GPIO name define
#define GPIO_PORT0 0
#define GPIO_PORT1 1
#define GPIO_PORT2 2
#define GPIO_PORT3 3
/* GPIO Pin Name Define */
#define GPIO_PIN0 0
#define GPIO_PIN1 1
#define GPIO_PIN2 2
#define GPIO_PIN3 3
#define GPIO_PIN4 4
#define GPIO_PIN5 5
#define GPIO_PIN6 6
#define GPIO_PIN7 7
#define GPIO_PIN8 8
#define GPIO_PIN9 9
#define GPIO_PIN10 10
#define GPIO_PIN11 11
#define GPIO_PIN12 12
#define GPIO_PIN13 13
#define GPIO_PIN14 14
#define GPIO_PIN15 15
/*_____ M A C R O S ________________________________________________________*/
/*_____ D E C L A R A T I O N S ____________________________________________*/
void GPIO_Init (void);
void GPIO_Mode(uint32_t port_number, uint32_t pin_number, uint32_t mode);
void GPIO_Set(uint32_t port_number, uint32_t pin_number);
void GPIO_Clr(uint32_t port_number, uint32_t pin_number);
void GPIO_P0Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev);
void GPIO_P1Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev);
void GPIO_P2Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev);
void GPIO_P3Trigger(uint32_t pin_number, uint32_t is, uint32_t ibs,uint32_t iev);
void GPIO_Interrupt(uint32_t port_number, uint32_t pin_number, uint32_t enable);
void GPIO_IntClr(uint32_t port_number, uint32_t pin_number);
void GPIO_Config(uint32_t port_number, uint32_t pin_number, uint32_t value);
void GPIO_OpenDrain(uint32_t port_number, uint32_t pin_number, uint32_t value);
uint32_t GPIO_IntStatus(uint32_t port_number, uint32_t pin_number);
#endif /*__SN32F240_GPIO_H*/

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os/hal/ports/SN32/LLD/SN32F24x/GPIO/driver.mk Normal file
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ifeq ($(USE_SMART_BUILD),yes)
ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/GPIO/hal_pal_lld.c
endif
else
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/GPIO/hal_pal_lld.c
endif
PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/GPIO

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/*
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file GPIOv3/hal_pal_lld.c
* @brief SN32 PAL low level driver code.
*
* @addtogroup PAL
* @{
*/
#include "hal.h"
#if HAL_USE_PAL || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
static void initgpio(SN_GPIO0_Type *gpiop, const sn32_gpio_setup_t *config) {
gpiop->DATA = config->data;
gpiop->MODE = config->mode;
gpiop->CFG = config->cfg;
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief SN32 I/O ports configuration.
* @details Ports A-D clocks enabled.
*
* @param[in] config the SN32 ports configuration
*
* @notapi
*/
void _pal_lld_init(const PALConfig *config) {
/*
* Initial GPIO setup.
*/
#if SN32_HAS_GPIOA
initgpio(GPIOA, &config->PAData);
#endif
#if SN32_HAS_GPIOB
initgpio(GPIOB, &config->PBData);
#endif
#if SN32_HAS_GPIOC
initgpio(GPIOC, &config->PCData);
#endif
#if SN32_HAS_GPIOD
initgpio(GPIOD, &config->PDData);
#endif
}
/**
* @brief Pad mode setup.
* @details This function programs a pad
* with the specified mode.
* @note @p PAL_MODE_UNCONNECTED is implemented as push pull at minimum
* speed.
*
* @param[in] port the port identifier
* @param[in] pad the pad number
* @param[in] mode the mode
*
* @notapi
*/
void _pal_lld_setpadmode(ioportid_t port,
uint32_t pad,
iomode_t mode) {
switch (mode)
{
case PAL_MODE_UNCONNECTED:
break;
case PAL_MODE_INPUT:
port->MODE &= ~(1 << pad);
break;
case PAL_MODE_INPUT_PULLUP:
port->MODE &= ~(1 << pad);
port->CFG &= ~(3 << (pad * 2));
// port->BSET = (1 << pad); // High 1
break;
case PAL_MODE_INPUT_PULLDOWN:
port->MODE &= ~(1 << pad);
port->CFG &= ~(3 << (pad * 2));
// port->BCLR = (1 << pad); // Low 0
break;
case PAL_MODE_INPUT_ANALOG:
port->MODE &= ~(1 << pad);
port->CFG &= ~(3 << (pad * 2));
break;
case PAL_MODE_OUTPUT_PUSHPULL:
port->MODE |= (1 << pad);
break;
case 7:
break;
default:
break;
}
}
#endif /* HAL_USE_PAL */
/** @} */

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/*
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file GPIOv3/hal_pal_lld.h
* @brief SN32 PAL low level driver header.
*
* @addtogroup PAL
* @{
*/
#ifndef HAL_PAL_LLD_H
#define HAL_PAL_LLD_H
#if HAL_USE_PAL || defined(__DOXYGEN__)
/*===========================================================================*/
/* Unsupported modes and specific modes */
/*===========================================================================*/
// /* Specifies palInit() without parameter, required until all platforms will
// be updated to the new style.*/
// // #define PAL_NEW_INIT
/* Discarded definitions from the ST headers, the PAL driver uses its own
definitions in order to have an unified handling for all devices.
Unfortunately the ST headers have no uniform definitions for the same
objects across the various sub-families.*/
#undef GPIOA
#undef GPIOB
#undef GPIOC
#undef GPIOD
/**
* @name GPIO ports definitions
* @{
*/
#define GPIOA ((SN_GPIO0_Type *)SN_GPIO0_BASE)// SN_GPIO0//
#define GPIOB ((SN_GPIO0_Type *)SN_GPIO1_BASE)// SN_GPIO1//
#define GPIOC ((SN_GPIO0_Type *)SN_GPIO2_BASE)// SN_GPIO2//
#define GPIOD ((SN_GPIO0_Type *)SN_GPIO3_BASE)// SN_GPIO3//
/** @} */
/*===========================================================================*/
/* I/O Ports Types and constants. */
/*===========================================================================*/
/**
* @name Port related definitions
* @{
*/
/**
* @brief Width, in bits, of an I/O port.
*/
#define PAL_IOPORTS_WIDTH 16
/**
* @brief Whole port mask.
* @details This macro specifies all the valid bits into a port.
*/
#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF)
/** @} */
// GPIO0 = 40044000
// pad = 5
// line = 40044005
/**
* @name Line handling macros
* @{
*/
/**
* @brief Forms a line identifier.
* @details A port/pad pair are encoded into an @p ioline_t type. The encoding
* of this type is platform-dependent.
* @note In this driver the pad number is encoded in the lower 4 bits of
* the GPIO address which are guaranteed to be zero.
*/
#define PAL_LINE(port, pad) \
((ioline_t)((uint32_t)(port)) | ((uint32_t)(pad)))
/**
* @brief Decodes a port identifier from a line identifier.
*/
#define PAL_PORT(line) \
((SN_GPIO0_Type *)(((uint32_t)(line)) & 0xFFFFFFF0U))
/**
* @brief Decodes a pad identifier from a line identifier.
*/
#define PAL_PAD(line) \
((uint32_t)((uint32_t)(line) & 0x0000000FU))
/**
* @brief Value identifying an invalid line.
*/
#define PAL_NOLINE 0U
/** @} */
/**
* @brief GPIO port setup info.
*/
typedef struct {
/** Initial value for DATA register.*/
uint32_t data;
/** Initial value for MODE register.*/
uint32_t mode;
/** Initial value for CFG register.*/
uint32_t cfg;
/** Initial value for IS register.*/
uint32_t is;
/** Initial value for IBS register.*/
uint32_t ibs;
/** Initial value for IEV register.*/
uint32_t iev;
/** Initial value for IE register.*/
uint32_t ie;
/** Initial value for RIS register.*/
uint32_t ris;
/** Initial value for IC register.*/
uint32_t ic;
/** Initial value for BSET register.*/
uint32_t bset;
/** Initial value for BCLR register.*/
uint32_t bclr;
} sn32_gpio_setup_t;
/**
* @brief SN32 GPIO static initializer.
* @details An instance of this structure must be passed to @p palInit() at
* system startup time in order to initialize the digital I/O
* subsystem. This represents only the initial setup, specific pads
* or whole ports can be reprogrammed at later time.
*/
typedef struct {
#if SN32_HAS_GPIOA || defined(__DOXYGEN__)
/** @brief Port A setup data.*/
sn32_gpio_setup_t PAData;
#endif
#if SN32_HAS_GPIOB || defined(__DOXYGEN__)
/** @brief Port B setup data.*/
sn32_gpio_setup_t PBData;
#endif
#if SN32_HAS_GPIOC || defined(__DOXYGEN__)
/** @brief Port C setup data.*/
sn32_gpio_setup_t PCData;
#endif
#if SN32_HAS_GPIOD || defined(__DOXYGEN__)
/** @brief Port D setup data.*/
sn32_gpio_setup_t PDData;
#endif
} PALConfig;
/**
* @brief Type of digital I/O port sized unsigned integer.
*/
typedef uint32_t ioportmask_t;
/**
* @brief Type of digital I/O modes.
*/
typedef uint32_t iomode_t;
/**
* @brief Type of an I/O line.
*/
typedef uint32_t ioline_t;
/**
* @brief Port Identifier.
* @details This type can be a scalar or some kind of pointer, do not make
* any assumption about it, use the provided macros when populating
* variables of this type.
*/
typedef SN_GPIO0_Type * ioportid_t;
/*===========================================================================*/
/* I/O Ports Identifiers. */
/* The low level driver wraps the definitions already present in the SN32 */
/* firmware library. */
/*===========================================================================*/
/**
* @brief GPIO port A identifier.
*/
#if SN32_HAS_GPIOA || defined(__DOXYGEN__)
#define IOPORT1 GPIOA
#endif
/**
* @brief GPIO port B identifier.
*/
#if SN32_HAS_GPIOB || defined(__DOXYGEN__)
#define IOPORT2 GPIOB
#endif
/**
* @brief GPIO port C identifier.
*/
#if SN32_HAS_GPIOC || defined(__DOXYGEN__)
#define IOPORT3 GPIOC
#endif
/**
* @brief GPIO port D identifier.
*/
#if SN32_HAS_GPIOD || defined(__DOXYGEN__)
#define IOPORT4 GPIOD
#endif
/*===========================================================================*/
/* Implementation, some of the following macros could be implemented as */
/* functions, if so please put them in pal_lld.c. */
/*===========================================================================*/
/**
* @brief Low level PAL subsystem initialization.
*
* @notapi
*/
#define pal_lld_init(config) _pal_lld_init(config)
/**
* @brief Reads the physical I/O port states.
*
* @param[in] port port identifier
* @return The port bits.
*
* @notapi
*/
#define pal_lld_readport(port) ((port)->DATA)
/**
* @brief Reads the output latch.
* @details The purpose of this function is to read back the latched output
* value.
*
* @param[in] port port identifier
* @return The latched logical states.
*
* @notapi
*/
// #define pal_lld_readlatch(port) ((port)->RIS)
/**
* @brief Writes a bits mask on a I/O port.
*
* @param[in] port port identifier
* @param[in] bits bits to be written on the specified port
*
* @notapi
*/
#define pal_lld_writeport(port, bits) ((port)->DATA = (uint16_t)(bits))
/**
* @brief Sets a bits mask on a I/O port.
* @note The @ref PAL provides a default software implementation of this
* functionality, implement this function if can optimize it by using
* special hardware functionalities or special coding.
*
* @param[in] port port identifier
* @param[in] bits bits to be ORed on the specified port
*
* @notapi
*/
#define pal_lld_setport(port, bits) ((port)->BSET = (uint16_t)(bits))
/**
* @brief Clears a bits mask on a I/O port.
* @note The @ref PAL provides a default software implementation of this
* functionality, implement this function if can optimize it by using
* special hardware functionalities or special coding.
*
* @param[in] port port identifier
* @param[in] bits bits to be cleared on the specified port
*
* @notapi
*/
#define pal_lld_clearport(port, bits) ((port)->BCLR = ~(uint16_t)(bits))
/**
* @brief Writes a group of bits.
* @details This function is implemented by writing the GPIO BSET register, the
* implementation has no side effects.
*
* @param[in] port port identifier
* @param[in] mask group mask
* @param[in] offset the group bit offset within the port
* @param[in] bits bits to be written. Values exceeding the group
* width are masked.
*
* @notapi
*/
#define pal_lld_writegroup(port, mask, offset, bits) { \
uint32_t w = ((~(uint32_t)(bits) & (uint32_t)(mask)) << (16U + (offset))) | \
((uint32_t)(bits) & (uint32_t)(mask)) << (offset); \
(port)->DATA = w; \
}
/**
* @brief Reads a logical state from an I/O pad.
* @note The @ref PAL provides a default software implementation of this
* functionality, implement this function if can optimize it by using
* special hardware functionalities or special coding.
*
* @param[in] port port identifier
* @param[in] pad pad number within the port
* @return The logical state.
* @retval PAL_LOW low logical state.
* @retval PAL_HIGH high logical state.
*
* @notapi
*/
#define pal_lld_readpad(port, pad) (((port)->DATA >> pad) & 1)
/**
* @brief Writes a logical state on an output pad.
* @note This function is not meant to be invoked directly by the
* application code.
* @note The @ref PAL provides a default software implementation of this
* functionality, implement this function if can optimize it by using
* special hardware functionalities or special coding.
*
* @param[in] port port identifier
* @param[in] pad pad number within the port
* @param[in] bit logical value, the value must be @p PAL_LOW or
* @p PAL_HIGH
*
* @notapi
*/
#define pal_lld_writepad(port, pad, bit) ((port)->DATA = (bit << pad))
/**
* @brief Sets a pad logical state to @p PAL_HIGH.
* @note The @ref PAL provides a default software implementation of this
* functionality, implement this function if can optimize it by using
* special hardware functionalities or special coding.
*
* @param[in] port port identifier
* @param[in] pad pad number within the port
*
* @notapi
*/
#define pal_lld_setpad(port, pad) ((port)->BSET = (0x1 << pad))
/**
* @brief Clears a pad logical state to @p PAL_LOW.
* @note The @ref PAL provides a default software implementation of this
* functionality, implement this function if can optimize it by using
* special hardware functionalities or special coding.
*
* @param[in] port port identifier
* @param[in] pad pad number within the port
*
* @notapi
*/
#define pal_lld_clearpad(port, pad) ((port)->BCLR = (0x1 << pad))
/**
* @brief Toggles a pad logical state.
* @note The @ref PAL provides a default software implementation of this
* functionality, implement this function if can optimize it by using
* special hardware functionalities or special coding.
*
* @param[in] port port identifier
* @param[in] pad pad number within the port
*
* @notapi
*/
// #define pal_lld_togglepad(port, pad)
/**
* @brief Pad mode setup.
* @details This function programs a pad with the specified mode.
* @note The @ref PAL provides a default software implementation of this
* functionality, implement this function if can optimize it by using
* special hardware functionalities or special coding.
* @note Programming an unknown or unsupported mode is silently ignored.
*
* @param[in] port port identifier
* @param[in] pad pad number within the port
* @param[in] mode pad mode
*
* @notapi
*/
// #define pal_lld_setpadmode(port, pad, mode) ((port)->MODE |= mode << pad)
#define pal_lld_setpadmode(port, pad, mode) \
_pal_lld_setpadmode(port, pad, mode)
#ifdef __cplusplus
extern "C" {
#endif
extern const PALConfig pal_default_config;
void _pal_lld_init(const PALConfig *config);
void _pal_lld_setpadmode(ioportid_t port,
uint32_t pad,
iomode_t mode);
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_PAL */
#endif /* HAL_PAL_LLD_H */
/** @} */

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ifeq ($(USE_SMART_BUILD),yes)
ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/SN32/LLD/SN32F24x/GPIOv3/hal_pal_lld.c
endif
else
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/SN32/LLD/SN32F24x/GPIOv3/hal_pal_lld.c
endif
PLATFORMINC += $(CHIBIOS)/os/hal/ports/SN32/LLD/SN32F24x/GPIOv3

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/*
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file GPIOv3/hal_pal_lld.c
* @brief SN32 PAL low level driver code.
*
* @addtogroup PAL
* @{
*/
#include "hal.h"
#if HAL_USE_PAL || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
#if defined(SN32F240B)
#define AHB2_EN_MASK SN32_GPIO_EN_MASK
#define AHB2_LPEN_MASK 0
#else
#error "missing or unsupported platform for GPIOv3 PAL driver"
#endif
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
static void initgpio(sn32_gpio_t *gpiop, const sn32_gpio_setup_t *config) {
gpiop->OTYPER = config->otyper;
gpiop->ASCR = config->ascr;
gpiop->OSPEEDR = config->ospeedr;
gpiop->PUPDR = config->pupdr;
gpiop->ODR = config->odr;
gpiop->AFRL = config->afrl;
gpiop->AFRH = config->afrh;
gpiop->MODER = config->moder;
gpiop->LOCKR = config->lockr;
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief SN32 I/O ports configuration.
* @details Ports A-D(E, F, G, H) clocks enabled.
*
* @param[in] config the SN32 ports configuration
*
* @notapi
*/
void _pal_lld_init(const PALConfig *config) {
/*
* Enables the GPIO related clocks.
*/
#if defined(SN32L4XX)
RCC->AHB2ENR |= AHB2_EN_MASK;
#endif
/*
* Initial GPIO setup.
*/
#if SN32_HAS_GPIOA
initgpio(GPIOA, &config->PAData);
#endif
#if SN32_HAS_GPIOB
initgpio(GPIOB, &config->PBData);
#endif
#if SN32_HAS_GPIOC
initgpio(GPIOC, &config->PCData);
#endif
#if SN32_HAS_GPIOD
initgpio(GPIOD, &config->PDData);
#endif
#if SN32_HAS_GPIOE
initgpio(GPIOE, &config->PEData);
#endif
}
/**
* @brief Pads mode setup.
* @details This function programs a pads group belonging to the same port
* with the specified mode.
* @note @p PAL_MODE_UNCONNECTED is implemented as push pull at minimum
* speed.
*
* @param[in] port the port identifier
* @param[in] mask the group mask
* @param[in] mode the mode
*
* @notapi
*/
void _pal_lld_setgroupmode(ioportid_t port,
ioportmask_t mask,
iomode_t mode) {
uint32_t moder = (mode & PAL_SN32_MODE_MASK) >> 0;
uint32_t otyper = (mode & PAL_SN32_OTYPE_MASK) >> 2;
uint32_t ospeedr = (mode & PAL_SN32_OSPEED_MASK) >> 3;
uint32_t pupdr = (mode & PAL_SN32_PUPDR_MASK) >> 5;
uint32_t altr = (mode & PAL_SN32_ALTERNATE_MASK) >> 7;
uint32_t ascr = (mode & PAL_SN32_ASCR_MASK) >> 11;
uint32_t lockr = (mode & PAL_SN32_LOCKR_MASK) >> 12;
uint32_t bit = 0;
while (true) {
if ((mask & 1) != 0) {
uint32_t altrmask, m1, m2, m4;
altrmask = altr << ((bit & 7) * 4);
m1 = 1 << bit;
m2 = 3 << (bit * 2);
m4 = 15 << ((bit & 7) * 4);
port->OTYPER = (port->OTYPER & ~m1) | otyper;
port->ASCR = (port->ASCR & ~m1) | ascr;
port->OSPEEDR = (port->OSPEEDR & ~m2) | ospeedr;
port->PUPDR = (port->PUPDR & ~m2) | pupdr;
if ((mode & PAL_SN32_MODE_MASK) == PAL_SN32_MODE_ALTERNATE) {
/* If going in alternate mode then the alternate number is set
before switching mode in order to avoid glitches.*/
if (bit < 8)
port->AFRL = (port->AFRL & ~m4) | altrmask;
else
port->AFRH = (port->AFRH & ~m4) | altrmask;
port->MODER = (port->MODER & ~m2) | moder;
}
else {
/* If going into a non-alternate mode then the mode is switched
before setting the alternate mode in order to avoid glitches.*/
port->MODER = (port->MODER & ~m2) | moder;
if (bit < 8)
port->AFRL = (port->AFRL & ~m4) | altrmask;
else
port->AFRH = (port->AFRH & ~m4) | altrmask;
}
port->LOCKR = (port->LOCKR & ~m1) | lockr;
}
mask >>= 1;
if (!mask)
return;
otyper <<= 1;
ospeedr <<= 2;
pupdr <<= 2;
moder <<= 2;
bit++;
}
}
#endif /* HAL_USE_PAL */
/** @} */

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/*
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file GPIOv3/hal_pal_lld.h
* @brief SN32 PAL low level driver header.
*
* @addtogroup PAL
* @{
*/
#ifndef HAL_PAL_LLD_H
#define HAL_PAL_LLD_H
#if HAL_USE_PAL || defined(__DOXYGEN__)
/*===========================================================================*/
/* Unsupported modes and specific modes */
/*===========================================================================*/
#undef PAL_MODE_RESET
#undef PAL_MODE_UNCONNECTED
#undef PAL_MODE_INPUT
#undef PAL_MODE_INPUT_PULLUP
#undef PAL_MODE_INPUT_PULLDOWN
#undef PAL_MODE_INPUT_ANALOG
#undef PAL_MODE_OUTPUT_PUSHPULL
#undef PAL_MODE_OUTPUT_OPENDRAIN
/**
* @name SN32-specific I/O mode flags
* @{
*/
#define PAL_SN32_MODE_MASK (3U << 0U)
#define PAL_SN32_MODE_INPUT (0U << 0U)
#define PAL_SN32_MODE_OUTPUT (1U << 0U)
#define PAL_SN32_MODE_ALTERNATE (2U << 0U)
#define PAL_SN32_MODE_ANALOG (3U << 0U)
#define PAL_SN32_OTYPE_MASK (1U << 2U)
#define PAL_SN32_OTYPE_PUSHPULL (0U << 2U)
#define PAL_SN32_OTYPE_OPENDRAIN (1U << 2U)
#define PAL_SN32_OSPEED_MASK (3U << 3U)
#define PAL_SN32_OSPEED_LOW (0U << 3U)
#define PAL_SN32_OSPEED_MEDIUM (1U << 3U)
#define PAL_SN32_OSPEED_FAST (2U << 3U)
#define PAL_SN32_OSPEED_HIGH (3U << 3U)
#define PAL_SN32_PUPDR_MASK (3U << 5U)
#define PAL_SN32_PUPDR_FLOATING (0U << 5U)
#define PAL_SN32_PUPDR_PULLUP (1U << 5U)
#define PAL_SN32_PUPDR_PULLDOWN (2U << 5U)
#define PAL_SN32_ALTERNATE_MASK (15U << 7U)
#define PAL_SN32_ALTERNATE(n) ((n) << 7U)
#define PAL_SN32_ASCR_MASK (1U << 11U)
#define PAL_SN32_ASCR_OFF (0U << 11U)
#define PAL_SN32_ASCR_ON (1U << 11U)
#define PAL_SN32_LOCKR_MASK (1U << 12U)
#define PAL_SN32_LOCKR_OFF (0U << 12U)
#define PAL_SN32_LOCKR_ON (1U << 12U)
/**
* @brief Alternate function.
*
* @param[in] n alternate function selector
*/
#define PAL_MODE_ALTERNATE(n) (PAL_SN32_MODE_ALTERNATE | \
PAL_SN32_ALTERNATE(n))
/** @} */
/**
* @name Standard I/O mode flags
* @{
*/
/**
* @brief Implemented as input.
*/
#define PAL_MODE_RESET PAL_SN32_MODE_INPUT
/**
* @brief Implemented as analog with analog switch disabled and lock.
*/
#define PAL_MODE_UNCONNECTED (PAL_SN32_MODE_ANALOG | \
PAL_SN32_ASCR_OFF | \
PAL_SN32_LOCKR_ON)
/**
* @brief Regular input high-Z pad.
*/
#define PAL_MODE_INPUT PAL_SN32_MODE_INPUT
/**
* @brief Input pad with weak pull up resistor.
*/
#define PAL_MODE_INPUT_PULLUP (PAL_SN32_MODE_INPUT | \
PAL_SN32_PUPDR_PULLUP)
/**
* @brief Input pad with weak pull down resistor.
*/
#define PAL_MODE_INPUT_PULLDOWN (PAL_SN32_MODE_INPUT | \
PAL_SN32_PUPDR_PULLDOWN)
/**
* @brief Analog input mode.
*/
#define PAL_MODE_INPUT_ANALOG (PAL_SN32_MODE_ANALOG | \
PAL_SN32_ASCR_ON)
/**
* @brief Push-pull output pad.
*/
#define PAL_MODE_OUTPUT_PUSHPULL (PAL_SN32_MODE_OUTPUT | \
PAL_SN32_OTYPE_PUSHPULL)
/**
* @brief Open-drain output pad.
*/
#define PAL_MODE_OUTPUT_OPENDRAIN (PAL_SN32_MODE_OUTPUT | \
PAL_SN32_OTYPE_OPENDRAIN)
/** @} */
/* Discarded definitions from the ST headers, the PAL driver uses its own
definitions in order to have an unified handling for all devices.
Unfortunately the ST headers have no uniform definitions for the same
objects across the various sub-families.*/
#undef GPIOA
#undef GPIOB
#undef GPIOC
#undef GPIOD
/**
* @name GPIO ports definitions
* @{
*/
#define GPIOA ((sn32_gpio_t *)GPIOA_BASE)
#define GPIOB ((sn32_gpio_t *)GPIOB_BASE)
#define GPIOC ((sn32_gpio_t *)GPIOC_BASE)
#define GPIOD ((sn32_gpio_t *)GPIOD_BASE)
/** @} */
/*===========================================================================*/
/* I/O Ports Types and constants. */
/*===========================================================================*/
/**
* @name Port related definitions
* @{
*/
/**
* @brief Width, in bits, of an I/O port.
*/
#define PAL_IOPORTS_WIDTH 16
/**
* @brief Whole port mask.
* @details This macro specifies all the valid bits into a port.
*/
#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF)
/** @} */
/**
* @name Line handling macros
* @{
*/
/**
* @brief Forms a line identifier.
* @details A port/pad pair are encoded into an @p ioline_t type. The encoding
* of this type is platform-dependent.
* @note In this driver the pad number is encoded in the lower 4 bits of
* the GPIO address which are guaranteed to be zero.
*/
#define PAL_LINE(port, pad) \
((ioline_t)((uint32_t)(port)) | ((uint32_t)(pad)))
/**
* @brief Decodes a port identifier from a line identifier.
*/
#define PAL_PORT(line) \
((sn32_gpio_t *)(((uint32_t)(line)) & 0xFFFFFFF0U))
/**
* @brief Decodes a pad identifier from a line identifier.
*/
#define PAL_PAD(line) \
((uint32_t)((uint32_t)(line) & 0x0000000FU))
/**
* @brief Value identifying an invalid line.
*/
#define PAL_NOLINE 0U
/** @} */
/**
* @brief SN32 GPIO registers block.
*/
typedef struct {
volatile uint32_t MODER;
volatile uint32_t OTYPER;
volatile uint32_t OSPEEDR;
volatile uint32_t PUPDR;
volatile uint32_t IDR;
volatile uint32_t ODR;
volatile union {
uint32_t W;
struct {
uint16_t set;
uint16_t clear;
} H;
} BSRR;
volatile uint32_t LOCKR;
volatile uint32_t AFRL;
volatile uint32_t AFRH;
volatile uint32_t BRR;
volatile uint32_t ASCR;
} sn32_gpio_t;
/**
* @brief GPIO port setup info.
*/
typedef struct {
/** Initial value for MODER register.*/
uint32_t moder;
/** Initial value for OTYPER register.*/
uint32_t otyper;
/** Initial value for OSPEEDR register.*/
uint32_t ospeedr;
/** Initial value for PUPDR register.*/
uint32_t pupdr;
/** Initial value for ODR register.*/
uint32_t odr;
/** Initial value for AFRL register.*/
uint32_t afrl;
/** Initial value for AFRH register.*/
uint32_t afrh;
/** Initial value for ASCR register.*/
uint32_t ascr;
/** Initial value for LOCKR register.*/
uint32_t lockr;
} sn32_gpio_setup_t;
/**
* @brief SN32 GPIO static initializer.
* @details An instance of this structure must be passed to @p palInit() at
* system startup time in order to initialize the digital I/O
* subsystem. This represents only the initial setup, specific pads
* or whole ports can be reprogrammed at later time.
*/
typedef struct {
#if SN32_HAS_GPIOA || defined(__DOXYGEN__)
/** @brief Port A setup data.*/
sn32_gpio_setup_t PAData;
#endif
#if SN32_HAS_GPIOB || defined(__DOXYGEN__)
/** @brief Port B setup data.*/
sn32_gpio_setup_t PBData;
#endif
#if SN32_HAS_GPIOC || defined(__DOXYGEN__)
/** @brief Port C setup data.*/
sn32_gpio_setup_t PCData;
#endif
#if SN32_HAS_GPIOD || defined(__DOXYGEN__)
/** @brief Port D setup data.*/
sn32_gpio_setup_t PDData;
#endif
} PALConfig;
/**
* @brief Type of digital I/O port sized unsigned integer.
*/
typedef uint32_t ioportmask_t;
/**
* @brief Type of digital I/O modes.
*/
typedef uint32_t iomode_t;
/**
* @brief Type of an I/O line.
*/
typedef uint32_t ioline_t;
/**
* @brief Port Identifier.
* @details This type can be a scalar or some kind of pointer, do not make
* any assumption about it, use the provided macros when populating
* variables of this type.
*/
typedef sn32_gpio_t * ioportid_t;
/*===========================================================================*/
/* I/O Ports Identifiers. */
/* The low level driver wraps the definitions already present in the SN32 */
/* firmware library. */
/*===========================================================================*/
/**
* @brief GPIO port A identifier.
*/
#if SN32_HAS_GPIOA || defined(__DOXYGEN__)
#define IOPORT1 GPIOA
#endif
/**
* @brief GPIO port B identifier.
*/
#if SN32_HAS_GPIOB || defined(__DOXYGEN__)
#define IOPORT2 GPIOB
#endif
/**
* @brief GPIO port C identifier.
*/
#if SN32_HAS_GPIOC || defined(__DOXYGEN__)
#define IOPORT3 GPIOC
#endif
/**
* @brief GPIO port D identifier.
*/
#if SN32_HAS_GPIOD || defined(__DOXYGEN__)
#define IOPORT4 GPIOD
#endif
/*===========================================================================*/
/* Implementation, some of the following macros could be implemented as */
/* functions, if so please put them in pal_lld.c. */
/*===========================================================================*/
/**
* @brief GPIO ports subsystem initialization.
*
* @notapi
*/
#define pal_lld_init(config) _pal_lld_init(config)
/**
* @brief Reads an I/O port.
* @details This function is implemented by reading the GPIO IDR register, the
* implementation has no side effects.
* @note This function is not meant to be invoked directly by the application
* code.
*
* @param[in] port port identifier
* @return The port bits.
*
* @notapi
*/
#define pal_lld_readport(port) ((port)->IDR)
/**
* @brief Reads the output latch.
* @details This function is implemented by reading the GPIO ODR register, the
* implementation has no side effects.
* @note This function is not meant to be invoked directly by the application
* code.
*
* @param[in] port port identifier
* @return The latched logical states.
*
* @notapi
*/
#define pal_lld_readlatch(port) ((port)->ODR)
/**
* @brief Writes on a I/O port.
* @details This function is implemented by writing the GPIO ODR register, the
* implementation has no side effects.
*
* @param[in] port port identifier
* @param[in] bits bits to be written on the specified port
*
* @notapi
*/
#define pal_lld_writeport(port, bits) ((port)->ODR = (bits))
/**
* @brief Sets a bits mask on a I/O port.
* @details This function is implemented by writing the GPIO BSRR register, the
* implementation has no side effects.
*
* @param[in] port port identifier
* @param[in] bits bits to be ORed on the specified port
*
* @notapi
*/
#define pal_lld_setport(port, bits) ((port)->BSRR.H.set = (uint16_t)(bits))
/**
* @brief Clears a bits mask on a I/O port.
* @details This function is implemented by writing the GPIO BSRR register, the
* implementation has no side effects.
*
* @param[in] port port identifier
* @param[in] bits bits to be cleared on the specified port
*
* @notapi
*/
#define pal_lld_clearport(port, bits) ((port)->BSRR.H.clear = (uint16_t)(bits))
/**
* @brief Writes a group of bits.
* @details This function is implemented by writing the GPIO BSRR register, the
* implementation has no side effects.
*
* @param[in] port port identifier
* @param[in] mask group mask
* @param[in] offset the group bit offset within the port
* @param[in] bits bits to be written. Values exceeding the group
* width are masked.
*
* @notapi
*/
#define pal_lld_writegroup(port, mask, offset, bits) \
((port)->BSRR.W = ((~(bits) & (mask)) << (16U + (offset))) | \
(((bits) & (mask)) << (offset)))
/**
* @brief Pads group mode setup.
* @details This function programs a pads group belonging to the same port
* with the specified mode.
*
* @param[in] port port identifier
* @param[in] mask group mask
* @param[in] offset group bit offset within the port
* @param[in] mode group mode
*
* @notapi
*/
#define pal_lld_setgroupmode(port, mask, offset, mode) \
_pal_lld_setgroupmode(port, mask << offset, mode)
/**
* @brief Writes a logical state on an output pad.
*
* @param[in] port port identifier
* @param[in] pad pad number within the port
* @param[in] bit logical value, the value must be @p PAL_LOW or
* @p PAL_HIGH
*
* @notapi
*/
#define pal_lld_writepad(port, pad, bit) pal_lld_writegroup(port, 1, pad, bit)
extern const PALConfig pal_default_config;
#ifdef __cplusplus
extern "C" {
#endif
void _pal_lld_init(const PALConfig *config);
void _pal_lld_setgroupmode(ioportid_t port,
ioportmask_t mask,
iomode_t mode);
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_PAL */
#endif /* HAL_PAL_LLD_H */
/** @} */

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#ifndef __SN32F240_I2C_H
#define __SN32F240_I2C_H
/*_____ I N C L U D E S ____________________________________________________*/
/*_____ D E F I N I T I O N S ______________________________________________*/
/*
Base Address: 0x4001 8000 (I2C0)
0x4005 A000 (I2C1)
*/
/* I2C n Control register <I2Cn_CTRL> (0x00) */
//[1:1]Assert NACK (HIGH level to SDA) flag
#define I2C_NACK_NOFUNCTION 0 //No function
#define I2C_NACK 1 //An NACK will be returned during the acknowledge clock pulse on SCLn
#define mskI2C_NACK_NOFUNCTION (I2C_NACK_NOFUNCTION<<1)
#define mskI2C_NACK (I2C_NACK<<1)
//[2:2]Assert ACK (Low level to SDA) flag
#define I2C_ACK_NOFUNCTION 0 //No function
#define I2C_ACK 1 //An ACK will be returned during the acknowledge clock pulse on SCLn
#define mskI2C_ACK_NOFUNCTION (I2C_ACK_NOFUNCTION<<2)
#define mskI2C_ACK (I2C_ACK<<2)
//[4:4]STOP flag
#define I2C_STO_IDLE 0 //Stop condition idle
#define I2C_STO_STOP 1 //Transmit a STOP condition in master mode, or recover from an error condition in slave mode.
#define mskI2C_STO_IDLE (I2C_STO_IDLE<<4)
#define mskI2C_STO_STOP (I2C_STO_STOP<<4)
//[5:5]START bit
#define I2C_STA_IDLE 0 //No START condition or Repeated START condition will be generated
#define I2C_STA_START 1 //transmit a START or a Repeated START condition
#define mskI2C_STA_IDLE (I2C_STA_IDLE<<5)
#define mskI2C_STA_START (I2C_STA_START<<5)
#define I2C_I2CEN_DIS 0 //[8:8]I2C Interface enable bit
#define I2C_I2CEN_EN 1
#define mskI2C_I2CEN_DIS (I2C_I2CEN_DIS<<8)
#define mskI2C_I2CEN_EN (I2C_I2CEN_EN<<8)
/* I2C n Status register <I2Cn_STAT> (0x04) */
//[0:0]RX done status
#define I2C_RX_DN_NO_HANDSHAKE 0 //No RX with ACK/NACK transfer
#define I2C_RX_DN_HANDSHAKE 1 //8-bit RX with ACK/NACK transfer is done
#define mskI2C_RX_DN_NO_HANDSHAKE (I2C_RX_DN_NO_HANDSHAKE<<0)
#define mskI2C_RX_DN_HANDSHAKE (I2C_RX_DN_HANDSHAKE<<0)
//[1:1]ACK done status
#define I2C_ACK_STAT_NO_RECEIVED_ACK 0 //Not received an ACK
#define I2C_ACK_STAT_RECEIVED_ACK 1 //Received an ACK
#define mskI2C_ACK_STAT_NO_RECEIVED_ACK (I2C_ACK_STAT_NO_RECEIVED_ACK<<1)
#define mskI2C_ACK_STAT_RECEIVED_ACK (I2C_ACK_STAT_RECEIVED_ACK<<1)
//[2:2]NACK done status
#define I2C_NACK_STAT_NO_RECEIVED_NACK 0 //Not received a NACK
#define I2C_NACK_STAT_RECEIVED_NACK 1 //Received a NACK
#define mskI2C_NACK_STAT_NO_RECEIVED_NACK (I2C_NACK_STAT_NO_RECEIVED_NACK<<2)
#define mskI2C_NACK_STAT_RECEIVED_NACK (I2C_NACK_STAT_RECEIVED_NACK<<2)
//[3:3]Stop done status
#define I2C_STOP_DN_NO_STOP 0 //No STOP bit
#define I2C_STOP_DN_STOP 1 //MASTER mode, a STOP condition was issued
//SLAVE mode, a STOP condition was received
#define mskI2C_STOP_DN_NO_STOP (I2C_STOP_DN_NO_STOP<<3)
#define mskI2C_STOP_DN_STOP (I2C_STOP_DN_STOP<<3)
//[4:4]Start done status
#define I2C_START_DN_NO_START 0 //No START bit
#define I2C_START_DN_START 1 //MASTER mode, a START bit was issued
//SLAVE mode, a START bit was received
#define mskI2C_START_DN_NO_START (I2C_START_DN_NO_START<<4)
#define mskI2C_START_DN_START (I2C_START_DN_START<<4)
#define I2C_MST_SLAVE 0 //[5:5]Master/Slave status
#define I2C_MST_MASTER 1
#define mskI2C_MST_SLAVE (I2C_MST_SLAVE<<5)
#define mskI2C_MST_MASTER (I2C_MST_MASTER<<5)
#define mskI2C_STA_STA_STO ((I2C_START_DN_START<<4)|(I2C_STOP_DN_STOP<<3))
#define mskI2C_STA_MASTER_STA_STO ((I2C_MST_MASTER<<5)|(I2C_START_DN_START<<4)|(I2C_STOP_DN_STOP<<3))
//[6:6]Slave address check
#define I2C_SLV_RX_NO_MATCH_ADDR 0 //No matched slave address
#define I2C_SLV_RX_MATCH_ADDR 1 //Slave address hit, and is called for RX in slave mode
#define mskI2C_SLV_RX_NO_MATCH_ADDR (I2C_SLV_RX_NO_MATCH_ADDR<<6)
#define mskI2C_SLV_RX_MATCH_ADDR (I2C_SLV_RX_MATCH_ADDR<<6)
//[7:7]Slave address check
#define I2C_SLV_TX_NO_MATCH_ADDR 0 //No matched slave address
#define I2C_SLV_TX_MATCH_ADDR 1 //Slave address hit, and is called for TX in slave mode.
#define mskI2C_SLV_TX_NO_MATCH_ADDR (I2C_SLV_TX_NO_MATCH_ADDR<<7)
#define mskI2C_SLV_TX_MATCH_ADDR (I2C_SLV_TX_MATCH_ADDR<<7)
//[8:8]Lost arbitration
#define I2C_LOST_ARB_NO_LOST 0 //Not lost arbitration
#define I2C_LOST_ARB_LOST_ARBITRATION 1 //Lost arbitration
#define mskI2C_LOST_ARB_NO_LOST (I2C_LOST_ARB_NO_LOST<<8)
#define mskI2C_LOST_ARB_LOST_ARBITRATION (I2C_LOST_ARB_LOST_ARBITRATION<<8)
//[9:9]Time-out status
#define I2C_TIMEOUT_NO_TIMEOUT 0 //No Timeout
#define I2C_TIMEOUT_TIMEOUT 1 //Timeout
#define mskI2C_TIMEOUT_TIMEOUT (I2C_TIMEOUT_TIMEOUT<<9)
#define mskI2C_TIMEOUT_NO_TIMEOUT (I2C_TIMEOUT_NO_TIMEOUT<<9)
//[15:15]I2C Interrupt flag
#define I2C_I2CIF_STAUS_NO_CHANGE 0 //I2C status doesn’t change
#define I2C_I2CIF_INTERRUPT 1 //Read, I2C status changes
//Write, Clear this flag
#define mskI2C_I2CIF_STAUS_NO_CHANGE (I2C_I2CIF_STAUS_NO_CHANGE<<15)
#define mskI2C_I2CIF_INTERRUPT (I2C_I2CIF_INTERRUPT<<15)
/* I2C n TX Data register <I2Cn_TXDATA> (0x08) */
/* I2C n RX Data register <I2Cn_RXDATA> (0x0C) */
/* I2C n Slave Address 0 register <I2Cn_SLVADDR0> (0x10) */
//[9:0]The I2C slave address
#define I2C_ADDR_SLAVE_ADDR0 0x07 //ADD[9:0] is valid when ADD_MODE = 1
//ADD[7:1] is valid when ADD_MODE = 0
//[30:30]General call address enable bit
#define I2C_GCEN_DIS 0 //Disable
#define I2C_GCEN_EN 1 //Enable general call address (0x0)
#define mskI2C_GCEN_DIS (I2C_GCEN_DIS<<30)
#define mskI2C_GCEN_EN (I2C_GCEN_EN<<30)
//[31:31]Slave address mode
#define I2C_ADD_MODE_7BIT 0 //7-bit address mode
#define I2C_ADD_MODE_10BIT 1 //10-bit address mode
#define mskI2C_ADD_MODE_7BIT (I2C_ADD_MODE_7BIT<<31)
#define mskI2C_ADD_MODE_10BIT (I2C_ADD_MODE_10BIT<<31)
/* I2C n Slave Address 1~3 register <I2Cn_SLVADDR1~3> (0x14/0x18/0x1C) */
//The I2C slave address 1~3
//ADD[9:0] is valid when ADD_MODE = 1
//ADD[7:1] is valid when ADD_MODE = 0
#define I2C_ADDR_SLAVE_ADDR1 0x0A //The I2C slave address 1
#define I2C_ADDR_SLAVE_ADDR2 0 //The I2C slave address 2
#define I2C_ADDR_SLAVE_ADDR3 0 //The I2C slave address 3
#define I2C_SLAVE0 0 //Slave Number 0
#define I2C_SLAVE1 1 //Slave Number 1
#define I2C_SLAVE2 2 //Slave Number 2
#define I2C_SLAVE3 3 //Slave Number 3
/* I2C n SCL High Time register <(I2Cn_SCLHT> (0x20) */
#define I2C0_SCLHT 14 //[7:0], Count for SCL High Period time
#define I2C1_SCLHT 4 //SCL High Period Time = (SCLH+1) * I2C0_PCLK cycle
/* I2C n SCL Low Time register <(I2Cn_SCLLT> (0x24) */
#define I2C0_SCLLT 14 //[7:0], Count for SCL Low Period time
#define I2C1_SCLLT 4 //SCL Loq Period Time = (SCLH+1) * I2C0_PCLK cycle
/* I2C n Timeout Control register <I2Cn_TOCTRL> (0x2C) */
#define I2C_TO_DIS 0 //[15:0], Count for checking Timeout
#define I2C_TO_PERIOD_TIME 0 //N: Timeout period time = N*I2Cn_PCLK cycle
/* I2C n Monitor Mode Control register <I2Cn_MMCTRL> (0x30) */
#define I2C_MMEN_MONITOR_DIS 0 //[0:0]Monitor mode enable bit
#define I2C_MMEN_MONITOR_EN 1
#define mskI2C_MMEN_MONITOR_DIS (I2C_MMEN_MONITOR_DIS<<0) //Monitor mode enable bit
#define mskI2C_MMEN_MONITOR_EN (I2C_MMEN_MONITOR_EN<<0)
//[1:1]SCL output enable bit
#define I2C_SCLOEN_DIS 0 //SCL output will be forced high
#define I2C_SCLOEN_EN 1 //I2C holds the clock line low until it has had time to respond to an I2C interrupt
#define mskI2C_SCLOEN_DIS (I2C_SCLOEN_DIS<<1) //SCL output enable bit
#define mskI2C_SCLOEN_EN (I2C_SCLOEN_EN<<1)
//[2:2]Match address selection
#define I2C_MATCH_ALL_ADDR0_3 0 //Interrupt will only be generated when the address matches
#define I2C_MATCH_ALL_ANY_ADDR 1 //In monitor mode, an interrupt will be generated on ANY address received
#define mskI2C_MATCH_ALL_ADDR0_3 (I2C_MATCH_ALL_ADDR0_3<<2)
#define mskI2C_MATCH_ALL_ANY_ADDR (I2C_MATCH_ALL_ANY_ADDR<<2)
#define I2C_ERROR 0x00001
/*_____ M A C R O S ________________________________________________________*/
/*_____ D E C L A R A T I O N S ____________________________________________*/
//------------------I2C-------------------------
//Address
extern uint16_t hwI2C_Device_Addr_I2C0;
extern uint16_t hwI2C_Device_Addr_I2C1;
//Check Flag
extern uint32_t wI2C_TimeoutFlag;
extern uint32_t wI2C_ArbitrationFlag;
//Error Flag
extern uint32_t wI2C_RegisterCheckError;
extern uint32_t wI2C_TotalError;
//------------------Master Tx-------------------------
//TX FIFO
extern uint8_t bI2C_MasTxData[10];
//Control Flag
extern uint8_t bI2C_MasTxPointer;
extern uint32_t wI2C_MasTxCtr;
//------------------Master Rx-------------------------
//RX FIFO
extern uint8_t bI2C_MasRxData[10];
//Rx Control Flag
extern uint8_t bI2C_MasRxPointer;
extern uint32_t wI2C_ReturnNackFlag;
extern uint32_t wI2C_RxControlFlag;
//------------------Slave Rx-------------------------
//RX FIFO
extern uint8_t bI2C_SlaRxData[10];
//Rx Control Flag
extern uint8_t bI2C_SlaRxPointer;
//extern volatile uint8_t bEndSRxFlagI2C;
//------------------Slave Tx-------------------------
//TX FIFO
extern uint8_t bI2C_SlaTxData[10];
//Tx Control Flag
extern uint8_t bI2C_SlaTxPointer;
//extern volatile uint8_t bEndSTxFlagI2C;
void I2C0_Init(void);
void I2C1_Init(void);
void I2C0_Timeout_Ctrl(uint32_t wI2CTo);
void I2C1_Timeout_Ctrl(uint32_t wI2CTo);
void I2C0_Monitor_Mode_Ctrl(uint32_t wI2CmatchAll, uint32_t wI2Cscloen, uint32_t wI2Cmmen);
void I2C1_Monitor_Mode_Ctrl(uint32_t wI2CmatchAll, uint32_t wI2Cscloen, uint32_t wI2Cmmen);
void Set_I2C0_Address(uint8_t bI2CaddMode, uint8_t bSlaveNo, uint32_t bSlaveAddr, uint8_t bGCEnable);
void Set_I2C1_Address(uint8_t bI2CaddMode, uint8_t bSlaveNo, uint32_t bSlaveAddr, uint8_t bGCEnable);
extern void I2C0_Enable(void);
extern void I2C0_Disable(void);
extern void I2C1_Enable(void);
extern void I2C1_Disable(void);
void I2C0_Master_Tx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint8_t bSlaveAddress, volatile uint32_t wTxNum, volatile uint32_t wRepeatTX, volatile uint32_t wReTxNum);
void I2C0_Master_Rx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint8_t bSlaveAddress, volatile uint32_t wRxNum, volatile uint32_t wRepeatRX, volatile uint32_t wReRxNum);
void I2C1_Master_Tx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint8_t bSlaveAddress, volatile uint32_t wTxNum, volatile uint32_t wRepeatTX, volatile uint32_t wReTxNum);
void I2C1_Master_Rx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint8_t bSlaveAddress, volatile uint32_t wRxNum, volatile uint32_t wRepeatRX, volatile uint32_t wReRxNum);
void I2C1_Slave_Rx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint32_t wNumForNack);
void I2C1_Slave_Tx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop);
void I2C1_Mointer_Mode(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop);
void I2C0_Slave_Rx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint32_t wNumForNack);
void I2C0_Slave_Tx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop);
void I2C0_Mointer_Mode(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop);
#endif /*__SN32F240_I2C_H*/

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/******************** (C) COPYRIGHT 2013 SONiX *******************************
* COMPANY: SONiX
* DATE: 2013/12
* AUTHOR: SA1
* IC: SN32F240/230/220
* DESCRIPTION: I2C0 related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2013/12/17 SA1 1. First release
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240.h>
#include "I2C.h"
#include "..\..\Utility\Utility.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
//------------------I2C-------------------------
//Address
uint16_t hwI2C_Device_Addr_I2C0 = 0x00;
uint16_t hwI2C_Device_Addr_I2C1 = 0x00;
//Check Flag
uint32_t wI2C_TimeoutFlag = 0;
uint32_t wI2C_ArbitrationFlag = 0;
//Error Flag
uint32_t wI2C_RegisterCheckError = 0;
uint32_t wI2C_TotalError = 0;
//------------------Master Tx-------------------------
//TX FIFO
uint8_t bI2C_MasTxData[10];
//Tx Control Flag
uint8_t bI2C_MasTxPointer=0;
uint32_t wI2C_MasTxCtr=0;
//------------------Master Rx-------------------------
//RX FIFO
uint8_t bI2C_MasRxData[10];
//Rx Control Flag
uint8_t bI2C_MasRxPointer=0;
uint32_t wI2C_ReturnNackFlag=0;
uint32_t wI2C_RxControlFlag=0;
//------------------Slave Rx-------------------------
//RX FIFO
uint8_t bI2C_SlaRxData[10];
//Rx Control Flag
uint8_t bI2C_SlaRxPointer=0;
//------------------Slave Tx-------------------------
//TX FIFO
uint8_t bI2C_SlaTxData[10];
//Tx Control Flag
uint8_t bI2C_SlaTxPointer=0;
//Mointer Mode
uint8_t bI2C0_MointerAddress = 0x00;
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
/*****************************************************************************
* Function : I2C0_Init
* Description : Set specified value to specified bits of assigned register
* Input : wI2C0SCLH - SCL High Time
* wI2C0SCLL - SCL Low Time
* wI2C0Mode - 0: Standard/Fast mode.1: Fast-mode Plus
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C0_Init(void)
{
//I2C0 interrupt enable
NVIC_ClearPendingIRQ(I2C0_IRQn);
NVIC_EnableIRQ(I2C0_IRQn);
NVIC_SetPriority(I2C0_IRQn,0);
//Enable HCLK for I2C0
SN_SYS1->AHBCLKEN |= (0x1 << 21); //Enable clock for I2C0
//I2C speed
SN_I2C0->SCLHT = I2C0_SCLHT;
SN_I2C0->SCLLT = I2C0_SCLLT;
//Mointer mode
//SN_I2C0->MMCTRL = 0x00;
SN_I2C0->MMCTRL = mskI2C_MATCH_ALL_ADDR0_3|
mskI2C_SCLOEN_DIS|
mskI2C_MMEN_MONITOR_DIS;
//I2C enable
SN_I2C0->CTRL_b.I2CEN = I2C_I2CEN_EN;
}
/*****************************************************************************
* Function : I2C0_Timeout_Ctrl
* Description : Set specified value to specified bits of assigned register
* Input : wI2CTo - TimeOut Value: wI2CTo * 32 * I2C_PCLK cycle
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C0_Timeout_Ctrl(uint32_t wI2CTo)
{
SN_I2C0->TOCTRL = wI2CTo;
}
/*****************************************************************************
* Function : I2C0_Monitor_Mode_Ctrl
* Description : Set specified value to specified bits of assigned register
* Input : wI2CmatchAll - 0: No use. 1: Interrupt will be generated on ANY address received.
* wI2Cscloen - 0: No use. 1: Let I2C holds the clock line low to get data.
* wI2Cmmen - 0: No use. 1: Monitor mode enable bit.
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C0_Monitor_Mode_Ctrl(uint32_t wI2CmatchAll, uint32_t wI2Cscloen, uint32_t wI2Cmmen)
{
SN_I2C0->TOCTRL = (wI2CmatchAll << 2) | (wI2Cscloen << 1) | (wI2Cmmen << 0);
}
/*****************************************************************************
* Function : Set_I2C0_Address
* Description : Set specified value to specified bits of assigned register
* Input : bI2CaddMode - 7 bits address is 0, 10 bits address is 1
* bSlaveNo - Slave address number 0, 1, 2, 3
* bSlaveAddr - Slave value
* bGCEnable - Genral call enable is 1
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void Set_I2C0_Address(uint8_t bI2CaddMode, uint8_t bSlaveNo, uint32_t bSlaveAddr, uint8_t bGCEnable)
{
volatile uint16_t hwAddressCom=0;
if(bI2CaddMode == 0)
{
hwAddressCom = bSlaveAddr << 1;
}
else
{
hwAddressCom = bSlaveAddr;
}
if(bGCEnable == 1)
{
SN_I2C0->SLVADDR0_b.GCEN = I2C_GCEN_EN;
}
else
{
SN_I2C0->SLVADDR0_b.GCEN = I2C_GCEN_DIS;
}
if(bI2CaddMode == 1)
{
SN_I2C0->SLVADDR0_b.ADD_MODE = I2C_ADD_MODE_10BIT;
}
else
{
SN_I2C0->SLVADDR0_b.ADD_MODE = I2C_ADD_MODE_7BIT;
}
switch (bSlaveNo)
{
case 0:
SN_I2C0->SLVADDR0 = hwAddressCom;
break;
case 1:
SN_I2C0->SLVADDR1 = hwAddressCom;
break;
case 2:
SN_I2C0->SLVADDR2 = hwAddressCom;
break;
case 3:
SN_I2C0->SLVADDR3 = hwAddressCom;
break;
default:
break;
}
}
/*****************************************************************************
* Function : I2C0_Enable
* Description : I2C0 enable setting
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C0_Enable(void)
{
//Enable HCLK for I2C0
SN_SYS1->AHBCLKEN |= (0x1 << 21); //Enable clock for I2C0
SN_I2C0->CTRL_b.I2CEN = I2C_I2CEN_EN; //I2C enable
}
/*****************************************************************************
* Function : I2C0_Disable
* Description : I2C0 disable setting
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C0_Disable(void)
{
SN_I2C0->CTRL_b.I2CEN = I2C_I2CEN_DIS; //I2C disable
//Disable HCLK for I2C0
SN_SYS1->AHBCLKEN &=~ (0x1 << 21); //Disable clock for I2C0
}
/*****************************************************************************
* Function : I2C0_Master_Tx
* Description : Set specified value to specified bits of assigned register
* Input : *bDataFIFO - Declare TX FIFO Register
* *bPointerFIFO - Declare TX FIFO Pointer Register
* *bCommStop - Declare the Register when get the STOP information
* bSlaveAddress - Set the Slave adress
* wTxNum - Set the Number of sending Data
* wRepeatTX - 0 : No use. 1: Next transfer with a Repated Start condition. 2: Work next transfer.
* wReTxNum - Send (wReTxNum + 1) Data when wRepeatTX is 1.
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C0_Master_Tx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint8_t bSlaveAddress, volatile uint32_t wTxNum, volatile uint32_t wRepeatTX, volatile uint32_t wReTxNum)
{
//wReTxNum = 0, Repeat once; wReTxNum = 1, Repeat twice
//if(((I2C_STAT) & (mskI2C_TIMEOUT_TIMEOUT)) != 0x00) //Timeout State
if(SN_I2C0->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_TimeoutFlag = 1;
}
else if(SN_I2C0->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_ArbitrationFlag = 1;
}
else if(((SN_I2C0->STAT) & (mskI2C_STA_MASTER_STA_STO)) == (mskI2C_STOP_DN_STOP)) //Stop Down
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
*bPointerFIFO = 0x00;
wI2C_MasTxCtr = 0x00;
*bCommStop = 1;
}
else if(((SN_I2C0->STAT) & (mskI2C_STA_MASTER_STA_STO)) == (mskI2C_STA_MASTER_STA_STO)) //Start and Stop Down
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
SN_I2C0->TXDATA = (bSlaveAddress << 0x01);
}
else
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
switch (SN_I2C0->STAT)
{
/* START has been transmitted and prepare SLA+W */
case (mskI2C_MST_MASTER|mskI2C_START_DN_START):
SN_I2C0->TXDATA = (bSlaveAddress << 0x01);
break;
/* SLA+W or Data has been transmitted and ACK has been received */
case (mskI2C_MST_MASTER|mskI2C_ACK_STAT_RECEIVED_ACK):
if ((*bPointerFIFO < wTxNum)&&(wI2C_MasTxCtr == 0x00))
{
SN_I2C0->TXDATA = *bDataFIFO;
*bPointerFIFO = *bPointerFIFO + 1;
}
else if ((*bPointerFIFO == wTxNum)&&(wI2C_MasTxCtr == 0x00))
{
if(wRepeatTX == 0) //No Repeat
{
SN_I2C0->CTRL |= mskI2C_STO_STOP;
}
else if(wRepeatTX == 1) //Repeat Start
{
SN_I2C0->CTRL |= mskI2C_STA_START;
wI2C_MasTxCtr++;
}
else if(wRepeatTX == 2) //Repeat Both
{
SN_I2C0->CTRL |= (mskI2C_STO_STOP|mskI2C_STA_START);
wI2C_MasTxCtr++;
}
else
{
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
}
}
else if ((*bPointerFIFO < (wTxNum+1+wReTxNum))&&(wI2C_MasTxCtr == 0x01))
{
SN_I2C0->TXDATA = *bDataFIFO;
*bPointerFIFO = *bPointerFIFO + 1;
}
else if ((*bPointerFIFO == (wTxNum+1+wReTxNum))&&(wI2C_MasTxCtr == 0x01))
{
SN_I2C0->CTRL |= mskI2C_STO_STOP;
}
else
{
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
}
break;
/* SLA+W or Data has been transmitted and NACK has been received */
case (mskI2C_MST_MASTER|mskI2C_NACK_STAT_RECEIVED_NACK):
if ((*bPointerFIFO == wTxNum)&&(wI2C_MasTxCtr == 0x00))
{
if(wRepeatTX == 0) //No Repeat
{
SN_I2C0->CTRL |= mskI2C_STO_STOP;
}
else if(wRepeatTX == 1) //Repeat Start
{
SN_I2C0->CTRL |= mskI2C_STA_START;
wI2C_MasTxCtr++;
}
else if(wRepeatTX == 2) //Repeat Both
{
SN_I2C0->CTRL |= (mskI2C_STO_STOP|mskI2C_STA_START);
wI2C_MasTxCtr++;
}
else
{
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
}
}
else if ((*bPointerFIFO == (wTxNum+1+wReTxNum))&&(wI2C_MasTxCtr == 0x01))
{
SN_I2C0->CTRL |= mskI2C_STO_STOP;
}
else
{
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
}
break;
/*Error State Check*/
default:
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
break;
}
}
}
/*****************************************************************************
* Function : I2C0_Master_Rx
* Description : Set specified value to specified bits of assigned register
* Input : *bDataFIFO - Declare RX FIFO Register
* *bPointerFIFO - Declare RX FIFO Pointer Register
* *bCommStop - Declare the Register when get the STOP information
* bSlaveAddress - Set the Slave adress
* wRxNum - Set the Number of getting Data
* wRepeatRX - 0 : No use. 1: Next transfer with a Repated Start condition 2: Work next transfer.
* wReRxNum - Get (wReRxNum + 1) data when wRepeatRX is 1.
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C0_Master_Rx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint8_t bSlaveAddress, volatile uint32_t wRxNum, volatile uint32_t wRepeatRX, volatile uint32_t wReRxNum)
{
uint32_t wDeboundNum = 0;
//if(((I2C_STAT) & (mskI2C_TIMEOUT_TIMEOUT)) != 0x00) //Timeout State
if(SN_I2C0->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_TimeoutFlag = 1;
}
else if(SN_I2C0->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_ArbitrationFlag = 1;
}
else if(((SN_I2C0->STAT) & (mskI2C_STA_STA_STO)) == (mskI2C_STOP_DN_STOP)) //Stop Down
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
*bPointerFIFO = 0x00;
wI2C_MasTxCtr = 0x00;
*bCommStop = 1;
wI2C_RxControlFlag = 0x00;
wI2C_ReturnNackFlag = 0x00;
}
else if(((SN_I2C0->STAT) & (mskI2C_STA_MASTER_STA_STO)) == (mskI2C_STA_MASTER_STA_STO)) //Start and Stop Down
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
SN_I2C0->TXDATA = (bSlaveAddress << 0x01) | 0x01;
}
else
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
switch (SN_I2C0->STAT)
{
/* START has been transmitted and prepare to send address */
case (mskI2C_MST_MASTER|mskI2C_START_DN_START):
SN_I2C0->TXDATA = (bSlaveAddress << 0x01) | 0x01;
break;
/* Received an ACK */
case (mskI2C_MST_MASTER|mskI2C_ACK_STAT_RECEIVED_ACK):
if((wRxNum == 1) && (wI2C_ReturnNackFlag == 0))
{
SN_I2C0->CTRL |= mskI2C_NACK; //NACK
wI2C_ReturnNackFlag++;
}
else if((wReRxNum == 0) && (wI2C_ReturnNackFlag == 1))
{
SN_I2C0->CTRL |= mskI2C_NACK; //NACK
wI2C_ReturnNackFlag++;
}
else
{
SN_I2C0->CTRL |= mskI2C_ACK; //ACK
}
break;
/* RX with ACK/NACK transfer is down */
case (mskI2C_MST_MASTER|mskI2C_RX_DN_HANDSHAKE):
*bDataFIFO = SN_I2C0->RXDATA;
*bPointerFIFO = *bPointerFIFO + 1;
if(wI2C_ReturnNackFlag == 0x00)
{
wDeboundNum = wRxNum-1;
}
else if(wI2C_ReturnNackFlag == 0x01)
{
wDeboundNum = wRxNum+wReRxNum;
}
if(wI2C_ReturnNackFlag == 0x02)
{
SN_I2C0->CTRL |= mskI2C_STO_STOP;
}
else if((wI2C_ReturnNackFlag == 0x01) && (wI2C_RxControlFlag == 0x00))
{
if(wRepeatRX == 0) //No Repeat
{
SN_I2C0->CTRL |= mskI2C_STO_STOP;
}
else if(wRepeatRX == 1) //Repeat Start
{
SN_I2C0->CTRL |= mskI2C_STA_START;
}
else if(wRepeatRX == 2) //Repeat Both
{
SN_I2C0->CTRL |= (mskI2C_STO_STOP|mskI2C_STA_START);
}
else
{
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
}
wI2C_RxControlFlag = 1;
}
else if((*bPointerFIFO < (wDeboundNum)))
{
//Return ACK
SN_I2C0->CTRL |= mskI2C_ACK; //ACK
}
else if((*bPointerFIFO >= (wDeboundNum)))
{
//Return NACK
SN_I2C0->CTRL |= mskI2C_NACK; //NACK
wI2C_ReturnNackFlag++;
}
else
{
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
}
break;
/*Error State Check*/
default:
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
break;
}
}
}
/*****************************************************************************
* Function : I2C0_Slave_Rx
* Description : Set specified value to specified bits of assigned register
* Input : *bDataFIFO - Declare RX FIFO Register
* *bPointerFIFO - Declare RX FIFO Pointer Register
* *bCommStop - Declare the Register when get the STOP information
* wNumForNack - Return NACK when getting the number of data is wNumForNack.
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C0_Slave_Rx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint32_t wNumForNack)
{
if(SN_I2C0->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_TimeoutFlag = 1;
}
else if(SN_I2C0->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_ArbitrationFlag = 1;
}
else if( SN_I2C0->STAT & mskI2C_STOP_DN_STOP) //Stop Down
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
*bCommStop = 0x01;
}
else
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
switch (SN_I2C0->STAT)
{
/* Slave addess hit for Rx */
case mskI2C_SLV_RX_MATCH_ADDR:
if(wNumForNack == 0)
{
SN_I2C0->CTRL |= mskI2C_ACK;; //ACK
}
else if(wNumForNack == 1)
{
SN_I2C0->CTRL |= mskI2C_NACK; //NACK
}
else
{
SN_I2C0->CTRL |= mskI2C_ACK; //ACK
}
break;
/* DATA has been received and ACK/NACK has been returned */
case mskI2C_RX_DN_HANDSHAKE:
*bDataFIFO = SN_I2C0->RXDATA ;
*bPointerFIFO = *bPointerFIFO + 1;
if(wNumForNack == 0)
{
SN_I2C0->CTRL |= mskI2C_ACK; //ACK
}
else if(*bPointerFIFO == (wNumForNack-1))
{
SN_I2C0->CTRL |= mskI2C_NACK; //NACK
}
else
{
SN_I2C0->CTRL |= mskI2C_ACK; //ACK
}
break;
/*Error State Check*/
default:
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
break;
}
}
}
/*****************************************************************************
* Function : I2C0_Slave_Tx
* Description : Set specified value to specified bits of assigned register
* Input : *bDataFIFO - Declare TX FIFO Register
* *bPointerFIFO - Declare TX FIFO Pointer Register
* *bCommStop - Declare the Register when get the STOP information
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C0_Slave_Tx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop)
{
if(SN_I2C0->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_TimeoutFlag = 1;
}
else if(SN_I2C0->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_ArbitrationFlag = 1;
}
else if( SN_I2C0->STAT & mskI2C_STOP_DN_STOP) //Stop Down
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
*bCommStop = 0x01;
}
else
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
switch (SN_I2C0->STAT)
{
/* Slave addess hit for Tx */
case mskI2C_SLV_TX_MATCH_ADDR:
SN_I2C0->TXDATA = *bDataFIFO;
*bPointerFIFO = *bPointerFIFO + 1;
break;
/* Received ACK */
case mskI2C_ACK_STAT_RECEIVED_ACK:
SN_I2C0->TXDATA = *bDataFIFO;
*bPointerFIFO = *bPointerFIFO + 1;
break;
/* Received NACK */
case mskI2C_NACK_STAT_RECEIVED_NACK:
SN_I2C0->CTRL |= mskI2C_ACK; //For release SCL and SDA
break;
/*Error State Check*/
default:
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
break;
}
}
}
/*****************************************************************************
* Function : I2C0_Mointer_Mode
* Description : Set specified value to specified bits of assigned register
* Input : *bDataFIFO - Declare RX FIFO Register
* *bPointerFIFO - Declare RX FIFO Pointer Register
* *bCommStop - Declare the Register when get the STOP information
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C0_Mointer_Mode(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop)
{
if(SN_I2C0->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_TimeoutFlag = 1;
}
else if(SN_I2C0->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_ArbitrationFlag = 1;
}
else if( SN_I2C0->STAT & mskI2C_STOP_DN_STOP) //Stop Down
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
*bCommStop = 0x01;
}
else
{
SN_I2C0->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
switch (SN_I2C0->STAT)
{
/* Slave addess hit for Rx */
case mskI2C_SLV_RX_MATCH_ADDR:
bI2C0_MointerAddress = SN_I2C0->RXDATA;
bI2C0_MointerAddress = bI2C0_MointerAddress >> 1;
SN_I2C0->CTRL |= mskI2C_ACK; //ACK
break;
/* Slave addess hit for Tx */
case mskI2C_SLV_TX_MATCH_ADDR:
bI2C0_MointerAddress = SN_I2C0->RXDATA;
bI2C0_MointerAddress = bI2C0_MointerAddress >> 1;
SN_I2C0->CTRL |= mskI2C_ACK; //ACK
break;
/* DATA has been received*/
case I2C_RX_DN_HANDSHAKE:
*bDataFIFO = SN_I2C0->RXDATA;
*bPointerFIFO = *bPointerFIFO + 1;
SN_I2C0->CTRL |= mskI2C_ACK; //ACK
break;
/*Error State Check*/
default:
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
break;
}
}
}

675
os/hal/ports/SN32/LLD/SN32F24x/I2C/I2C1.c Normal file
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@ -0,0 +1,675 @@
/******************** (C) COPYRIGHT 2013 SONiX *******************************
* COMPANY: SONiX
* DATE: 2013/12
* AUTHOR: SA1
* IC: SN32F240/230/220
* DESCRIPTION: I2C1 related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2013/12/17 SA1 1. First release
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240.h>
#include "I2C.h"
#include "..\..\Utility\Utility.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
//Mointer Mode
uint8_t bI2C1_MointerAddress = 0x00;
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
/*****************************************************************************
* Function : I2C1_Init
* Description : Set specified value to specified bits of assigned register
* Input : wI2C1SCLH - SCL High Time
* wI2C1SCLL - SCL Low Time
* wI2C1Mode - 0: Standard/Fast mode.1: Fast-mode Plus
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C1_Init(void)
{
//I2C1 interrupt enable
NVIC_ClearPendingIRQ(I2C1_IRQn);
NVIC_EnableIRQ(I2C1_IRQn);
NVIC_SetPriority(I2C1_IRQn,0);
//Enable HCLK for I2C1
SN_SYS1->AHBCLKEN |= (0x1 << 20); //Enable clock for I2C1
//I2C speed
SN_I2C1->SCLHT = I2C1_SCLHT;
SN_I2C1->SCLLT = I2C1_SCLLT;
//I2C enable
SN_I2C1->CTRL_b.I2CEN = I2C_I2CEN_EN;
//I2C1 address set
Set_I2C1_Address(I2C_ADD_MODE_7BIT, I2C_SLAVE0, I2C_ADDR_SLAVE_ADDR0, I2C_GCEN_DIS);
Set_I2C1_Address(I2C_ADD_MODE_7BIT, I2C_SLAVE1, I2C_ADDR_SLAVE_ADDR1, I2C_GCEN_DIS);
}
/*****************************************************************************
* Function : I2C1_Timeout_Ctrl
* Description : Set specified value to specified bits of assigned register
* Input : wI2CTo - TimeOut Value: wI2CTo * 32 * I2C_PCLK cycle
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C01_Timeout_Ctrl(uint32_t wI2CTo)
{
SN_I2C1->TOCTRL = wI2CTo;
}
/*****************************************************************************
* Function : I2C1_Monitor_Mode_Ctrl
* Description : Set specified value to specified bits of assigned register
* Input : wI2CmatchAll - 0: No use. 1: Interrupt will be generated on ANY address received.
* wI2Cscloen - 0: No use. 1: Let I2C holds the clock line low to get data.
* wI2Cmmen - 0: No use. 1: Monitor mode enable bit.
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C1_Monitor_Mode_Ctrl(uint32_t wI2CmatchAll, uint32_t wI2Cscloen, uint32_t wI2Cmmen)
{
SN_I2C1->TOCTRL = (wI2CmatchAll << 2) | (wI2Cscloen << 1) | (wI2Cmmen << 0);
}
/*****************************************************************************
* Function : Set_I2C1_Address
* Description : Set specified value to specified bits of assigned register
* Input : bI2CaddMode - 7 bits address is 0, 10 bits address is 1
* bSlaveNo - Slave address number 0, 1, 2, 3
* bSlaveAddr - Slave value
* bGCEnable - Genral call enable is 1
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void Set_I2C1_Address(uint8_t bI2CaddMode, uint8_t bSlaveNo, uint32_t bSlaveAddr, uint8_t bGCEnable)
{
volatile uint16_t hwAddressCom=0;
if(bI2CaddMode == 0)
{
hwAddressCom = bSlaveAddr << 1;
}
else
{
hwAddressCom = bSlaveAddr;
}
if(bGCEnable == 1)
{
SN_I2C1->SLVADDR0_b.GCEN = I2C_GCEN_EN;
}
else
{
SN_I2C1->SLVADDR0_b.GCEN = I2C_GCEN_DIS;
}
if(bI2CaddMode == 1)
{
SN_I2C1->SLVADDR0_b.ADD_MODE = I2C_ADD_MODE_10BIT;
}
else
{
SN_I2C1->SLVADDR0_b.ADD_MODE = I2C_ADD_MODE_7BIT;
}
switch (bSlaveNo)
{
case 0:
SN_I2C1->SLVADDR0 = hwAddressCom;
break;
case 1:
SN_I2C1->SLVADDR1 = hwAddressCom;
break;
case 2:
SN_I2C1->SLVADDR2 = hwAddressCom;
break;
case 3:
SN_I2C1->SLVADDR3 = hwAddressCom;
break;
default:
break;
}
}
/*****************************************************************************
* Function : I2C1_Enable
* Description : I2C1 enable setting
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C1_Enable(void)
{
//Enable HCLK for I2C1
SN_SYS1->AHBCLKEN |= (0x1 << 20); //Enable clock for I2C1
SN_I2C1->CTRL_b.I2CEN = I2C_I2CEN_EN; //I2C1 enable
}
/*****************************************************************************
* Function : I2C1_Disable
* Description : I2C1 disable setting
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C1_Disable(void)
{
SN_I2C1->CTRL_b.I2CEN = I2C_I2CEN_DIS; //I2C1 disable
//Disable HCLK for I2C1
SN_SYS1->AHBCLKEN &=~ (0x1 << 20); //Disable clock for I2C1
}
/*****************************************************************************
* Function : I2C1_Master_Tx
* Description : Set specified value to specified bits of assigned register
* Input : *bDataFIFO - Declare TX FIFO Register
* *bPointerFIFO - Declare TX FIFO Pointer Register
* *bCommStop - Declare the Register when get the STOP information
* bSlaveAddress - Set the Slave adress
* wTxNum - Set the Number of sending Data
* wRepeatTX - 0 : No use. 1: Next transfer with a Repated Start condition. 2: Work next transfer.
* wReTxNum - Send (wReTxNum + 1) Data when wRepeatTX is 1.
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C1_Master_Tx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint8_t bSlaveAddress, volatile uint32_t wTxNum, volatile uint32_t wRepeatTX, volatile uint32_t wReTxNum)
{
//wReTxNum = 0, Repeat once; wReTxNum = 1, Repeat twice
if(SN_I2C1->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_TimeoutFlag = 1;
}
else if(SN_I2C1->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_ArbitrationFlag = 1;
}
else if(((SN_I2C1->STAT) & (mskI2C_STA_MASTER_STA_STO)) == (mskI2C_STOP_DN_STOP)) //Stop Down
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
*bPointerFIFO = 0x00;
wI2C_MasTxCtr = 0x00;
*bCommStop = 1;
}
else if(((SN_I2C1->STAT) & (mskI2C_STA_MASTER_STA_STO)) == (mskI2C_STA_MASTER_STA_STO)) //Start and Stop Down
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
SN_I2C1->TXDATA = (bSlaveAddress << 0x01);
}
else
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
switch (SN_I2C1->STAT)
{
/* START has been transmitted and prepare SLA+W */
case (mskI2C_MST_MASTER|mskI2C_START_DN_START):
SN_I2C1->TXDATA = (bSlaveAddress << 0x01);
break;
/* SLA+W or Data has been transmitted and ACK has been received */
case (mskI2C_MST_MASTER|mskI2C_ACK_STAT_RECEIVED_ACK):
if ((*bPointerFIFO < wTxNum)&&(wI2C_MasTxCtr == 0x00))
{
SN_I2C1->TXDATA = *bDataFIFO;
*bPointerFIFO = *bPointerFIFO + 1;
}
else if ((*bPointerFIFO == wTxNum)&&(wI2C_MasTxCtr == 0x00))
{
if(wRepeatTX == 0) //No Repeat
{
SN_I2C1->CTRL |= mskI2C_STO_STOP;
}
else if(wRepeatTX == 1) //Repeat Start
{
SN_I2C1->CTRL |= mskI2C_STA_START;
wI2C_MasTxCtr++;
}
else if(wRepeatTX == 2) //Repeat Both
{
SN_I2C1->CTRL |= (mskI2C_STO_STOP|mskI2C_STA_START);
wI2C_MasTxCtr++;
}
else
{
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
}
}
else if ((*bPointerFIFO < (wTxNum+1+wReTxNum))&&(wI2C_MasTxCtr == 0x01))
{
SN_I2C1->TXDATA = *bDataFIFO;
*bPointerFIFO = *bPointerFIFO + 1;
}
else if ((*bPointerFIFO == (wTxNum+1+wReTxNum))&&(wI2C_MasTxCtr == 0x01))
{
SN_I2C1->CTRL |= mskI2C_STO_STOP;
}
else
{
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
}
break;
/* SLA+W or Data has been transmitted and NACK has been received */
case (mskI2C_MST_MASTER|mskI2C_NACK_STAT_RECEIVED_NACK):
if ((*bPointerFIFO == wTxNum)&&(wI2C_MasTxCtr == 0x00))
{
if(wRepeatTX == 0) //No Repeat
{
SN_I2C1->CTRL |= mskI2C_STO_STOP;
}
else if(wRepeatTX == 1) //Repeat Start
{
SN_I2C1->CTRL |= mskI2C_STA_START;
wI2C_MasTxCtr++;
}
else if(wRepeatTX == 2) //Repeat Both
{
SN_I2C1->CTRL |= (mskI2C_STO_STOP|mskI2C_STA_START);
wI2C_MasTxCtr++;
}
else
{
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
}
}
else if ((*bPointerFIFO == (wTxNum+1+wReTxNum))&&(wI2C_MasTxCtr == 0x01))
{
SN_I2C1->CTRL |= mskI2C_STO_STOP;
}
else
{
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
}
break;
/*Error State Check*/
default:
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
break;
}
}
}
/*****************************************************************************
* Function : I2C1_Master_Rx
* Description : Set specified value to specified bits of assigned register
* Input : *bDataFIFO - Declare RX FIFO Register
* *bPointerFIFO - Declare RX FIFO Pointer Register
* *bCommStop - Declare the Register when get the STOP information
* bSlaveAddress - Set the Slave adress
* wRxNum - Set the Number of getting Data
* wRepeatRX - 0 : No use. 1: Next transfer with a Repated Start condition 2: Work next transfer.
* wReRxNum - Get (wReRxNum + 1) data when wRepeatRX is 1.
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C1_Master_Rx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint8_t bSlaveAddress, volatile uint32_t wRxNum, volatile uint32_t wRepeatRX, volatile uint32_t wReRxNum)
{
uint32_t wDeboundNum = 0;
if(SN_I2C1->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_TimeoutFlag = 1;
}
else if(SN_I2C1->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_ArbitrationFlag = 1;
}
else if(((SN_I2C1->STAT) & (mskI2C_STA_STA_STO)) == (mskI2C_STOP_DN_STOP)) //Stop Down
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
*bPointerFIFO = 0x00;
wI2C_MasTxCtr = 0x00;
*bCommStop = 1;
wI2C_RxControlFlag = 0x00;
wI2C_ReturnNackFlag = 0x00;
}
else if(((SN_I2C1->STAT) & (mskI2C_STA_MASTER_STA_STO)) == (mskI2C_STA_MASTER_STA_STO)) //Start and Stop Down
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
SN_I2C1->TXDATA = (bSlaveAddress << 0x01) | 0x01;
}
else
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
switch (SN_I2C1->STAT)
{
/* START has been transmitted and prepare to send address */
case (mskI2C_MST_MASTER|mskI2C_START_DN_START):
SN_I2C1->TXDATA = (bSlaveAddress << 0x01) | 0x01;
break;
/* Received an ACK */
case (mskI2C_MST_MASTER|mskI2C_ACK_STAT_RECEIVED_ACK):
if((wRxNum == 1) && (wI2C_ReturnNackFlag == 0))
{
SN_I2C1->CTRL |= mskI2C_NACK; //NACK
wI2C_ReturnNackFlag++;
}
else if((wReRxNum == 0) && (wI2C_ReturnNackFlag == 1))
{
SN_I2C1->CTRL |= mskI2C_NACK; //NACK
wI2C_ReturnNackFlag++;
}
else
{
SN_I2C1->CTRL |= mskI2C_ACK; //ACK
}
break;
/* RX with ACK/NACK transfer is down */
case (mskI2C_MST_MASTER|mskI2C_RX_DN_HANDSHAKE):
*bDataFIFO = SN_I2C1->RXDATA;
*bPointerFIFO = *bPointerFIFO + 1;
if(wI2C_ReturnNackFlag == 0x00)
{
wDeboundNum = wRxNum-1;
}
else if(wI2C_ReturnNackFlag == 0x01)
{
wDeboundNum = wRxNum+wReRxNum;
}
if(wI2C_ReturnNackFlag == 0x02)
{
SN_I2C1->CTRL |= mskI2C_STO_STOP;
}
else if((wI2C_ReturnNackFlag == 0x01) && (wI2C_RxControlFlag == 0x00))
{
if(wRepeatRX == 0) //No Repeat
{
SN_I2C1->CTRL |= mskI2C_STO_STOP;
}
else if(wRepeatRX == 1) //Repeat Start
{
SN_I2C1->CTRL |= mskI2C_STA_START;
}
else if(wRepeatRX == 2) //Repeat Both
{
SN_I2C1->CTRL |= (mskI2C_STO_STOP|mskI2C_STA_START);
}
else
{
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
}
wI2C_RxControlFlag = 1;
}
else if((*bPointerFIFO < (wDeboundNum)))
{
//Return ACK
SN_I2C1->CTRL |= mskI2C_ACK; //ACK
}
else if((*bPointerFIFO >= (wDeboundNum)))
{
//Return NACK
SN_I2C1->CTRL |= mskI2C_NACK; //NACK
wI2C_ReturnNackFlag++;
}
else
{
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
}
break;
/*Error State Check*/
default:
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
break;
}
}
}
/*****************************************************************************
* Function : I2C1_Slave_Rx
* Description : Set specified value to specified bits of assigned register
* Input : *bDataFIFO - Declare RX FIFO Register
* *bPointerFIFO - Declare RX FIFO Pointer Register
* *bCommStop - Declare the Register when get the STOP information
* wNumForNack - Return NACK when getting the number of data is wNumForNack.
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C1_Slave_Rx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop, volatile uint32_t wNumForNack)
{
if(SN_I2C1->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_TimeoutFlag = 1;
}
else if(SN_I2C1->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_ArbitrationFlag = 1;
}
else if( SN_I2C1->STAT & mskI2C_STOP_DN_STOP) //Stop Down
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
*bCommStop = 0x01;
}
else
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
switch (SN_I2C1->STAT)
{
/* Slave addess hit for Rx */
case mskI2C_SLV_RX_MATCH_ADDR:
if(wNumForNack == 0)
{
SN_I2C1->CTRL |= mskI2C_ACK;; //ACK
}
else if(wNumForNack == 1)
{
SN_I2C1->CTRL |= mskI2C_NACK; //NACK
}
else
{
SN_I2C1->CTRL |= mskI2C_ACK; //ACK
}
break;
/* DATA has been received and ACK/NACK has been returned */
case mskI2C_RX_DN_HANDSHAKE:
*bDataFIFO = SN_I2C1->RXDATA ;
*bPointerFIFO = *bPointerFIFO + 1;
if(wNumForNack == 0)
{
SN_I2C1->CTRL |= mskI2C_ACK; //ACK
}
else if(*bPointerFIFO == (wNumForNack-1))
{
SN_I2C1->CTRL |= mskI2C_NACK; //NACK
}
else
{
SN_I2C1->CTRL |= mskI2C_ACK; //ACK
}
break;
/*Error State Check*/
default:
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
break;
}
}
}
/*****************************************************************************
* Function : I2C1_Slave_Tx
* Description : Set specified value to specified bits of assigned register
* Input : *bDataFIFO - Declare TX FIFO Register
* *bPointerFIFO - Declare TX FIFO Pointer Register
* *bCommStop - Declare the Register when get the STOP information
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C1_Slave_Tx(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop)
{
if(SN_I2C1->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_TimeoutFlag = 1;
}
else if(SN_I2C1->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_ArbitrationFlag = 1;
}
else if( SN_I2C1->STAT & mskI2C_STOP_DN_STOP) //Stop Down
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
*bCommStop = 0x01;
}
else
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
switch (SN_I2C1->STAT)
{
/* Slave addess hit for Tx */
case mskI2C_SLV_TX_MATCH_ADDR:
SN_I2C1->TXDATA = *bDataFIFO;
*bPointerFIFO = *bPointerFIFO + 1;
break;
/* Received ACK */
case mskI2C_ACK_STAT_RECEIVED_ACK:
SN_I2C1->TXDATA = *bDataFIFO;
*bPointerFIFO = *bPointerFIFO + 1;
break;
/* Received NACK */
case mskI2C_NACK_STAT_RECEIVED_NACK:
SN_I2C1->CTRL |= mskI2C_ACK; //For release SCL and SDA
break;
/*Error State Check*/
default:
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
break;
}
}
}
/*****************************************************************************
* Function : I2C1_Mointer_Mode
* Description : Set specified value to specified bits of assigned register
* Input : *bDataFIFO - Declare RX FIFO Register
* *bPointerFIFO - Declare RX FIFO Pointer Register
* *bCommStop - Declare the Register when get the STOP information
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2C1_Mointer_Mode(volatile uint8_t *bDataFIFO, volatile uint8_t *bPointerFIFO, volatile uint8_t *bCommStop)
{
if(SN_I2C1->STAT & mskI2C_TIMEOUT_TIMEOUT) //Timeout State
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_TimeoutFlag = 1;
}
else if(SN_I2C1->STAT & mskI2C_LOST_ARB_LOST_ARBITRATION) //ARB State
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
wI2C_ArbitrationFlag = 1;
}
else if( SN_I2C1->STAT & mskI2C_STOP_DN_STOP) //Stop Down
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
*bCommStop = 0x01;
}
else
{
SN_I2C1->STAT |= mskI2C_I2CIF_INTERRUPT; //Clear I2C flag
switch (SN_I2C1->STAT)
{
/* Slave addess hit for Rx */
case mskI2C_SLV_RX_MATCH_ADDR:
bI2C1_MointerAddress = SN_I2C1->RXDATA;
bI2C1_MointerAddress = bI2C1_MointerAddress >> 1;
SN_I2C1->CTRL |= mskI2C_ACK; //ACK
break;
/* Slave addess hit for Tx */
case mskI2C_SLV_TX_MATCH_ADDR:
bI2C1_MointerAddress = SN_I2C1->RXDATA;
bI2C1_MointerAddress = bI2C1_MointerAddress >> 1;
SN_I2C1->CTRL |= mskI2C_ACK; //ACK
break;
/* DATA has been received*/
case I2C_RX_DN_HANDSHAKE:
*bDataFIFO = SN_I2C1->RXDATA;
*bPointerFIFO = *bPointerFIFO + 1;
SN_I2C1->CTRL |= mskI2C_ACK; //ACK
break;
/*Error State Check*/
default:
wI2C_RegisterCheckError |= I2C_ERROR;
wI2C_TotalError++;
break;
}
}
}

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/******************** (C) COPYRIGHT 2014 SONiX *******************************
* COMPANY: SONiX
* DATE: 2014/02
* AUTHOR: SA1
* IC: SN32F240/730/220
* DESCRIPTION: I2S related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2013/12/17 SA1 1. First release
* 2.0 2014/02/27 SA1 1. Update I2S functions.
* 3.2 2019/05/31 SA1 1. Fix I2S_Master_Init and I2S_Slave_Init.
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240.h>
#include "I2S.h"
#include "..\..\Utility\Utility.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
/**************************************************************
* Function : I2S_Master_INIT
* Description : Set I2S as master
* Input : None
* Output : None
* Return : None
* Note : None
****************************************************************/
void I2S_Master_Init(void)
{
__I2S_ENABLE_I2SHCLK; //Enable HCLK for I2S
SN_I2S->CTRL_b.I2SEN = I2S_I2SEN_EN; //I2S enable bit
SN_I2S->CTRL_b.CHLENGTH = I2S_CHLENGTH_32BITS; //Single channel[4:0]
SN_I2S->CTRL_b.RXFIFOTH = I2S_RXFIFOTH_2; //RX FIFO Threshold level
SN_I2S->CTRL_b.TXFIFOTH = I2S_TXFIFOTH_6; //TX FIFO Threshold level
SN_I2S->CTRL_b.DL = I2S_DL_24BITS; //I2S Data Length
__I2S_RESET_RXFIFO; //Clear I2S RX FIFO
__I2S_RESET_TXFIFO; //Clear I2S TX FIFO
SN_I2S->CTRL_b.RXEN = I2S_RXEN_EN; //Receiver enable bit
SN_I2S->CTRL_b.TXEN = I2S_TXEN_EN; //Transmit enable bit
SN_I2S->CTRL_b.FORMAT=I2S_FORMAT_STANDARD; //I2S operation format
SN_I2S->CTRL_b.MS=I2S_MS_MASTER_MODE; //Master selection bit
SN_I2S->CTRL_b.MONO=I2S_MONO_STERO; //Stereo selection bit
SN_I2S->CTRL_b.MUTE=I2S_MUTE_DIS; //Mute enable bit
//I2S clk
SN_I2S->CLK = mskI2S_CLKSEL_HCLK| //I2S clock source selection
mskI2S_BCLKDIV_DIV| //MCLK/n, n = 2, 4, 6, 8, ...,512
mskI2S_MCLKSEL_I2S_PCLK| //MCLK source of master is from I2S_PCLK
mskI2S_MCLKOEN_OUTPUT_DIS| //MCLK output enable bit
mskI2S_MCLKDIV_DIV3; //MCLK = MCLK source / 6
}
/**************************************************************
* Function : I2S_Slave_Init
* Description : Set I2S as slave
* Input : None
* Output : None
* Return : None
* Note : None
****************************************************************/
void I2S_Slave_Init(void)
{
__I2S_ENABLE_I2SHCLK; //Enable HCLK for I2S
SN_I2S->CTRL_b.I2SEN = I2S_I2SEN_EN ; //I2S enable bit
SN_I2S->CTRL_b.CHLENGTH = I2S_CHLENGTH_32BITS; //Single channel[4:0]
SN_I2S->CTRL_b.RXFIFOTH = I2S_RXFIFOTH_2; //RX FIFO Threshold level
SN_I2S->CTRL_b.TXFIFOTH = I2S_TXFIFOTH_6;
SN_I2S->CTRL_b.DL = I2S_DL_24BITS; //I2S Data Length
__I2S_RESET_RXFIFO; //Clear I2S RX FIFO
__I2S_RESET_TXFIFO; //Clear I2S TX FIFO
SN_I2S->CTRL_b.RXEN = I2S_RXEN_EN; //Receiver enable bit
SN_I2S->CTRL_b.TXEN = I2S_TXEN_EN;
SN_I2S->CTRL_b.FORMAT=I2S_FORMAT_STANDARD; //I2S operation format
SN_I2S->CTRL_b.MS=I2S_MS_SLAVE_MODE; //Master selection bit
SN_I2S->CTRL_b.MONO=I2S_MONO_STERO; //Stereo selection bit
SN_I2S->CTRL_b.MUTE=I2S_MUTE_DIS;
}
/*****************************************************************************
* Function : I2S_Enable
* Description : I2S enable
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2S_Enable(void)
{
__I2S_ENABLE_I2SHCLK; //Enable HCLK for I2S
SN_I2S->CTRL_b.I2SEN = I2S_I2SEN_EN ; //I2S enable bit
__I2S_RESET_TXFIFO;
__I2S_RESET_RXFIFO;
}
/*****************************************************************************
* Function : I2S_Disable
* Description : I2S disable
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void I2S_Disable(void)
{
SN_I2S->CTRL_b.I2SEN = I2S_I2SEN_DIS; //I2S disable bit
__I2S_DISABLE_I2SHCLK; //Disable HCLK for I2S
}
/**********************************
* Function : I2S_Interrupt_Enable
* Description : I2S interrupt enable
* Input : None
* Output : None
* Return : None
* Note : None
**********************************/
void I2S_Interrupt_Enable(void)
{
SN_I2S->IC = mskI2S_RXFIFOTHIC| //Clear RXFIFOTHIF bit
mskI2S_TXFIFOTHIC| //Clear TXFIFOTHIF bit
mskI2S_RXFIFOUDIC| //Clear RXFIFOOUDIF bit
mskI2S_TXFIFOOVIC; //Clear TXFIFOOVIF bit
SN_I2S->IE = mskI2S_TXFIFOOVFIEN_EN| //TX FIFO overflow interrupt enable bit
mskI2S_RXFIFOUDFIEN_EN| //RX FIFO underflow interrupt enable bit
mskI2S_TXFIFOTHIEN_EN| //TX FIFO threshold interrupt enable bit
mskI2S_RXFIFOTHIEN_EN; //RX FIFO threshold interrupt enable bit
}

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#ifndef __SN32F240_I2S_H
#define __SN32F240_I2S_H
/*_____ I N C L U D E S ____________________________________________________*/
/*_____ D E F I N I T I O N S ______________________________________________*/
/*
Base Address: 0x4001 A000
*/
/* I2S Control register <I2S_CTRL> (0x00) */
#define I2S_START_DIS 0 //[0:0]Start Transmit/Receive bit
#define I2S_START_EN 1
#define mskI2S_START_DIS (mskI2S_START_DIS<<0)
#define mskI2S_START_EN (mskI2S_START_EN<<0)
#define I2S_MUTE_DIS 0 //[1:1]Mute enable bit
#define I2S_MUTE_EN 1
#define mskI2S_MUTE_DIS (I2S_MUTE_DIS<<1)
#define mskI2S_MUTE_EN (I2S_MUTE_EN<<1)
#define I2S_MONO_STERO 0 //[2:2]Mono/Stereo selection bit
#define I2S_MONO_MONO 1
#define mskI2S_MONO_STERO (I2S_MONO_STERO<<2)
#define mskI2S_MONO_MONO (I2S_MONO_MONO<<2)
#define I2S_MS_MASTER_MODE 0 //[3:3]Master/Slave selection bit
#define I2S_MS_SLAVE_MODE 1
#define mskI2S_MS_MASTER_MODE (I2S_MS_MASTER_MODE<<3)
#define mskI2S_MS_SLAVE_MODE (I2S_MS_SLAVE_MODE<<3)
//[5:4]I2S operation format
#define I2S_FORMAT_STANDARD 0 //Standard I2S format
#define I2S_FORMAT_LEFTJUST 1 //Left-justified format
#define I2S_FORMAT_RIGHTJUST 2 //Right(MSB)-justified format
#define mskI2S_FORMAT_STANDARD (I2S_FORMAT_STANDARD<<4)
#define mskI2S_FORMAT_LEFTJUST (I2S_FORMAT_LEFTJUST<<4)
#define mskI2S_FORMAT_RIGHTJUST (I2S_FORMAT_RIGHTJUST<<4)
#define I2S_TXEN_DIS 0 //[6:6]Transmit enable bit
#define I2S_TXEN_EN 1
#define mskI2S_TXEN_DIS (I2S_TXEN_DIS<<6)
#define mskI2S_TXEN_EN (I2S_TXEN_EN<<6)
#define I2S_RXEN_DIS 0 //[7:7]Receiver enable bit
#define I2S_RXEN_EN 1
#define mskI2S_RXEN_DIS (I2S_RXEN_DIS<<7)
#define mskI2S_RXEN_EN (I2S_RXEN_EN<<7)
#define I2S_CLRTXFIFO_RESET_TXFIFO 1 //[8:8]Clear I2S TX FIFO
#define I2S_CLRRXFIFO_RESET_RXFIFO 1 //[9:9]Clear I2S TX FIFO
#define I2S_DL_8BITS 0 //[11:10]I2S Data Length
#define I2S_DL_16BITS 1
#define I2S_DL_24BITS 2
#define I2S_DL_32BITS 3
#define I2S_TXFIFOTH_0 0 //[14:12]TX FIFO Threshold level[2:0]
#define I2S_TXFIFOTH_1 1
#define I2S_TXFIFOTH_2 2
#define I2S_TXFIFOTH_3 3
#define I2S_TXFIFOTH_4 4
#define I2S_TXFIFOTH_5 5
#define I2S_TXFIFOTH_6 6
#define I2S_TXFIFOTH_7 7
#define I2S_RXFIFOTH_0 0 //[18:16]RX FIFO Threshold level[2:0]
#define I2S_RXFIFOTH_1 1
#define I2S_RXFIFOTH_2 2
#define I2S_RXFIFOTH_3 3
#define I2S_RXFIFOTH_4 4
#define I2S_RXFIFOTH_5 5
#define I2S_RXFIFOTH_6 6
#define I2S_RXFIFOTH_7 7
#define I2S_CHLENGTH_8BITS 7 //[24:20]Bit number of single channel[4:0]
#define I2S_CHLENGTH_9BITS 8
#define I2S_CHLENGTH_10BITS 9
#define I2S_CHLENGTH_11BITS 10
#define I2S_CHLENGTH_12BITS 11
#define I2S_CHLENGTH_13BITS 12
#define I2S_CHLENGTH_14BITS 13
#define I2S_CHLENGTH_15BITS 14
#define I2S_CHLENGTH_16BITS 15
#define I2S_CHLENGTH_17BITS 16
#define I2S_CHLENGTH_18BITS 17
#define I2S_CHLENGTH_19BITS 18
#define I2S_CHLENGTH_20BITS 19
#define I2S_CHLENGTH_21BITS 20
#define I2S_CHLENGTH_22BITS 21
#define I2S_CHLENGTH_23BITS 22
#define I2S_CHLENGTH_24BITS 23
#define I2S_CHLENGTH_25BITS 24
#define I2S_CHLENGTH_26BITS 25
#define I2S_CHLENGTH_27BITS 26
#define I2S_CHLENGTH_28BITS 27
#define I2S_CHLENGTH_29BITS 28
#define I2S_CHLENGTH_30BITS 29
#define I2S_CHLENGTH_31BITS 30
#define I2S_CHLENGTH_32BITS 31
#define I2S_I2SEN_DIS 0 //[31:31]I2S enable bit
#define I2S_I2SEN_EN 1
#define mskI2S_I2SEN_DIS (I2S_I2SEN_DIS<<31)
#define mskI2S_I2SEN_EN (I2S_I2SEN_EN<<31)
/* I2S Clock register <I2S_CLK> (0x04) */
//[2:0]MCLK divider
#define I2S_MCLKDIV_DIV0 0 //MCLK = MCLK source
#define mskI2S_MCLKDIV_DIV0 (I2S_MCLKDIV_DIV0<<0)
#define I2S_MCLKDIV_DIV1 1 //MCLK = MCLK source / 2
#define mskI2S_MCLKDIV_DIV1 (I2S_MCLKDIV_DIV1<<0)
#define I2S_MCLKDIV_DIV2 2 //MCLK = MCLK source / 4
#define mskI2S_MCLKDIV_DIV2 (I2S_MCLKDIV_DIV2<<0)
#define I2S_MCLKDIV_DIV3 3 //MCLK = MCLK source / 6
#define mskI2S_MCLKDIV_DIV3 (I2S_MCLKDIV_DIV3<<0)
#define I2S_MCLKDIV_DIV4 4 //MCLK = MCLK source / 8
#define mskI2S_MCLKDIV_DIV4 (I2S_MCLKDIV_DIV4<<0)
#define I2S_MCLKDIV_DIV5 5 //MCLK = MCLK source / 10
#define mskI2S_MCLKDIV_DIV5 (I2S_MCLKDIV_DIV5<<0)
#define I2S_MCLKDIV_DIV6 6 //MCLK = MCLK source / 12
#define mskI2S_MCLKDIV_DIV6 (I2S_MCLKDIV_DIV6<<0)
#define I2S_MCLKDIV_DIV7 7 //MCLK = MCLK source / 14
#define mskI2S_MCLKDIV_DIV7 (I2S_MCLKDIV_DIV7<<0)
#define I2S_MCLKOEN_OUTPUT_DIS 0 //[3:3]MCLK output enable bit
#define I2S_MCLKOEN_OUTPUT_EN 1
#define mskI2S_MCLKOEN_OUTPUT_DIS (I2S_MCLKOEN_OUTPUT_DIS<<3)
#define mskI2S_MCLKOEN_OUTPUT_EN (I2S_MCLKOEN_OUTPUT_EN<<3)
//[4:4]MCLK source selection bit
#define I2S_MCLKSEL_I2S_PCLK 0 //MCLK source of master is from I2S_PCLK
#define I2S_MCLKSEL_GPIO 1 //MCLK source of master is from GPIO
#define mskI2S_MCLKSEL_I2S_PCLK (I2S_MCLKSEL_I2S_PCLK<<4)
#define mskI2S_MCLKSEL_GPIO (I2S_MCLKSEL_GPIO<<4)
//[15:8]BCLK divider
#define I2S_BCLKDIV_DIV 0 // MCLK/n, n = 2, 4, 6, 8, ...,512
#define mskI2S_BCLKDIV_DIV (I2S_BCLKDIV_DIV<<8)
//[16:16]I2S clock source selection
#define I2S_CLKSEL_HCLK 0 //HCLK
#define I2S_CLKSEL_EHS 1 //EHS
#define mskI2S_CLKSEL_HCLK (I2S_CLKSEL_HCLK<<16)
#define mskI2S_CLKSEL_EHS (I2S_CLKSEL_EHS<<16)
/* I2S Status register <I2S_STATUS> (0x08) */
#define mskI2S_I2SINT (0x1<<0) //I2S interrupt flag
#define mskI2S_RIGHTCH (0x1<<1) //Current channel status
#define mskI2S_TXFIFOTHF (0x1<<6) //TX FIFO threshold flag
#define mskI2S_RXFIFOTHF (0x1<<7) //RX FIFO threshold flag
#define mskI2S_TXFIFOFULL (0x1<<8) //TX FIFO full flag
#define mskI2S_RXFIFOFULL (0x1<<9) //RX FIFO full flag
#define mskI2S_TXFIFOEMPTY (0x1<<10) //TX FIFO empty flag
#define mskI2S_RXFIFOEMPTY (0x1<<11) //RX FIFO empty flag
#define mskI2S_TXFIFOLV (0xf<<12) //TX FIFO used level
#define mskI2S_RXFIFOLV (0xf<<17) //RX FIFO used level
/* I2S Interrupt Enable register <I2S_IE> (0x0C) */
#define I2S_TXFIFOOVFIEN_DIS 0 //[4:4]TX FIFO overflow interrupt enable bit
#define I2S_TXFIFOOVFIEN_EN 1
#define mskI2S_TXFIFOOVFIEN_DIS (I2S_TXFIFOOVFIEN_DIS<<4)
#define mskI2S_TXFIFOOVFIEN_EN (I2S_TXFIFOOVFIEN_EN<<4)
#define I2S_RXFIFOUDFIEN_DIS 0 //[5:5]RX FIFO underflow interrupt enable bit
#define I2S_RXFIFOUDFIEN_EN 1
#define mskI2S_RXFIFOUDFIEN_DIS (I2S_RXFIFOUDFIEN_DIS<<5)
#define mskI2S_RXFIFOUDFIEN_EN (I2S_RXFIFOUDFIEN_EN<<5)
#define I2S_TXFIFOTHIEN_DIS 0 //[6:6]TX FIFO threshold interrupt enable bit
#define I2S_TXFIFOTHIEN_EN 1
#define mskI2S_TXFIFOTHIEN_DIS (I2S_TXFIFOTHIEN_DIS<<6)
#define mskI2S_TXFIFOTHIEN_EN (I2S_TXFIFOTHIEN_EN<<6)
#define I2S_RXFIFOTHIEN_DIS 0 //[7:7]RX FIFO threshold interrupt enable bit
#define I2S_RXFIFOTHIEN_EN 1
#define mskI2S_RXFIFOTHIEN_DIS (I2S_RXFIFOTHIEN_DIS<<7)
#define mskI2S_RXFIFOTHIEN_EN (I2S_RXFIFOTHIEN_EN<<7)
/* I2S Raw Interrupt Status register <I2S_RIS> (0x10) */
/* I2S Interrupt Clear register <I2S_IC> (0x14) */
#define mskI2S_TXFIFOOVIF (0x1<<4) //TX FIFO overflow interrupt flag
#define mskI2S_TXFIFOOVIC mskI2S_TXFIFOOVIF
#define mskI2S_RXFIFOUDIF (0x1<<5) //RX FIFO underflow interrupt flag
#define mskI2S_RXFIFOUDIC mskI2S_RXFIFOUDIF
#define mskI2S_TXFIFOTHIF (0x1<<6) //TX FIFO threshold interrupt flag
#define mskI2S_TXFIFOTHIC mskI2S_TXFIFOTHIF
#define mskI2S_RXFIFOTHIF (0x1<<7) //RX FIFO threshold interrupt flag
#define mskI2S_RXFIFOTHIC mskI2S_RXFIFOTHIF
/*_____ M A C R O S ________________________________________________________*/
//I2S HCLK Enable/Disable
#define __I2S_ENABLE_I2SHCLK SN_SYS1->AHBCLKEN |= (1<<22)
#define __I2S_DISABLE_I2SHCLK SN_SYS1->AHBCLKEN &= ~(1<<22)
//Reset I2S FIFO
#define __I2S_RESET_TXFIFO (SN_I2S->CTRL_b.CLRTXFIFO = I2S_CLRTXFIFO_RESET_TXFIFO)
#define __I2S_RESET_RXFIFO (SN_I2S->CTRL_b.CLRRXFIFO = I2S_CLRRXFIFO_RESET_RXFIFO)
//I2S Start
#define __I2S_START (SN_I2S->CTRL_b.START = 1)
/*_____ D E C L A R A T I O N S ____________________________________________*/
void I2S_Master_Init(void);
void I2S_Slave_Init(void);
void I2S_Enable(void);
void I2S_Disable(void);
void I2S_Interrupt_Enable(void);
#endif /*__SN32F240_I2S_H*/

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/******************** (C) COPYRIGHT 2013 SONiX *******************************
* COMPANY: SONiX
* DATE: 2013/12
* AUTHOR: SA1
* IC: SN32F240/230/220
* DESCRIPTION: LCD related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2013/12/17 SA1 1. First release
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240.h>
#include "LCD.h"
#include "..\..\System\SYS_con_drive.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
#if LCD_TYPE == LCD_R_TYPE
/***********************************************************************************
* Function : LCD_RtypeInit
* Description : Initialization of R-type LCD driver
* Input : None
* Output : None
* Return : None
* Note : User shall follow the notice in 16.6 R-TYPE LCD APPLICATION CIRCUIT
* to take care of the circuit.
***********************************************************************************/
void LCD_RtypeInit(void)
{
__LCD_ENABLE_LCDHCLK; //Enable HCLK for LCD
//<-------------------- TODO: User modify on demand BEGIN -------------------->
//Setup LCD Driving ability, Clock rate, Duty, Bias, Type
SN_LCD->CTRL = (mskLCD_DRIVEP_LOW|mskLCD_RATE_DIV64|mskLCD_ONE_FOURTH_DUTY|mskLCD_ONE_THIRD_BIAS|mskLCD_R_TYPE);
LCD_SelectClockSource(LCD_CLOCK_ILRC); //Setup LCD Clock source
//Setup ITB bit, R-type resistance
SN_LCD->CTRL1 = (0|mskLCD_REF_400K); //Only value 0 is allowed for ITB bit
__LCD_SEGMENT_GROUP1_ENABLE; //Enable SEG12~23 (P0.10~P0.15, P1.0~P1.5) as LCD pins
__LCD_SEGMENT_GROUP2_ENABLE; //Enable SEG24~31 (P0.0~P0.7) as LCD pins
//<-------------------- TODO: User modify on demand END -------------------->
__LCD_ENABLE; //Enable LCD
}
#endif
#if LCD_TYPE == LCD_1C_TYPE
/***********************************************************************************
* Function : LCD_1CtypeInit
* Description : Initialization of 1C-type LCD driver
* Input : None
* Output : None
* Return : None
* Note : User shall follow the notice in 16.7 C-TYPE LCD APPLICATION CIRCUIT
* to take care of the circuit.
***********************************************************************************/
void LCD_1CtypeInit(void)
{
__LCD_ENABLE_LCDHCLK; //Enable HCLK for LCD
//<-------------------- TODO: User modify on demand BEGIN -------------------->
//Setup LCD Driving ability, Clock rate, Duty, Bias, Type
SN_LCD->CTRL = (mskLCD_DRIVEP_LOW|mskLCD_RATE_DIV64|mskLCD_ONE_FOURTH_DUTY|
mskLCD_ONE_THIRD_BIAS|mskLCD_1C_TYPE);
LCD_SelectClockSource(LCD_CLOCK_ILRC); //Setup LCD Clock source
//Setup IT1 bits, IT2 bits, VCP
SN_LCD->CCTRL1 = (0x44020000|mskLCD_1C_VCP_3P3V);
__LCD_SEGMENT_GROUP1_ENABLE; //Enable SEG12~23 (P0.10~P0.15, P1.0~P1.5) as LCD pins
__LCD_SEGMENT_GROUP2_ENABLE; //Enable SEG24~31 (P0.0~P0.7) as LCD pins
//<-------------------- TODO: User modify on demand END -------------------->
SN_LCD->CCTRL2 = 4; //Only value 0x4 is allowed
__LCD_ENABLE; //Enable LCD
}
#endif
#if LCD_TYPE == LCD_4C_TYPE
/***********************************************************************************
* Function : LCD_4CtypeInit
* Description : Initialization of 4C-type LCD driver
* Input : None
* Output : None
* Return : None
* Note : User shall follow the notice in 16.7 C-TYPE LCD APPLICATION CIRCUIT
* to take care of the circuit.
***********************************************************************************/
void LCD_4CtypeInit(void)
{
__LCD_ENABLE_LCDHCLK; //Enable HCLK for LCD
//<-------------------- TODO: User modify on demand BEGIN -------------------->
//Setup LCD Driving ability, Clock rate, Duty, Bias, Type
SN_LCD->CTRL = (mskLCD_DRIVEP_LOW|mskLCD_RATE_DIV64|mskLCD_ONE_FOURTH_DUTY|
mskLCD_ONE_THIRD_BIAS|mskLCD_4C_TYPE);
LCD_SelectClockSource(LCD_CLOCK_ILRC); //Setup LCD Clock source
//Setup IT1 bits, IT2 bits, VCP
SN_LCD->CCTRL1 = (0x44020000|mskLCD_4C_VCP_3P0V);
__LCD_SEGMENT_GROUP1_ENABLE; //Enable SEG12~23 (P0.10~P0.15, P1.0~P1.5) as LCD pins
__LCD_SEGMENT_GROUP2_ENABLE; //Enable SEG24~31 (P0.0~P0.7) as LCD pins
//<-------------------- TODO: User modify on demand END -------------------->
SN_LCD->CCTRL2 = 4; //Only value 0x4 is allowed
__LCD_ENABLE; //Enable LCD
}
#endif
/***********************************************************************************
* Function : LCD_SelectClockSource
* Description : Select LCD clcok source
* Input : LCD clock source - LCD_CLOCK_ILRC or LCD_CLOCK_ELS
* Output : None
* Return : None
* Note : None
***********************************************************************************/
void LCD_SelectClockSource(uint32_t src)
{
if (src == LCD_CLOCK_ELS)
SYS0_EnableELSXtal();
SN_LCD->CTRL_b.LCDCLK = src;
}
/***********************************************************************************
* Function : LCD_FrameInterruptEnable
* Description : LCD Frame interrupt enable function
* Input : CEN - Enable/Disable counter (ENABLE or DISABLE)
* FCT - Frame counter threshold value
* IE - LCD interrupt Enable/Disable (ENABLE or DISABLE)
* Output : None
* Return : None
* Note : 0 < FCT < 32
***********************************************************************************/
void LCD_SetFrameCounterInterrupt(uint32_t CEN, uint32_t FCT, uint32_t IE)
{
if (IE == ENABLE)
{
NVIC_ClearPendingIRQ(LCD_IRQn);
NVIC_EnableIRQ(LCD_IRQn);
}
SN_LCD->FCC = (CEN | (FCT<<1) | (IE<<7));
}
/*****************************************************************************
* Function : LCD_IRQHandler
* Description : ISR of LCD frame interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
__irq void LCD_IRQHandler(void)
{
SN_LCD->RIS = 0; //Write 0 to clear LCD interurpt flag
}

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#ifndef __SN32F240_LCD_H
#define __SN32F240_LCD_H
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240.h>
#include <SN32F200_Def.h>
/*_____ D E F I N I T I O N S ______________________________________________*/
#define LCD_TYPE LCD_R_TYPE //LCD_R_TYPE, LCD_1C_TYPE, or LCD_4C_TYPE
//LCD Panel driving ability
#define LCD_DRIVEP_STRONG 0
#define LCD_DRIVEP_MEDIUM 1
#define LCD_DRIVEP_LOW 3
#define mskLCD_DRIVEP_STRONG (LCD_DRIVEP_STRONG<<28)
#define mskLCD_DRIVEP_MEDIUM (LCD_DRIVEP_MEDIUM<<28)
#define mskLCD_DRIVEP_LOW (LCD_DRIVEP_LOW<<28)
//LCD_PCLK rate
#define LCD_RATE_DIV64 0
#define LCD_RATE_DIV128 1
#define mskLCD_RATE_DIV64 (LCD_RATE_DIV64<<11)
#define mskLCD_RATE_DIV128 (LCD_RATE_DIV128<<11)
//LCD Clock source
#define LCD_CLOCK_ILRC 0
#define LCD_CLOCK_ELS 1
#define mskLCD_CLOCK_ILRC (LCD_CLOCK_ILRC<<10)
#define mskLCD_CLOCK_ELS (LCD_CLOCK_ELS<<10)
//LCD Duty
#define LCD_HALF_DUTY 1 // 1/2 duty
#define LCD_ONE_THIRD_DUTY 2 // 1/3 duty
#define LCD_ONE_FOURTH_DUTY 3 // 1/4 duty
#define mskLCD_HALF_DUTY (LCD_HALF_DUTY<<8)
#define mskLCD_ONE_THIRD_DUTY (LCD_ONE_THIRD_DUTY<<8)
#define mskLCD_ONE_FOURTH_DUTY (LCD_ONE_FOURTH_DUTY<<8)
//LCD Bias
#define LCD_ONE_THIRD_BIAS 0 // 1/3 bias
#define LCD_HALF_BIAS 1 // 1/2 bias
#define mskLCD_ONE_THIRD_BIAS (LCD_ONE_THIRD_BIAS<<4)
#define mskLCD_HALF_BIAS (LCD_HALF_BIAS<<4)
//LCD Type
#define LCD_R_TYPE 0
#define LCD_4C_TYPE 1
#define LCD_1C_TYPE 2
#define mskLCD_R_TYPE (LCD_R_TYPE<<2)
#define mskLCD_4C_TYPE (LCD_4C_TYPE<<2)
#define mskLCD_1C_TYPE (LCD_1C_TYPE<<2)
//LCD R-type resistance
#define LCD_REF_400K 0
#define LCD_REF_200K 1
#define LCD_REF_100K 2
#define LCD_REF_35K 3
#define mskLCD_REF_400K (LCD_REF_400K<<1)
#define mskLCD_REF_200K (LCD_REF_200K<<1)
#define mskLCD_REF_100K (LCD_REF_100K<<1)
#define mskLCD_REF_35K (LCD_REF_35K<<1)
//LCD 1C-type VCP
#define mskLCD_1C_VCP_2P7V 0
#define mskLCD_1C_VCP_2P8V 1
#define mskLCD_1C_VCP_2P9V 2
#define mskLCD_1C_VCP_3P0V 3
#define mskLCD_1C_VCP_3P1V 4
#define mskLCD_1C_VCP_3P2V 5
#define mskLCD_1C_VCP_3P3V 6
#define mskLCD_1C_VCP_3P4V 7
//LCD 4C-type VCP
#define mskLCD_4C_VCP_2P7V 0
#define mskLCD_4C_VCP_2P8V 1
#define mskLCD_4C_VCP_2P9V 2
#define mskLCD_4C_VCP_3P0V 3
#define mskLCD_4C_VCP_3P06V 4
#define mskLCD_4C_VCP_3P14V 5
#define mskLCD_4C_VCP_3P2V 6
#define mskLCD_4C_VCP_3P3V 7
#define mskLCD_4C_VCP_3P4V 8
#define mskLCD_4C_VCP_3P6V 9
#define mskLCD_4C_VCP_3P8V 10
#define mskLCD_4C_VCP_4P0V 11
#define mskLCD_4C_VCP_4P2V 12
#define mskLCD_4C_VCP_4P4V 13
#define mskLCD_4C_VCP_4P7V 14
#define mskLCD_4C_VCP_5P0V 15
//LCD Frame Interrupt Enable/Disable
#define LCD_FRAME_IE_ENABLE 1
#define LCD_FRAME_IE_DISABLE 0
#define mskLCD_FRAME_IE_ENABLE (LCD_FRAME_IE_ENABLE<<7)
#define mskLCD_FRAME_IE_DISABLE (LCD_FRAME_IE_DISABLE<<7)
//LCD Frame Counter Enable/Disable
#define LCD_FRAME_COUNTER_ENABLE 1
#define LCD_FRAME_COUNTER_DISABLE 0
#define mskLCD_FRAME_COUNTER_ENABLE LCD_FRAME_COUNTER_ENABLE
#define mskLCD_FRAME_COUNTER_DISABLE LCD_FRAME_COUNTER_DISABLE
//LCD Frame Counter Threshold
#define LCD_FRAME_COUNTER_THRESHOLD 31 //0 < LCD_FRAME_COUNTER_THRESHOLD < 32
/*_____ M A C R O S ________________________________________________________*/
//LCD HCLK Enable/Disable
#define __LCD_ENABLE_LCDHCLK SN_SYS1->AHBCLKEN |= (1<<2)
#define __LCD_DISABLE_LCDHCLK SN_SYS1->AHBCLKEN &= ~(1<<2)
//LCD Driver Enable/Disable
#define __LCD_ENABLE SN_LCD->CTRL |= 0x1
#define __LCD_DISENABLE SN_LCD->CTRL &= ~0x1
//LCD SEGMENT Group 2 Enable/Disable
#define __LCD_SEGMENT_GROUP2_ENABLE SN_LCD->CTRL_b.SEGSEL2 = ENABLE
#define __LCD_SEGMENT_GROUP2_DISABLE SN_LCD->CTRL_b.SEGSEL2 = DISABLE
//LCD SEGMENT Group 1 Enable/Disable
#define __LCD_SEGMENT_GROUP1_ENABLE SN_LCD->CTRL_b.SEGSEL1 = ENABLE
#define __LCD_SEGMENT_GROUP1_DISABLE SN_LCD->CTRL_b.SEGSEL1 = DISABLE
//LCD Blank mode Enable/Disable
#define __LCD_DISPLAY_BLANK_ENABLE SN_LCD->CTRL1_b.LCDBNK = ENABLE
#define __LCD_DISPLAY_BLANK_DISABLE SN_LCD->CTRL1_b.LCDBNK = DISABLE
/*_____ D E C L A R A T I O N S ____________________________________________*/
void LCD_RtypeInit(void);
void LCD_1CtypeInit(void);
void LCD_4CtypeInit(void);
void LCD_SelectClockSource(uint32_t src);
void LCD_SetFrameCounterInterrupt(uint32_t CEN, uint32_t FCT, uint32_t IE);
#endif /*__SN32F760_PMU_H*/

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/******************** (C) COPYRIGHT 2013 SONiX *******************************
* COMPANY: SONiX
* DATE: 2013/12
* AUTHOR: SA1
* IC: SN32F240/230/220
* DESCRIPTION: RTC related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2013/12/17 SA1 First release
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240.h>
#include "RTC.h"
#include "..\..\System\SYS_con_drive.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
/*****************************************************************************
* Function : RTC_IRQHandler
* Description : None
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
__irq void RTC_IRQHandler(void)
{
if(SN_RTC->RIS & mskRTC_SECIF)
{
SN_GPIO0->DATA_b.DATA0 = ~SN_GPIO0->DATA_b.DATA0;
SN_RTC->IC = mskRTC_SECIC; //Clear Second interrupt status
}
if(SN_RTC->RIS & mskRTC_ALMIF)
{
SN_GPIO0->DATA_b.DATA1 = ~SN_GPIO0->DATA_b.DATA1;
SN_RTC->IC = mskRTC_ALMIC; //Clear Alarm interrupt status
}
if(SN_RTC->RIS & mskRTC_OVFIF)
{
SN_GPIO0->DATA_b.DATA2 = ~SN_GPIO0->DATA_b.DATA2;
SN_RTC->IC = mskRTC_OVFIC; //Clear Overflow interrupt status
}
}
/*****************************************************************************
* Function : RTC_Initial
* Description : RTC initial set
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void RTC_Init(void)
{
__RTC_ENABLE_RTCHCLK; //Enable HCLK for RTC
#if RTC_MODE == SECOND //Second will occur every 1 second
RTC_SelectClockSource(RTC_CLKSEL_ELS); //Clock Source select
SN_RTC->IE = mskRTC_SECIE_ENABLE; //Enable Second Interrupt
__RTC_SECCNTV(32767); //Second counter reload value
#endif
#if RTC_MODE == ALARM //Alarm will occur after 10 seconds
RTC_SelectClockSource(RTC_CLKSEL_ELS); //Clock Source select
SN_RTC->IE = mskRTC_ALMIE_ENABLE; //Enable Alarm Interrupt
__RTC_SECCNTV(32767); //Second counter reload value
__RTC_ALMCNTV(9); //Alarm counter reload value
#endif
#if RTC_MODE == OVERFLOW //Overflow will occur in 54975.58139 seconds(15.271 hours)
RTC_SelectClockSource(RTC_CLKSEL_EHS); //Clock Source select
SN_RTC->IE =
(mskRTC_OVFIE_ENABLE | mskRTC_ALMIE_ENABLE); //Enable Overflow Interrupt
__RTC_SECCNTV(1); //Second counter reload value & Second will occur in 12.8u second
__RTC_ALMCNTV(75000000); //Alarm counter reload value & Alarm will occur in 960 seconds(16 minutes)
#endif
//Enable RTC NVIC interrupt
RTC_NvicEnable();
__RTC_ENABLE; //Enable RTC
}
/***********************************************************************************
* Function : RTC_SelectClockSource
* Description : Select RTC clcok source
* Input : RTC clock source -
RTC_CLKSEL_ILRC or RTC_CLKSEL_ELS or RTC_CLKSEL_EHS
* Output : None
* Return : None
* Note : None
***********************************************************************************/
void RTC_SelectClockSource(uint32_t src)
{
if (src == RTC_CLKSEL_ELS)
SYS0_EnableELSXtal();
else if (src == RTC_CLKSEL_EHS)
SYS0_EnableEHSXtal(SYS0_EHS_FREQ_DRIVE_HIGH);
SN_RTC->CLKS = src; //clock source select
}
/*****************************************************************************
* Function : RTC_NvicEnable
* Description : Enable RTC interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void RTC_NvicEnable(void)
{
NVIC_ClearPendingIRQ(RTC_IRQn);
NVIC_EnableIRQ(RTC_IRQn);
NVIC_SetPriority(RTC_IRQn,0); // Set interrupt priority (default)
}
/*****************************************************************************
* Function : RTC_NvicDisable
* Description : Disable RTC interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void RTC_NvicDisable(void)
{
NVIC_DisableIRQ(RTC_IRQn);
}

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#ifndef __SN32F240_RTC_H
#define __SN32F240_RTC_H
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240.h>
/*_____ D E F I N I T I O N S ______________________________________________*/
#define SECOND 0
#define ALARM 1
#define OVERFLOW 2
#define RTC_MODE SECOND //SECOND, ALARM, OVERFLOW
//RTC enable
#define mskRTC_RTCEN_DISABLE 0
#define mskRTC_RTCEN_ENABLE 1
//RTC Clock source
#define RTC_CLKSEL_ILRC 0
#define RTC_CLKSEL_ELS 1
#define RTC_CLKSEL_EHS 3
//RTC Interrupt Enable/Disable
#define RTC_IE_ENABLE 1
#define RTC_IE_DISABLE 0
#define mskRTC_SECIE_ENABLE RTC_IE_ENABLE
#define mskRTC_SECIE_DISABLE RTC_IE_DISABLE
#define mskRTC_ALMIE_ENABLE (RTC_IE_ENABLE<<1)
#define mskRTC_ALMIE_DISABLE (RTC_IE_DISABLE<<1)
#define mskRTC_OVFIE_ENABLE (RTC_IE_ENABLE<<2)
#define mskRTC_OVFIE_DISABLE (RTC_IE_DISABLE<<2)
#define mskRTC_SECIF (0x1<<0) //Interrupt flag for Second
#define mskRTC_ALMIF (0x1<<1) //Interrupt flag for Alarm
#define mskRTC_OVFIF (0x1<<2) //Interrupt flag for Overflow
#define mskRTC_SECIC mskRTC_SECIF
#define mskRTC_ALMIC mskRTC_ALMIF
#define mskRTC_OVFIC mskRTC_OVFIF
/*_____ M A C R O S ________________________________________________________*/
//LCD HCLK Enable/Disable
#define __RTC_ENABLE_RTCHCLK (SN_SYS1->AHBCLKEN |= (1<<23))
#define __RTC_DISABLE_RTCHCLK (SN_SYS1->AHBCLKEN &= ~(1<<23))
//RTC Enable/Disable
#define __RTC_ENABLE (SN_RTC->CTRL |= mskRTC_RTCEN_ENABLE)
#define __RTC_SECCNTV(value) (SN_RTC->SECCNTV = value)
#define __RTC_ALMCNTV(value) (SN_RTC->ALMCNTV = value)
/*_____ D E C L A R A T I O N S ____________________________________________*/
void RTC_Init(void);
void RTC_SelectClockSource(uint32_t src);
void RTC_NvicEnable(void);
void RTC_NvicDisable(void);
#endif /*__SN32F240_RTC_H*/

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#ifndef __SN32F240_SSP_H
#define __SN32F240_SSP_H
/*_____ I N C L U D E S ____________________________________________________*/
/*_____ D E F I N I T I O N S ______________________________________________*/
/*
Base Address: 0x4001 C000 (SSP0)
0x4005 8000 (SSP1)
*/
/* SSP n Control register 0 <SSPn_CTRL0> (0x00) */
#define SSP_SSPEN_DIS 0 //[0:0] SSP enable bit
#define SSP_SSPEN_EN 1
#define mskSSP_SSPEN_DIS (SSP_SSPEN_DIS<<0)
#define mskSSP_SSPEN_EN (SSP_SSPEN_EN<<0)
//[1:1] Loop back mode disable
#define SSP_LOOPBACK_DIS 0 //Disable
#define SSP_LOOPBACK_EN 1 //Data input from data output
#define mskSSP_LOOPBACK_DIS (SSP_LOOPBACK_DIS<<1)
#define mskSSP_LOOPBACK_EN (SSP_LOOPBACK_EN<<1)
//[2:2] Slave data output disable bit (ONLY used in slave mode)
#define SSP_SDODIS_EN 0 //Enable slave data output
#define SSP_SDODIS_DIS 1 //Disable slave data output. (MISO=0)
#define mskSSP_SDODIS_EN (SSP_SDODIS_EN<<2)
#define mskSSP_SDODIS_DIS (SSP_SDODIS_DIS<<2)
#define SSP_MS_MASTER_MODE 0 //[3:3] Master/Slave selection bit
#define SSP_MS_SLAVE_MODE 1
#define mskSSP_MS_MASTER_MODE (SSP_MS_MASTER_MODE<<3)
#define mskSSP_MS_SLAVE_MODE (SSP_MS_SLAVE_MODE<<3)
#define SSP_FORMAT_SPI_MODE 0 //[4:4] Interface format
#define SSP_FORMAT_SSP_MODE 1
#define mskSSP_FORMAT_SPI_MODE (SSP_FORMAT_SPI_MODE<<4)
#define mskSSP_FORMAT_SSP_MODE (SSP_FORMAT_SSP_MODE<<4)
//[7:6] SSP FSM and FIFO Reset bit
#define SSP_FRESET_DO_NOTHING 0 //Do nothing
#define SSP_FRESET_RESET_FIFO 3 //Reset finite state machine and FIFO
#define mskSSP_FRESET_DO_NOTHING (SSP_FRESET_DO_NOTHING<<6)
#define mskSSP_FRESET_RESET_FIFO (SSP_FRESET_RESET_FIFO<<6)
#define SSP_DL_3 2 //[11:8] Data Length = DL[3:0]+1
#define SSP_DL_4 3
#define SSP_DL_5 4
#define SSP_DL_6 5
#define SSP_DL_7 6
#define SSP_DL_8 7
#define SSP_DL_9 8
#define SSP_DL_10 9
#define SSP_DL_11 10
#define SSP_DL_12 11
#define SSP_DL_13 12
#define SSP_DL_14 13
#define SSP_DL_15 14
#define SSP_DL_16 15
#define SSP_TXFIFOTH_0 0 //[14:12]TX FIFO Threshold level
#define SSP_TXFIFOTH_1 1
#define SSP_TXFIFOTH_2 2
#define SSP_TXFIFOTH_3 3
#define SSP_TXFIFOTH_4 4
#define SSP_TXFIFOTH_5 5
#define SSP_TXFIFOTH_6 6
#define SSP_TXFIFOTH_7 7
#define SSP_RXFIFOTH_0 0 //[17:15]RX FIFO Threshold level
#define SSP_RXFIFOTH_1 1
#define SSP_RXFIFOTH_2 2
#define SSP_RXFIFOTH_3 3
#define SSP_RXFIFOTH_4 4
#define SSP_RXFIFOTH_5 5
#define SSP_RXFIFOTH_6 6
#define SSP_RXFIFOTH_7 7
//[18:18]Auto-SEL disable bit. For SPI mode only.
#define SSP_SELDIS_EN 0 //Enable Auto-SEL flow control
#define SSP_SELDIS_DIS 1 //Disable Auto-SEL flow control
#define mskSSP_SELDIS_EN (SSP_SELDIS_EN<<18)
#define mskSSP_SELDIS_DIS (SSP_SELDIS_DIS<<18)
/* SSP n Control register 1 <SSPn_CTRL1> (0x04) */
//[0:0]MSB/LSB selection bit
#define SSP_MLSB_MSB 0 //MSB transmit first
#define SSP_MLSB_LSB 1 //LSB transmit first
#define mskSSP_MLSB_MSB (SSP_MLSB_MSB<<0)
#define mskSSP_MLSB_LSB (SSP_MLSB_LSB<<0)
//[1:1]Clock polarity selection bit
#define SSP_CPOL_SCK_IDLE_LOW 0 //SCK idles at Low level
#define SSP_CPOL_SCK_IDLE_HIGH 1 //SCK idles at High level
#define mskSSP_CPOL_SCK_IDLE_LOW (SSP_CPOL_SCK_IDLE_LOW<<1)
#define mskSSP_CPOL_SCK_IDLE_HIGH (SSP_CPOL_SCK_IDLE_HIGH<<1)
//[2:2]Clock phase for edge sampling
#define SSP_CPHA_FALLING_EDGE 0 //Data changes at clock falling edge
#define SSP_CPHA_RISING_EDGE 1 //Data changes at clock rising edge
#define mskSSP_CPHA_FALLING_EDGE (SSP_CPHA_FALLING_EDGE<<2)
#define mskSSP_CPHA_RISING_EDGE (SSP_CPHA_RISING_EDGE<<2)
/* SSP n Clock Divider register <SSPn_CLKDIV> (0x08) */
//[7:0]SSPn clock divider
#define SSP_DIV 6 //MCLK/n, n = 2, 4, 6, 8, ...,512
/* SSP n Status register <SSPn_STAT> (0x0C) */
#define mskSSP_TX_EMPTY (0x1<<0) //TX FIFO empty flag
#define mskSSP_TX_FULL (0x1<<1) //TX FIFO full flag
#define mskSSP_RX_EMPTY (0x1<<2) //RX FIFO empty flag
#define mskSSP_RX_FULL (0x1<<3) //RX FIFO full flag
#define mskSSP_BUSY (0x1<<4) //Busy flag
#define mskSSP_TXFIFOTHF (0x1<<5) //TX FIFO threshold flag
#define mskSSP_RXFIFOTHF (0x1<<6) //RX FIFO threshold flag
/* SSP n Interrupt Enable register <SSPn_IE> (0x10) */
#define SSP_RXOVFIE_DIS 0 //[0:0]RX Overflow interrupt enable
#define SSP_RXOVFIE_EN 1
#define mskSSP_RXOVFIE_DIS (SSP_RXOVFIE_DIS<<0)
#define mskSSP_RXOVFIE_EN (SSP_RXOVFIE_EN<<0)
#define SSP_RXTOIE_DIS 0 //[1:1]RX time-out interrupt enable
#define SSP_RXTOIE_EN 1
#define mskSSP_RXTOIE_DIS (SSP_RXTOIE_DIS<<1)
#define mskSSP_RXTOIE_EN (SSP_RXTOIE_EN<<1)
#define SSP_RXFIFOTHIE_DIS 0 //[2:2]RX FIFO threshold interrupt enable
#define SSP_RXFIFOTHIE_EN 1
#define mskSSP_RXFIFOTHIE_DIS (SSP_RXFIFOTHIE_DIS<<2)
#define mskSSP_RXFIFOTHIE_EN (SSP_RXFIFOTHIE_EN <<2)
#define SSP_TXFIFOTHIE_DIS 0 //[3:3]TX FIFO threshold interrupt enable
#define SSP_TXFIFOTHIE_EN 1
#define mskSSP_TXFIFOTHIE_DIS (SSP_TXFIFOTHIE_DIS<<3)
#define mskSSP_TXFIFOTHIE_EN (SSP_TXFIFOTHIE_EN<<3)
/* SSP n Raw Interrupt Status register <SSPn_RIS> (0x14) */
/* SSP n Interrupt Clear register <SSPn_IC> (0x18) */
#define mskSSP_RXOVFIF (0x1<<0) //[0:0]RX overflow interrupt flag
#define mskSSP_RXOVFIC mskSSP_RXOVFIF
#define mskSSP_RXTOIF (0x1<<1) //[1:1]RX time-out interrupt flag
#define mskSSP_RXTOIC mskSSP_RXTOIF
#define mskSSP_RXFIFOTHIF (0x1<<2) //[2:2]RX FIFO threshold interrupt flag
#define mskSSP_RXFIFOTHIC mskSSP_RXFIFOTHIF
#define mskSSP_TXFIFOTHIF (0x1<<3) //[3:3]TX FIFO threshold interrupt flag
#define mskSSP_TXFIFOTHIC mskSSP_TXFIFOTHIF
/* SSP n Data Fetch register <SSPn_DF> (0x20) */
//[0:0]SSP data fetch control bit
#define SSP_DF_DIS 0 //Disable
#define SSP_DF_EN 1 //Enable when SCKn frequency > 6MHz
#define mskSSP_DF_DIS (SSP_DF_DIS<<0)
#define mskSSP_SSP_DF_EN (SSP_DF_EN<<0)
/*_____ M A C R O S ________________________________________________________*/
#define __SPI0_FIFO_RESET (SN_SSP0->CTRL0_b.FRESET = SSP_FRESET_RESET_FIFO)
#define __SPI1_FIFO_RESET (SN_SSP1->CTRL0_b.FRESET = SSP_FRESET_RESET_FIFO)
#define __SPI0_CLR_SEL0 (SN_GPIO2->DATA_b.DATA15=0)
#define __SPI0_SET_SEL0 (SN_GPIO2->DATA_b.DATA15=1)
#define __SPI1_CLR_SEL1 (SN_GPIO2->DATA_b.DATA14=0)
#define __SPI1_SET_SEL1 (SN_GPIO2->DATA_b.DATA14=1)
//SSP Data Fetch speed (High: SCK>6MHz)
#define __SSP0_DATA_FETCH_HIGH_SPEED (SN_SSP0->DF = SSP_DF_EN) //*(volatile unsigned long *)(0x4001C020) = 1
#define __SSP1_DATA_FETCH_HIGH_SPEED (SN_SSP1->DF = SSP_DF_EN) //*(volatile unsigned long *)(0x40058020) = 1
/*_____ D E C L A R A T I O N S ____________________________________________*/
extern void SPI0_Init(void);
extern void SPI0_Enable(void);
extern void SPI0_Disable(void);
extern void SPI1_Init(void);
extern void SPI1_Enable(void);
extern void SPI1_Disable(void);
#endif /*__SN32F760_SSP_H*/

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/******************** (C) COPYRIGHT 2014 SONiX *******************************
* COMPANY: SONiX
* DATE: 2014/05
* AUTHOR: SA1
* IC: SN32F240/230/220
* DESCRIPTION: SPI0 related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2013/12/17 SA1 1. First release
* 1.1 2014/05/23 SA1 1. Add __SSP0_DATA_FETCH_HIGH_SPEED macro
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240.h>
#include "SPI.h"
#include "..\..\Utility\Utility.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
/*****************************************************************************
* Function : SPI0_Init
* Description : Initialization of SPI0 init
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void SPI0_Init(void)
{
//Enable HCLK for SSP0
SN_SYS1->AHBCLKEN |= (0x1 << 12); //Enable clock for SSP0.
//SSP0 PCLK
SN_SYS1->APBCP0 |= (0x00 << 20); //PCLK = HCLK/1
//SN_SYS1->APBCP0 |= (0x01 << 20); //PCLK = HCLK/2
//SN_SYS1->APBCP0 |= (0x02 << 20); //PCLK = HCLK/4
//SN_SYS1->APBCP0 |= (0x03 << 20); //PCLK = HCLK/8
//SN_SYS1->APBCP0 |= (0x04 << 20); //PCLK = HCLK/16
//SSP0 setting
SN_SSP0->CTRL0_b.DL = SSP_DL_8; //3 ~ 16 Data length
SN_SSP0->CTRL0_b.FORMAT = SSP_FORMAT_SPI_MODE; //Interface format
SN_SSP0->CTRL0_b.MS = SSP_MS_MASTER_MODE; //Master/Slave selection bit
SN_SSP0->CTRL0_b.LOOPBACK = SSP_LOOPBACK_DIS; //Loop back mode
SN_SSP0->CTRL0_b.SDODIS = SSP_SDODIS_EN; //Slave data output
//(ONLY used in slave mode)
SN_SSP0->CLKDIV_b.DIV = (SSP_DIV/2) - 1; //SSPn clock divider
//SSP0 SPI mode
SN_SSP0->CTRL1 = SSP_CPHA_FALLING_EDGE| //Clock phase for edge sampling
SSP_CPOL_SCK_IDLE_LOW| //Clock polarity selection bit
SSP_MLSB_MSB; //MSB/LSB selection bit
//SSP0 SEL0 setting
SN_SSP0->CTRL0_b.SELDIS = SSP_SELDIS_DIS; //Auto-SEL disable bit
SN_GPIO2->MODE_b.MODE15=1; //SEL(P2.15) is outout high
__SPI0_SET_SEL0;
//SSP0 Fifo reset
__SPI0_FIFO_RESET;
//SSP0 interrupt enable
NVIC_ClearPendingIRQ(SSP0_IRQn);
NVIC_EnableIRQ(SSP0_IRQn);
//NVIC_SetPriority(SSP0_IRQn,0);
//__SSP0_DATA_FETCH_HIGH_SPEED; //Enable if Freq. of SCK > 6MHz
//SSP0 enable
SN_SSP0->CTRL0_b.SSPEN = SSP_SSPEN_EN; //SSP enable bit
}
/*****************************************************************************
* Function : SPI0_Enable
* Description : SPI0 enable setting
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void SPI0_Enable(void)
{
//Enable HCLK for SSP0
SN_SYS1->AHBCLKEN |= (0x1 << 12); //Enable clock for SSP0.
SN_SSP0->CTRL0_b.SSPEN = SSP_SSPEN_EN; //SSP enable bit
__SPI0_FIFO_RESET;
}
/*****************************************************************************
* Function : SPI0_Disable
* Description : SPI0 disable setting
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void SPI0_Disable(void)
{
SN_SSP0->CTRL0_b.SSPEN = SSP_SSPEN_DIS; //SSP disable bit
//Disable HCLK for SSP0
SN_SYS1->AHBCLKEN &=~ (0x1 << 12); //Disable clock for SSP0.
}

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/******************** (C) COPYRIGHT 2014 SONiX *******************************
* COMPANY: SONiX
* DATE: 2014/05
* AUTHOR: SA1
* IC: SN32F240/230/220
* DESCRIPTION: SPI1 related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2013/12/17 SA1 1. First release
* 1.1 2014/05/23 SA1 1. Add __SSP1_DATA_FETCH_HIGH_SPEED macro
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240.h>
#include "SPI.h"
#include "..\..\Utility\Utility.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
/*****************************************************************************
* Function : SPI1_Init
* Description : Initialization of SPI1 init
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void SPI1_Init(void)
{
//Enable HCLK for SSP1
SN_SYS1->AHBCLKEN |= (0x1 << 13); //Enable clock for SSP1.
//SSP1 PCLK
SN_SYS1->APBCP0 |= (0x00 << 24); //PCLK = HCLK/1
//SN_SYS1->APBCP0 |= (0x01 << 24); //PCLK = HCLK/2
//SN_SYS1->APBCP0 |= (0x02 << 24); //PCLK = HCLK/4
//SN_SYS1->APBCP0 |= (0x03 << 24); //PCLK = HCLK/8
//SN_SYS1->APBCP0 |= (0x04 << 24); //PCLK = HCLK/16
//SSP1 setting
SN_SSP1->CTRL0_b.DL = SSP_DL_8; //3 ~ 16 Data length
SN_SSP1->CTRL0_b.FORMAT = SSP_FORMAT_SPI_MODE; //Interface format
SN_SSP1->CTRL0_b.MS = SSP_MS_MASTER_MODE; //Master/Slave selection bit
SN_SSP1->CTRL0_b.LOOPBACK = SSP_LOOPBACK_DIS; //Loop back mode
SN_SSP1->CTRL0_b.SDODIS = SSP_SDODIS_EN; //Slave data output
SN_SSP1->CLKDIV_b.DIV = (SSP_DIV/2) - 1; //SSPn clock divider
//SSP1 SPI mode
SN_SSP1->CTRL1 = SSP_CPHA_FALLING_EDGE| //Clock phase for edge sampling
SSP_CPOL_SCK_IDLE_LOW| //Clock polarity selection bit
SSP_MLSB_MSB; //MSB/LSB selection bit
//SSP1 SEL1 Setting
SN_SSP1->CTRL0_b.SELDIS = SSP_SELDIS_DIS; //Auto-SEL disable bit
SN_GPIO2->MODE_b.MODE14=1; //SEL1(P2.14) is outout high
__SPI1_SET_SEL1;
//SSP1 Fifo reset
__SPI1_FIFO_RESET;
//SSP1 interrupt enable
NVIC_ClearPendingIRQ(SSP1_IRQn);
NVIC_EnableIRQ(SSP1_IRQn);
//NVIC_SetPriority(SSP1_IRQn,0);
//__SSP1_DATA_FETCH_HIGH_SPEED; //Enable if Freq. of SCK > 6MHz
//SSP1 enable
SN_SSP1->CTRL0_b.SSPEN = SSP_SSPEN_EN; //SSP enable bit
}
/*****************************************************************************
* Function : SPI1_Enable
* Description : SPI1 enable setting
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void SPI1_Enable(void)
{
//Enable HCLK for SSP1
SN_SYS1->AHBCLKEN |= (0x1 << 13); //Enable clock for SSP0.
SN_SSP1->CTRL0_b.SSPEN = SSP_SSPEN_EN; //SSP enable bit
__SPI1_FIFO_RESET;
}
/*****************************************************************************
* Function : SPI1_Disable
* Description : SPI1 disable setting
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void SPI1_Disable(void)
{
SN_SSP1->CTRL0_b.SSPEN = SSP_SSPEN_DIS; //SSP disable bit
//Disable HCLK for SSP1
SN_SYS1->AHBCLKEN &=~ (0x1 << 13); //Disable clock for SSP0.
}

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/******************** (C) COPYRIGHT 2013 SONiX *******************************
* COMPANY: SONiX
* DATE: 2013/12
* AUTHOR: SA1
* IC: SN32F240/230/220
* DESCRIPTION: SysTick related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2013/12/17 SA1 First release
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include "SysTick.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
/*****************************************************************************
* Function : SysTick_Init
* Description : Initialization of SysTick timer
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void SysTick_Init (void)
{
SystemCoreClockUpdate();
__SYSTICK_SET_TIMER_PERIOD(10); //RELOAD = (system tick clock frequency ¡Ñ 10 ms)/1000 -1
__SYSTICK_CLEAR_COUNTER_AND_FLAG;
#if SYSTICK_IRQ == INTERRUPT_METHOD
SysTick->CTRL = 0x7; //Enable SysTick timer and interrupt
#else
SysTick->CTRL = 0x5; //Enable SysTick timer ONLY
#endif
}
/*****************************************************************************
* Function : SysTick_Handler
* Description : ISR of SysTick interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
__irq void SysTick_Handler(void)
{
__SYSTICK_CLEAR_COUNTER_AND_FLAG;
}

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#ifndef __SN32F240_SYSTICK_H
#define __SN32F240_SYSTICK_H
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240.h>
#include <SN32F200_Def.h>
/*_____ D E F I N I T I O N S ______________________________________________*/
#define SYSTICK_IRQ POLLING_METHOD //INTERRUPT_METHOD: Enable SysTick timer and interrupt
//POLLING_METHOD: Enable SysTick timer ONLY
/*_____ M A C R O S ________________________________________________________*/
#define __SYSTICK_SET_TIMER_PERIOD(ms) SysTick->LOAD = SystemCoreClock * ms /1000 - 1
#define __SYSTICK_CLEAR_COUNTER_AND_FLAG SysTick->VAL = 0xFF
/*_____ D E C L A R A T I O N S ____________________________________________*/
void SysTick_Init(void);
#endif /*__SN32F240_SYSTICK_H*/

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#ifndef __SN32F240_USART_H
#define __SN32F240_USART_H
/*_____ I N C L U D E S ____________________________________________________*/
#include <stdint.h>
/*_____ D E F I N I T I O N S ______________________________________________*/
/*
Base Address: 0x4001 6000 (USART0)
0x4005 6000 (USART1)
*/
#define USART0_CLK_EN (0x01<<16)
#define USART1_CLK_EN (0x01<<17)
#define USART0_PLKSEL_DIV1 (0x00)
#define USART0_PLKSEL_DIV2 (0x01)
#define USART0_PLKSEL_DIV4 (0x02)
#define USART0_PLKSEL_DIV8 (0x03)
#define USART0_PLKSEL_DIV16 (0x04)
#define USART1_PLKSEL_DIV1 (0x00<<4)
#define USART1_PLKSEL_DIV2 (0x01<<4)
#define USART1_PLKSEL_DIV4 (0x02<<4)
#define USART1_PLKSEL_DIV8 (0x03<<4)
#define USART1_PLKSEL_DIV16 (0x04<<4)
/**************Line Control Define******/
#define USART_CHARACTER_LEN5BIT (0x00)
#define USART_CHARACTER_LEN6BIT (0x01)
#define USART_CHARACTER_LEN7BIT (0x02)
#define USART_CHARACTER_LEN8BIT (0x03)
/***********************/
#define USART_STOPBIT_1BIT (0x0<<2)
#define USART_STOPBIT_2BIT (0x1<<2)
/***********************/
#define USART_PARITY_BIT_DISEN (0x0<<3)
#define USART_PARITY_BIT_EN (0x1<<3)
/***********************/
#define USART_PARITY_SELECTODD (0x00<<4)
#define USART_PARITY_SELECTEVEN (0x01<<4)
#define USART_PARITY_SELECTFORC1 (0x02<<4)
#define USART_PARITY_SELECTFORC0 (0x03<<4)
/***********************/
#define USART_BREAK_DISEN (0x0<<6)
#define USART_BREAK_EN (0x1<<6)
/***********************/
#define USART_DIVISOR_DISEN (0x0<<7)
#define USART_DIVISOR_EN (0x1<<7)
#define USART_OVER_SAMPLE_16 (0x0<<8)
#define USART_OVER_SAMPLE_8 (0x1<<8)
/***Baud rate pre-scaler multilier = MULVAL+1***/
#define USART_MULVAL_0 (0x0000<<4)
#define USART_MULVAL_1 (0x0001<<4)
#define USART_MULVAL_2 (0x0002<<4)
#define USART_MULVAL_3 (0x0003<<4)
#define USART_MULVAL_4 (0x0004<<4)
#define USART_MULVAL_5 (0x0005<<4)
#define USART_MULVAL_6 (0x0006<<4)
#define USART_MULVAL_7 (0x0007<<4)
#define USART_MULVAL_8 (0x0008<<4)
#define USART_MULVAL_9 (0x0009<<4)
#define USART_MULVAL_10 (0x000A<<4)
#define USART_MULVAL_11 (0x000B<<4)
#define USART_MULVAL_12 (0x000C<<4)
#define USART_MULVAL_13 (0x000D<<4)
#define USART_MULVAL_14 (0x000E<<4)
#define USART_MULVAL_15 (0x000F<<4)
/***Buad rate pre-scaler divisor value********/
#define USART_DIVADDVAL_0 (0x000)
#define USART_DIVADDVAL_1 (0x001)
#define USART_DIVADDVAL_2 (0x002)
#define USART_DIVADDVAL_3 (0x003)
#define USART_DIVADDVAL_4 (0x004)
#define USART_DIVADDVAL_5 (0x005)
#define USART_DIVADDVAL_6 (0x006)
#define USART_DIVADDVAL_7 (0x007)
#define USART_DIVADDVAL_8 (0x008)
#define USART_DIVADDVAL_9 (0x009)
#define USART_DIVADDVAL_10 (0x00A)
#define USART_DIVADDVAL_11 (0x00B)
#define USART_DIVADDVAL_12 (0x00C)
#define USART_DIVADDVAL_13 (0x00D)
#define USART_DIVADDVAL_14 (0x00E)
#define USART_DIVADDVAL_15 (0x00F)
/***USART divisor latch MSB reg[7:0]. determines the baud rate***/
/***USART divisor latch LSB reg[7:0]. determines the baud rate***/
#define USART_FIFO_ENABLE (0x01)
#define USART_RXFIFO_RESET (0x01<<1)
#define USART_TXFIFO_RESET (0x01<<2)
#define USART_RXTRIGGER_LEVEL1 (0x00<<6)
#define USART_RXTRIGGER_LEVEL4 (0x01<<6)
#define USART_RXTRIGGER_LEVEL8 (0x02<<6)
#define USART_RXTRIGGER_LEVEL14 (0x03<<6)
/***USART Interrupt Enable register***/
#define USART_TXERRIE_EN (0x01<<10) //Tx error flag INT
#define USART_ABTOIE_EN (0x01<<9) //auto-buad time out INT
#define USART_ABEOIE_EN (0x01<<8) //End of auto-buad INT
#define USART_TEMTIE_EN (0x01<<4) //Transmitter empty flag
#define USART_MSIE_EN (0x01<<3) //Modem status INT
#define USART_RLSIE_EN (0x01<<2) //Rx Receive line status(RLS) INT
#define USART_THREIE_EN (0x01<<1) //Transmitter holding register empty flag INT
#define USART_RDAIE_EN (0x01) //character receive(RDA) time-out INT
/*** USARTn_CTRL************/
#define USART_EN (0x01)
#define USART_MODE_UART (0x00<<1)
#define USART_MODE_MODEN (0x01<<1)
#define USART_MODE_SMARTCARD (0x03<<1)
#define USART_MODE_SYNCH (0x04<<1)
#define USART_MODE_RS485 (0x05<<1)
#define USART_RX_EN (0x01<<6)
#define USART_TX_EN (0x01<<7)
#define USART_CTRL_EN 1
#define USART_CTRL_DIS 0
#define USART_FIFOCTRL_RESET 1
/*** USARTn_ABCCTRL************/
#define USART_ABCCTRL_START (0x01) //START:1(Auto-baud is running), START:0(Auto-baud is not running)
#define USART_ABCCTRL_MODE0 (0x00<<1)
#define USART_ABCCTRL_MODE1 (0x01<<1)
#define USART_ABCCTRL_RESTART (0x01<<2)
#define USART_ABEO_EN (0x01<<8)
#define USART_ABTO_EN (0x01<<9)
/*** USARTn_MC(modem contro)************/
#define USART_MC_RTSCTRL (0x01<<1) //Source for modem output pin RTS
#define USART_MCCTS_EN (0x01<<6) //Auto-CTS 1:enable 0:disable
#define USART_MCRTS_EN (0x01<<7) //Auto-RTS 1:enable 0:disable
/*** USARTn_RS485(modem contro)************/
#define USART_NMM_EN (0x01) //Normal Multidrop Mode(NMM) 1:enable 0:disable
#define USART_485RX_EN (0x01<<1) //RS-485 Receiver bit 1:enalbe 0:disable
#define USART_AAD_EN (0x01<<2) //Auto address detect(AAD) bit 1:enable 0:disable
#define USART_ADC_EN (0x01<<4) //Auto Direction control bit 1:enable 0:disable
#define USART_OINV_SEL1 (0x01<<5)
#define USART_OINV_SEL0 (0x00<<5)
#define RS485_ADDRESS 40
#define RS485_DELAY_TIME 40
/*** USARTn_Synchronous Mode(modem contro)************/
#define USART_SCLK_LOW (0x0<<1) //SCLK idle low
#define USART_SCLK_HIGH (0x1<<1) //SCLK idle high
#define USART_POLAR_RISING (0x0<<2) //sample on Rising edge
#define USART_POLAR_FALLING (0x1<<2) //sample on Falling edge
/*** Line status register************/
#define USART_LS_RDR (0x01) //receiver data ready flag
#define USART_LS_OE (0x01<<1) //overrun error flag
#define USART_LS_PE (0x01<<2) //parity error flag
#define USART_LS_FE (0x01<<3) //framing error flag
#define USART_LS_BI (0x01<<4) //break interrupt flag
#define USART_LS_THRE (0x01<<5) //transmitter holding register empty flag
#define USART_LS_TEMT (0x01<<6) //transmitter empty flag
#define USART_LS_RXFE (0x01<<7) //error in RX FIFO flag
#define USART_LS_THERR (0x01<<8) //TX error flag
#define mskUSART_LS_RDR (0x01)
#define mskUSART_LS_OE (0x01<<1)
#define mskUSART_LS_PE (0x01<<2)
#define mskUSART_LS_FE (0x01<<3)
#define mskUSART_LS_BI (0x01<<4)
#define mskUSART_LS_THRE (0x01<<5)
#define mskUSART_LS_TEMT (0x01<<6)
#define mskUSART_LS_RXFE (0x01<<7)
#define mskUSART_LS_TXERR (0x01<<8)
/*** Line status register************/
#define USART_MS_DCTS (0x01)
#define USART_MS_CTS (0x01<<4)
#define mskUSART_MS_DCTS (0x01)
#define mskUSART_MS_CTS (0x01<<4)
/*** Interrupt Identification register************/
#define USART_RLS 3
#define USART_RDA 2
#define USART_CTI 6
#define USART_THRE 1
#define USART_MODEM 0
#define USART_TEMT 7
#define USART_II_STATUS 0 //the INTstatus can be determined by USARTn_II[3:1]
#define USART_II_ABEOIF (0x01<<8) //end of auto-baud interrupt flag
#define USART_II_ABTOIF (0x01<<9) //auto-baud time-out interrupt flag
#define USART_II_TXERRIF (0x01<<10) //TXERR interrupt flag
#define mskUSART_INTID_STATUS 7 //interrupt corresponding to the USARTn RX FIFO
#define mskUSART_II_STATUS (0x01)
#define mskUSART_II_ABEOIF (0x01<<8)
#define mskUSART_II_ABTOIF (0x01<<9)
#define mskUSART_II_TXERRIF (0x01<<10)
/*_____ M A C R O S ________________________________________________________*/
#define __USART0_RXFIFO_RESET (SN_USART0->FIFOCTRL_b.RXFIFORST = USART_FIFOCTRL_RESET)
#define __USART0_TXFIFO_RESET (SN_USART0->FIFOCTRL_b.TXFIFORST = USART_FIFOCTRL_RESET)
#define __USART1_RXFIFO_RESET (SN_USART1->FIFOCTRL_b.RXFIFORST = USART_FIFOCTRL_RESET)
#define __USART1_TXFIFO_RESET (SN_USART1->FIFOCTRL_b.TXFIFORST = USART_FIFOCTRL_RESET)
/*_____ D E C L A R A T I O N S ____________________________________________*/
extern uint32_t GulNum;
extern uint8_t bUSART0_RecvFIFO[16];
extern uint32_t GulNum1;
extern uint8_t bUSART1_RecvFIFO[16];
extern volatile uint8_t bUSART0_RecvNew;
extern volatile uint8_t bUSART1_RecvNew;
/*_____ D E C L A R A T I O N S ____________________________________________*/
extern void USART0_Init(void);
extern void USART0_SendByte(void);
extern void USART0_Enable(void);
extern void USART0_Disable(void);
extern void USART0_InterruptEnable(void);
extern void USART0_AutoBaudrateInit(void);
extern void USART1_Init(void);
extern void USART1_SendByte(void);
extern void USART1_Enable(void);
extern void USART1_Disable(void);
extern void USART1_InterruptEnable(void);
extern void USART1_AutoBaudrateInit(void);
extern void USART0_Modem_Init(void);
extern void USART0_RS485_Init(void);
extern void USART0_SyncMode_Init(void);
#endif /*__SN32F240_USART_H*/

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/******************** (C) COPYRIGHT 2015 SONiX *******************************
* COMPANY: SONiX
* DATE: 2015/05
* AUTHOR: SA1
* IC: SN32F240/230/220
* DESCRIPTION: USART0 related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2013/12/17 SA1 First release
* 1.1 2014/01/20 SA1 1. Modify USART0_SendByte sub function
* 1.2 2014/02/27 SA1 1. Fix typing errors.
* 1.22 2014/05/23 SA1 1. Fix USART0_Init for BR=115200
* 2.0 2015/05/29 SA1 1. Fix USART0_Init for BR=115200 & 57600 @ PCLK=12MHz
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240.h>
#include "USART.h"
#include "..\..\Utility\Utility.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
volatile uint8_t bUSART0_RecvNew;
uint32_t GulNum;
uint8_t bUSART0_RecvFIFO[16];
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
/*****************************************************************************
* Function : UART0_IRQHandler
* Description : USART0 interrupt service routine
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
__irq void USART0_IRQHandler (void)
{
uint32_t II_Buf, LS_Buf, MS_Buf;
volatile uint32_t Null_Buf;
II_Buf = SN_USART0->II;
while ((II_Buf & mskUSART_II_STATUS) == USART_II_STATUS) //check interrupt status, the INT can be determined by USARTn_II[3:1]
{
switch ((II_Buf>>1) & mskUSART_INTID_STATUS)
{
case USART_RLS: //Receive Line Status
LS_Buf = SN_USART0->LS;
if((LS_Buf & mskUSART_LS_OE) == USART_LS_OE) //Overrun Error
{ }
if((LS_Buf & mskUSART_LS_RXFE) == USART_LS_RXFE)//RX FIFO Error
{
if((LS_Buf & mskUSART_LS_PE) == USART_LS_PE)//Parity Error
Null_Buf = SN_USART0->RB; //Clear interrupt
if((LS_Buf & mskUSART_LS_FE) == USART_LS_FE) //Framing Error
Null_Buf = SN_USART0->RB; //Clear interrupt
if((LS_Buf & mskUSART_LS_BI) == USART_LS_BI) //Break Interrupt
Null_Buf = SN_USART0->RB; //Clear interrupt
}
break;
case USART_RDA: //Receive Data Available
case USART_CTI: //Character Time-out Indicator
LS_Buf = SN_USART0->LS;
bUSART0_RecvNew = 1;
if((LS_Buf & mskUSART_LS_RDR) == USART_LS_RDR)//Receiver Data Ready
{
bUSART0_RecvFIFO[GulNum] = SN_USART0->RB;
GulNum++;
}
if(GulNum == 16)
GulNum = 0;
break;
case USART_THRE: //THRE interrupt
LS_Buf = SN_USART0->LS;
if((LS_Buf & mskUSART_LS_THRE) == USART_LS_THRE)//THRE empty
{ //SN_USART0->TH = Null_Buf; //Clear interrupt
}
break;
case USART_TEMT: //TEMT interrupt
LS_Buf = SN_USART0->LS;
if((LS_Buf & mskUSART_LS_TEMT) == USART_LS_TEMT)
{ //SN_USART0->TH = Null_Buf; //Clear interrupt
}
break;
case USART_MODEM: //Modem status
MS_Buf = SN_USART0->MS;
if((MS_Buf & mskUSART_MS_DCTS) == USART_MS_DCTS)//Delta CTS
{
if((MS_Buf & mskUSART_MS_CTS) == USART_MS_CTS)
{ //Low to High transition
}
else
{ //High to Low transition
}
}
break;
default:
break;
} //end switch ((II_Buf>>1) & mskUSART_INTID_STATUS)
II_Buf = SN_USART0->II;
//LS_Buf = SN_USART0->LS;
} //end while ((II_Buf&0x01) == mskUSART_II_STATUS)
if ((II_Buf & mskUSART_II_ABEOIF) == USART_II_ABEOIF) //Auto Baud interrupt
SN_USART0->ABCTRL |= USART_ABEO_EN;
else if((II_Buf & mskUSART_II_ABTOIF) == USART_II_ABTOIF) //Auto Baud time-out interrupt
SN_USART0->ABCTRL |= USART_ABTO_EN;
if((II_Buf & mskUSART_II_TXERRIF) == USART_II_TXERRIF)//TXERR interrupt
{
LS_Buf = SN_USART0->LS;
if ((LS_Buf & mskUSART_LS_TXERR) == USART_LS_THERR)//TX Error
SN_USART0->FIFOCTRL|= USART_TXFIFO_RESET; //TX FIFO Reset
}
}
/*****************************************************************************
* Function : USART0_Init
* Description : Initialization of USART0
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USART0_Init (void)
{
SN_SYS1->AHBCLKEN |= USART0_CLK_EN; //Enables clock for USART0
SN_SYS1->APBCP1 |= USART0_PLKSEL_DIV1; //USART0 PCLK = HCLK/1 = 12MHz
//SN_SYS1->APBCP1 |= USART0_PLKSEL_DIV2; //USART0 PCLK = HCLK/2 = 6MHz
//SN_SYS1->APBCP1 |= USART0_PLKSEL_DIV4; //USART0 PCLK = HCLK/4 = 3MHz
//SN_SYS1->APBCP1 |= USART0_PLKSEL_DIV8; //USART0 PCLK = HCLK/8 = 1.5MHz
//SN_SYS1->APBCP1 |= USART0_PLKSEL_DIV16; //USART0 PCLK = HCLK/16= 0.75MHz
//===Line Control===
//setting character Word length(5/6/7/8 bit)
SN_USART0->LC = (USART_CHARACTER_LEN8BIT //8bit character length.
| USART_STOPBIT_1BIT //stop bit of 1 bit
| USART_PARITY_BIT_DISEN //parity bit is disable
| USART_PARITY_SELECTODD //parity bit is odd
| USART_BREAK_DISEN //Break Transmission control disable
| USART_DIVISOR_EN); //Divisor Latch Access enable
//===Baud Rate Calculation===
//USART PCLK = 12MHz, Baud rate = 115200
SN_USART0->FD = (USART_OVER_SAMPLE_16|USART_MULVAL_7|USART_DIVADDVAL_5);
SN_USART0->DLM = 0;
SN_USART0->DLL = 4;
/*
//USART PCLK = 12MHz, Baud rate = 57600
SN_USART0->FD = (OVER_SAMPLE_16|USART_MULVAL_7|USART_DIVADDVAL_5);
SN_USART0->DLM = 0;
SN_USART0->DLL = 8;
*/
SN_USART0->LC &= ~(USART_DIVISOR_EN); //Disable divisor latch
//===Auto Baud Rate===
//USART0_Autobaudrate_Init(); //Auto buad rate initial
//===FIFO Control===
SN_USART0->FIFOCTRL =(USART_FIFO_ENABLE //Enable USART FIFOs
| USART_RXFIFO_RESET //RX FIFO Reset
| USART_TXFIFO_RESET //TX FIFO Reset
| USART_RXTRIGGER_LEVEL1); //RX Trigger Level(1/4/8/14 characters)
//===Modem Control===
//USART0_Modem_Init(); //Initialization of USART0 Modem.
//===Smart Card Control===
//SN_USART0->SCICTRL_b.NACKDIS = 1; //NACK response disable, T=0 only (0:NACK response is enabled, 1:NACK response is inhibited)
//SN_USART0->SCICTRL_b.PROTSEL = 1; //Protocol selection (0:T=0, 1:T=1)
//SN_USART0->SCICTRL_b.SCLKEN = 1; //SCLK out enable (0:Disable, 1:Enable)
//SN_USART0->SCICTRL_b.TXRETRY = 0; //T=0 only, the field controls the maximum number of retransmissions that the USART will attempt if the remote device signal NACK.
//SN_USART0->SCICTRL_b.XTRAGUARD = 0; //T=0 only, this field indicates the Guard time value in terms of number of bit times
//SN_USART0->SCICTRL_b.TC = 0; //TC[7:0] (Count for SCLK clock cycle when SCLKEN=1. SCLK will toggle every (TC[7:0]+1)*USARTn_PCLK cycle)
//===Synchronous Mode Control===
//USART0_SyncMode_Init(); //USART0_SyncMode_Init
//===RS485 Control===
//USART0_RS485_Init(); //USART0_RS485_Init
//===Scratch Pad===
//SN_USART0->SP = 0; //A readable, writable byte
//===Oversampling===
//SN_USART0->FD |= USART_OVER_SAMPLE_8; //OVER8(Oversampling Value), 1:Oversampling by 8. 0:Oversampling by 16
//===Half-duplex===
//SN_USART0->HDEN = 1; //Half-duplex mode enable
//===Interrupt Enable===
USART0_InterruptEnable();
//===USART Control===
SN_USART0->CTRL =(USART_EN //Enable USART0
| USART_MODE_UART //USART Mode = USAT
| USART_RX_EN //Enable RX
| USART_TX_EN); //Enable TX
//===NVIC===
NVIC_EnableIRQ(USART0_IRQn); //Enable USART0 INT
}
/*****************************************************************************
* Function : USART0_SendByte
* Description : USART0 Send data
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USART0_SendByte(void)
{
uint32_t i;
for (i=0; i<8; i++)
{
SN_USART0->TH= ('a'+i);
while ((SN_USART0->LS & 0x40) == 0);
}
}
/*****************************************************************************
* Function : USART0_AutoBaudrateInit
* Description : Initialization of USART0 Auto baud rate.
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USART0_AutoBaudrateInit(void)
{
SN_USART0->ABCTRL =(USART_ABTO_EN //Clear Auto Baud Time-out interrupt
| USART_ABEO_EN //Clear Auto Baud interrupt
| USART_ABCCTRL_RESTART //Restart in case of time-out
| USART_ABCCTRL_MODE1 //Auto Baud mode, 0:mode 0, 1:mode 1
| USART_ABCCTRL_START); //Auto Baud start, 0:stop(not running), 1:start(running)
}
/*****************************************************************************
* Function : USART0_Modem_Init
* Description : Initialization of USART0 Modem.
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USART0_Modem_Init(void)
{
SN_USART0->MC =(USART_MC_RTSCTRL //Source for modem output pin RTS
| USART_MCCTS_EN //CTS enable
| USART_MCRTS_EN); //RTS enable
}
/*****************************************************************************
* Function : USART0_RS485_Init
* Description : Initialization of USART0 RS-485.
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USART0_RS485_Init(void)
{
SN_USART0->RS485CTRL=(USART_NMM_EN //RS-485 Normal Multidrop Mode enable
| USART_485RX_EN //RS-485 Receiver enable, NMMEN=1 only
| USART_AAD_EN //Auto Address Detect enable
| USART_ADC_EN //Direction control enable
| USART_OINV_SEL1); //Polarity control
SN_USART0->RS485ADRMATCH = RS485_ADDRESS; //the address match value for RS-485mode
SN_USART0->RS485DLYV = RS485_DELAY_TIME; //The direction control (RTS or DTR) delay value,this time is in periods of the baud clock
}
/*****************************************************************************
* Function : USART0_SyncMode_Init
* Description : Initialization of USART0 Synchronous Mode.
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USART0_SyncMode_Init(void)
{
SN_USART0->SYNCCTRL=(USART_SCLK_HIGH //SCLK idle high
|USART_POLAR_FALLING); //sample on Falling edge
}
/*****************************************************************************
* Function : USART0_Smartcard_Init
* Description : Initialization of USART0 Smart Card.
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USART0_Smartcard_Init(void)
{
}
/*****************************************************************************
* Function : USART0_Enable
* Description : Enable USART0
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USART0_Enable(void)
{
//Enable HCLK for USART0
SN_SYS1->AHBCLKEN |= USART0_CLK_EN; //Enables clock for USART0
SN_USART0->CTRL_b.USARTEN = USART_CTRL_EN; //USART enable bit
__USART0_RXFIFO_RESET;
__USART0_TXFIFO_RESET;
}
/*****************************************************************************
* Function : USART0_Disable
* Description : Disable USART0
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USART0_Disable(void)
{
SN_USART0->CTRL_b.USARTEN = USART_CTRL_DIS; //USART disable
//Disable HCLK for USART0
SN_SYS1->AHBCLKEN &= ~(USART0_CLK_EN); //Disable clock for USART0
}
/*****************************************************************************
* Function : USART0_InterruptEnable
* Description : Interrupt Enable
* Input : wTxhfie- TX half empty interrupt enable. 0: Disable, 1: Enable.
wRxhfie- RX half empty interrupt enable. 0: Disable, 1: Enable.
wRxtoie- RX Time-out interrupt enable. 0: Disable, 1: Enable.
wRxovfie- RXOverflow interrupt enable. 0: Disable, 1: Enable.
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USART0_InterruptEnable(void)
{
SN_USART0->IE =(USART_RDAIE_EN //Enables the Receive Data Available(RDA) interrupt
| USART_THREIE_EN //Enable THRE interrupt
| USART_RLSIE_EN //Enable Receive Line Status(RLS) interrupt
| USART_TEMTIE_EN //Enable TEMT interrupt
| USART_ABEOIE_EN //Enable Auto Baud interrupt
| USART_ABTOIE_EN //Enable Auto Baud time-out interrupt
| USART_TXERRIE_EN);//Enable TXERR interrupt
}

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os/hal/ports/SN32/LLD/SN32F24x/USART/USART1.c Normal file
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/******************** (C) COPYRIGHT 2015 SONiX *******************************
* COMPANY: SONiX
* DATE: 2015/05
* AUTHOR: SA1
* IC: SN32F240/230/220
* DESCRIPTION: USART1 related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2013/12/17 SA1 First release
* 1.1 2014/01/20 SA1 1. Modify USART0_SendByte sub function
* 1.2 2014/02/27 SA1 1. Fix typing errors.
* 1.22 2014/05/23 SA1 1. Fix USART1_Init for BR=115200
* 2.0 2015/05/29 SA1 1. Fix USART1_Init for BR=115200 & 57600 @ PCLK=12MHz
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240.h>
#include "USART.h"
#include "..\..\Utility\Utility.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
volatile uint8_t bUSART1_RecvNew;
uint32_t GulNum1;
uint8_t bUSART1_RecvFIFO[16];
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
/*****************************************************************************
* Function : UART1_IRQHandler
* Description : USART1 interrupt service routine
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
__irq void USART1_IRQHandler (void)
{
uint32_t II_Buf, LS_Buf;
volatile uint32_t Null_Buf;
II_Buf = SN_USART1->II;
while ((II_Buf & mskUSART_II_STATUS) == USART_II_STATUS) //check interrupt status, the INT can be determined by USARTn_II[3:1]
{
switch ((II_Buf>>1) & mskUSART_INTID_STATUS)
{
case USART_RLS: //Receive Line Status
LS_Buf = SN_USART1->LS;
if((LS_Buf & mskUSART_LS_OE) == USART_LS_OE) //Overrun Error
{ }
if((LS_Buf & mskUSART_LS_RXFE) == USART_LS_RXFE)//RX FIFO Error
{
if((LS_Buf & mskUSART_LS_PE) == USART_LS_PE)//Parity Error
Null_Buf = SN_USART1->RB; //Clear interrupt
if((LS_Buf & mskUSART_LS_FE) == USART_LS_FE) //Framing Error
Null_Buf = SN_USART1->RB; //Clear interrupt
if((LS_Buf & mskUSART_LS_BI) == USART_LS_BI) //Break Interrupt
Null_Buf = SN_USART1->RB; //Clear interrupt
}
break;
case USART_RDA: //Receive Data Available
case USART_CTI: //Character Time-out Indicator
LS_Buf = SN_USART1->LS;
bUSART1_RecvNew = 1;
if((LS_Buf & mskUSART_LS_RDR) == USART_LS_RDR)//Receiver Data Ready
{
bUSART1_RecvFIFO[GulNum1] = SN_USART1->RB;
GulNum1++;
}
if(GulNum1 == 16)
GulNum1 = 0;
break;
case USART_THRE: //THRE interrupt
LS_Buf = SN_USART1->LS;
if((LS_Buf & mskUSART_LS_THRE) == USART_LS_THRE)//THRE empty
{ //SN_USART1->TH = Null_Buf; //Clear interrupt
}
break;
case USART_TEMT: //TEMT interrupt
LS_Buf = SN_USART1->LS;
if((LS_Buf & mskUSART_LS_TEMT) == USART_LS_TEMT)
{ //SN_USART1->TH = Null_Buf; //Clear interrupt
}
break;
default:
break;
} //end switch ((II_Buf>>1) & mskUSART_INTID_STATUS)
II_Buf = SN_USART1->II;
} //end while ((II_Buf&0x01) == mskUSART_II_STATUS)
if ((II_Buf & mskUSART_II_ABEOIF) == USART_II_ABEOIF) //Auto Baud interrupt
SN_USART1->ABCTRL |= USART_ABEO_EN;
else if((II_Buf & mskUSART_II_ABTOIF) == USART_II_ABTOIF) //Auto Baud time-out interrupt
SN_USART1->ABCTRL |= USART_ABTO_EN;
if((II_Buf & mskUSART_II_TXERRIF) == USART_II_TXERRIF)//TXERR interrupt
{
LS_Buf = SN_USART1->LS;
if ((LS_Buf & mskUSART_LS_TXERR) == USART_LS_THERR)//TX Error
SN_USART1->FIFOCTRL|= USART_TXFIFO_RESET; //TX FIFO Reset
}
}
/*****************************************************************************
* Function : USART1_Init
* Description : Initialization of USART1
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USART1_Init (void)
{
SN_SYS1->AHBCLKEN |= USART1_CLK_EN; //Enables clock for USART0
SN_SYS1->APBCP1 |= USART1_PLKSEL_DIV1; //USART0 PCLK = HCLK/1 = 12MHz
//SN_SYS1->APBCP1 |= USART1_PLKSEL_DIV2; //USART0 PCLK = HCLK/2 = 6MHz
//SN_SYS1->APBCP1 |= USART1_PLKSEL_DIV4; //USART0 PCLK = HCLK/4 = 3MHz
//SN_SYS1->APBCP1 |= USART1_PLKSEL_DIV8; //USART0 PCLK = HCLK/8 = 1.5MHz
//SN_SYS1->APBCP1 |= USART1_PLKSEL_DIV16; //USART0 PCLK = HCLK/16= 0.75MHz
//===Line Control===
//setting character Word length(5/6/7/8 bit)
SN_USART1->LC = (USART_CHARACTER_LEN8BIT //8bit character length.
| USART_STOPBIT_1BIT //stop bit of 1 bit
| USART_PARITY_BIT_DISEN //parity bit is disable
| USART_PARITY_SELECTODD //parity bit is odd
| USART_BREAK_DISEN //Break Transmission control disable
| USART_DIVISOR_EN); //Divisor Latch Access enable
//===Baud Rate Calculation===
//USART PCLK = 12MHz, Baud rate = 115200
SN_USART1->FD = (USART_OVER_SAMPLE_16|USART_MULVAL_7|USART_DIVADDVAL_5);
SN_USART1->DLM = 0;
SN_USART1->DLL = 4;
/*
//USART PCLK = 12MHz, Baud rate = 57600
SN_USART1->FD = (OVER_SAMPLE_16|USART_MULVAL_7|USART_DIVADDVAL_5);
SN_USART1->DLM = 0;
SN_USART1->DLL = 8;
*/
SN_USART1->LC &= ~(USART_DIVISOR_EN); //Disable divisor latch
//===Auto Baud Rate===
//USART0_Autobaudrate_Init(); //Auto buad rate initial
//===FIFO Control===
SN_USART1->FIFOCTRL =(USART_FIFO_ENABLE //Enable USART FIFOs
| USART_RXFIFO_RESET //RX FIFO Reset
| USART_TXFIFO_RESET //TX FIFO Reset
| USART_RXTRIGGER_LEVEL1); //RX Trigger Level(1/4/8/14 characters)
//===Scratch Pad===
//SN_USART1->SP = 0; //A readable, writable byte
//===Oversampling===
//SN_USART1->FD |= USART_OVER_SAMPLE_8; //OVER8(Oversampling Value), 1:Oversampling by 8. 0:Oversampling by 16
//===Half-duplex===
//SN_USART1->HDEN = 1; //Half-duplex mode enable
//===Interrupt Enable===
USART1_InterruptEnable();
//===USART Control===
SN_USART1->CTRL =(USART_EN //Enable USART0
| USART_MODE_UART //USART Mode = USAT
| USART_RX_EN //Enable RX
| USART_TX_EN); //Enable TX
//===NVIC===
NVIC_EnableIRQ(USART1_IRQn); //Enable USART1 INT
}
/*****************************************************************************
* Function : USART1_SendByte
* Description : USART1 Send data
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USART1_SendByte(void)
{
uint32_t i;
for (i=0; i<8; i++)
{
SN_USART1->TH= ('a'+i);
while ((SN_USART1->LS & 0x40) == 0);
}
}
/*****************************************************************************
* Function : USART1_AutoBaudrateInit
* Description : Initialization of USART1 Auto baud rate.
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USART1_AutoBaudrateInit(void)
{
SN_USART1->ABCTRL =(USART_ABTO_EN //Clear Auto Baud Time-out interrupt
| USART_ABEO_EN //Clear Auto Baud interrupt
| USART_ABCCTRL_RESTART //Restart in case of time-out
| USART_ABCCTRL_MODE1 //Auto Baud mode, 0:mode 0, 1:mode 1
| USART_ABCCTRL_START); //Auto Baud start, 0:stop(not running), 1:start(running)
}
/*****************************************************************************
* Function : USART1_Enable
* Description : Enable USART1
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USART1_Enable(void)
{
//Enable HCLK for USART1
SN_SYS1->AHBCLKEN |= USART1_CLK_EN; //Enables clock for USART0
SN_USART1->CTRL_b.USARTEN = USART_CTRL_EN; //USART enable bit
__USART1_RXFIFO_RESET;
__USART1_TXFIFO_RESET;
}
/*****************************************************************************
* Function : USART1_Disable
* Description : Disable USART1
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USART1_Disable(void)
{
SN_USART1->CTRL_b.USARTEN = USART_CTRL_DIS; //USART disable
//Disable HCLK for USART1
SN_SYS1->AHBCLKEN &= ~(USART1_CLK_EN); //Disable clock for USART0
}
/*****************************************************************************
* Function : USART1_InterruptEnable
* Description : Interrupt Enable
* Input : wTxhfie- TX half empty interrupt enable. 0: Disable, 1: Enable.
wRxhfie- RX half empty interrupt enable. 0: Disable, 1: Enable.
wRxtoie- RX Time-out interrupt enable. 0: Disable, 1: Enable.
wRxovfie- RXOverflow interrupt enable. 0: Disable, 1: Enable.
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USART1_InterruptEnable(void)
{
SN_USART1->IE =(USART_RDAIE_EN //Enables the Receive Data Available(RDA) interrupt
| USART_THREIE_EN //Enable THRE interrupt
| USART_RLSIE_EN //Enable Receive Line Status(RLS) interrupt
| USART_TEMTIE_EN //Enable TEMT interrupt
| USART_ABEOIE_EN //Enable Auto Baud interrupt
| USART_ABTOIE_EN //Enable Auto Baud time-out interrupt
| USART_TXERRIE_EN);//Enable TXERR interrupt
}

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os/hal/ports/SN32/LLD/SN32F24x/USB/driver.mk Normal file
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PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/USB/hal_usb_lld.c
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/USB/usbhw.c
PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/USB/usbsystem.c
PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F24x/USB

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os/hal/ports/SN32/LLD/SN32F24x/USB/hal_usb_lld.c Normal file
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os/hal/ports/SN32/LLD/SN32F24x/USB/hal_usb_lld.h Normal file
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/*
ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file hal_usb_lld.h
* @brief PLATFORM USB subsystem low level driver header.
*
* @addtogroup USB
* @{
*/
#ifndef HAL_USB_LLD_H
#define HAL_USB_LLD_H
#if (HAL_USE_USB == TRUE) || defined(__DOXYGEN__)
#include "sn32_usb.h"
/*===========================================================================*/
/* Driver constants. */
/*===========================================================================*/
/**
* @brief Status stage handling method.
*/
#define USB_EP0_STATUS_STAGE USB_EP0_STATUS_STAGE_SW
/**
* @brief The address can be changed immediately upon packet reception.
*/
#define USB_SET_ADDRESS_MODE USB_EARLY_SET_ADDRESS // FixMe: USB_LATE_SET_ADDRESS ?
/**
* @brief Method for set address acknowledge.
*/
#define USB_SET_ADDRESS_ACK_HANDLING USB_SET_ADDRESS_ACK_SW
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
/**
* @name PLATFORM configuration options
* @{
*/
/**
* @brief USB driver enable switch.
* @details If set to @p TRUE the support for USB1 is included.
* @note The default is @p FALSE.
*/
#if !defined(PLATFORM_USB_USE_USB1) || defined(__DOXYGEN__)
#define PLATFORM_USB_USE_USB1 TRUE
#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
/**
* @brief Type of an IN endpoint state structure.
*/
typedef struct {
/**
* @brief Requested transmit transfer size.
*/
size_t txsize;
/**
* @brief Transmitted bytes so far.
*/
size_t txcnt;
/**
* @brief Pointer to the transmission linear buffer.
*/
const uint8_t *txbuf;
#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__)
/**
* @brief Waiting thread.
*/
thread_reference_t thread;
#endif
/* End of the mandatory fields.*/
/**
* @brief Size of the last transmitted packet.
*/
size_t txlast;
} USBInEndpointState;
/**
* @brief Type of an OUT endpoint state structure.
*/
typedef struct {
/**
* @brief Requested receive transfer size.
*/
size_t rxsize;
/**
* @brief Received bytes so far.
*/
size_t rxcnt;
/**
* @brief Pointer to the receive linear buffer.
*/
uint8_t *rxbuf;
#if (USB_USE_WAIT == TRUE) || defined(__DOXYGEN__)
/**
* @brief Waiting thread.
*/
thread_reference_t thread;
#endif
/* End of the mandatory fields.*/
/**
* @brief Number of packets to receive.
*/
uint16_t rxpkts;
} USBOutEndpointState;
/**
* @brief Type of an USB endpoint configuration structure.
* @note Platform specific restrictions may apply to endpoints.
*/
typedef struct {
/**
* @brief Type and mode of the endpoint.
*/
uint32_t ep_mode;
/**
* @brief Setup packet notification callback.
* @details This callback is invoked when a setup packet has been
* received.
* @post The application must immediately call @p usbReadPacket() in
* order to access the received packet.
* @note This field is only valid for @p USB_EP_MODE_TYPE_CTRL
* endpoints, it should be set to @p NULL for other endpoint
* types.
*/
usbepcallback_t setup_cb;
/**
* @brief IN endpoint notification callback.
* @details This field must be set to @p NULL if the IN endpoint is not
* used.
*/
usbepcallback_t in_cb;
/**
* @brief OUT endpoint notification callback.
* @details This field must be set to @p NULL if the OUT endpoint is not
* used.
*/
usbepcallback_t out_cb;
/**
* @brief IN endpoint maximum packet size.
* @details This field must be set to zero if the IN endpoint is not
* used.
*/
uint16_t in_maxsize;
/**
* @brief OUT endpoint maximum packet size.
* @details This field must be set to zero if the OUT endpoint is not
* used.
*/
uint16_t out_maxsize;
/**
* @brief @p USBEndpointState associated to the IN endpoint.
* @details This structure maintains the state of the IN endpoint.
*/
USBInEndpointState *in_state;
/**
* @brief @p USBEndpointState associated to the OUT endpoint.
* @details This structure maintains the state of the OUT endpoint.
*/
USBOutEndpointState *out_state;
/* End of the mandatory fields.*/
/* End of the mandatory fields.*/
/**
* @brief Reserved field, not currently used.
* @note Initialize this field to 1 in order to be forward compatible.
*/
uint16_t ep_buffers;
/**
* @brief Pointer to a buffer for setup packets.
* @details Setup packets require a dedicated 8-bytes buffer, set this
* field to @p NULL for non-control endpoints.
*/
uint8_t *setup_buf;
} USBEndpointConfig;
/**
* @brief Type of an USB driver configuration structure.
*/
typedef struct {
/**
* @brief USB events callback.
* @details This callback is invoked when an USB driver event is registered.
*/
usbeventcb_t event_cb;
/**
* @brief Device GET_DESCRIPTOR request callback.
* @note This callback is mandatory and cannot be set to @p NULL.
*/
usbgetdescriptor_t get_descriptor_cb;
/**
* @brief Requests hook callback.
* @details This hook allows to be notified of standard requests or to
* handle non standard requests.
*/
usbreqhandler_t requests_hook_cb;
/**
* @brief Start Of Frame callback.
*/
usbcallback_t sof_cb;
/* End of the mandatory fields.*/
} USBConfig;
/**
* @brief Structure representing an USB driver.
*/
struct USBDriver {
/**
* @brief Driver state.
*/
usbstate_t state;
/**
* @brief Current configuration data.
*/
const USBConfig *config;
/**
* @brief Bit map of the transmitting IN endpoints.
*/
uint16_t transmitting;
/**
* @brief Bit map of the receiving OUT endpoints.
*/
uint16_t receiving;
/**
* @brief Active endpoints configurations.
*/
const USBEndpointConfig *epc[USB_MAX_ENDPOINTS + 1];
/**
* @brief Fields available to user, it can be used to associate an
* application-defined handler to an IN endpoint.
* @note The base index is one, the endpoint zero does not have a
* reserved element in this array.
*/
void *in_params[USB_MAX_ENDPOINTS];
/**
* @brief Fields available to user, it can be used to associate an
* application-defined handler to an OUT endpoint.
* @note The base index is one, the endpoint zero does not have a
* reserved element in this array.
*/
void *out_params[USB_MAX_ENDPOINTS];
/**
* @brief Endpoint 0 state.
*/
usbep0state_t ep0state;
/**
* @brief Next position in the buffer to be transferred through endpoint 0.
*/
uint8_t *ep0next;
/**
* @brief Number of bytes yet to be transferred through endpoint 0.
*/
size_t ep0n;
/**
* @brief Endpoint 0 end transaction callback.
*/
usbcallback_t ep0endcb;
/**
* @brief Setup packet buffer.
*/
uint8_t setup[8];
/**
* @brief Current USB device status.
*/
uint16_t status;
/**
* @brief Assigned USB address.
*/
uint8_t address;
/**
* @brief Current USB device configuration.
*/
uint8_t configuration;
/**
* @brief State of the driver when a suspend happened.
*/
usbstate_t saved_state;
#if defined(USB_DRIVER_EXT_FIELDS)
USB_DRIVER_EXT_FIELDS
#endif
/* End of the mandatory fields.*/
/**
* @brief Pointer to the next address in the packet memory.
*/
uint32_t pmnext;
};
/*===========================================================================*/
/* Driver macros. */
/*===========================================================================*/
/**
* @brief Returns the current frame number.
*
* @param[in] usbp pointer to the @p USBDriver object
* @return The current frame number.
*
* @notapi
*/
#define usb_lld_get_frame_number(usbp) 0
/**
* @brief Returns the exact size of a receive transaction.
* @details The received size can be different from the size specified in
* @p usbStartReceiveI() because the last packet could have a size
* different from the expected one.
* @pre The OUT endpoint must have been configured in transaction mode
* in order to use this function.
*
* @param[in] usbp pointer to the @p USBDriver object
* @param[in] ep endpoint number
* @return Received data size.
*
* @notapi
*/
#define usb_lld_get_transaction_size(usbp, ep) \
((usbp)->epc[ep]->out_state->rxcnt)
/**
* @brief Connects the USB device.
*
* @api
*/
#define usb_lld_connect_bus(usbp)
/**
* @brief Disconnect the USB device.
*
* @api
*/
#define usb_lld_disconnect_bus(usbp)
/**
* @brief Start of host wake-up procedure.
*
* @notapi
*/
#define usb_lld_wakeup_host(usbp)
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
/* Descriptor related */
/* bmAttributes in Endpoint Descriptor */
#define USB_ENDPOINT_TYPE_MASK 0x03
#define USB_ENDPOINT_TYPE_CONTROL 0x00
#define USB_ENDPOINT_TYPE_ISOCHRONOUS 0x01
#define USB_ENDPOINT_TYPE_BULK 0x02
#define USB_ENDPOINT_TYPE_INTERRUPT 0x03
#define USB_ENDPOINT_SYNC_MASK 0x0C
#define USB_ENDPOINT_SYNC_NO_SYNCHRONIZATION 0x00
#define USB_ENDPOINT_SYNC_ASYNCHRONOUS 0x04
#define USB_ENDPOINT_SYNC_ADAPTIVE 0x08
#define USB_ENDPOINT_SYNC_SYNCHRONOUS 0x0C
#define USB_ENDPOINT_USAGE_MASK 0x30
#define USB_ENDPOINT_USAGE_DATA 0x00
#define USB_ENDPOINT_USAGE_FEEDBACK 0x10
#define USB_ENDPOINT_USAGE_IMPLICIT_FEEDBACK 0x20
#define USB_ENDPOINT_USAGE_RESERVED 0x30
/* bEndpointAddress in Endpoint Descriptor */
#define USB_ENDPOINT_DIRECTION_MASK 0x80
#if (PLATFORM_USB_USE_USB1 == TRUE) && !defined(__DOXYGEN__)
extern USBDriver USBD1;
#endif
#ifdef __cplusplus
extern "C" {
#endif
void usb_lld_init(void);
void usb_lld_start(USBDriver *usbp);
void usb_lld_stop(USBDriver *usbp);
void usb_lld_reset(USBDriver *usbp);
void usb_lld_set_address(USBDriver *usbp);
void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep);
void usb_lld_disable_endpoints(USBDriver *usbp);
usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep);
usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep);
void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf);
void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep);
void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep);
void usb_lld_start_out(USBDriver *usbp, usbep_t ep);
void usb_lld_start_in(USBDriver *usbp, usbep_t ep);
void usb_lld_stall_out(USBDriver *usbp, usbep_t ep);
void usb_lld_stall_in(USBDriver *usbp, usbep_t ep);
void usb_lld_clear_out(USBDriver *usbp, usbep_t ep);
void usb_lld_clear_in(USBDriver *usbp, usbep_t ep);
#ifdef __cplusplus
}
#endif
#endif /* HAL_USE_USB == TRUE */
#endif /* HAL_USB_LLD_H */
/** @} */

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/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/**
* @file USBv1/sn32_usb.h
* @brief SN32 USB registers layout header.
* @note This file requires definitions from the ST STM32 header files
* sn32f124x.h
*
* @addtogroup USB
* @{
*/
#ifndef SN32_USB_H
#define SN32_USB_H
// TODO: ENDPOINTS nubmer is chip dependent and needs to be organized better
/**
* @brief Number of the available endpoints.
* @details This value does not include the endpoint 0 which is always present.
*/
#define USB_MAX_ENDPOINTS 6
/**
* @brief USB registers block numeric address.
*/
#define SN32_USB_BASE SN_USB_BASE
/**
* @brief USB RAM numeric address.
*/
#define SN32_USBRAM_BASE SN_USB_BASE + 0x100
/**
* @brief Pointer to the USB registers block.
*/
// #define SN32_USB ((sn32_usb_t *)SN32_USB_BASE)
/**
* @brief Pointer to the USB RAM.
*/
#define SN32_USBRAM ((sn32_usb_pma_t *)SN32_USBRAM_BASE)
#endif /* SN32_USB_H */
/** @} */

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/*----------------------------------------------------------------------------
* U S B - K e r n e l
*----------------------------------------------------------------------------
* Name: usbhw.c
* Purpose: USB Custom User Module
* Version: V1.01
* Date: 2017/07
*------------------------------------------------------------------------------*/
#include <SN32F240.h>
#include "SN32F200_Def.h"
#include "usbhw.h"
#include "usbsystem.h"
volatile uint32_t wUSB_EPnOffset[7];
volatile uint32_t wUSB_EPnMaxPacketsize[7];
/*****************************************************************************
* Function : USB_Init
* Description : 1. setting IDLE_TIME, REPORT_PROTOCOL, S_USB_EP0setupdata.wUSB_Status
* 2. set EP1~EP6 FIFO RAM address.
* 3. save EP1~EP6 FIFO RAM point address.
* 4. save EP1~EP6 Package Size.
* 5. Enable USB function and setting EP1~EP6 Direction.
* 6. NEVER REMOVE !! USB D+/D- Dischage
* 7. Enable USB PHY and USB interrupt.
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USB_Init (void)
{
volatile uint32_t *pRam;
uint32_t wTmp, i;
/* Initialize clock and Enable USB PHY. */
USB_SystemInit(); // enable System,PLL,EHS XTAL by user setting
SN_SYS1->AHBCLKEN |= 0x02; // Enable USBCLKEN
__USB_PHY_ENABLE; // enable ESD_EN & PHY_EN
/* Initialize USB EP1~EP6 RAM address base on 64-bytes. */
USB_EPnBufferOffset(1,EP1_BUFFER_OFFSET_VALUE);
USB_EPnBufferOffset(2,EP2_BUFFER_OFFSET_VALUE);
USB_EPnBufferOffset(3,EP3_BUFFER_OFFSET_VALUE);
USB_EPnBufferOffset(4,EP4_BUFFER_OFFSET_VALUE);
USB_EPnBufferOffset(5,EP5_BUFFER_OFFSET_VALUE);
USB_EPnBufferOffset(6,EP6_BUFFER_OFFSET_VALUE);
/* Initialize EP1~EP6 RAM point address to array(wUSB_EPnOffset).*/
pRam = &wUSB_EPnOffset[0];
*(pRam+0) = (uint32_t)(&USB_SRAM_EP0_W0) + EP1_BUFFER_OFFSET_VALUE;
*(pRam+1) = (uint32_t)(&USB_SRAM_EP0_W0) + EP2_BUFFER_OFFSET_VALUE;
*(pRam+2) = (uint32_t)(&USB_SRAM_EP0_W0) + EP3_BUFFER_OFFSET_VALUE;
*(pRam+3) = (uint32_t)(&USB_SRAM_EP0_W0) + EP4_BUFFER_OFFSET_VALUE;
*(pRam+4) = (uint32_t)(&USB_SRAM_EP0_W0) + EP5_BUFFER_OFFSET_VALUE;
*(pRam+5) = (uint32_t)(&USB_SRAM_EP0_W0) + EP6_BUFFER_OFFSET_VALUE;
/* Initialize EP0~EP6 package size to array(wUSB_EPnPacketsize).*/
pRam = &wUSB_EPnMaxPacketsize[0];
*(pRam+0) = USB_EP0_PACKET_SIZE;
*(pRam+1) = USB_EP1_PACKET_SIZE;
*(pRam+2) = USB_EP2_PACKET_SIZE;
*(pRam+3) = USB_EP3_PACKET_SIZE;
*(pRam+4) = USB_EP4_PACKET_SIZE;
*(pRam+5) = USB_EP5_PACKET_SIZE;
*(pRam+6) = USB_EP6_PACKET_SIZE;
/* Enable the USB Interrupt */
SN_USB->INTEN = (mskBUS_IE|mskUSB_IE|mskUSB_BUSWK_IE);
SN_USB->INTEN |= mskEP1_NAK_EN;
SN_USB->INTEN |= mskEP2_NAK_EN;
SN_USB->INTEN |= mskEP3_NAK_EN;
SN_USB->INTEN |= mskEP4_NAK_EN;
SN_USB->INTEN |= mskEP5_NAK_EN;
SN_USB->INTEN |= mskEP6_NAK_EN;
SN_USB->INTEN |= mskUSB_SOF_IE;
NVIC_ClearPendingIRQ(USB_IRQn);
NVIC_EnableIRQ(USB_IRQn);
/* BUS_DRVEN = 0, BUS_DP = 1, BUS_DN = 0 */
SN_USB->SGCTL = mskBUS_J_STATE;
/* VREG33_EN = 1, PHY_EN = 1, DPPU_EN = 1, SIE_EN = 1, USBRAM_EN = 1, FLTDET_PUEN = 1 */
wTmp = (mskVREG33_EN|mskPHY_EN|mskDPPU_EN|mskSIE_EN|mskESD_EN|mskUSBRAM_EN|mskVREG33DIS_EN|mskFLTDET_PUEN_DISABLE);
//!!NEVER REMOVE!!!
SN_USB->CFG = wTmp;
for (i = 0; i < DISCHARE_DELAY; i++);
SN_USB->CFG = (wTmp&(~mskVREG33DIS_EN))|mskDPPU_EN;
//!!NEVER REMOVE!!!
SN_USB->PHYPRM = (0x01U<<31);
return;
}
/*****************************************************************************
* Function : USB_ClrEPnToggle
* Description : USB Clear EP1~EP6 toggle bit to DATA0
* write 1: toggle bit Auto.
* write 0: clear EPn toggle bit to DATA0
* Input : hwEPNum ->EP1~EP6
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USB_ClrEPnToggle (uint32_t hwEPNum)
{
SN_USB->EPTOGGLE &= ~(0x1<<hwEPNum);
}
/*****************************************************************************
* Function : USB_EPnDisable
* Description : Disable EP1~EP6
* Input : wEPNum
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USB_EPnDisable (uint32_t wEPNum)
{
volatile uint32_t *pEPn_ptr;
if(wEPNum > USB_EP6)
return;
pEPn_ptr = &SN_USB->EP0CTL + wEPNum;
*pEPn_ptr = 0; //** SET DISABLE. No handshake IN/OUT token.
}
/*****************************************************************************
* Function : USB_EPnNak
* Description : SET EP1~EP6 is NAK.
* For IN will handshake NAK to IN token.
* For OUT will handshake NAK to OUT token.
* Input : wEPNum
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USB_EPnNak (uint32_t wEPNum)
{
volatile uint32_t *pEPn_ptr;
if(wEPNum > USB_EP6)
return;
pEPn_ptr = &SN_USB->EP0CTL + wEPNum;
*pEPn_ptr = mskEPn_ENDP_EN; //** SET NAK
}
/*****************************************************************************
* Function : USB_EPnAck
* Description : SET EP1~EP6 is ACK.
* For IN will handshake bBytent to IN token.
* For OUT will handshake ACK to OUT token.
* Input : wEPNum:EP1~EP6.
* bBytecnt: Byte Number of Handshake.
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USB_EPnAck (uint32_t wEPNum, uint8_t bBytecnt)
{
volatile uint32_t *pEPn_ptr;
if (wEPNum > USB_EP6)
return;
pEPn_ptr = &SN_USB->EP0CTL + wEPNum;
*pEPn_ptr = (mskEPn_ENDP_EN|mskEPn_ENDP_STATE_ACK|bBytecnt);
}
/*****************************************************************************
* Function : USB_EPnAck
* Description : SET EP1~EP6 is STALL. For IN will handshake STALL to IN token.
* For OUT will handshake STALL to OUT token.
* Input : wEPNum:EP1~EP6.
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USB_EPnStall (uint32_t wEPNum)
{
volatile uint32_t *pEPn_ptr;
if(wEPNum > USB_EP6) //wEPNum != EP0~EP6
return;
pEPn_ptr = &SN_USB->EP0CTL + wEPNum;
if (wEPNum == USB_EP0)
{
if(SN_USB->INSTS & mskEP0_PRESETUP)
return;
}
*pEPn_ptr = (mskEPn_ENDP_EN|mskEPn_ENDP_STATE_STALL);
}
/*****************************************************************************
* Function : USB_EPnEnabled
* Description : check if EP0~EP4 enabled or not
* Input : wEPNum:EP0~EP4.
* Output : None
* Return : true - enabled/false - disabled
* Note : None
*****************************************************************************/
_Bool USB_EPnEnabled(uint32_t wEPNum)
{
volatile uint32_t *pEPn_ptr;
if(wEPNum > USB_EP6) //** wEPNum != EP0~EP6
return 0;
pEPn_ptr = &SN_USB->EP0CTL + wEPNum;
return (((*pEPn_ptr) & mskEPn_ENDP_EN) == mskEPn_ENDP_EN);
}
/*****************************************************************************
* Function : USB_EPnStalled
* Description : GET EP0~EP4 state.
* Input : wEPNum:EP0~EP4.
* Output : None
* Return : mskEPn_ENDP_STATE
* Note : None
*****************************************************************************/
_Bool USB_EPnStalled(uint32_t wEPNum)
{
volatile uint32_t *pEPn_ptr;
if(wEPNum > USB_EP6) //** wEPNum != EP0~EP6
return 0;
pEPn_ptr = &SN_USB->EP0CTL + wEPNum;
return (((*pEPn_ptr) & mskEPn_ENDP_STATE) == mskEPn_ENDP_STATE_STALL);
}
/*****************************************************************************
* Function : USB_RemoteWakeUp
* Description : USB Remote wakeup: USB D+/D- siganl is J-K state.
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USB_RemoteWakeUp()
{
__USB_JSTATE_DRIVER; //** J state ;Full speed D+ = 1, D- = 0
USB_DelayJstate();
__USB_KSTATE_DRIVER; //** K state ;Full speed D+ = 0, D- = 1
USB_DelayKstate();
SN_USB->SGCTL &= ~mskBUS_DRVEN;
}
/*****************************************************************************
* Function : USB_DelayJstate
* Description : For J state delay. about 180us
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USB_DelayJstate()
{
uint32_t i;
for (i = 0; i < 300; i++)
; // delay 180us
}
/*****************************************************************************
* Function : USB_DelayKstate
* Description : For K state delay. about 14 ~ 14.5ms
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USB_DelayKstate()
{
uint32_t i;
for (i = 0; i < K_STATE_DELAY; i++)
; // require delay 1ms ~ 15ms
}
/*****************************************************************************
* Function : USB_EPnBufferOffset
* Description : SET EP1~EP6 RAM point address
* Input : wEPNum: EP1~EP6
* wAddr of device address
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USB_EPnBufferOffset(uint32_t wEPNum, uint32_t wAddr)
{
volatile uint32_t *pEPn_ptr;
if ((wEPNum > USB_EP0) && (wEPNum <= USB_EP6)) //wEPNum = EP1 ~ EP6
{
pEPn_ptr = &SN_USB->EP1BUFOS; // Assign point to EP1 RAM address
*(pEPn_ptr+wEPNum-1) = wAddr; // SET point to EPn RAM address
}
}
/*****************************************************************************
* Function : USB_ResetEvent
* Description : recevice USB bus reset to Initial parameter
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USB_ResetEvent (void)
{
uint32_t wLoop;
__USB_CLRINSTS(0xFFFFFFFF); // Clear all USB Event status
__USB_SETADDRESS(0); // Set USB address = 0
USB_EPnStall(USB_EP0); // Set EP0 enable & INOUTSTALL
for (wLoop=USB_EP1; wLoop<=USB_EP6; wLoop++)
USB_EPnDisable(wLoop); // Set EP1~EP6 disable & NAK
}
/*****************************************************************************
* Function : USB_WakeupEvent
* Description : Enable USB CLK and PHY
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void USB_WakeupEvent (void)
{
USB_SystemInit(); // enable System,PLL,EHS XTAL by user setting
__USB_PHY_ENABLE; //** enable ESD_EN & PHY_EN
__USB_CLRINSTS(mskBUS_WAKEUP); //** Clear BUS_WAKEUP
}

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/****************************************************************************
****************************************************************************
****************************************************************************/
#ifndef __USBHW_H__
#define __USBHW_H__
//** USB Remote Wakeup I/O Define
//** USB Remote Wakeup I/O Port Define, Default P1.5
#define REMOTE_WAKEUP_IO_P0 DISABLE
#define REMOTE_WAKEUP_IO_P1 ENABLE
#define REMOTE_WAKEUP_IO_P2 DISABLE
#define REMOTE_WAKEUP_IO_P3 DISABLE
//** USB Remote Wakeup I/O Bit Define
#define REMOTE_WAKEUP_IO_P0_BIT 0x0000
#define REMOTE_WAKEUP_IO_P1_BIT 0x0020
#define REMOTE_WAKEUP_IO_P2_BIT 0x0000
#define REMOTE_WAKEUP_IO_P3_BIT 0x0000
//** USB EPn NAK interrupt
#define EP1_NAK_IE DISABLE
#define EP2_NAK_IE DISABLE
#define EP3_NAK_IE DISABLE
#define EP4_NAK_IE DISABLE
//** USB SOF interrupt
#define SOF_IE DISABLE
/* AHB Clock Enable register <SYS1_AHBCLKEN> */
#define mskP0CLK_EN (0x1<<0)
#define mskP1CLK_EN (0x1<<1)
#define mskP2CLK_EN (0x1<<2)
#define mskP3CLK_EN (0x1<<3)
#define mskUSBCLK_EN (0x1<<4)
#define mskCT16B0CLK_EN (0x1<<6)
#define mskCT16B1CLK_EN (0x1<<7)
#define mskADCCLK_EN (0x1<<11)
#define mskSPI0CLK_EN (0x1<<12)
#define mskUART0CLK_EN (0x1<<16)
#define mskUART1CLK_EN (0x1<<17)
#define mskUART2CLK_EN (0x1<<18)
#define mskI2C0CLK_EN (0x1<<21)
#define mskWDTCLK_EN (0x1<<24)
/* USB Interrupt Enable Bit Definitions <USB_INTEN> */
#define mskEP1_NAK_EN (0x1<<0)
#define mskEP2_NAK_EN (0x1<<1)
#define mskEP3_NAK_EN (0x1<<2)
#define mskEP4_NAK_EN (0x1<<3)
#define mskEP5_NAK_EN (0x1<<4)
#define mskEP6_NAK_EN (0x1<<5)
#define mskUSB_BUSWK_IE (0x1<<28)
#define mskUSB_IE (0x1<<29)
#define mskUSB_SOF_IE (0x1<<30)
#define mskBUS_IE (0x1U<<31)
/* USB Interrupt Event Status Bit Definitions <USB_INSTS/USB_INSTSC> */
#define mskEP1_NAK (0x1<<0)
#define mskEP2_NAK (0x1<<1)
#define mskEP3_NAK (0x1<<2)
#define mskEP4_NAK (0x1<<3)
#define mskEP5_NAK (0x1<<4)
#define mskEP6_NAK (0x1<<5)
#define mskEP1_ACK (0x1<<8)
#define mskEP2_ACK (0x1<<9)
#define mskEP3_ACK (0x1<<10)
#define mskEP4_ACK (0x1<<11)
#define mskEP5_ACK (0x1<<12)
#define mskEP6_ACK (0x1<<13)
#define mskERR_TIMEOUT (0x1<<17)
#define mskERR_SETUP (0x1<<18)
#define mskEP0_OUT_STALL (0x1<<19)
#define mskEP0_IN_STALL (0x1<<20)
#define mskEP0_OUT (0x1<<21)
#define mskEP0_IN (0x1<<22)
#define mskEP0_SETUP (0x1<<23)
#define mskEP0_PRESETUP (0x1<<24)
#define mskBUS_WAKEUP (0x1<<25)
#define mskUSB_SOF (0x1<<26)
#define mskBUS_RESUME (0x1<<29)
#define mskBUS_SUSPEND (0x1<<30)
#define mskBUS_RESET (0x1U<<31)
/* USB Device Address Bit Definitions <USB_ADDR> */
#define mskUADDR (0x7F<<0)
/* USB Configuration Bit Definitions <USB_CFG> */
#define mskEP1_DIR (0x1<<0)
#define mskEP2_DIR (0x1<<1)
#define mskEP3_DIR (0x1<<2)
#define mskEP4_DIR (0x1<<3)
#define mskEP5_DIR (0x1<<4)
#define mskEP6_DIR (0x1<<5)
#define mskEP2_ISO (0x1<<9)
#define mskEP3_ISO (0x1<<10)
#define mskEP4_ISO (0x1<<11)
#define mskEP5_ISO (0x1<<12)
#define mskEP6_ISO (0x1<<13)
#define mskVREG33DIS_EN (0x1<<31)
#define mskUSBRAM_EN (0x1<<25)
#define mskFLTDET_PUEN_DISABLE (0x1<<26) // FixMe ? // #define mskDIS_PDEN (0x1<<26)
#define mskESD_EN (0x1<<27)
#define mskSIE_EN (0x1<<28)
#define mskDPPU_EN (0x1<<29)
#define mskPHY_EN (0x1<<30)
#define mskVREG33_EN (0x1U<<31)
/* USB Signal Control Bit Definitions <USB_SGCTL> */
#define mskBUS_DRVEN (0x1<<2)
#define mskBUS_DPDN_STATE (0x3<<0)
#define mskBUS_J_STATE (0x2<<0) // D+ = 1, D- = 0
#define mskBUS_K_STATE (0x1<<0) // D+ = 0, D- = 1
#define mskBUS_SE0_STATE (0x0<<0) // D+ = 0, D- = 0
#define mskBUS_SE1_STATE (0x3<<0) // D+ = 1, D- = 1
#define mskBUS_IDLE_STATE mskBUS_J_STATE
/* USB Configuration Bit Definitions <USB_EPnCTL> */
#define mskEPn_CNT (0x1FF<<0)
#define mskEP0_OUT_STALL_EN (0x1<<27)
#define mskEP0_IN_STALL_EN (0x1<<28)
#define mskEPn_ENDP_STATE (0x3<<29)
#define mskEPn_ENDP_STATE_ACK (0x1<<29)
#define mskEPn_ENDP_STATE_NAK (0x0<<29)
#define mskEPn_ENDP_STATE_STALL (0x3<<29)
#define mskEPn_ENDP_EN (0x1U<<31)
/* USB Endpoint Data Toggle Bit Definitions <USB_EPTOGGLE> */
#define mskEP1_CLEAR_DATA0 (0x1<<0)
#define mskEP2_CLEAR_DATA0 (0x1<<1)
#define mskEP3_CLEAR_DATA0 (0x1<<2)
#define mskEP4_CLEAR_DATA0 (0x1<<3)
#define mskEP5_CLEAR_DATA0 (0x1<<4)
#define mskEP6_CLEAR_DATA0 (0x1<<5)
/* USB Endpoint n Buffer Offset Bit Definitions <USB_EPnBUFOS> */
#define mskEPn_OFFSET (0x1FF<<0)
/* USB Frame Number Bit Definitions <USB_FRMNO> */
#define mskFRAME_NO (0x7FF<<0)
/* Rx & Tx Packet Length Definitions */
#define PKT_LNGTH_MASK 0x000003FF
/* nUsb_Status Register Definitions */
#define mskBUSRESET (0x1<<0)
#define mskBUSSUSPEND (0x1<<1)
#define mskBUSRESUME (0x1<<2)
#define mskREMOTEWAKEUP (0x1<<3)
#define mskSETCONFIGURATION0CMD (0x1<<4)
#define mskSETADDRESS (0x1<<5)
#define mskSETADDRESSCMD (0x1<<6)
#define mskREMOTE_WAKEUP (0x1<<7)
#define mskDEV_FEATURE_CMD (0x1<<8)
#define mskSET_REPORT_FLAG (0x1<<9)
#define mskPROTOCOL_GET_REPORT (0x1<<10)
#define mskPROTOCOL_SET_IDLE (0x1<<11)
#define mskPROTOCOL_ARRIVAL (0x1<<12)
#define mskSET_REPORT_DONE (0x1<<13)
#define mskNOT_8BYTE_ENDDING (0x1<<14)
#define mskSETUP_OUT (0x1<<15)
#define mskSETUP_IN (0x1<<16)
#define mskINITREPEAT (0x1<<17)
#define mskREMOTE_WAKEUP_ACT (0x1<<18)
//ISP KERNEL MODE
#define RETURN_KERNEL_0 0x5AA555AA
#define RETURN_KERNEL_1 0xCC3300FF
/*********Marco function***************/
//USB device address set
#define __USB_SETADDRESS(addr) (SN_USB->ADDR = addr)
//USB INT status register clear
#define __USB_CLRINSTS(Clrflag) (SN_USB->INSTSC = Clrflag)
//USB EP0_IN token set STALL
#define __USB_EP0INSTALL_EN (SN_USB->EP0CTL |= mskEP0_IN_STALL_EN)
//USB EP0_OUT token set STALL
#define __USB_EP0OUTSTALL_EN (SN_USB->EP0CTL |= mskEP0_OUT_STALL_EN)
//USB bus driver J state
#define __USB_JSTATE_DRIVER (SN_USB->SGCTL = (mskBUS_DRVEN|mskBUS_J_STATE))
//USB bus driver K state
#define __USB_KSTATE_DRIVER (SN_USB->SGCTL = (mskBUS_DRVEN|mskBUS_K_STATE))
//USB PHY set enable
#define __USB_PHY_ENABLE (SN_USB->CFG |= (mskESD_EN|mskPHY_EN))
//USB PHY set Disable
#define __USB_PHY_DISABLE (SN_USB->CFG &= ~(mskESD_EN|mskPHY_EN))
/***************************************/
/* USB SRAM */
#define USB_SRAM_EP0_W0 *((uint32_t *)&SN_USB->SRAM+0) // EP0 SRAM Byte 0~3
#define USB_SRAM_EP0_W1 *((uint32_t *)&SN_USB->SRAM+1) // EP0 SRAM Byte 4~7
#define USB_SRAM_EP0_W2 *((uint32_t *)&SN_USB->SRAM+2) // EP0 SRAM Byte 8~11
#define USB_SRAM_EP0_W3 *((uint32_t *)&SN_USB->SRAM+3) // EP0 SRAM Byte 12~15
#define USB_SRAM_EP0_W4 *((uint32_t *)&SN_USB->SRAM+4) // EP0 SRAM Byte 16~19
#define USB_SRAM_EP0_W5 *((uint32_t *)&SN_USB->SRAM+5) // EP0 SRAM Byte 20~23
#define USB_SRAM_EP0_W6 *((uint32_t *)&SN_USB->SRAM+6) // EP0 SRAM Byte 24~27
#define USB_SRAM_EP0_W7 *((uint32_t *)&SN_USB->SRAM+7) // EP0 SRAM Byte 28~31
#define USB_SRAM_EP0_W8 *((uint32_t *)&SN_USB->SRAM+8) // EP0 SRAM Byte 32~35
#define USB_SRAM_EP0_W9 *((uint32_t *)&SN_USB->SRAM+9) // EP0 SRAM Byte 36~39
#define USB_SRAM_EP0_W10 *((uint32_t *)&SN_USB->SRAM+10) // EP0 SRAM Byte 40~43
#define USB_SRAM_EP0_W11 *((uint32_t *)&SN_USB->SRAM+11) // EP0 SRAM Byte 44~47
#define USB_SRAM_EP0_W12 *((uint32_t *)&SN_USB->SRAM+12) // EP0 SRAM Byte 48~51
#define USB_SRAM_EP0_W13 *((uint32_t *)&SN_USB->SRAM+13) // EP0 SRAM Byte 52~55
#define USB_SRAM_EP0_W14 *((uint32_t *)&SN_USB->SRAM+14) // EP0 SRAM Byte 56~59
#define USB_SRAM_EP0_W15 *((uint32_t *)&SN_USB->SRAM+15) // EP0 SRAM Byte 60~63
/* TODO: orgaize better since this is MCU dependent:
* 240b has 1+4 EPs/256 Bytes USB SRAM
* 240 has 1+6 EPs/512 Bytes USB SRAM
* 260 has 1+4 EPs/256 Bytes USB SRAM
* */
// USB EPn Buffer Offset Register
#define EP1_BUFFER_OFFSET_VALUE 0x40
#define EP2_BUFFER_OFFSET_VALUE 0x80
#define EP3_BUFFER_OFFSET_VALUE 0xC0
#define EP4_BUFFER_OFFSET_VALUE 0x100
#define EP5_BUFFER_OFFSET_VALUE 0x140
#define EP6_BUFFER_OFFSET_VALUE 0x180
/* USB Endpoint Max Packet Size */
#define USB_EP0_PACKET_SIZE 64 // only 8, 64
#define USB_EP1_PACKET_SIZE 0x40
#define USB_EP2_PACKET_SIZE 0x40
#define USB_EP3_PACKET_SIZE 0x20
#define USB_EP4_PACKET_SIZE 0x20
#define USB_EP5_PACKET_SIZE 0x20
#define USB_EP6_PACKET_SIZE 0x20
/* USB Endpoint Direction */
#define USB_DIRECTION_OUT 0
#define USB_DIRECTION_IN 1
/* USB Endpoint Address */
#define USB_EP0 0x0
#define USB_EP1 0x1
#define USB_EP2 0x2
#define USB_EP3 0x3
#define USB_EP4 0x4
#define USB_EP5 0x5
#define USB_EP6 0x6
extern volatile uint32_t wUSB_EPnOffset[];
extern volatile uint32_t wUSB_EPnMaxPacketSize[];
/* USB Hardware Functions */
extern void USB_Init(void);
extern void USB_ClrEPnToggle(uint32_t wEPNum);
extern void USB_EPnDisable(uint32_t wEPNum);
extern void USB_EPnNak(uint32_t wEPNum);
extern void USB_EPnAck(uint32_t wEPNum, uint8_t bBytecnt);
extern void USB_EPnStall(uint32_t wEPNum);
extern _Bool USB_EPnEnabled(uint32_t wEPNum);
extern _Bool USB_EPnStalled(uint32_t wEPNum);
extern void USB_RemoteWakeUp(void);
extern void USB_DelayJstate(void);
extern void USB_DelayKstate(void);
extern void USB_EPnBufferOffset(uint32_t wEPNum, uint32_t wAddr);
/* USB IRQ Functions*/
extern void USB_ResetEvent(void);
extern void USB_WakeupEvent(void);
#endif /* __USBHW_H__ */

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/*----------------------------------------------------------------------------
* U S B - K e r n e l
*----------------------------------------------------------------------------
* Name: usbsystem.c
* Purpose: USB Custom User Module
* Version: V1.01
* Date: 2013/12
*------------------------------------------------------------------------------*/
#include <SN32F240.h>
//#include "type.h"
//#include "..\Utility\Utility.h"
#include "usbsystem.h"
void USB_SystemInit (void)
{
SN_FLASH->LPCTRL = 0x5AFA0000; //Disable Slow mode power saving
//***********************************
#if (USB_SYS_CLOCK_SETUP)
#if (USB_SYS0_CLKCFG_VAL == USB_IHRC) //IHRC
SN_SYS0->ANBCTRL |= USB_IHRC_EN; //enable IHRC
while ((SN_SYS0->CSST & 0x01) != 0x01); //check IHRC ready
SN_SYS0->CLKCFG = 0x00; //switch IHRC
while ((SN_SYS0->CLKCFG & 0x70) != 0x00);
#endif
#if (USB_SYS0_CLKCFG_VAL == USB_ILRC) //ILRC
SN_SYS0->CLKCFG = 0x1;
while ((SN_SYS0->CLKCFG & 0x70) != 0x10); //switch ILRC
#endif
#if (USB_SYS0_CLKCFG_VAL == USB_EHSXTAL) //EHS XTAL
#if (USB_EHS_FREQ > 12)
SN_SYS0->ANBCTRL |= (1<<5); //Enable XTAL > 12MHz
#else
SN_SYS0->ANBCTRL &=~(1<<5); //Enable XTAL <= 12MHz
#endif
SN_SYS0->ANBCTRL |= (1<<4); //Enable XTAL
while ((SN_SYS0->CSST & 0x10) != 0x10);
SN_SYS0->CLKCFG = 0x02; //switch XTAL
while ((SN_SYS0->CLKCFG & 0x70) != 0X20);
#endif
#endif
#if (USB_PLL_ENABLE == 0x01) //SET PLL
SN_SYS0->PLLCTRL = USB_SYS0_PLLCTRL_EN; //ENABLE PLL
if(USB_PLL_CLKIN == 0x0) //PLL clk source is IHRC
{
SN_SYS0->ANBCTRL |= USB_IHRC_EN; //enable IHRC
SN_SYS0->PLLCTRL |= USB_PLL_CLKSOURCE_IHRC;
}
else //PLL clk source is XTAL
{
#if (USB_EHS_FREQ > 12)
SN_SYS0->ANBCTRL |= (1<<5); //Enable XTAL > 12MHz
#else
SN_SYS0->ANBCTRL &=~(1<<5); //Enable XTAL <= 12MHz
#endif
SN_SYS0->ANBCTRL |= (1<<4); //Enable XTAL
while ((SN_SYS0->CSST & 0x10) != 0x10);
#if (USB_EHS_FREQ == 12) //XTAL = 12MHz
//SN_SYS0->ANBCTRL |= (1<<5); //Enable XTAL < 12MHz
SN_SYS0->PLLCTRL |= USB_PLL_CLKSOURCE_12MHz;
#endif
#if (USB_EHS_FREQ == 16) //XTAL = 16MHz
SN_SYS0->ANBCTRL |=(1<<5); //Enable XTAL > 12MHz
SN_SYS0->PLLCTRL |= USB_PLL_CLKSOURCE_16MHz;
#endif
#if (USB_EHS_FREQ == 24) //XTAL = 24MHz
SN_SYS0->ANBCTRL |=(1<<5); //Enable XTAL > 12MHz
SN_SYS0->PLLCTRL |= USB_PLL_CLKSOURCE_24MHz;
#endif
SN_SYS0->ANBCTRL |= (1<<4); //Enable EHS XTAL
while ((SN_SYS0->CSST & 0x10) != 0x10);
#if (USB_PLL_CLKIN == 0x01 )
SN_SYS0->PLLCTRL |= (0x01<<12);
SN_SYS0->PLLCTRL |= (0x01<<15); //ENABLE PLL
#endif
}
#endif
#if (USB_SYS0_CLKCFG_VAL == USB_PLL)
{
while ((SN_SYS0->CSST & 0x40) != 0x40);
SN_SYS0->CLKCFG = 0x4; //CLK switch PLL
while ((SN_SYS0->CLKCFG & 0x70) != 0x40);
}
#endif
SN_SYS0->AHBCP = USB_AHB_PRESCALAR;
#if (USB_CLKOUT_SEL_VAL > 0) //CLKOUT
SN_SYS1->AHBCLKEN |= (USB_CLKOUT_SEL_VAL<<28);
#endif
}

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/*----------------------------------------------------------------------------
* U S B - K e r n e l
*----------------------------------------------------------------------------
* Name: usbsystem.h
* Purpose: USB Custom User Definitions
* Version: V1.20
*----------------------------------------------------------------------------*/
#ifndef __USBSYSTEM_H__
#define __USBSYSTEM_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*--------------------- Clock Configuration ----------------------------------
//
//<e> System Clock Configuration
// <o1.0..2> SYSCLKSEL (SYS0_CLKCFG)
// <0=> ILRC
// <1=> IHRC
// <2=> EHS X'TAL
// <4=> PLL
//
// <o2> EHS Source Frequency (MHz)
// <10-25>
//
// <h> PLL Control Register (SYS0_PLLCTRL)
// <i> F_CLKOUT = F_VCO / P = (F_CLKIN / F * M) / P
// <i> 10 MHz <= F_CLKIN <= 25 MHz
// <i> 156 MHz <= (F_CLKIN / F * M) <= 320 MHz
// <o3> MSEL
// <24=> MSEL = 24
// <18=> MSEL = 18
// <12=> MSEL = 12
// <o4> PSEL
// <3=> P = 6
// <4=> P = 8
// <o5> FSEL
// <0=> F = 1
// <1=> F = 2
// <o6> PLL CLKIN Source selection
// <0=> IHRC
// <1=> EHS X'TAL
// <o7> PLL Enable selection
// <1=> Enable
// </h>
//
// <o8> AHB Clock Prescaler Register (SYS0_AHBCP)
// <0=> SYSCLK/1
// <1=> SYSCLK/2
// <2=> SYSCLK/4
// <3=> SYSCLK/8
// <4=> SYSCLK/16
// <5=> SYSCLK/32
// <6=> SYSCLK/64
// <7=> SYSCLK/128
// <8=> SYSCLK/256
// <9=> SYSCLK/512
//
// <o9> CLKOUT selection
// <0=> Disable
// <1=> ILRC
// <2=> ELS X'TAL
// <4=> HCLK
// <5=> IHRC
// <6=> EHS X'TAL
// <7=> PLL
//</e>
*/
#define USB_SYS_CLOCK_SETUP 1
#define USB_SYS0_CLKCFG_VAL USB_PLL
#define USB_EHS_FREQ 12
#define USB_PLL_MSEL 18
#define USB_PLL_PSEL 3
#define USB_PLL_FSEL 0
#define USB_PLL_CLKIN 0
#define USB_PLL_ENABLE 1
#define USB_AHB_PRESCALAR 0x0
#define USB_CLKOUT_SEL_VAL 0x0
/*
//-------- <<< end of configuration section >>> ------------------------------
*/
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
#define USB_IHRC 0
#define USB_ILRC 1
#define USB_EHSXTAL 2
#define USB_ELSXTAL 3
#define USB_PLL 4
#define USB_IHRC_EN 1
#define USB_SYS0_PLLCTRL_EN 0x8000
#define USB_PSEL_6 (0x03<<5)
#define USB_PSEL_8 (0x04<<5)
#define USB_MSEL_24 24
#define USB_MSEL_18 18
#define USB_MSEL_12 12
#define USB_PLL_CLKSOURCE_IHRC (USB_PSEL_6|USB_MSEL_24)
#define USB_PLL_CLKSOURCE_12MHz (USB_PSEL_6|USB_MSEL_24)
#define USB_PLL_CLKSOURCE_16MHz (USB_PSEL_6|USB_MSEL_18)
#define USB_PLL_CLKSOURCE_24MHz (USB_PSEL_6|USB_MSEL_12)
#define USB_PLL_DLEYA_TIME 100000
#define USB_PLL_10US_TIME 76
#if (USB_SYS0_CLKCFG_VAL == USB_PLL)
#define K_STATE_DELAY USB_PLL_DLEYA_TIME*(USB_AHB_PRESCALAR+1)
#define DISCHARE_DELAY K_STATE_DELAY
#define UTILITY_10US_DELAY USB_PLL_10US_TIME*(USB_AHB_PRESCALAR+1)
#endif //end USB_SYS0_CLKCFG_VAL == PLL
#if (USB_SYS0_CLKCFG_VAL == USB_IHRC)
#define K_STATE_DELAY (USB_PLL_DLEYA_TIME/4)*(USB_AHB_PRESCALAR+1)
#define DISCHARE_DELAY K_STATE_DELAY
#define UTILITY_10US_DELAY (USB_PLL_10US_TIME/4)*(USB_AHB_PRESCALAR+1)
#endif //end USB_SYS0_CLKCFG_VAL == USB_IHRC
#if (USB_SYS0_CLKCFG_VAL == USB_EHSXTAL)
#if (USB_EHS_FREQ == 12)
#define K_STATE_DELAY (USB_PLL_DLEYA_TIME/4)*(USB_AHB_PRESCALAR+1)
#define DISCHARE_DELAY K_STATE_DELAY
#define UTILITY_10US_DELAY (USB_PLL_10US_TIME/4)*(USB_AHB_PRESCALAR+1)
#elif (USB_EHS_FREQ == 16)
#define K_STATE_DELAY (USB_PLL_DLEYA_TIME/3)*(USB_AHB_PRESCALAR+1)
#define DISCHARE_DELAY K_STATE_DELAY
#define UTILITY_10US_DELAY (USB_PLL_10US_TIME/3)*(USB_AHB_PRESCALAR+1)
#elif (USB_EHS_FREQ == 24)
#define K_STATE_DELAY (USB_PLL_DLEYA_TIME/2)*(USB_AHB_PRESCALAR+1)
#define DISCHARE_DELAY K_STATE_DELAY
#define UTILITY_10US_DELAY (USB_PLL_10US_TIME/2)*(USB_AHB_PRESCALAR+1)
#endif //end USB_EHS_FREQ
#endif //end USB_SYS0_CLKCFG_VAL == USB_EHSTAL
extern void USB_SystemInit (void);
#endif /* __USBSYSTEM_H__ */

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/******************** (C) COPYRIGHT 2014 SONiX *******************************
* COMPANY: SONiX
* DATE: 2014/01
* AUTHOR: SA1
* IC: SN32F240/230/220
* DESCRIPTION: WDT related functions.
*____________________________________________________________________________
* REVISION Date User Description
* 1.0 2013/12/17 SA1 First release
* 1.1 2014/01/20 SA1 1. Modify WDT_ReloadValue function
*
*____________________________________________________________________________
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
* IN CONNECTION WITH THEIR PRODUCTS.
*****************************************************************************/
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240.h>
#include <SN32F200_Def.h>
#include "WDT.h"
#include "..\..\System\SYS_con_drive.h"
/*_____ D E C L A R A T I O N S ____________________________________________*/
/*_____ D E F I N I T I O N S ______________________________________________*/
/*_____ M A C R O S ________________________________________________________*/
/*_____ F U N C T I O N S __________________________________________________*/
/*****************************************************************************
* Function : WDT_IRQHandler
* Description : ISR of WDT interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
__irq void WDT_IRQHandler(void)
{
SN_GPIO2->DATA_b.DATA0 = ~SN_GPIO2->DATA_b.DATA0; //P2.0 toggle
__WDT_FEED_VALUE;
__WDT_CLRINSTS; //Clear WDT interrupt flag
}
/*****************************************************************************
* Function : WDT_Init
* Description : WDT initial
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void WDT_Init(void)
{
uint32_t wRegBuf;
WDT_SelectClockSource(WDT_CLKSEL_ILRC); //clock source select
#if WDT_MODE == INTERRUPT
wRegBuf = mskWDT_WDTIE_ENABLE; //WDT as interrupt mode
#endif
#if WDT_MODE == RESET
wRegBuf = mskWDT_WDTIE_DISABLE; //WDT as reset mode
#endif
wRegBuf = wRegBuf & (~mskWDT_WDTINT); //Clear WDT interrupt flag
wRegBuf = wRegBuf | mskWDT_WDKEY;
SN_WDT->CFG = wRegBuf;
WDT_ReloadValue(61); //Set overflow time = 250ms
WDT_NvicEnable(); //Enable WDT NVIC interrupt
__WDT_ENABLE; //Enable WDT
}
/*****************************************************************************
* Function : WDT_ReloadValue
* Description : set WDT reload value
* Input : time -
0~255: overflow time set
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void WDT_ReloadValue(uint32_t time)
{
uint32_t wRegBuf;
wRegBuf = time | mskWDT_WDKEY;
SN_WDT->TC = wRegBuf;
__WDT_FEED_VALUE;
}
/***********************************************************************************
* Function : WDT_SelectClockSource
* Description : Select WDT clcok source
* Input : WDT clock source -
WDT_CLKSEL_IHRC or WDT_CLKSEL_HCLK or WDT_CLKSEL_ILRC or WDT_CLKSEL_ELS
* Output : None
* Return : None
* Note : None
***********************************************************************************/
void WDT_SelectClockSource(uint32_t src)
{
if (src == WDT_CLKSEL_IHRC)
SYS0_EnableIHRC();
else if (src == WDT_CLKSEL_ELS)
SYS0_EnableELSXtal();
SN_WDT->CLKSOURCE = mskWDT_WDKEY | src; //clock source select
}
/*****************************************************************************
* Function : WDT_NvicEnable
* Description : Enable WDT interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void WDT_NvicEnable(void)
{
NVIC_ClearPendingIRQ(WDT_IRQn);
NVIC_EnableIRQ(WDT_IRQn);
NVIC_SetPriority(WDT_IRQn, 0); // Set interrupt priority (default)
}
/*****************************************************************************
* Function : WDT_NvicDisable
* Description : Disable WDT interrupt
* Input : None
* Output : None
* Return : None
* Note : None
*****************************************************************************/
void WDT_NvicDisable(void)
{
NVIC_DisableIRQ(WDT_IRQn);
}

55
os/hal/ports/SN32/LLD/SN32F24x/WDT/WDT.h Normal file
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#ifndef __SN32F240_WDT_H
#define __SN32F240_WDT_H
/*_____ I N C L U D E S ____________________________________________________*/
#include <SN32F240.h>
/*_____ D E F I N I T I O N S ______________________________________________*/
#define RESET 0 //WDT as Reset mode
#define INTERRUPT 1 //WDT as Interrupt mode
#define WDT_MODE INTERRUPT
//RESET_MODE : WDT as Reset mode
//Watchdog register key
#define mskWDT_WDKEY (0x5AFA<<16)
//Watchdog interrupt flag
#define mskWDT_WDTINT (1<<2)
//Watchdog interrupt enable
#define WDT_WDTIE_DISABLE 0
#define WDT_WDTIE_ENABLE 1
#define mskWDT_WDTIE_DISABLE (WDT_WDTIE_DISABLE<<1)
#define mskWDT_WDTIE_ENABLE (WDT_WDTIE_ENABLE<<1)
//Watchdog enable
#define mskWDT_WDTEN_DISABLE 0
#define mskWDT_WDTEN_ENABLE 1
//Watchdog Clock source
#define WDT_CLKSEL_IHRC 0
#define WDT_CLKSEL_HCLK 1
#define WDT_CLKSEL_ILRC 2
#define WDT_CLKSEL_ELS 3
//Watchdog Feed value
#define mskWDT_FV 0x55AA
/*_____ M A C R O S ________________________________________________________*/
//Watchdog Feed Value
#define __WDT_FEED_VALUE (SN_WDT->FEED = (mskWDT_WDKEY | mskWDT_FV))
//WDT Enable/Disable
#define __WDT_ENABLE (SN_WDT->CFG |= (mskWDT_WDKEY | mskWDT_WDTEN_ENABLE))
#define __WDT_DISABLE (SN_WDT->CFG = (mskWDT_WDKEY | (SN_WDT->CFG & ~mskWDT_WDTEN_ENABLE)))
//WDT INT status register clear
#define __WDT_CLRINSTS (SN_WDT->CFG = (mskWDT_WDKEY | (SN_WDT->CFG & ~mskWDT_WDTINT)))
/*_____ D E C L A R A T I O N S ____________________________________________*/
void WDT_Init(void);
void WDT_ReloadValue(uint32_t time);
void WDT_SelectClockSource(uint32_t src);
void WDT_NvicEnable(void);
void WDT_NvicDisable(void);
#endif /*__SN32F240_WDT_H*/

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