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10,227 Commits 18 Branches 2 Tags 110 MiB
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10227 Commits

Author SHA1 Message Date
Andrey Gusakov 69aef364b5 AT_START_F435: update 2023-11-03 11:18:11 +03:00
rusefillc 12889f8530 avoid shadowing with build-in function 2023-11-01 09:44:02 -04:00
Andrey G 53613ddde6
Merge pull request #38 from dron0gus/artery-dev-backport 
at32: fix DBGMCU struct, FLASHSIZE and UID addresses
 2023-10-30 13:24:33 +03:00
Andrey Gusakov 3234650abb at32: fix DBGMCU struct, FLASHSIZE and UID addresses 2023-10-30 12:28:52 +03:00
rusefillc c4096585ca
Merge pull request #37 from dron0gus/artery-dev-backport 
Artery dev backport
 2023-10-29 12:27:46 -04:00
Andrey Gusakov b1510d74cd STM32: SPIv1: integration with DMAv1 with MUX 2023-10-29 18:43:09 +03:00
Andrey Gusakov 95a93b98dc port: at32: fix isr 2023-10-29 18:43:09 +03:00
Andrey Gusakov 6b87450ccb port: AT32: fix IRQ handler offsets and numbers 2023-10-29 18:43:09 +03:00
Andrey Gusakov f1099e4ed2 AT32: do not suppress IRQs 2023-10-29 18:43:09 +03:00
Andrey Gusakov 64a7efb04a testhal: AT32: ADC: fixes for backport 2023-10-29 18:43:00 +03:00
Andrey Gusakov 7927c7881b AT32: USB_CDC_IAD: update mcuconf.h 2023-10-29 15:38:08 +03:00
Andrey Gusakov dbd86dc430 port: AT32: ADC fix 2023-10-29 15:38:08 +03:00
Andrey Gusakov 448b07c245 STM32: ADCv2: integration with DMAv1 with MUX 2023-10-29 15:38:08 +03:00
Andrey Gusakov 7f73c584f8 STM32: DMAv1: support for AT32 variant of DMA 2023-10-28 00:27:26 +03:00
Andrey Gusakov a2394a794e port: AT32: fix DMA support (DMAv1 from STM32 is reused) 2023-10-28 00:27:26 +03:00
Andrey Gusakov 155eb66585 AT32: USB_CDC: gdb scripts 2023-10-28 00:16:06 +03:00
Andrey Gusakov 9ac21ccdd9 Add flashing script 2023-07-06 22:15:27 -04:00
rusefillc b74e190446 ADC GHA 2023-07-06 22:15:27 -04:00
Vladimir Shamaev 882837271e Add ADC test 2023-07-06 22:15:27 -04:00
rusefillc 7da110d779 explicit message 2023-07-06 22:15:27 -04:00
rusefillc 9a1c8b6bd7 i am lazy 2023-07-06 22:15:27 -04:00
rusefillc 3ceb780f5c progress 2023-07-06 22:15:27 -04:00
rusefillc 2569430100 upload-artifact 2023-07-06 22:15:27 -04:00
Andrey d1e70072fc fancy! 2023-07-06 22:15:27 -04:00
Andrey 9a08015a4b port to 20 2023-07-06 22:15:27 -04:00
Andrey a33b2fc418 GHA CI for testhal 2023-07-06 22:15:27 -04:00
Andrey Gusakov d2d5bf9e8b AT-START-F435 board: update pinmuxes 2023-07-06 22:15:27 -04:00
Andrey Gusakov 738d752d77 Artery AT32F4xx port: updates: gpio, otg, ldo 2023-07-06 22:15:27 -04:00
Andrey Gusakov 79c636def1 USB demo update 2023-07-06 22:15:27 -04:00
Andrey Gusakov c272d0c241 AT-START-F435 board: fix OTG1 and OTG2 pinmuxes 2023-07-06 22:15:27 -04:00
Andrey Gusakov c39a274485 Artery AT32F4xx port: USB clock settings 2023-07-06 22:15:27 -04:00
Andrey Gusakov d24b9f19e7 AT32F4xx: USB demo 2023-07-06 22:15:27 -04:00
Andrey Gusakov 86cacdf737 port to 20 more 2023-07-06 22:15:27 -04:00
Andrey 2bbee81c28 port to 20 2023-07-06 22:15:27 -04:00
Andrey 06851f264c GHA CI for AT32 2023-07-06 22:15:26 -04:00
Andrey Gusakov f92d48f48e Artery AT32F4xx port: update, cleanup 2023-07-06 22:15:26 -04:00
Andrey Gusakov 11b7cf2bf1 AT-START-F435 demo: update, switch to 288Mhz 2023-07-06 22:15:26 -04:00
Andrey Gusakov 519c42bce3 Fix SD1/USART1 2023-07-06 22:15:26 -04:00
Andrey Gusakov ebe2fba0d6 AT-START-F435 demo: fix pinmuxes 2023-07-06 22:15:26 -04:00
Andrey Gusakov 2601494a03 Scripts: helpers for OpenOCD and GDB 2023-07-06 22:15:26 -04:00
Andrey Gusakov b15894f119 AT-START-F435 demo project 
Based on RT-STM32F429ZI-NUCLEO144
 2023-07-06 22:15:26 -04:00
Andrey Gusakov 4fcf789174 Artery AT32F4xx port: update clocks 2023-07-06 22:15:26 -04:00
Andrey Gusakov 066a657ad0 Artery AT32F4xx port: update 2023-07-06 22:15:26 -04:00
Andrey Gusakov deadc35124 Artery AT32F4xx port 2023-07-06 22:15:26 -04:00
Nathan Schulte 600ebfeec0 LSE max wait patches for rusEFI 2023-07-06 22:11:52 -04:00
Andrey Gusakov 4f0ee12e2e CANv1: fix for GD32 devices 
On GD32 CAN_TSTAT bits [25:24] has another meaning vs STM32:
"These bits are the number of the Tx FIFO mailbox in which the
frame will be transmitted if at least one mailbox is empty."
While on STM32:
"In case at least one transmit mailbox is free, the code value
is equal to the number of the next transmit mailbox free."
So to determine free mailbox we need to check TMEx bits on GD32.
 2023-07-06 22:11:52 -04:00
Matthew Kennedy 5a0633f0d2 why does it spinwait for subseconds? 2023-07-06 22:11:52 -04:00
Andrey 1d292943f0 https://github.com/rusefi/rusefi/issues/4115 2023-07-06 22:11:52 -04:00
Andrey eef3946f58 https://github.com/rusefi/rusefi/issues/4115 2023-07-06 22:11:52 -04:00
Matthew Kennedy 6c65213123 fix H7 CAN memory allocation 2023-07-06 22:11:52 -04:00