32bcb42776
Merge pull request #299 from hanya/picolinker
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RP2040: Add linker script for FLASH with boot2
2021-09-18 12:44:00 +02:00
6421c89c61
Merge pull request #297 from fauxpark/k60f-improvements
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K60x improvements
2021-09-18 12:34:16 +02:00
48218bd9ef
RP2040: Add linker script for FLASH with boot2
2021-09-14 18:26:05 +09:00
cc5a81bf99
Added WB32F3G71xx support
2021-09-12 18:02:41 -03:00
4b24d2e9c0
K60F improvements
2021-09-12 02:59:33 +10:00
8e86276eb8
Add startup code to the vectors section
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The startup code that initializes the mcu is moved to be the first entry
in the vectors section, so it will always be the first to run after a reset.
Because of a typo the vector table would have been there, but was relocated
into the text section. So this setup compiled by sheer luck into a working executable
that had the _start function at the flash base (0x8000000) up to this point.
2021-09-07 00:02:25 +02:00
3fc7254ad3
Merge pull request #280 from fauxpark/kinetis-ldscripts
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Add flash4-7 to MK64FX512 and MK66FX1M0 ldscripts
2021-06-30 10:06:06 +02:00
c9d507e687
Add flash4-7 to MK64FX512 and MK66FX1M0 ldscripts
2021-05-14 21:58:12 +10:00
b5d78c64c4
Add RV32E support
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* Make SP 16 byte aligned as the risc-v abi wants it.
* Correct IRQ context check.
2021-05-10 10:16:54 +02:00
5e096e01c9
Context switch only on irq tail
2021-05-09 11:16:09 +02:00
0a66a0660b
Fix t0 restore when exiting interrupt
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An oversight when arrangeing the code according to the nucleisys docs,
t0 was overriden with the value of msubm and never actually restored. To
fix the issue we restore the csrs after the general purpose registers.
The offical docs want it the other way around but this should be fine as
well, as the interrupts are still globaly disabled at this point.
2021-04-25 13:23:47 +02:00
9a64f5c17c
Force machine mode on interrupt exit for context switches
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The first attempt to solve illegal instruction expections was made in commit
b875108cd0
2021-04-17 19:36:44 +02:00
c1dfb65aa0
Revert "Add R/W memory and instruction barrier after mstatus access"
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This reverts commit b875108cd0
2021-04-16 21:52:41 +02:00
b875108cd0
Add R/W memory and instruction barrier after mstatus access
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Fast subsequent reads and writes to the mstatus csr lead to
illegal instruction exceptions on the nucleisys bumblee core
of the gd32vf103. This behavior only occurred in high load
situations e.g. interrupt frequency of 5khz but reliably let
to these errors. Adding the instruction and memory barriers solved
the problem. There is some negligible performance impact.
2021-04-16 16:10:08 +02:00
35a04fc72c
Add myself to copyright notes :-)
2021-04-06 13:38:23 +02:00
fcb66ed300
Add previously undefined constants
2021-04-06 13:38:23 +02:00
73336cf3b6
Increase idle stacksize, add isr locking/unlocking
2021-04-06 13:38:21 +02:00
5abb73e524
Migrate port and startup code to nmsis
2021-04-06 13:38:21 +02:00
bb7a299638
Add RISC-V ECLIC startup and port files
2021-04-06 13:38:21 +02:00
b729125bdd
Add Nucleisys NMSIS sources
2021-04-06 13:38:21 +02:00
9a861b0e8c
Merge branch 'chibios-20.3.x' into nuc123-kvs-example
2021-04-03 08:58:28 +09:00
22b4ec3b6b
MIMXRT1062: hal: port Arduino Teensy 4 Core startup code and linker script
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The one oddity of this platform is that it requires using XIP (eXecute In
Place), which for us largely means setting up a few special sections at special
flash locations.
References:
https://www.nxp.com/docs/en/application-note/AN12107.pdf
https://github.com/PaulStoffregen/cores/blob/master/teensy4/imxrt1062_t41.ld
https://www.pjrc.com/store/teensy40.html#memory_layout
2021-03-31 13:59:00 +02:00
a96c5d87d8
cmparams: set correct ARM version and number of vectors
2021-03-27 16:03:55 +01:00
f19da3e183
replace file names to use MIMXRT1062
2021-03-27 16:03:55 +01:00
b4b3579c86
branch startup (no changes yet)
2021-03-27 16:03:55 +01:00
09394a1b1a
NUC123: Added CONFIG0/1 settings, and updated linker script
2021-02-14 14:34:24 -05:00
7230eb96cc
[HAL/HT32]: Initial HT32 Support with a USB-DFU Demo
2020-12-31 02:27:13 -05:00
0b4b1d7542
NUC123SD4AN0 -> NUC123 conversion
2020-12-12 18:18:57 -05:00
adc44c4276
Use OEM CMSIS peripheral access headers
2020-12-05 17:05:14 -05:00
c5bd388844
Merge remote-tracking branch 'origin/lpc11uxx' into lpc11uxx-v20.x
2020-12-05 10:17:49 -05:00
674cf13603
SPI Driver + modified vector file
2020-12-05 10:14:03 -05:00
9f194d72dc
USB Works
2020-12-05 10:14:03 -05:00
4e5d4015b8
[LPC11Uxx]: Initial support for GPIO (PAL)
2020-12-05 10:14:03 -05:00
325bd43323
[LPC11Uxx]: Initial Support: RT + HAL ClockInit
2020-12-05 10:14:02 -05:00
dae27fbf5f
UART + Serial Driver
2020-12-03 22:31:21 -05:00
feb46948da
SPI Driver + modified vector file
2020-11-30 13:13:07 -05:00
f065a3bb2e
USB Works
2020-11-29 15:20:58 -05:00
2e9d04fb80
[LPC11Uxx]: Initial support for GPIO (PAL)
2020-11-26 23:31:17 -05:00
20369a3011
[LPC11Uxx]: Initial Support: RT + HAL ClockInit
2020-11-26 16:04:08 -05:00
469b5a35c2
Nuvoton NUC123SD4AN0 build fix
2020-11-08 20:38:01 +08:00
08e48cd50b
Update to integrate OSS re-engineer of NUMICRO MCU
2020-11-04 12:05:16 +08:00
beaf559be9
Nuvoton NUC123SD4AN0 MCU port, ready for Ducky One 2 Mini keyboard integration
2020-11-04 12:05:16 +08:00
571691aeab
fix a couple of forgotten SET calls
2020-06-03 22:02:29 +02:00
f43207c75f
MK66F18.h: fix typo: UARTTypeDef → UART_TypeDef
2020-06-02 21:07:38 +02:00
f6f1185a10
Various fixes to make it pass tests
2020-04-08 19:55:22 +02:00
f53e426780
Update NRF52832 device headers to latest version from NRF5 SDK.
2020-01-05 12:11:10 +07:00
1ca49e0b90
Fault handlers: v7m: simplify
2019-10-02 15:18:08 -03:00
41f2f8462a
Add fault handlers to ease ARM-v7m (Cortex M3/M4(F)/M7 debugging
2019-10-02 15:14:28 -03:00
f1dce4dc14
Kinetis makefiles fixes
2019-10-02 10:47:02 +02:00
d921781a45
KINETIS platform update for ChibiOS 18.2.x.
2018-11-20 09:53:30 +07:00
Fabien Poussin
Hanya
Joy
fauxpark
Stefan Kerkmann
a_p_u_r_o
Michael Stapelberg
Alex Lewontin
codetector
Reza Jelveh
GitWellBack
Konstantin Oblaukhov
Diego Ismirlian