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/**
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* @ file stm32f105xc . h
* @ author MCD Application Team
* @ version V4 .2 .0
* @ date 31 - March - 2017
* @ brief CMSIS Cortex - M3 Device Peripheral Access Layer Header File .
* This file contains all the peripheral register ' s definitions , bits
* definitions and memory mapping for STM32F1xx devices .
*
* This file contains :
* - Data structures and the address mapping for all peripherals
* - Peripheral ' s registers declarations and bits definition
* - Macros to access peripheral <EFBFBD> s registers hardware
*
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* @ attention
*
* < h2 > < center > & copy ; COPYRIGHT ( c ) 2017 STMicroelectronics < / center > < / h2 >
*
* Redistribution and use in source and binary forms , with or without modification ,
* are permitted provided that the following conditions are met :
* 1. Redistributions of source code must retain the above copyright notice ,
* this list of conditions and the following disclaimer .
* 2. Redistributions in binary form must reproduce the above copyright notice ,
* this list of conditions and the following disclaimer in the documentation
* and / or other materials provided with the distribution .
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission .
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS " AS IS "
* AND ANY EXPRESS OR IMPLIED WARRANTIES , INCLUDING , BUT NOT LIMITED TO , THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED . IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT , INDIRECT , INCIDENTAL , SPECIAL , EXEMPLARY , OR CONSEQUENTIAL
* DAMAGES ( INCLUDING , BUT NOT LIMITED TO , PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES ; LOSS OF USE , DATA , OR PROFITS ; OR BUSINESS INTERRUPTION ) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY , WHETHER IN CONTRACT , STRICT LIABILITY ,
* OR TORT ( INCLUDING NEGLIGENCE OR OTHERWISE ) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE , EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE .
*
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
*/
/** @addtogroup CMSIS
* @ {
*/
/** @addtogroup stm32f105xc
* @ {
*/
# ifndef __STM32F105xC_H
# define __STM32F105xC_H
# ifdef __cplusplus
extern " C " {
# endif
/** @addtogroup Configuration_section_for_CMSIS
* @ {
*/
/**
* @ brief Configuration of the Cortex - M3 Processor and Core Peripherals
*/
/**
* @ }
*/
/** @addtogroup Peripheral_interrupt_number_definition
* @ {
*/
/**
* @ brief STM32F10x Interrupt Number Definition , according to the selected device
* in @ ref Library_configuration_section
*/
# include <stdint.h>
/** @addtogroup Peripheral_registers_structures
* @ {
*/
/**
* @ brief Analog to Digital Converter
*/
typedef struct
{
__IO uint32_t SR ;
__IO uint32_t CR1 ;
__IO uint32_t CR2 ;
__IO uint32_t SMPR1 ;
__IO uint32_t SMPR2 ;
__IO uint32_t JOFR1 ;
__IO uint32_t JOFR2 ;
__IO uint32_t JOFR3 ;
__IO uint32_t JOFR4 ;
__IO uint32_t HTR ;
__IO uint32_t LTR ;
__IO uint32_t SQR1 ;
__IO uint32_t SQR2 ;
__IO uint32_t SQR3 ;
__IO uint32_t JSQR ;
__IO uint32_t JDR1 ;
__IO uint32_t JDR2 ;
__IO uint32_t JDR3 ;
__IO uint32_t JDR4 ;
__IO uint32_t DR ;
} ADC_TypeDef ;
typedef struct
{
__IO uint32_t SR ; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */
__IO uint32_t CR1 ; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */
__IO uint32_t CR2 ; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */
uint32_t RESERVED [ 16 ] ;
__IO uint32_t DR ; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */
} ADC_Common_TypeDef ;
/**
* @ brief Backup Registers
*/
typedef struct
{
uint32_t RESERVED0 ;
__IO uint32_t DR1 ;
__IO uint32_t DR2 ;
__IO uint32_t DR3 ;
__IO uint32_t DR4 ;
__IO uint32_t DR5 ;
__IO uint32_t DR6 ;
__IO uint32_t DR7 ;
__IO uint32_t DR8 ;
__IO uint32_t DR9 ;
__IO uint32_t DR10 ;
__IO uint32_t RTCCR ;
__IO uint32_t CR ;
__IO uint32_t CSR ;
uint32_t RESERVED13 [ 2 ] ;
__IO uint32_t DR11 ;
__IO uint32_t DR12 ;
__IO uint32_t DR13 ;
__IO uint32_t DR14 ;
__IO uint32_t DR15 ;
__IO uint32_t DR16 ;
__IO uint32_t DR17 ;
__IO uint32_t DR18 ;
__IO uint32_t DR19 ;
__IO uint32_t DR20 ;
__IO uint32_t DR21 ;
__IO uint32_t DR22 ;
__IO uint32_t DR23 ;
__IO uint32_t DR24 ;
__IO uint32_t DR25 ;
__IO uint32_t DR26 ;
__IO uint32_t DR27 ;
__IO uint32_t DR28 ;
__IO uint32_t DR29 ;
__IO uint32_t DR30 ;
__IO uint32_t DR31 ;
__IO uint32_t DR32 ;
__IO uint32_t DR33 ;
__IO uint32_t DR34 ;
__IO uint32_t DR35 ;
__IO uint32_t DR36 ;
__IO uint32_t DR37 ;
__IO uint32_t DR38 ;
__IO uint32_t DR39 ;
__IO uint32_t DR40 ;
__IO uint32_t DR41 ;
__IO uint32_t DR42 ;
} BKP_TypeDef ;
/**
* @ brief Controller Area Network TxMailBox
*/
typedef struct
{
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__IO uint32_t TMI ;
__IO uint32_t TMP ;
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__IO uint32_t TMDATA0 ;
__IO uint32_t TMDATA1 ;
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} CAN_TxMailBox_TypeDef ;
/**
* @ brief Controller Area Network FIFOMailBox
*/
typedef struct
{
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__IO uint32_t RFIFOMI ;
__IO uint32_t RFIFOMP ;
__IO uint32_t RFIFOMDATA0 ;
__IO uint32_t RFIFOMDATA1 ;
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} CAN_FIFOMailBox_TypeDef ;
/**
* @ brief Controller Area Network FilterRegister
*/
typedef struct
{
__IO uint32_t FR1 ;
__IO uint32_t FR2 ;
} CAN_FilterRegister_TypeDef ;
/**
* @ brief Controller Area Network
*/
typedef struct
{
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__IO uint32_t CTL ;
__IO uint32_t STAT ;
__IO uint32_t TSTAT ;
__IO uint32_t RFIFO0 ;
__IO uint32_t RFIFO1 ;
__IO uint32_t INTEN ;
__IO uint32_t ERR ;
__IO uint32_t BT ;
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uint32_t RESERVED0 [ 88 ] ;
CAN_TxMailBox_TypeDef sTxMailBox [ 3 ] ;
CAN_FIFOMailBox_TypeDef sFIFOMailBox [ 2 ] ;
uint32_t RESERVED1 [ 12 ] ;
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__IO uint32_t FCTL ;
__IO uint32_t FMCFG ;
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uint32_t RESERVED2 ;
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__IO uint32_t FSCFG ;
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uint32_t RESERVED3 ;
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__IO uint32_t FAFIFO ;
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uint32_t RESERVED4 ;
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__IO uint32_t FW ;
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uint32_t RESERVED5 [ 8 ] ;
CAN_FilterRegister_TypeDef sFilterRegister [ 28 ] ;
} CAN_TypeDef ;
/**
* @ brief CRC calculation unit
*/
typedef struct
{
__IO uint32_t DR ; /*!< CRC Data register, Address offset: 0x00 */
__IO uint8_t IDR ; /*!< CRC Independent data register, Address offset: 0x04 */
uint8_t RESERVED0 ; /*!< Reserved, Address offset: 0x05 */
uint16_t RESERVED1 ; /*!< Reserved, Address offset: 0x06 */
__IO uint32_t CR ; /*!< CRC Control register, Address offset: 0x08 */
} CRC_TypeDef ;
/**
* @ brief Digital to Analog Converter
*/
typedef struct
{
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__IO uint32_t CTL ;
__IO uint32_t SWT ;
__IO uint32_t R12DH0 ;
__IO uint32_t L12DH0 ;
__IO uint32_t R8DH0 ;
__IO uint32_t R12DH1 ;
__IO uint32_t L12DH1 ;
__IO uint32_t R8DH1 ;
__IO uint32_t R12DH ;
__IO uint32_t L12DH ;
__IO uint32_t R8DH ;
__IO uint32_t DO0 ;
__IO uint32_t DO1 ;
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} DAC_TypeDef ;
/**
* @ brief Debug MCU
*/
typedef struct
{
__IO uint32_t IDCODE ;
__IO uint32_t CR ;
} DBGMCU_TypeDef ;
/**
* @ brief DMA Controller
*/
typedef struct
{
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__IO uint32_t CTL ;
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__IO uint32_t CNT ;
__IO uint32_t PADDR ;
__IO uint32_t MADDR ;
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} DMA_Channel_TypeDef ;
typedef struct
{
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__IO uint32_t INTF ;
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__IO uint32_t INTC ;
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} DMA_TypeDef ;
/**
* @ brief External Interrupt / Event Controller
*/
typedef struct
{
__IO uint32_t IMR ;
__IO uint32_t EMR ;
__IO uint32_t RTSR ;
__IO uint32_t FTSR ;
__IO uint32_t SWIER ;
__IO uint32_t PR ;
} EXTI_TypeDef ;
/**
* @ brief FLASH Registers
*/
typedef struct
{
__IO uint32_t ACR ;
__IO uint32_t KEYR ;
__IO uint32_t OPTKEYR ;
__IO uint32_t SR ;
__IO uint32_t CR ;
__IO uint32_t AR ;
__IO uint32_t RESERVED ;
__IO uint32_t OBR ;
__IO uint32_t WRPR ;
} FLASH_TypeDef ;
/**
* @ brief Option Bytes Registers
*/
typedef struct
{
__IO uint16_t RDP ;
__IO uint16_t USER ;
__IO uint16_t Data0 ;
__IO uint16_t Data1 ;
__IO uint16_t WRP0 ;
__IO uint16_t WRP1 ;
__IO uint16_t WRP2 ;
__IO uint16_t WRP3 ;
} OB_TypeDef ;
/**
* @ brief General Purpose I / O
*/
typedef struct
{
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__IO uint32_t CTL0 ;
__IO uint32_t CTL1 ;
__IO uint32_t ISTAT ;
__IO uint32_t OCTL ;
__IO uint32_t BOP ;
__IO uint32_t BC ;
__IO uint32_t LOCK ;
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} GPIO_TypeDef ;
/**
* @ brief Alternate Function I / O
*/
typedef struct
{
__IO uint32_t EVCR ;
__IO uint32_t MAPR ;
__IO uint32_t EXTICR [ 4 ] ;
uint32_t RESERVED0 ;
__IO uint32_t MAPR2 ;
} AFIO_TypeDef ;
/**
* @ brief Inter Integrated Circuit Interface
*/
typedef struct
{
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__IO uint32_t CTL0 ;
__IO uint32_t CTL1 ;
__IO uint32_t SADDR0 ;
__IO uint32_t SADDR1 ;
__IO uint32_t DATA ;
__IO uint32_t STAT0 ;
__IO uint32_t STAT1 ;
__IO uint32_t CKCFG ;
__IO uint32_t RT ;
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uint32_t RESERVED [ 27 ] ;
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__IO uint32_t FMPCFG ;
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} I2C_TypeDef ;
/**
* @ brief Independent WATCHDOG
*/
typedef struct
{
__IO uint32_t KR ; /*!< Key register, Address offset: 0x00 */
__IO uint32_t PR ; /*!< Prescaler register, Address offset: 0x04 */
__IO uint32_t RLR ; /*!< Reload register, Address offset: 0x08 */
__IO uint32_t SR ; /*!< Status register, Address offset: 0x0C */
} IWDG_TypeDef ;
/**
* @ brief Power Control
*/
typedef struct
{
__IO uint32_t CR ;
__IO uint32_t CSR ;
} PWR_TypeDef ;
/**
* @ brief Reset and Clock Control
*/
typedef struct
{
__IO uint32_t CR ;
__IO uint32_t CFGR ;
__IO uint32_t CIR ;
__IO uint32_t APB2RSTR ;
__IO uint32_t APB1RSTR ;
__IO uint32_t AHBENR ;
__IO uint32_t APB2ENR ;
__IO uint32_t APB1ENR ;
__IO uint32_t BDCR ;
__IO uint32_t CSR ;
__IO uint32_t AHBRSTR ;
__IO uint32_t CFGR2 ;
} RCC_TypeDef ;
/**
* @ brief Real - Time Clock
*/
typedef struct
{
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__IO uint32_t INTEN ;
__IO uint32_t CTL ;
__IO uint32_t PSCH ;
__IO uint32_t PSCL ;
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__IO uint32_t DIVH ;
__IO uint32_t DIVL ;
__IO uint32_t CNTH ;
__IO uint32_t CNTL ;
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__IO uint32_t ALRMH ;
__IO uint32_t ALRML ;
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} RTC_TypeDef ;
/**
* @ brief Serial Peripheral Interface
*/
typedef struct
{
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__IO uint32_t CTL0 ;
__IO uint32_t CTL1 ;
__IO uint32_t STAT ;
__IO uint32_t DATA ;
__IO uint32_t CRCPOLY ;
__IO uint32_t RCRC ;
__IO uint32_t TCRC ;
__IO uint32_t I2SCTL ;
__IO uint32_t I2SPSC ;
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} SPI_TypeDef ;
/**
* @ brief TIM Timers
*/
typedef struct
{
__IO uint32_t CR1 ; /*!< TIM control register 1, Address offset: 0x00 */
__IO uint32_t CR2 ; /*!< TIM control register 2, Address offset: 0x04 */
__IO uint32_t SMCR ; /*!< TIM slave Mode Control register, Address offset: 0x08 */
__IO uint32_t DIER ; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
__IO uint32_t SR ; /*!< TIM status register, Address offset: 0x10 */
__IO uint32_t EGR ; /*!< TIM event generation register, Address offset: 0x14 */
__IO uint32_t CCMR1 ; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
__IO uint32_t CCMR2 ; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
__IO uint32_t CCER ; /*!< TIM capture/compare enable register, Address offset: 0x20 */
__IO uint32_t CNT ; /*!< TIM counter register, Address offset: 0x24 */
__IO uint32_t PSC ; /*!< TIM prescaler register, Address offset: 0x28 */
__IO uint32_t ARR ; /*!< TIM auto-reload register, Address offset: 0x2C */
__IO uint32_t RCR ; /*!< TIM repetition counter register, Address offset: 0x30 */
__IO uint32_t CCR1 ; /*!< TIM capture/compare register 1, Address offset: 0x34 */
__IO uint32_t CCR2 ; /*!< TIM capture/compare register 2, Address offset: 0x38 */
__IO uint32_t CCR3 ; /*!< TIM capture/compare register 3, Address offset: 0x3C */
__IO uint32_t CCR4 ; /*!< TIM capture/compare register 4, Address offset: 0x40 */
__IO uint32_t BDTR ; /*!< TIM break and dead-time register, Address offset: 0x44 */
__IO uint32_t DCR ; /*!< TIM DMA control register, Address offset: 0x48 */
__IO uint32_t DMAR ; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
__IO uint32_t OR ; /*!< TIM option register, Address offset: 0x50 */
} TIM_TypeDef ;
/**
* @ brief Universal Synchronous Asynchronous Receiver Transmitter
*/
typedef struct
{
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__IO uint32_t STAT ; /*!< USART Status register, Address offset: 0x00 */
__IO uint32_t DATA ; /*!< USART Data register, Address offset: 0x04 */
__IO uint32_t BAUD ; /*!< USART Baud rate register, Address offset: 0x08 */
__IO uint32_t CTL0 ; /*!< USART Control register 1, Address offset: 0x0C */
__IO uint32_t CTL1 ; /*!< USART Control register 2, Address offset: 0x10 */
__IO uint32_t CTL2 ; /*!< USART Control register 3, Address offset: 0x14 */
__IO uint32_t GP ; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
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} USART_TypeDef ;
/**
* @ brief __USB_OTG_Core_register
*/
typedef struct
{
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__IO uint32_t GOTGCS ; /*!< USB_OTG Control and Status Register Address offset: 000h */
__IO uint32_t GOTGINTF ; /*!< USB_OTG Interrupt Register Address offset: 004h */
__IO uint32_t GAHBCS ; /*!< Core AHB Configuration Register Address offset: 008h */
__IO uint32_t GUSBCS ; /*!< Core USB Configuration Register Address offset: 00Ch */
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__IO uint32_t GRSTCTL ; /*!< Core Reset Register Address offset: 010h */
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__IO uint32_t GINTF ; /*!< Core Interrupt Register Address offset: 014h */
__IO uint32_t GINTEN ; /*!< Core Interrupt Mask Register Address offset: 018h */
__IO uint32_t GRSTATR ; /*!< Receive Sts Q Read Register Address offset: 01Ch */
__IO uint32_t GRSTATP ; /*!< Receive Sts Q Read & POP Register Address offset: 020h */
__IO uint32_t GRFLEN ; /*!< Receive FIFO Size Register Address offset: 024h */
__IO uint32_t HNPTFLEN_DIEP0TFLEN ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset: 028h */
__IO uint32_t HNPTFQSTAT ; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset: 02Ch */
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uint32_t Reserved30 [ 2 ] ; /*!< Reserved 030h*/
__IO uint32_t GCCFG ; /*!< General Purpose IO Register Address offset: 038h */
__IO uint32_t CID ; /*!< User ID Register Address offset: 03Ch */
uint32_t Reserved40 [ 48 ] ; /*!< Reserved 040h-0FFh */
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__IO uint32_t HPTFLEN ; /*!< Host Periodic Tx FIFO Size Reg Address offset: 100h */
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__IO uint32_t DIEPTFLEN [ 0x0F ] ; /*!< dev Periodic Transmit FIFO Address offset: 0x104 */
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} USB_OTG_GlobalTypeDef ;
/**
* @ brief __device_Registers
*/
typedef struct
{
__IO uint32_t DCFG ; /*!< dev Configuration Register Address offset: 800h*/
__IO uint32_t DCTL ; /*!< dev Control Register Address offset: 804h*/
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__IO uint32_t DSTAT ; /*!< dev Status Register (RO) Address offset: 808h*/
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uint32_t Reserved0C ; /*!< Reserved 80Ch*/
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__IO uint32_t DIEPINTF ; /*!< dev IN Endpoint Mask Address offset: 810h*/
__IO uint32_t DOEPINTF ; /*!< dev OUT Endpoint Mask Address offset: 814h*/
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__IO uint32_t DAEPINT ; /*!< dev All Endpoints Itr Reg Address offset: 818h*/
__IO uint32_t DAEPINTEN ; /*!< dev All Endpoints Itr Mask Address offset: 81Ch*/
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uint32_t Reserved20 ; /*!< Reserved 820h*/
uint32_t Reserved9 ; /*!< Reserved 824h*/
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__IO uint32_t DVBUSDT ; /*!< dev VBUS discharge Register Address offset: 828h*/
__IO uint32_t DVBUSPT ; /*!< dev VBUS Pulse Register Address offset: 82Ch*/
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__IO uint32_t DTHRCTL ; /*!< dev thr Address offset: 830h*/
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__IO uint32_t DIEPFEINTEN ; /*!< dev empty msk Address offset: 834h*/
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__IO uint32_t DEACHINT ; /*!< dedicated EP interrupt Address offset: 838h*/
__IO uint32_t DEACHMSK ; /*!< dedicated EP msk Address offset: 83Ch*/
uint32_t Reserved40 ; /*!< dedicated EP mask Address offset: 840h*/
__IO uint32_t DINEP1MSK ; /*!< dedicated EP mask Address offset: 844h*/
uint32_t Reserved44 [ 15 ] ; /*!< Reserved 844-87Ch*/
__IO uint32_t DOUTEP1MSK ; /*!< dedicated EP msk Address offset: 884h*/
} USB_OTG_DeviceTypeDef ;
/**
* @ brief __IN_Endpoint - Specific_Register
*/
typedef struct
{
__IO uint32_t DIEPCTL ; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
uint32_t Reserved04 ; /*!< Reserved 900h + (ep_num * 20h) + 04h*/
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__IO uint32_t DIEPINTF ; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
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uint32_t Reserved0C ; /*!< Reserved 900h + (ep_num * 20h) + 0Ch*/
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__IO uint32_t DIEPLEN ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
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__IO uint32_t DIEPDMA ; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
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__IO uint32_t DIEPTFSTAT ; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
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uint32_t Reserved18 ; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
} USB_OTG_INEndpointTypeDef ;
/**
* @ brief __OUT_Endpoint - Specific_Registers
*/
typedef struct
{
__IO uint32_t DOEPCTL ; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
uint32_t Reserved04 ; /*!< Reserved B00h + (ep_num * 20h) + 04h*/
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__IO uint32_t DOEPINTF ; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
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uint32_t Reserved0C ; /*!< Reserved B00h + (ep_num * 20h) + 0Ch*/
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__IO uint32_t DOEPLEN ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
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__IO uint32_t DOEPDMA ; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
uint32_t Reserved18 [ 2 ] ; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
} USB_OTG_OUTEndpointTypeDef ;
/**
* @ brief __Host_Mode_Register_Structures
*/
typedef struct
{
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__IO uint32_t HCTL ; /*!< Host Configuration Register 400h*/
__IO uint32_t HFT ; /*!< Host Frame Interval Register 404h*/
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__IO uint32_t HFINFR ; /*!< Host Frame Nbr/Frame Remaining 408h*/
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uint32_t Reserved40C ; /*!< Reserved 40Ch*/
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__IO uint32_t HPTFQSTAT ; /*!< Host Periodic Tx FIFO/ Queue Status 410h*/
__IO uint32_t HACHINT ; /*!< Host All Channels Interrupt Register 414h*/
__IO uint32_t HACHINTEN ; /*!< Host All Channels Interrupt Mask 418h*/
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} USB_OTG_HostTypeDef ;
/**
* @ brief __Host_Channel_Specific_Registers
*/
typedef struct
{
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__IO uint32_t HCHCTL ;
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__IO uint32_t HCSPLT ;
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__IO uint32_t HCHINTF ;
__IO uint32_t HCHINTEN ;
__IO uint32_t HCHLEN ;
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__IO uint32_t HCDMA ;
uint32_t Reserved [ 2 ] ;
} USB_OTG_HostChannelTypeDef ;
/**
* @ brief Window WATCHDOG
*/
typedef struct
{
__IO uint32_t CR ; /*!< WWDG Control register, Address offset: 0x00 */
__IO uint32_t CFR ; /*!< WWDG Configuration register, Address offset: 0x04 */
__IO uint32_t SR ; /*!< WWDG Status register, Address offset: 0x08 */
} WWDG_TypeDef ;
/**
* @ }
*/
/** @addtogroup Peripheral_memory_map
* @ {
*/
//#define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */
# define FLASH_BANK1_END 0x0803FFFFU /*!< FLASH END address of bank1 */
//#define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */
# define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
# define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */
# define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
/*!< Peripheral memory map */
# define APB1PERIPH_BASE PERIPH_BASE
# define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
# define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
# define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U)
# define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U)
# define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U)
# define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00U)
# define TIM6_BASE (APB1PERIPH_BASE + 0x00001000U)
# define TIM7_BASE (APB1PERIPH_BASE + 0x00001400U)
//#define RTC_BASE (APB1PERIPH_BASE + 0x00002800U)
# define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U)
# define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)
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# define SPI1_BASE (APB1PERIPH_BASE + 0x00003800U)
# define SPI2_BASE (APB1PERIPH_BASE + 0x00003C00U)
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# define USART1_BASE (APB1PERIPH_BASE + 0x00004400U)
# define USART2_BASE (APB1PERIPH_BASE + 0x00004800U)
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# define UART3_BASE (APB1PERIPH_BASE + 0x00004C00U)
# define UART4_BASE (APB1PERIPH_BASE + 0x00005000U)
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# define I2C0_BASE (APB1PERIPH_BASE + 0x00005400U)
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# define I2C1_BASE (APB1PERIPH_BASE + 0x5800)
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# define CAN1_BASE (APB1PERIPH_BASE + 0x00006400U)
# define CAN2_BASE (APB1PERIPH_BASE + 0x00006800U)
//#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00U)
# define PWR_BASE (APB1PERIPH_BASE + 0x00007000U)
//#define DAC_BASE (APB1PERIPH_BASE + 0x00007400U)
//#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000U)
//#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U)
# define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U)
# define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00U)
# define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000U)
# define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400U)
# define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800U)
# define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U)
# define ADC2_BASE (APB2PERIPH_BASE + 0x00002800U)
# define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00U)
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# define SPI0_BASE (APB2PERIPH_BASE + 0x00003000U)
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# define USART0_BASE (APB2PERIPH_BASE + 0x00003800U)
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# define SDIO_BASE (PERIPH_BASE + 0x00018000U)
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# define DMA0_BASE (AHBPERIPH_BASE + 0x00000000U)
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# define DMA0_Channel0_BASE (AHBPERIPH_BASE + 0x00000008U)
# define DMA0_Channel1_BASE (AHBPERIPH_BASE + 0x0000001CU)
# define DMA0_Channel2_BASE (AHBPERIPH_BASE + 0x00000030U)
# define DMA0_Channel3_BASE (AHBPERIPH_BASE + 0x00000044U)
# define DMA0_Channel4_BASE (AHBPERIPH_BASE + 0x00000058U)
# define DMA0_Channel5_BASE (AHBPERIPH_BASE + 0x0000006CU)
# define DMA0_Channel6_BASE (AHBPERIPH_BASE + 0x00000080U)
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# define DMA1_BASE (AHBPERIPH_BASE + 0x00000400U)
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# define DMA1_Channel0_BASE (AHBPERIPH_BASE + 0x00000408U)
# define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0000041CU)
# define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x00000430U)
# define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000444U)
# define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000458U)
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# define RCC_BASE (AHBPERIPH_BASE + 0x00001000U)
//#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
# define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */
# define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */
# define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */
//#define OB_BASE 0x1FFFF800U /*!< Flash Option Bytes base address */
# define DBGMCU_BASE 0xE0042000U /*!< Debug MCU registers base address */
/*!< USB registers base address */
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# define USB_USBFS_PERIPH_BASE 0x50000000U
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# define USB_OTG_GLOBAL_BASE 0x00000000U
# define USB_OTG_DEVICE_BASE 0x00000800U
# define USB_OTG_IN_ENDPOINT_BASE 0x00000900U
# define USB_OTG_OUT_ENDPOINT_BASE 0x00000B00U
# define USB_OTG_EP_REG_SIZE 0x00000020U
# define USB_OTG_HOST_BASE 0x00000400U
# define USB_OTG_HOST_PORT_BASE 0x00000440U
# define USB_OTG_HOST_CHANNEL_BASE 0x00000500U
# define USB_OTG_HOST_CHANNEL_SIZE 0x00000020U
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# define USB_OTG_PWRCLKCTL_BASE 0x00000E00U
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# define USB_OTG_FIFO_BASE 0x00001000U
# define USB_OTG_FIFO_SIZE 0x00001000U
/**
* @ }
*/
/** @addtogroup Peripheral_declaration
* @ {
*/
# define TIM2 ((TIM_TypeDef *)TIM2_BASE)
# define TIM3 ((TIM_TypeDef *)TIM3_BASE)
# define TIM4 ((TIM_TypeDef *)TIM4_BASE)
# define TIM5 ((TIM_TypeDef *)TIM5_BASE)
# define TIM6 ((TIM_TypeDef *)TIM6_BASE)
# define TIM7 ((TIM_TypeDef *)TIM7_BASE)
# define RTC ((RTC_TypeDef *)RTC_BASE)
# define WWDG ((WWDG_TypeDef *)WWDG_BASE)
# define IWDG ((IWDG_TypeDef *)IWDG_BASE)
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# define SPI1 ((SPI_TypeDef *)SPI1_BASE)
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# define SPI2 ((SPI_TypeDef *)SPI2_BASE)
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# define USART1 ((USART_TypeDef *)USART1_BASE)
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# define USART2 ((USART_TypeDef *)USART2_BASE)
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# define UART3 ((USART_TypeDef *)UART3_BASE)
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# define UART4 ((USART_TypeDef *)UART4_BASE)
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# define I2C0 ((I2C_TypeDef *)I2C0_BASE)
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# define I2C1 ((I2C_TypeDef *)I2C1_BASE)
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# define CAN1 ((CAN_TypeDef *)CAN1_BASE)
# define CAN2 ((CAN_TypeDef *)CAN2_BASE)
# define BKP ((BKP_TypeDef *)BKP_BASE)
# define PWR ((PWR_TypeDef *)PWR_BASE)
# define DAC1 ((DAC_TypeDef *)DAC_BASE)
# define DAC ((DAC_TypeDef *)DAC_BASE) /* Kept for legacy purpose */
# define AFIO ((AFIO_TypeDef *)AFIO_BASE)
# define EXTI ((EXTI_TypeDef *)EXTI_BASE)
# define GPIOA ((GPIO_TypeDef *)GPIOA_BASE)
# define GPIOB ((GPIO_TypeDef *)GPIOB_BASE)
# define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)
# define GPIOD ((GPIO_TypeDef *)GPIOD_BASE)
# define GPIOE ((GPIO_TypeDef *)GPIOE_BASE)
# define ADC1 ((ADC_TypeDef *)ADC1_BASE)
# define ADC2 ((ADC_TypeDef *)ADC2_BASE)
# define ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE)
# define TIM1 ((TIM_TypeDef *)TIM1_BASE)
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# define SPI0 ((SPI_TypeDef *)SPI0_BASE)
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# define USART0 ((USART_TypeDef *)USART0_BASE)
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# define SDIO ((SDIO_TypeDef *)SDIO_BASE)
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# define DMA0 ((DMA_TypeDef *)DMA0_BASE)
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# define DMA1 ((DMA_TypeDef *)DMA1_BASE)
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# define DMA0_Channel0 ((DMA_Channel_TypeDef *)DMA0_Channel0_BASE)
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# define DMA0_Channel1 ((DMA_Channel_TypeDef *)DMA0_Channel1_BASE)
# define DMA0_Channel2 ((DMA_Channel_TypeDef *)DMA0_Channel2_BASE)
# define DMA0_Channel3 ((DMA_Channel_TypeDef *)DMA0_Channel3_BASE)
# define DMA0_Channel4 ((DMA_Channel_TypeDef *)DMA0_Channel4_BASE)
# define DMA0_Channel5 ((DMA_Channel_TypeDef *)DMA0_Channel5_BASE)
# define DMA0_Channel6 ((DMA_Channel_TypeDef *)DMA0_Channel6_BASE)
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# define DMA1_Channel0 ((DMA_Channel_TypeDef *)DMA1_Channel0_BASE)
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# define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
# define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
# define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
# define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
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# define RCC ((RCC_TypeDef *)RCC_BASE)
# define CRC ((CRC_TypeDef *)CRC_BASE)
# define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)
# define OB ((OB_TypeDef *)OB_BASE)
# define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)
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# define USB_USBFS ((USB_OTG_GlobalTypeDef *)USB_USBFS_PERIPH_BASE)
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/**
* @ }
*/
/** @addtogroup Exported_constants
* @ {
*/
/** @addtogroup Peripheral_Registers_Bits_Definition
* @ {
*/
/******************************************************************************/
/* Peripheral Registers_Bits_Definition */
/******************************************************************************/
/******************************************************************************/
/* */
/* CRC calculation unit (CRC) */
/* */
/******************************************************************************/
/******************* Bit definition for CRC_DR register *********************/
# define CRC_DR_DR_Pos (0U)
# define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
# define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
/******************* Bit definition for CRC_IDR register ********************/
# define CRC_IDR_IDR_Pos (0U)
# define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
# define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
# define CRC_CR_RESET_Pos (0U)
# define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
# define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
/******************************************************************************/
/* */
/* Power Control */
/* */
/******************************************************************************/
/******************** Bit definition for PWR_CR register ********************/
# define PWR_CR_LPDS_Pos (0U)
# define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
# define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
# define PWR_CR_PDDS_Pos (1U)
# define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
# define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
# define PWR_CR_CWUF_Pos (2U)
# define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
# define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
# define PWR_CR_CSBF_Pos (3U)
# define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
# define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
# define PWR_CR_PVDE_Pos (4U)
# define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
# define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
# define PWR_CR_PLS_Pos (5U)
# define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
# define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
# define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
# define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
# define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
/*!< PVD level configuration */
# define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */
# define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */
# define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */
# define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */
# define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */
# define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */
# define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */
# define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */
/* Legacy defines */
# define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0
# define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1
# define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2
# define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3
# define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4
# define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5
# define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6
# define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7
# define PWR_CR_DBP_Pos (8U)
# define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
# define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
/******************* Bit definition for PWR_CSR register ********************/
# define PWR_CSR_WUF_Pos (0U)
# define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
# define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
# define PWR_CSR_SBF_Pos (1U)
# define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
# define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
# define PWR_CSR_PVDO_Pos (2U)
# define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
# define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
# define PWR_CSR_EWUP_Pos (8U)
# define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
# define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
/******************************************************************************/
/* */
/* Backup registers */
/* */
/******************************************************************************/
/******************* Bit definition for BKP_DR1 register ********************/
# define BKP_DR1_D_Pos (0U)
# define BKP_DR1_D_Msk (0xFFFFU << BKP_DR1_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR2 register ********************/
# define BKP_DR2_D_Pos (0U)
# define BKP_DR2_D_Msk (0xFFFFU << BKP_DR2_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR3 register ********************/
# define BKP_DR3_D_Pos (0U)
# define BKP_DR3_D_Msk (0xFFFFU << BKP_DR3_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR4 register ********************/
# define BKP_DR4_D_Pos (0U)
# define BKP_DR4_D_Msk (0xFFFFU << BKP_DR4_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR5 register ********************/
# define BKP_DR5_D_Pos (0U)
# define BKP_DR5_D_Msk (0xFFFFU << BKP_DR5_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR6 register ********************/
# define BKP_DR6_D_Pos (0U)
# define BKP_DR6_D_Msk (0xFFFFU << BKP_DR6_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR7 register ********************/
# define BKP_DR7_D_Pos (0U)
# define BKP_DR7_D_Msk (0xFFFFU << BKP_DR7_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR8 register ********************/
# define BKP_DR8_D_Pos (0U)
# define BKP_DR8_D_Msk (0xFFFFU << BKP_DR8_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR9 register ********************/
# define BKP_DR9_D_Pos (0U)
# define BKP_DR9_D_Msk (0xFFFFU << BKP_DR9_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR10 register *******************/
# define BKP_DR10_D_Pos (0U)
# define BKP_DR10_D_Msk (0xFFFFU << BKP_DR10_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR11 register *******************/
# define BKP_DR11_D_Pos (0U)
# define BKP_DR11_D_Msk (0xFFFFU << BKP_DR11_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR11_D BKP_DR11_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR12 register *******************/
# define BKP_DR12_D_Pos (0U)
# define BKP_DR12_D_Msk (0xFFFFU << BKP_DR12_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR12_D BKP_DR12_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR13 register *******************/
# define BKP_DR13_D_Pos (0U)
# define BKP_DR13_D_Msk (0xFFFFU << BKP_DR13_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR13_D BKP_DR13_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR14 register *******************/
# define BKP_DR14_D_Pos (0U)
# define BKP_DR14_D_Msk (0xFFFFU << BKP_DR14_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR14_D BKP_DR14_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR15 register *******************/
# define BKP_DR15_D_Pos (0U)
# define BKP_DR15_D_Msk (0xFFFFU << BKP_DR15_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR15_D BKP_DR15_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR16 register *******************/
# define BKP_DR16_D_Pos (0U)
# define BKP_DR16_D_Msk (0xFFFFU << BKP_DR16_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR16_D BKP_DR16_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR17 register *******************/
# define BKP_DR17_D_Pos (0U)
# define BKP_DR17_D_Msk (0xFFFFU << BKP_DR17_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR17_D BKP_DR17_D_Msk /*!< Backup data */
/****************** Bit definition for BKP_DR18 register ********************/
# define BKP_DR18_D_Pos (0U)
# define BKP_DR18_D_Msk (0xFFFFU << BKP_DR18_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR18_D BKP_DR18_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR19 register *******************/
# define BKP_DR19_D_Pos (0U)
# define BKP_DR19_D_Msk (0xFFFFU << BKP_DR19_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR19_D BKP_DR19_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR20 register *******************/
# define BKP_DR20_D_Pos (0U)
# define BKP_DR20_D_Msk (0xFFFFU << BKP_DR20_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR20_D BKP_DR20_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR21 register *******************/
# define BKP_DR21_D_Pos (0U)
# define BKP_DR21_D_Msk (0xFFFFU << BKP_DR21_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR21_D BKP_DR21_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR22 register *******************/
# define BKP_DR22_D_Pos (0U)
# define BKP_DR22_D_Msk (0xFFFFU << BKP_DR22_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR22_D BKP_DR22_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR23 register *******************/
# define BKP_DR23_D_Pos (0U)
# define BKP_DR23_D_Msk (0xFFFFU << BKP_DR23_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR23_D BKP_DR23_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR24 register *******************/
# define BKP_DR24_D_Pos (0U)
# define BKP_DR24_D_Msk (0xFFFFU << BKP_DR24_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR24_D BKP_DR24_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR25 register *******************/
# define BKP_DR25_D_Pos (0U)
# define BKP_DR25_D_Msk (0xFFFFU << BKP_DR25_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR25_D BKP_DR25_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR26 register *******************/
# define BKP_DR26_D_Pos (0U)
# define BKP_DR26_D_Msk (0xFFFFU << BKP_DR26_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR26_D BKP_DR26_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR27 register *******************/
# define BKP_DR27_D_Pos (0U)
# define BKP_DR27_D_Msk (0xFFFFU << BKP_DR27_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR27_D BKP_DR27_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR28 register *******************/
# define BKP_DR28_D_Pos (0U)
# define BKP_DR28_D_Msk (0xFFFFU << BKP_DR28_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR28_D BKP_DR28_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR29 register *******************/
# define BKP_DR29_D_Pos (0U)
# define BKP_DR29_D_Msk (0xFFFFU << BKP_DR29_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR29_D BKP_DR29_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR30 register *******************/
# define BKP_DR30_D_Pos (0U)
# define BKP_DR30_D_Msk (0xFFFFU << BKP_DR30_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR30_D BKP_DR30_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR31 register *******************/
# define BKP_DR31_D_Pos (0U)
# define BKP_DR31_D_Msk (0xFFFFU << BKP_DR31_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR31_D BKP_DR31_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR32 register *******************/
# define BKP_DR32_D_Pos (0U)
# define BKP_DR32_D_Msk (0xFFFFU << BKP_DR32_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR32_D BKP_DR32_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR33 register *******************/
# define BKP_DR33_D_Pos (0U)
# define BKP_DR33_D_Msk (0xFFFFU << BKP_DR33_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR33_D BKP_DR33_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR34 register *******************/
# define BKP_DR34_D_Pos (0U)
# define BKP_DR34_D_Msk (0xFFFFU << BKP_DR34_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR34_D BKP_DR34_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR35 register *******************/
# define BKP_DR35_D_Pos (0U)
# define BKP_DR35_D_Msk (0xFFFFU << BKP_DR35_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR35_D BKP_DR35_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR36 register *******************/
# define BKP_DR36_D_Pos (0U)
# define BKP_DR36_D_Msk (0xFFFFU << BKP_DR36_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR36_D BKP_DR36_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR37 register *******************/
# define BKP_DR37_D_Pos (0U)
# define BKP_DR37_D_Msk (0xFFFFU << BKP_DR37_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR37_D BKP_DR37_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR38 register *******************/
# define BKP_DR38_D_Pos (0U)
# define BKP_DR38_D_Msk (0xFFFFU << BKP_DR38_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR38_D BKP_DR38_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR39 register *******************/
# define BKP_DR39_D_Pos (0U)
# define BKP_DR39_D_Msk (0xFFFFU << BKP_DR39_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR39_D BKP_DR39_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR40 register *******************/
# define BKP_DR40_D_Pos (0U)
# define BKP_DR40_D_Msk (0xFFFFU << BKP_DR40_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR40_D BKP_DR40_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR41 register *******************/
# define BKP_DR41_D_Pos (0U)
# define BKP_DR41_D_Msk (0xFFFFU << BKP_DR41_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR41_D BKP_DR41_D_Msk /*!< Backup data */
/******************* Bit definition for BKP_DR42 register *******************/
# define BKP_DR42_D_Pos (0U)
# define BKP_DR42_D_Msk (0xFFFFU << BKP_DR42_D_Pos) /*!< 0x0000FFFF */
# define BKP_DR42_D BKP_DR42_D_Msk /*!< Backup data */
# define RTC_BKP_NUMBER 42
/****************** Bit definition for BKP_RTCCR register *******************/
# define BKP_RTCCR_CAL_Pos (0U)
# define BKP_RTCCR_CAL_Msk (0x7FU << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */
# define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */
# define BKP_RTCCR_CCO_Pos (7U)
# define BKP_RTCCR_CCO_Msk (0x1U << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */
# define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */
# define BKP_RTCCR_ASOE_Pos (8U)
# define BKP_RTCCR_ASOE_Msk (0x1U << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */
# define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */
# define BKP_RTCCR_ASOS_Pos (9U)
# define BKP_RTCCR_ASOS_Msk (0x1U << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */
# define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */
/******************** Bit definition for BKP_CR register ********************/
# define BKP_CR_TPE_Pos (0U)
# define BKP_CR_TPE_Msk (0x1U << BKP_CR_TPE_Pos) /*!< 0x00000001 */
# define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */
# define BKP_CR_TPAL_Pos (1U)
# define BKP_CR_TPAL_Msk (0x1U << BKP_CR_TPAL_Pos) /*!< 0x00000002 */
# define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */
/******************* Bit definition for BKP_CSR register ********************/
# define BKP_CSR_CTE_Pos (0U)
# define BKP_CSR_CTE_Msk (0x1U << BKP_CSR_CTE_Pos) /*!< 0x00000001 */
# define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */
# define BKP_CSR_CTI_Pos (1U)
# define BKP_CSR_CTI_Msk (0x1U << BKP_CSR_CTI_Pos) /*!< 0x00000002 */
# define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */
# define BKP_CSR_TPIE_Pos (2U)
# define BKP_CSR_TPIE_Msk (0x1U << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */
# define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */
# define BKP_CSR_TEF_Pos (8U)
# define BKP_CSR_TEF_Msk (0x1U << BKP_CSR_TEF_Pos) /*!< 0x00000100 */
# define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */
# define BKP_CSR_TIF_Pos (9U)
# define BKP_CSR_TIF_Msk (0x1U << BKP_CSR_TIF_Pos) /*!< 0x00000200 */
# define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */
/******************************************************************************/
/* */
/* Reset and Clock Control */
/* */
/******************************************************************************/
/******************** Bit definition for RCC_CR register ********************/
# define RCC_CR_HSION_Pos (0U)
# define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
# define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
# define RCC_CR_HSIRDY_Pos (1U)
# define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
# define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
# define RCC_CR_HSITRIM_Pos (3U)
# define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
# define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
# define RCC_CR_HSICAL_Pos (8U)
# define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
# define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
# define RCC_CR_HSEON_Pos (16U)
# define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
# define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
# define RCC_CR_HSERDY_Pos (17U)
# define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
# define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
# define RCC_CR_HSEBYP_Pos (18U)
# define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
# define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
# define RCC_CR_CSSON_Pos (19U)
# define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
# define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */
# define RCC_CR_PLLON_Pos (24U)
# define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
# define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
# define RCC_CR_PLLRDY_Pos (25U)
# define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
# define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
/*
* @ brief Specific device feature definitions ( not present on all devices in the STM32F1 serie )
*/
# define RCC_PLL2_SUPPORT /*!< Support PLL2 */
# define RCC_CR_PLL2ON_Pos (26U)
# define RCC_CR_PLL2ON_Msk (0x1U << RCC_CR_PLL2ON_Pos) /*!< 0x04000000 */
# define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< PLL2 enable */
# define RCC_CR_PLL2RDY_Pos (27U)
# define RCC_CR_PLL2RDY_Msk (0x1U << RCC_CR_PLL2RDY_Pos) /*!< 0x08000000 */
# define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */
/*
* @ brief Specific device feature definitions ( not present on all devices in the STM32F1 serie )
*/
# define RCC_PLLI2S_SUPPORT /*!< Support PLL3 (PLLI2S)*/
# define RCC_CR_PLL3ON_Pos (28U)
# define RCC_CR_PLL3ON_Msk (0x1U << RCC_CR_PLL3ON_Pos) /*!< 0x10000000 */
# define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< PLL3 enable */
# define RCC_CR_PLL3RDY_Pos (29U)
# define RCC_CR_PLL3RDY_Msk (0x1U << RCC_CR_PLL3RDY_Pos) /*!< 0x20000000 */
# define RCC_CR_PLL3RDY RCC_CR_PLL3RDY_Msk /*!< PLL3 clock ready flag */
/******************* Bit definition for RCC_CFGR register *******************/
/*!< SW configuration */
# define RCC_CFGR_SW_Pos (0U)
# define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
# define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
# define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
# define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
# define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
# define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
# define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
/*!< SWS configuration */
# define RCC_CFGR_SWS_Pos (2U)
# define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
# define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
# define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
# define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
# define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
# define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
# define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
/*!< HPRE configuration */
# define RCC_CFGR_HPRE_Pos (4U)
# define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
# define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
# define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
# define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
# define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
# define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
# define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
# define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
# define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
# define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
# define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
# define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
# define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
# define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
# define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
/*!< PPRE1 configuration */
# define RCC_CFGR_PPRE1_Pos (8U)
# define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
# define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
# define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
# define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
# define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
# define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
# define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */
# define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */
# define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */
# define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */
/*!< PPRE2 configuration */
# define RCC_CFGR_PPRE2_Pos (11U)
# define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
# define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
# define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
# define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
# define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
# define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
# define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */
# define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */
# define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */
# define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */
/*!< ADCPPRE configuration */
# define RCC_CFGR_ADCPRE_Pos (14U)
# define RCC_CFGR_ADCPRE_Msk (0x3U << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */
# define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */
# define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
# define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
# define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */
# define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */
# define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */
# define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */
# define RCC_CFGR_PLLSRC_Pos (16U)
# define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
# define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
# define RCC_CFGR_PLLXTPRE_Pos (17U)
# define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
# define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */
/*!< PLLMUL configuration */
# define RCC_CFGR_PLLMULL_Pos (18U)
# define RCC_CFGR_PLLMULL_Msk (0xFU << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */
# define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
# define RCC_CFGR_PLLMULL_0 (0x1U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */
# define RCC_CFGR_PLLMULL_1 (0x2U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */
# define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
# define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
# define RCC_CFGR_PLLXTPRE_PREDIV1 0x00000000U /*!< PREDIV1 clock not divided for PLL entry */
# define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 0x00020000U /*!< PREDIV1 clock divided by 2 for PLL entry */
# define RCC_CFGR_PLLMULL4_Pos (19U)
# define RCC_CFGR_PLLMULL4_Msk (0x1U << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */
# define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock * 4 */
# define RCC_CFGR_PLLMULL5_Pos (18U)
# define RCC_CFGR_PLLMULL5_Msk (0x3U << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */
# define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock * 5 */
# define RCC_CFGR_PLLMULL6_Pos (20U)
# define RCC_CFGR_PLLMULL6_Msk (0x1U << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */
# define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock * 6 */
# define RCC_CFGR_PLLMULL7_Pos (18U)
# define RCC_CFGR_PLLMULL7_Msk (0x5U << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */
# define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock * 7 */
# define RCC_CFGR_PLLMULL8_Pos (19U)
# define RCC_CFGR_PLLMULL8_Msk (0x3U << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */
# define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock * 8 */
# define RCC_CFGR_PLLMULL9_Pos (18U)
# define RCC_CFGR_PLLMULL9_Msk (0x7U << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */
# define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock * 9 */
# define RCC_CFGR_PLLMULL6_5 0x00340000U /*!< PLL input clock * 6.5 */
# define RCC_CFGR_OTGFSPRE_Pos (22U)
# define RCC_CFGR_OTGFSPRE_Msk (0x1U << RCC_CFGR_OTGFSPRE_Pos) /*!< 0x00400000 */
# define RCC_CFGR_OTGFSPRE RCC_CFGR_OTGFSPRE_Msk /*!< USB OTG FS prescaler */
/*!< MCO configuration */
# define RCC_CFGR_MCO_Pos (24U)
# define RCC_CFGR_MCO_Msk (0xFU << RCC_CFGR_MCO_Pos) /*!< 0x0F000000 */
# define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */
# define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */
# define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
# define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
# define RCC_CFGR_MCO_3 (0x8U << RCC_CFGR_MCO_Pos) /*!< 0x08000000 */
# define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */
# define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */
# define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */
# define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */
# define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */
# define RCC_CFGR_MCO_PLL2CLK 0x08000000U /*!< PLL2 clock selected as MCO source*/
# define RCC_CFGR_MCO_PLL3CLK_DIV2 0x09000000U /*!< PLL3 clock divided by 2 selected as MCO source*/
# define RCC_CFGR_MCO_EXT_HSE 0x0A000000U /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */
# define RCC_CFGR_MCO_PLL3CLK 0x0B000000U /*!< PLL3 clock selected as MCO source */
/* Reference defines */
# define RCC_CFGR_MCOSEL RCC_CFGR_MCO
# define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
# define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
# define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
# define RCC_CFGR_MCOSEL_3 RCC_CFGR_MCO_3
# define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
# define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
# define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
# define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
# define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
# define RCC_CFGR_MCOSEL_PLL2 RCC_CFGR_MCO_PLL2CLK
# define RCC_CFGR_MCOSEL_PLL3_DIV2 RCC_CFGR_MCO_PLL3CLK_DIV2
# define RCC_CFGR_MCOSEL_EXT_HSE RCC_CFGR_MCO_EXT_HSE
# define RCC_CFGR_MCOSEL_PLL3CLK RCC_CFGR_MCO_PLL3CLK
/*!<****************** Bit definition for RCC_CIR register ********************/
# define RCC_CIR_LSIRDYF_Pos (0U)
# define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
# define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
# define RCC_CIR_LSERDYF_Pos (1U)
# define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
# define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
# define RCC_CIR_HSIRDYF_Pos (2U)
# define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
# define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
# define RCC_CIR_HSERDYF_Pos (3U)
# define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
# define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
# define RCC_CIR_PLLRDYF_Pos (4U)
# define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
# define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
# define RCC_CIR_CSSF_Pos (7U)
# define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
# define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
# define RCC_CIR_LSIRDYIE_Pos (8U)
# define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
# define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
# define RCC_CIR_LSERDYIE_Pos (9U)
# define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
# define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
# define RCC_CIR_HSIRDYIE_Pos (10U)
# define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
# define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
# define RCC_CIR_HSERDYIE_Pos (11U)
# define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
# define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
# define RCC_CIR_PLLRDYIE_Pos (12U)
# define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
# define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
# define RCC_CIR_LSIRDYC_Pos (16U)
# define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
# define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
# define RCC_CIR_LSERDYC_Pos (17U)
# define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
# define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
# define RCC_CIR_HSIRDYC_Pos (18U)
# define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
# define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
# define RCC_CIR_HSERDYC_Pos (19U)
# define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
# define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
# define RCC_CIR_PLLRDYC_Pos (20U)
# define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
# define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
# define RCC_CIR_CSSC_Pos (23U)
# define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
# define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
# define RCC_CIR_PLL2RDYF_Pos (5U)
# define RCC_CIR_PLL2RDYF_Msk (0x1U << RCC_CIR_PLL2RDYF_Pos) /*!< 0x00000020 */
# define RCC_CIR_PLL2RDYF RCC_CIR_PLL2RDYF_Msk /*!< PLL2 Ready Interrupt flag */
# define RCC_CIR_PLL3RDYF_Pos (6U)
# define RCC_CIR_PLL3RDYF_Msk (0x1U << RCC_CIR_PLL3RDYF_Pos) /*!< 0x00000040 */
# define RCC_CIR_PLL3RDYF RCC_CIR_PLL3RDYF_Msk /*!< PLL3 Ready Interrupt flag */
# define RCC_CIR_PLL2RDYIE_Pos (13U)
# define RCC_CIR_PLL2RDYIE_Msk (0x1U << RCC_CIR_PLL2RDYIE_Pos) /*!< 0x00002000 */
# define RCC_CIR_PLL2RDYIE RCC_CIR_PLL2RDYIE_Msk /*!< PLL2 Ready Interrupt Enable */
# define RCC_CIR_PLL3RDYIE_Pos (14U)
# define RCC_CIR_PLL3RDYIE_Msk (0x1U << RCC_CIR_PLL3RDYIE_Pos) /*!< 0x00004000 */
# define RCC_CIR_PLL3RDYIE RCC_CIR_PLL3RDYIE_Msk /*!< PLL3 Ready Interrupt Enable */
# define RCC_CIR_PLL2RDYC_Pos (21U)
# define RCC_CIR_PLL2RDYC_Msk (0x1U << RCC_CIR_PLL2RDYC_Pos) /*!< 0x00200000 */
# define RCC_CIR_PLL2RDYC RCC_CIR_PLL2RDYC_Msk /*!< PLL2 Ready Interrupt Clear */
# define RCC_CIR_PLL3RDYC_Pos (22U)
# define RCC_CIR_PLL3RDYC_Msk (0x1U << RCC_CIR_PLL3RDYC_Pos) /*!< 0x00400000 */
# define RCC_CIR_PLL3RDYC RCC_CIR_PLL3RDYC_Msk /*!< PLL3 Ready Interrupt Clear */
/***************** Bit definition for RCC_APB2RSTR register *****************/
# define RCC_APB2RSTR_AFIORST_Pos (0U)
# define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */
# define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */
# define RCC_APB2RSTR_IOPARST_Pos (2U)
# define RCC_APB2RSTR_IOPARST_Msk (0x1U << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */
# define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */
# define RCC_APB2RSTR_IOPBRST_Pos (3U)
# define RCC_APB2RSTR_IOPBRST_Msk (0x1U << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */
# define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */
# define RCC_APB2RSTR_IOPCRST_Pos (4U)
# define RCC_APB2RSTR_IOPCRST_Msk (0x1U << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */
# define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */
# define RCC_APB2RSTR_IOPDRST_Pos (5U)
# define RCC_APB2RSTR_IOPDRST_Msk (0x1U << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */
# define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */
# define RCC_APB2RSTR_ADC1RST_Pos (9U)
# define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
# define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */
# define RCC_APB2RSTR_ADC2RST_Pos (10U)
# define RCC_APB2RSTR_ADC2RST_Msk (0x1U << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */
# define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk /*!< ADC 2 interface reset */
# define RCC_APB2RSTR_TIM1RST_Pos (11U)
# define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
# define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */
# define RCC_APB2RSTR_SPI1RST_Pos (12U)
# define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
# define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */
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# define RCC_APB2RSTR_USART0RST_Pos (14U)
# define RCC_APB2RSTR_USART0RST_Msk (0x1U << RCC_APB2RSTR_USART0RST_Pos) /*!< 0x00004000 */
# define RCC_APB2RSTR_USART0RST RCC_APB2RSTR_USART0RST_Msk /*!< USART0 reset */
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# define RCC_APB2RSTR_IOPERST_Pos (6U)
# define RCC_APB2RSTR_IOPERST_Msk (0x1U << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */
# define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */
/***************** Bit definition for RCC_APB1RSTR register *****************/
# define RCC_APB1RSTR_TIM2RST_Pos (0U)
# define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
# define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
# define RCC_APB1RSTR_TIM3RST_Pos (1U)
# define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
# define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
# define RCC_APB1RSTR_WWDGRST_Pos (11U)
# define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
# define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
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# define RCC_APB1RSTR_USART1RST_Pos (17U)
# define RCC_APB1RSTR_USART1RST_Msk (0x1U << RCC_APB1RSTR_USART1RST_Pos) /*!< 0x00020000 */
# define RCC_APB1RSTR_USART1RST RCC_APB1RSTR_USART1RST_Msk /*!< USART 2 reset */
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# define RCC_APB1RSTR_I2C0RST_Pos (21U)
# define RCC_APB1RSTR_I2C0RST_Msk (0x1U << RCC_APB1RSTR_I2C0RST_Pos) /*!< 0x00200000 */
# define RCC_APB1RSTR_I2C0RST RCC_APB1RSTR_I2C0RST_Msk /*!< I2C 1 reset */
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# define RCC_APB1RSTR_CAN1RST_Pos (25U)
# define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
# define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk /*!< CAN1 reset */
# define RCC_APB1RSTR_BKPRST_Pos (27U)
# define RCC_APB1RSTR_BKPRST_Msk (0x1U << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */
# define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */
# define RCC_APB1RSTR_PWRRST_Pos (28U)
# define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
# define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */
# define RCC_APB1RSTR_TIM4RST_Pos (2U)
# define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
# define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */
# define RCC_APB1RSTR_SPI2RST_Pos (14U)
# define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
# define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */
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# define RCC_APB1RSTR_USART2RST_Pos (18U)
# define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00040000 */
# define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 3 reset */
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# define RCC_APB1RSTR_I2C1RST_Pos (22U)
# define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00400000 */
# define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 2 reset */
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# define RCC_APB1RSTR_TIM5RST_Pos (3U)
# define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
# define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk /*!< Timer 5 reset */
# define RCC_APB1RSTR_TIM6RST_Pos (4U)
# define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
# define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */
# define RCC_APB1RSTR_TIM7RST_Pos (5U)
# define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
# define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */
# define RCC_APB1RSTR_SPI3RST_Pos (15U)
# define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
# define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk /*!< SPI 3 reset */
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# define RCC_APB1RSTR_UART3RST_Pos (19U)
# define RCC_APB1RSTR_UART3RST_Msk (0x1U << RCC_APB1RSTR_UART3RST_Pos) /*!< 0x00080000 */
# define RCC_APB1RSTR_UART3RST RCC_APB1RSTR_UART3RST_Msk /*!< UART 4 reset */
# define RCC_APB1RSTR_UART4RST_Pos (20U)
# define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00100000 */
# define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk /*!< UART 5 reset */
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# define RCC_APB1RSTR_CAN2RST_Pos (26U)
# define RCC_APB1RSTR_CAN2RST_Msk (0x1U << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
# define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk /*!< CAN2 reset */
# define RCC_APB1RSTR_DACRST_Pos (29U)
# define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
# define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC interface reset */
/****************** Bit definition for RCC_AHBENR register ******************/
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# define RCC_AHBENR_DMA0EN_Pos (0U)
# define RCC_AHBENR_DMA0EN_Msk (0x1U << RCC_AHBENR_DMA0EN_Pos) /*!< 0x00000001 */
# define RCC_AHBENR_DMA0EN RCC_AHBENR_DMA0EN_Msk /*!< DMA0 clock enable */
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# define RCC_AHBENR_SRAMEN_Pos (2U)
# define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
# define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */
# define RCC_AHBENR_FLITFEN_Pos (4U)
# define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
# define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */
# define RCC_AHBENR_CRCEN_Pos (6U)
# define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
# define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
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# define RCC_AHBENR_DMA1EN_Pos (1U)
# define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000002 */
# define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */
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# define RCC_AHBENR_OTGFSEN_Pos (12U)
# define RCC_AHBENR_OTGFSEN_Msk (0x1U << RCC_AHBENR_OTGFSEN_Pos) /*!< 0x00001000 */
# define RCC_AHBENR_OTGFSEN RCC_AHBENR_OTGFSEN_Msk /*!< USB OTG FS clock enable */
/****************** Bit definition for RCC_APB2ENR register *****************/
# define RCC_APB2ENR_AFIOEN_Pos (0U)
# define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */
# define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */
# define RCC_APB2ENR_IOPAEN_Pos (2U)
# define RCC_APB2ENR_IOPAEN_Msk (0x1U << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */
# define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */
# define RCC_APB2ENR_IOPBEN_Pos (3U)
# define RCC_APB2ENR_IOPBEN_Msk (0x1U << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */
# define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */
# define RCC_APB2ENR_IOPCEN_Pos (4U)
# define RCC_APB2ENR_IOPCEN_Msk (0x1U << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */
# define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */
# define RCC_APB2ENR_IOPDEN_Pos (5U)
# define RCC_APB2ENR_IOPDEN_Msk (0x1U << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */
# define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */
# define RCC_APB2ENR_ADC1EN_Pos (9U)
# define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */
# define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */
# define RCC_APB2ENR_ADC2EN_Pos (10U)
# define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000400 */
# define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk /*!< ADC 2 interface clock enable */
# define RCC_APB2ENR_TIM1EN_Pos (11U)
# define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
# define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */
# define RCC_APB2ENR_SPI1EN_Pos (12U)
# define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
# define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */
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# define RCC_APB2ENR_USART0EN_Pos (14U)
# define RCC_APB2ENR_USART0EN_Msk (0x1U << RCC_APB2ENR_USART0EN_Pos) /*!< 0x00004000 */
# define RCC_APB2ENR_USART0EN RCC_APB2ENR_USART0EN_Msk /*!< USART0 clock enable */
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# define RCC_APB2ENR_IOPEEN_Pos (6U)
# define RCC_APB2ENR_IOPEEN_Msk (0x1U << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */
# define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */
/***************** Bit definition for RCC_APB1ENR register ******************/
# define RCC_APB1ENR_TIM2EN_Pos (0U)
# define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
# define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/
# define RCC_APB1ENR_TIM3EN_Pos (1U)
# define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
# define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
# define RCC_APB1ENR_WWDGEN_Pos (11U)
# define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
# define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
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# define RCC_APB1ENR_USART1EN_Pos (17U)
# define RCC_APB1ENR_USART1EN_Msk (0x1U << RCC_APB1ENR_USART1EN_Pos) /*!< 0x00020000 */
# define RCC_APB1ENR_USART1EN RCC_APB1ENR_USART1EN_Msk /*!< USART 2 clock enable */
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# define RCC_APB1ENR_I2C0EN_Pos (21U)
# define RCC_APB1ENR_I2C0EN_Msk (0x1U << RCC_APB1ENR_I2C0EN_Pos) /*!< 0x00200000 */
# define RCC_APB1ENR_I2C0EN RCC_APB1ENR_I2C0EN_Msk /*!< I2C 1 clock enable */
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# define RCC_APB1ENR_CAN1EN_Pos (25U)
# define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
# define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk /*!< CAN1 clock enable */
# define RCC_APB1ENR_BKPEN_Pos (27U)
# define RCC_APB1ENR_BKPEN_Msk (0x1U << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */
# define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */
# define RCC_APB1ENR_PWREN_Pos (28U)
# define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
# define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */
# define RCC_APB1ENR_TIM4EN_Pos (2U)
# define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
# define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */
# define RCC_APB1ENR_SPI2EN_Pos (14U)
# define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
# define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */
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# define RCC_APB1ENR_USART2EN_Pos (18U)
# define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00040000 */
# define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 3 clock enable */
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# define RCC_APB1ENR_I2C1EN_Pos (22U)
# define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00400000 */
# define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 2 clock enable */
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# define RCC_APB1ENR_TIM5EN_Pos (3U)
# define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
# define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk /*!< Timer 5 clock enable */
# define RCC_APB1ENR_TIM6EN_Pos (4U)
# define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
# define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */
# define RCC_APB1ENR_TIM7EN_Pos (5U)
# define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
# define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */
# define RCC_APB1ENR_SPI3EN_Pos (15U)
# define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
# define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI 3 clock enable */
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# define RCC_APB1ENR_UART3EN_Pos (19U)
# define RCC_APB1ENR_UART3EN_Msk (0x1U << RCC_APB1ENR_UART3EN_Pos) /*!< 0x00080000 */
# define RCC_APB1ENR_UART3EN RCC_APB1ENR_UART3EN_Msk /*!< UART 4 clock enable */
# define RCC_APB1ENR_UART4EN_Pos (20U)
# define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00100000 */
# define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk /*!< UART 5 clock enable */
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# define RCC_APB1ENR_CAN2EN_Pos (26U)
# define RCC_APB1ENR_CAN2EN_Msk (0x1U << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
# define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk /*!< CAN2 clock enable */
# define RCC_APB1ENR_DACEN_Pos (29U)
# define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
# define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC interface clock enable */
/******************* Bit definition for RCC_BDCR register *******************/
# define RCC_BDCR_LSEON_Pos (0U)
# define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
# define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */
# define RCC_BDCR_LSERDY_Pos (1U)
# define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
# define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
# define RCC_BDCR_LSEBYP_Pos (2U)
# define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
# define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
# define RCC_BDCR_RTCSEL_Pos (8U)
# define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
# define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
# define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
# define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
/*!< RTC congiguration */
# define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */
# define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */
# define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */
# define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */
# define RCC_BDCR_RTCEN_Pos (15U)
# define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
# define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */
# define RCC_BDCR_BDRST_Pos (16U)
# define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
# define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */
/******************* Bit definition for RCC_CSR register ********************/
# define RCC_CSR_LSION_Pos (0U)
# define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
# define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
# define RCC_CSR_LSIRDY_Pos (1U)
# define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
# define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
# define RCC_CSR_RMVF_Pos (24U)
# define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
# define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
# define RCC_CSR_PINRSTF_Pos (26U)
# define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
# define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
# define RCC_CSR_PORRSTF_Pos (27U)
# define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
# define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
# define RCC_CSR_SFTRSTF_Pos (28U)
# define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
# define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
# define RCC_CSR_IWDGRSTF_Pos (29U)
# define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
# define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
# define RCC_CSR_WWDGRSTF_Pos (30U)
# define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
# define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
# define RCC_CSR_LPWRRSTF_Pos (31U)
# define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
# define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
/******************* Bit definition for RCC_AHBRSTR register ****************/
# define RCC_AHBRSTR_OTGFSRST_Pos (12U)
# define RCC_AHBRSTR_OTGFSRST_Msk (0x1U << RCC_AHBRSTR_OTGFSRST_Pos) /*!< 0x00001000 */
# define RCC_AHBRSTR_OTGFSRST RCC_AHBRSTR_OTGFSRST_Msk /*!< USB OTG FS reset */
/******************* Bit definition for RCC_CFGR2 register ******************/
/*!< PREDIV1 configuration */
# define RCC_CFGR2_PREDIV1_Pos (0U)
# define RCC_CFGR2_PREDIV1_Msk (0xFU << RCC_CFGR2_PREDIV1_Pos) /*!< 0x0000000F */
# define RCC_CFGR2_PREDIV1 RCC_CFGR2_PREDIV1_Msk /*!< PREDIV1[3:0] bits */
# define RCC_CFGR2_PREDIV1_0 (0x1U << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000001 */
# define RCC_CFGR2_PREDIV1_1 (0x2U << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000002 */
# define RCC_CFGR2_PREDIV1_2 (0x4U << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000004 */
# define RCC_CFGR2_PREDIV1_3 (0x8U << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000008 */
# define RCC_CFGR2_PREDIV1_DIV1 0x00000000U /*!< PREDIV1 input clock not divided */
# define RCC_CFGR2_PREDIV1_DIV2_Pos (0U)
# define RCC_CFGR2_PREDIV1_DIV2_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV2_Pos) /*!< 0x00000001 */
# define RCC_CFGR2_PREDIV1_DIV2 RCC_CFGR2_PREDIV1_DIV2_Msk /*!< PREDIV1 input clock divided by 2 */
# define RCC_CFGR2_PREDIV1_DIV3_Pos (1U)
# define RCC_CFGR2_PREDIV1_DIV3_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV3_Pos) /*!< 0x00000002 */
# define RCC_CFGR2_PREDIV1_DIV3 RCC_CFGR2_PREDIV1_DIV3_Msk /*!< PREDIV1 input clock divided by 3 */
# define RCC_CFGR2_PREDIV1_DIV4_Pos (0U)
# define RCC_CFGR2_PREDIV1_DIV4_Msk (0x3U << RCC_CFGR2_PREDIV1_DIV4_Pos) /*!< 0x00000003 */
# define RCC_CFGR2_PREDIV1_DIV4 RCC_CFGR2_PREDIV1_DIV4_Msk /*!< PREDIV1 input clock divided by 4 */
# define RCC_CFGR2_PREDIV1_DIV5_Pos (2U)
# define RCC_CFGR2_PREDIV1_DIV5_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV5_Pos) /*!< 0x00000004 */
# define RCC_CFGR2_PREDIV1_DIV5 RCC_CFGR2_PREDIV1_DIV5_Msk /*!< PREDIV1 input clock divided by 5 */
# define RCC_CFGR2_PREDIV1_DIV6_Pos (0U)
# define RCC_CFGR2_PREDIV1_DIV6_Msk (0x5U << RCC_CFGR2_PREDIV1_DIV6_Pos) /*!< 0x00000005 */
# define RCC_CFGR2_PREDIV1_DIV6 RCC_CFGR2_PREDIV1_DIV6_Msk /*!< PREDIV1 input clock divided by 6 */
# define RCC_CFGR2_PREDIV1_DIV7_Pos (1U)
# define RCC_CFGR2_PREDIV1_DIV7_Msk (0x3U << RCC_CFGR2_PREDIV1_DIV7_Pos) /*!< 0x00000006 */
# define RCC_CFGR2_PREDIV1_DIV7 RCC_CFGR2_PREDIV1_DIV7_Msk /*!< PREDIV1 input clock divided by 7 */
# define RCC_CFGR2_PREDIV1_DIV8_Pos (0U)
# define RCC_CFGR2_PREDIV1_DIV8_Msk (0x7U << RCC_CFGR2_PREDIV1_DIV8_Pos) /*!< 0x00000007 */
# define RCC_CFGR2_PREDIV1_DIV8 RCC_CFGR2_PREDIV1_DIV8_Msk /*!< PREDIV1 input clock divided by 8 */
# define RCC_CFGR2_PREDIV1_DIV9_Pos (3U)
# define RCC_CFGR2_PREDIV1_DIV9_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV9_Pos) /*!< 0x00000008 */
# define RCC_CFGR2_PREDIV1_DIV9 RCC_CFGR2_PREDIV1_DIV9_Msk /*!< PREDIV1 input clock divided by 9 */
# define RCC_CFGR2_PREDIV1_DIV10_Pos (0U)
# define RCC_CFGR2_PREDIV1_DIV10_Msk (0x9U << RCC_CFGR2_PREDIV1_DIV10_Pos) /*!< 0x00000009 */
# define RCC_CFGR2_PREDIV1_DIV10 RCC_CFGR2_PREDIV1_DIV10_Msk /*!< PREDIV1 input clock divided by 10 */
# define RCC_CFGR2_PREDIV1_DIV11_Pos (1U)
# define RCC_CFGR2_PREDIV1_DIV11_Msk (0x5U << RCC_CFGR2_PREDIV1_DIV11_Pos) /*!< 0x0000000A */
# define RCC_CFGR2_PREDIV1_DIV11 RCC_CFGR2_PREDIV1_DIV11_Msk /*!< PREDIV1 input clock divided by 11 */
# define RCC_CFGR2_PREDIV1_DIV12_Pos (0U)
# define RCC_CFGR2_PREDIV1_DIV12_Msk (0xBU << RCC_CFGR2_PREDIV1_DIV12_Pos) /*!< 0x0000000B */
# define RCC_CFGR2_PREDIV1_DIV12 RCC_CFGR2_PREDIV1_DIV12_Msk /*!< PREDIV1 input clock divided by 12 */
# define RCC_CFGR2_PREDIV1_DIV13_Pos (2U)
# define RCC_CFGR2_PREDIV1_DIV13_Msk (0x3U << RCC_CFGR2_PREDIV1_DIV13_Pos) /*!< 0x0000000C */
# define RCC_CFGR2_PREDIV1_DIV13 RCC_CFGR2_PREDIV1_DIV13_Msk /*!< PREDIV1 input clock divided by 13 */
# define RCC_CFGR2_PREDIV1_DIV14_Pos (0U)
# define RCC_CFGR2_PREDIV1_DIV14_Msk (0xDU << RCC_CFGR2_PREDIV1_DIV14_Pos) /*!< 0x0000000D */
# define RCC_CFGR2_PREDIV1_DIV14 RCC_CFGR2_PREDIV1_DIV14_Msk /*!< PREDIV1 input clock divided by 14 */
# define RCC_CFGR2_PREDIV1_DIV15_Pos (1U)
# define RCC_CFGR2_PREDIV1_DIV15_Msk (0x7U << RCC_CFGR2_PREDIV1_DIV15_Pos) /*!< 0x0000000E */
# define RCC_CFGR2_PREDIV1_DIV15 RCC_CFGR2_PREDIV1_DIV15_Msk /*!< PREDIV1 input clock divided by 15 */
# define RCC_CFGR2_PREDIV1_DIV16_Pos (0U)
# define RCC_CFGR2_PREDIV1_DIV16_Msk (0xFU << RCC_CFGR2_PREDIV1_DIV16_Pos) /*!< 0x0000000F */
# define RCC_CFGR2_PREDIV1_DIV16 RCC_CFGR2_PREDIV1_DIV16_Msk /*!< PREDIV1 input clock divided by 16 */
/*!< PREDIV2 configuration */
# define RCC_CFGR2_PREDIV2_Pos (4U)
# define RCC_CFGR2_PREDIV2_Msk (0xFU << RCC_CFGR2_PREDIV2_Pos) /*!< 0x000000F0 */
# define RCC_CFGR2_PREDIV2 RCC_CFGR2_PREDIV2_Msk /*!< PREDIV2[3:0] bits */
# define RCC_CFGR2_PREDIV2_0 (0x1U << RCC_CFGR2_PREDIV2_Pos) /*!< 0x00000010 */
# define RCC_CFGR2_PREDIV2_1 (0x2U << RCC_CFGR2_PREDIV2_Pos) /*!< 0x00000020 */
# define RCC_CFGR2_PREDIV2_2 (0x4U << RCC_CFGR2_PREDIV2_Pos) /*!< 0x00000040 */
# define RCC_CFGR2_PREDIV2_3 (0x8U << RCC_CFGR2_PREDIV2_Pos) /*!< 0x00000080 */
# define RCC_CFGR2_PREDIV2_DIV1 0x00000000U /*!< PREDIV2 input clock not divided */
# define RCC_CFGR2_PREDIV2_DIV2_Pos (4U)
# define RCC_CFGR2_PREDIV2_DIV2_Msk (0x1U << RCC_CFGR2_PREDIV2_DIV2_Pos) /*!< 0x00000010 */
# define RCC_CFGR2_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2_Msk /*!< PREDIV2 input clock divided by 2 */
# define RCC_CFGR2_PREDIV2_DIV3_Pos (5U)
# define RCC_CFGR2_PREDIV2_DIV3_Msk (0x1U << RCC_CFGR2_PREDIV2_DIV3_Pos) /*!< 0x00000020 */
# define RCC_CFGR2_PREDIV2_DIV3 RCC_CFGR2_PREDIV2_DIV3_Msk /*!< PREDIV2 input clock divided by 3 */
# define RCC_CFGR2_PREDIV2_DIV4_Pos (4U)
# define RCC_CFGR2_PREDIV2_DIV4_Msk (0x3U << RCC_CFGR2_PREDIV2_DIV4_Pos) /*!< 0x00000030 */
# define RCC_CFGR2_PREDIV2_DIV4 RCC_CFGR2_PREDIV2_DIV4_Msk /*!< PREDIV2 input clock divided by 4 */
# define RCC_CFGR2_PREDIV2_DIV5_Pos (6U)
# define RCC_CFGR2_PREDIV2_DIV5_Msk (0x1U << RCC_CFGR2_PREDIV2_DIV5_Pos) /*!< 0x00000040 */
# define RCC_CFGR2_PREDIV2_DIV5 RCC_CFGR2_PREDIV2_DIV5_Msk /*!< PREDIV2 input clock divided by 5 */
# define RCC_CFGR2_PREDIV2_DIV6_Pos (4U)
# define RCC_CFGR2_PREDIV2_DIV6_Msk (0x5U << RCC_CFGR2_PREDIV2_DIV6_Pos) /*!< 0x00000050 */
# define RCC_CFGR2_PREDIV2_DIV6 RCC_CFGR2_PREDIV2_DIV6_Msk /*!< PREDIV2 input clock divided by 6 */
# define RCC_CFGR2_PREDIV2_DIV7_Pos (5U)
# define RCC_CFGR2_PREDIV2_DIV7_Msk (0x3U << RCC_CFGR2_PREDIV2_DIV7_Pos) /*!< 0x00000060 */
# define RCC_CFGR2_PREDIV2_DIV7 RCC_CFGR2_PREDIV2_DIV7_Msk /*!< PREDIV2 input clock divided by 7 */
# define RCC_CFGR2_PREDIV2_DIV8_Pos (4U)
# define RCC_CFGR2_PREDIV2_DIV8_Msk (0x7U << RCC_CFGR2_PREDIV2_DIV8_Pos) /*!< 0x00000070 */
# define RCC_CFGR2_PREDIV2_DIV8 RCC_CFGR2_PREDIV2_DIV8_Msk /*!< PREDIV2 input clock divided by 8 */
# define RCC_CFGR2_PREDIV2_DIV9_Pos (7U)
# define RCC_CFGR2_PREDIV2_DIV9_Msk (0x1U << RCC_CFGR2_PREDIV2_DIV9_Pos) /*!< 0x00000080 */
# define RCC_CFGR2_PREDIV2_DIV9 RCC_CFGR2_PREDIV2_DIV9_Msk /*!< PREDIV2 input clock divided by 9 */
# define RCC_CFGR2_PREDIV2_DIV10_Pos (4U)
# define RCC_CFGR2_PREDIV2_DIV10_Msk (0x9U << RCC_CFGR2_PREDIV2_DIV10_Pos) /*!< 0x00000090 */
# define RCC_CFGR2_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10_Msk /*!< PREDIV2 input clock divided by 10 */
# define RCC_CFGR2_PREDIV2_DIV11_Pos (5U)
# define RCC_CFGR2_PREDIV2_DIV11_Msk (0x5U << RCC_CFGR2_PREDIV2_DIV11_Pos) /*!< 0x000000A0 */
# define RCC_CFGR2_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11_Msk /*!< PREDIV2 input clock divided by 11 */
# define RCC_CFGR2_PREDIV2_DIV12_Pos (4U)
# define RCC_CFGR2_PREDIV2_DIV12_Msk (0xBU << RCC_CFGR2_PREDIV2_DIV12_Pos) /*!< 0x000000B0 */
# define RCC_CFGR2_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12_Msk /*!< PREDIV2 input clock divided by 12 */
# define RCC_CFGR2_PREDIV2_DIV13_Pos (6U)
# define RCC_CFGR2_PREDIV2_DIV13_Msk (0x3U << RCC_CFGR2_PREDIV2_DIV13_Pos) /*!< 0x000000C0 */
# define RCC_CFGR2_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13_Msk /*!< PREDIV2 input clock divided by 13 */
# define RCC_CFGR2_PREDIV2_DIV14_Pos (4U)
# define RCC_CFGR2_PREDIV2_DIV14_Msk (0xDU << RCC_CFGR2_PREDIV2_DIV14_Pos) /*!< 0x000000D0 */
# define RCC_CFGR2_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14_Msk /*!< PREDIV2 input clock divided by 14 */
# define RCC_CFGR2_PREDIV2_DIV15_Pos (5U)
# define RCC_CFGR2_PREDIV2_DIV15_Msk (0x7U << RCC_CFGR2_PREDIV2_DIV15_Pos) /*!< 0x000000E0 */
# define RCC_CFGR2_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15_Msk /*!< PREDIV2 input clock divided by 15 */
# define RCC_CFGR2_PREDIV2_DIV16_Pos (4U)
# define RCC_CFGR2_PREDIV2_DIV16_Msk (0xFU << RCC_CFGR2_PREDIV2_DIV16_Pos) /*!< 0x000000F0 */
# define RCC_CFGR2_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16_Msk /*!< PREDIV2 input clock divided by 16 */
/*!< PLL2MUL configuration */
# define RCC_CFGR2_PLL2MUL_Pos (8U)
# define RCC_CFGR2_PLL2MUL_Msk (0xFU << RCC_CFGR2_PLL2MUL_Pos) /*!< 0x00000F00 */
# define RCC_CFGR2_PLL2MUL RCC_CFGR2_PLL2MUL_Msk /*!< PLL2MUL[3:0] bits */
# define RCC_CFGR2_PLL2MUL_0 (0x1U << RCC_CFGR2_PLL2MUL_Pos) /*!< 0x00000100 */
# define RCC_CFGR2_PLL2MUL_1 (0x2U << RCC_CFGR2_PLL2MUL_Pos) /*!< 0x00000200 */
# define RCC_CFGR2_PLL2MUL_2 (0x4U << RCC_CFGR2_PLL2MUL_Pos) /*!< 0x00000400 */
# define RCC_CFGR2_PLL2MUL_3 (0x8U << RCC_CFGR2_PLL2MUL_Pos) /*!< 0x00000800 */
# define RCC_CFGR2_PLL2MUL8_Pos (9U)
# define RCC_CFGR2_PLL2MUL8_Msk (0x3U << RCC_CFGR2_PLL2MUL8_Pos) /*!< 0x00000600 */
# define RCC_CFGR2_PLL2MUL8 RCC_CFGR2_PLL2MUL8_Msk /*!< PLL2 input clock * 8 */
# define RCC_CFGR2_PLL2MUL9_Pos (8U)
# define RCC_CFGR2_PLL2MUL9_Msk (0x7U << RCC_CFGR2_PLL2MUL9_Pos) /*!< 0x00000700 */
# define RCC_CFGR2_PLL2MUL9 RCC_CFGR2_PLL2MUL9_Msk /*!< PLL2 input clock * 9 */
# define RCC_CFGR2_PLL2MUL10_Pos (11U)
# define RCC_CFGR2_PLL2MUL10_Msk (0x1U << RCC_CFGR2_PLL2MUL10_Pos) /*!< 0x00000800 */
# define RCC_CFGR2_PLL2MUL10 RCC_CFGR2_PLL2MUL10_Msk /*!< PLL2 input clock * 10 */
# define RCC_CFGR2_PLL2MUL11_Pos (8U)
# define RCC_CFGR2_PLL2MUL11_Msk (0x9U << RCC_CFGR2_PLL2MUL11_Pos) /*!< 0x00000900 */
# define RCC_CFGR2_PLL2MUL11 RCC_CFGR2_PLL2MUL11_Msk /*!< PLL2 input clock * 11 */
# define RCC_CFGR2_PLL2MUL12_Pos (9U)
# define RCC_CFGR2_PLL2MUL12_Msk (0x5U << RCC_CFGR2_PLL2MUL12_Pos) /*!< 0x00000A00 */
# define RCC_CFGR2_PLL2MUL12 RCC_CFGR2_PLL2MUL12_Msk /*!< PLL2 input clock * 12 */
# define RCC_CFGR2_PLL2MUL13_Pos (8U)
# define RCC_CFGR2_PLL2MUL13_Msk (0xBU << RCC_CFGR2_PLL2MUL13_Pos) /*!< 0x00000B00 */
# define RCC_CFGR2_PLL2MUL13 RCC_CFGR2_PLL2MUL13_Msk /*!< PLL2 input clock * 13 */
# define RCC_CFGR2_PLL2MUL14_Pos (10U)
# define RCC_CFGR2_PLL2MUL14_Msk (0x3U << RCC_CFGR2_PLL2MUL14_Pos) /*!< 0x00000C00 */
# define RCC_CFGR2_PLL2MUL14 RCC_CFGR2_PLL2MUL14_Msk /*!< PLL2 input clock * 14 */
# define RCC_CFGR2_PLL2MUL16_Pos (9U)
# define RCC_CFGR2_PLL2MUL16_Msk (0x7U << RCC_CFGR2_PLL2MUL16_Pos) /*!< 0x00000E00 */
# define RCC_CFGR2_PLL2MUL16 RCC_CFGR2_PLL2MUL16_Msk /*!< PLL2 input clock * 16 */
# define RCC_CFGR2_PLL2MUL20_Pos (8U)
# define RCC_CFGR2_PLL2MUL20_Msk (0xFU << RCC_CFGR2_PLL2MUL20_Pos) /*!< 0x00000F00 */
# define RCC_CFGR2_PLL2MUL20 RCC_CFGR2_PLL2MUL20_Msk /*!< PLL2 input clock * 20 */
/*!< PLL3MUL configuration */
# define RCC_CFGR2_PLL3MUL_Pos (12U)
# define RCC_CFGR2_PLL3MUL_Msk (0xFU << RCC_CFGR2_PLL3MUL_Pos) /*!< 0x0000F000 */
# define RCC_CFGR2_PLL3MUL RCC_CFGR2_PLL3MUL_Msk /*!< PLL3MUL[3:0] bits */
# define RCC_CFGR2_PLL3MUL_0 (0x1U << RCC_CFGR2_PLL3MUL_Pos) /*!< 0x00001000 */
# define RCC_CFGR2_PLL3MUL_1 (0x2U << RCC_CFGR2_PLL3MUL_Pos) /*!< 0x00002000 */
# define RCC_CFGR2_PLL3MUL_2 (0x4U << RCC_CFGR2_PLL3MUL_Pos) /*!< 0x00004000 */
# define RCC_CFGR2_PLL3MUL_3 (0x8U << RCC_CFGR2_PLL3MUL_Pos) /*!< 0x00008000 */
# define RCC_CFGR2_PLL3MUL8_Pos (13U)
# define RCC_CFGR2_PLL3MUL8_Msk (0x3U << RCC_CFGR2_PLL3MUL8_Pos) /*!< 0x00006000 */
# define RCC_CFGR2_PLL3MUL8 RCC_CFGR2_PLL3MUL8_Msk /*!< PLL3 input clock * 8 */
# define RCC_CFGR2_PLL3MUL9_Pos (12U)
# define RCC_CFGR2_PLL3MUL9_Msk (0x7U << RCC_CFGR2_PLL3MUL9_Pos) /*!< 0x00007000 */
# define RCC_CFGR2_PLL3MUL9 RCC_CFGR2_PLL3MUL9_Msk /*!< PLL3 input clock * 9 */
# define RCC_CFGR2_PLL3MUL10_Pos (15U)
# define RCC_CFGR2_PLL3MUL10_Msk (0x1U << RCC_CFGR2_PLL3MUL10_Pos) /*!< 0x00008000 */
# define RCC_CFGR2_PLL3MUL10 RCC_CFGR2_PLL3MUL10_Msk /*!< PLL3 input clock * 10 */
# define RCC_CFGR2_PLL3MUL11_Pos (12U)
# define RCC_CFGR2_PLL3MUL11_Msk (0x9U << RCC_CFGR2_PLL3MUL11_Pos) /*!< 0x00009000 */
# define RCC_CFGR2_PLL3MUL11 RCC_CFGR2_PLL3MUL11_Msk /*!< PLL3 input clock * 11 */
# define RCC_CFGR2_PLL3MUL12_Pos (13U)
# define RCC_CFGR2_PLL3MUL12_Msk (0x5U << RCC_CFGR2_PLL3MUL12_Pos) /*!< 0x0000A000 */
# define RCC_CFGR2_PLL3MUL12 RCC_CFGR2_PLL3MUL12_Msk /*!< PLL3 input clock * 12 */
# define RCC_CFGR2_PLL3MUL13_Pos (12U)
# define RCC_CFGR2_PLL3MUL13_Msk (0xBU << RCC_CFGR2_PLL3MUL13_Pos) /*!< 0x0000B000 */
# define RCC_CFGR2_PLL3MUL13 RCC_CFGR2_PLL3MUL13_Msk /*!< PLL3 input clock * 13 */
# define RCC_CFGR2_PLL3MUL14_Pos (14U)
# define RCC_CFGR2_PLL3MUL14_Msk (0x3U << RCC_CFGR2_PLL3MUL14_Pos) /*!< 0x0000C000 */
# define RCC_CFGR2_PLL3MUL14 RCC_CFGR2_PLL3MUL14_Msk /*!< PLL3 input clock * 14 */
# define RCC_CFGR2_PLL3MUL16_Pos (13U)
# define RCC_CFGR2_PLL3MUL16_Msk (0x7U << RCC_CFGR2_PLL3MUL16_Pos) /*!< 0x0000E000 */
# define RCC_CFGR2_PLL3MUL16 RCC_CFGR2_PLL3MUL16_Msk /*!< PLL3 input clock * 16 */
# define RCC_CFGR2_PLL3MUL20_Pos (12U)
# define RCC_CFGR2_PLL3MUL20_Msk (0xFU << RCC_CFGR2_PLL3MUL20_Pos) /*!< 0x0000F000 */
# define RCC_CFGR2_PLL3MUL20 RCC_CFGR2_PLL3MUL20_Msk /*!< PLL3 input clock * 20 */
# define RCC_CFGR2_PREDIV1SRC_Pos (16U)
# define RCC_CFGR2_PREDIV1SRC_Msk (0x1U << RCC_CFGR2_PREDIV1SRC_Pos) /*!< 0x00010000 */
# define RCC_CFGR2_PREDIV1SRC RCC_CFGR2_PREDIV1SRC_Msk /*!< PREDIV1 entry clock source */
# define RCC_CFGR2_PREDIV1SRC_PLL2_Pos (16U)
# define RCC_CFGR2_PREDIV1SRC_PLL2_Msk (0x1U << RCC_CFGR2_PREDIV1SRC_PLL2_Pos) /*!< 0x00010000 */
# define RCC_CFGR2_PREDIV1SRC_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2_Msk /*!< PLL2 selected as PREDIV1 entry clock source */
# define RCC_CFGR2_PREDIV1SRC_HSE 0x00000000U /*!< HSE selected as PREDIV1 entry clock source */
# define RCC_CFGR2_I2S2SRC_Pos (17U)
# define RCC_CFGR2_I2S2SRC_Msk (0x1U << RCC_CFGR2_I2S2SRC_Pos) /*!< 0x00020000 */
# define RCC_CFGR2_I2S2SRC RCC_CFGR2_I2S2SRC_Msk /*!< I2S2 entry clock source */
# define RCC_CFGR2_I2S3SRC_Pos (18U)
# define RCC_CFGR2_I2S3SRC_Msk (0x1U << RCC_CFGR2_I2S3SRC_Pos) /*!< 0x00040000 */
# define RCC_CFGR2_I2S3SRC RCC_CFGR2_I2S3SRC_Msk /*!< I2S3 clock source */
/******************************************************************************/
/* */
/* General Purpose and Alternate Function I/O */
/* */
/******************************************************************************/
2021-03-22 06:19:35 -07:00
/******************* Bit definition for GPIO_CTL0 register *******************/
# define GPIO_CTL0_MODE_Pos (0U)
# define GPIO_CTL0_MODE_Msk (0x33333333U << GPIO_CTL0_MODE_Pos) /*!< 0x33333333 */
# define GPIO_CTL0_MODE GPIO_CTL0_MODE_Msk /*!< Port x mode bits */
# define GPIO_CTL0_MD0_Pos (0U)
# define GPIO_CTL0_MD0_Msk (0x3U << GPIO_CTL0_MD0_Pos) /*!< 0x00000003 */
# define GPIO_CTL0_MD0 GPIO_CTL0_MD0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
# define GPIO_CTL0_MD0_0 (0x1U << GPIO_CTL0_MD0_Pos) /*!< 0x00000001 */
# define GPIO_CTL0_MD0_1 (0x2U << GPIO_CTL0_MD0_Pos) /*!< 0x00000002 */
# define GPIO_CTL0_MD1_Pos (4U)
# define GPIO_CTL0_MD1_Msk (0x3U << GPIO_CTL0_MD1_Pos) /*!< 0x00000030 */
# define GPIO_CTL0_MD1 GPIO_CTL0_MD1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
# define GPIO_CTL0_MD1_0 (0x1U << GPIO_CTL0_MD1_Pos) /*!< 0x00000010 */
# define GPIO_CTL0_MD1_1 (0x2U << GPIO_CTL0_MD1_Pos) /*!< 0x00000020 */
# define GPIO_CTL0_MD2_Pos (8U)
# define GPIO_CTL0_MD2_Msk (0x3U << GPIO_CTL0_MD2_Pos) /*!< 0x00000300 */
# define GPIO_CTL0_MD2 GPIO_CTL0_MD2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
# define GPIO_CTL0_MD2_0 (0x1U << GPIO_CTL0_MD2_Pos) /*!< 0x00000100 */
# define GPIO_CTL0_MD2_1 (0x2U << GPIO_CTL0_MD2_Pos) /*!< 0x00000200 */
# define GPIO_CTL0_MD3_Pos (12U)
# define GPIO_CTL0_MD3_Msk (0x3U << GPIO_CTL0_MD3_Pos) /*!< 0x00003000 */
# define GPIO_CTL0_MD3 GPIO_CTL0_MD3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
# define GPIO_CTL0_MD3_0 (0x1U << GPIO_CTL0_MD3_Pos) /*!< 0x00001000 */
# define GPIO_CTL0_MD3_1 (0x2U << GPIO_CTL0_MD3_Pos) /*!< 0x00002000 */
# define GPIO_CTL0_MD4_Pos (16U)
# define GPIO_CTL0_MD4_Msk (0x3U << GPIO_CTL0_MD4_Pos) /*!< 0x00030000 */
# define GPIO_CTL0_MD4 GPIO_CTL0_MD4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
# define GPIO_CTL0_MD4_0 (0x1U << GPIO_CTL0_MD4_Pos) /*!< 0x00010000 */
# define GPIO_CTL0_MD4_1 (0x2U << GPIO_CTL0_MD4_Pos) /*!< 0x00020000 */
# define GPIO_CTL0_MD5_Pos (20U)
# define GPIO_CTL0_MD5_Msk (0x3U << GPIO_CTL0_MD5_Pos) /*!< 0x00300000 */
# define GPIO_CTL0_MD5 GPIO_CTL0_MD5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
# define GPIO_CTL0_MD5_0 (0x1U << GPIO_CTL0_MD5_Pos) /*!< 0x00100000 */
# define GPIO_CTL0_MD5_1 (0x2U << GPIO_CTL0_MD5_Pos) /*!< 0x00200000 */
# define GPIO_CTL0_MD6_Pos (24U)
# define GPIO_CTL0_MD6_Msk (0x3U << GPIO_CTL0_MD6_Pos) /*!< 0x03000000 */
# define GPIO_CTL0_MD6 GPIO_CTL0_MD6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
# define GPIO_CTL0_MD6_0 (0x1U << GPIO_CTL0_MD6_Pos) /*!< 0x01000000 */
# define GPIO_CTL0_MD6_1 (0x2U << GPIO_CTL0_MD6_Pos) /*!< 0x02000000 */
# define GPIO_CTL0_MD7_Pos (28U)
# define GPIO_CTL0_MD7_Msk (0x3U << GPIO_CTL0_MD7_Pos) /*!< 0x30000000 */
# define GPIO_CTL0_MD7 GPIO_CTL0_MD7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
# define GPIO_CTL0_MD7_0 (0x1U << GPIO_CTL0_MD7_Pos) /*!< 0x10000000 */
# define GPIO_CTL0_MD7_1 (0x2U << GPIO_CTL0_MD7_Pos) /*!< 0x20000000 */
# define GPIO_CTL0_CTL_Pos (2U)
# define GPIO_CTL0_CTL_Msk (0x33333333U << GPIO_CTL0_CTL_Pos) /*!< 0xCCCCCCCC */
# define GPIO_CTL0_CTL GPIO_CTL0_CTL_Msk /*!< Port x configuration bits */
# define GPIO_CTL0_CTL0_Pos (2U)
# define GPIO_CTL0_CTL0_Msk (0x3U << GPIO_CTL0_CTL0_Pos) /*!< 0x0000000C */
# define GPIO_CTL0_CTL0 GPIO_CTL0_CTL0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
# define GPIO_CTL0_CTL0_0 (0x1U << GPIO_CTL0_CTL0_Pos) /*!< 0x00000004 */
# define GPIO_CTL0_CTL0_1 (0x2U << GPIO_CTL0_CTL0_Pos) /*!< 0x00000008 */
# define GPIO_CTL0_CTL1_Pos (6U)
# define GPIO_CTL0_CTL1_Msk (0x3U << GPIO_CTL0_CTL1_Pos) /*!< 0x000000C0 */
# define GPIO_CTL0_CTL1 GPIO_CTL0_CTL1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
# define GPIO_CTL0_CTL1_0 (0x1U << GPIO_CTL0_CTL1_Pos) /*!< 0x00000040 */
# define GPIO_CTL0_CTL1_1 (0x2U << GPIO_CTL0_CTL1_Pos) /*!< 0x00000080 */
# define GPIO_CTL0_CTL2_Pos (10U)
# define GPIO_CTL0_CTL2_Msk (0x3U << GPIO_CTL0_CTL2_Pos) /*!< 0x00000C00 */
# define GPIO_CTL0_CTL2 GPIO_CTL0_CTL2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
# define GPIO_CTL0_CTL2_0 (0x1U << GPIO_CTL0_CTL2_Pos) /*!< 0x00000400 */
# define GPIO_CTL0_CTL2_1 (0x2U << GPIO_CTL0_CTL2_Pos) /*!< 0x00000800 */
# define GPIO_CTL0_CTL3_Pos (14U)
# define GPIO_CTL0_CTL3_Msk (0x3U << GPIO_CTL0_CTL3_Pos) /*!< 0x0000C000 */
# define GPIO_CTL0_CTL3 GPIO_CTL0_CTL3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
# define GPIO_CTL0_CTL3_0 (0x1U << GPIO_CTL0_CTL3_Pos) /*!< 0x00004000 */
# define GPIO_CTL0_CTL3_1 (0x2U << GPIO_CTL0_CTL3_Pos) /*!< 0x00008000 */
# define GPIO_CTL0_CTL4_Pos (18U)
# define GPIO_CTL0_CTL4_Msk (0x3U << GPIO_CTL0_CTL4_Pos) /*!< 0x000C0000 */
# define GPIO_CTL0_CTL4 GPIO_CTL0_CTL4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
# define GPIO_CTL0_CTL4_0 (0x1U << GPIO_CTL0_CTL4_Pos) /*!< 0x00040000 */
# define GPIO_CTL0_CTL4_1 (0x2U << GPIO_CTL0_CTL4_Pos) /*!< 0x00080000 */
# define GPIO_CTL0_CTL5_Pos (22U)
# define GPIO_CTL0_CTL5_Msk (0x3U << GPIO_CTL0_CTL5_Pos) /*!< 0x00C00000 */
# define GPIO_CTL0_CTL5 GPIO_CTL0_CTL5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
# define GPIO_CTL0_CTL5_0 (0x1U << GPIO_CTL0_CTL5_Pos) /*!< 0x00400000 */
# define GPIO_CTL0_CTL5_1 (0x2U << GPIO_CTL0_CTL5_Pos) /*!< 0x00800000 */
# define GPIO_CTL0_CTL6_Pos (26U)
# define GPIO_CTL0_CTL6_Msk (0x3U << GPIO_CTL0_CTL6_Pos) /*!< 0x0C000000 */
# define GPIO_CTL0_CTL6 GPIO_CTL0_CTL6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
# define GPIO_CTL0_CTL6_0 (0x1U << GPIO_CTL0_CTL6_Pos) /*!< 0x04000000 */
# define GPIO_CTL0_CTL6_1 (0x2U << GPIO_CTL0_CTL6_Pos) /*!< 0x08000000 */
# define GPIO_CTL0_CTL7_Pos (30U)
# define GPIO_CTL0_CTL7_Msk (0x3U << GPIO_CTL0_CTL7_Pos) /*!< 0xC0000000 */
# define GPIO_CTL0_CTL7 GPIO_CTL0_CTL7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
# define GPIO_CTL0_CTL7_0 (0x1U << GPIO_CTL0_CTL7_Pos) /*!< 0x40000000 */
# define GPIO_CTL0_CTL7_1 (0x2U << GPIO_CTL0_CTL7_Pos) /*!< 0x80000000 */
/******************* Bit definition for GPIO_CTL1 register *******************/
# define GPIO_CTL1_MD_Pos (0U)
# define GPIO_CTL1_MD_Msk (0x33333333U << GPIO_CTL1_MD_Pos) /*!< 0x33333333 */
# define GPIO_CTL1_MD GPIO_CTL1_MD_Msk /*!< Port x mode bits */
# define GPIO_CTL1_MD8_Pos (0U)
# define GPIO_CTL1_MD8_Msk (0x3U << GPIO_CTL1_MD8_Pos) /*!< 0x00000003 */
# define GPIO_CTL1_MD8 GPIO_CTL1_MD8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
# define GPIO_CTL1_MD8_0 (0x1U << GPIO_CTL1_MD8_Pos) /*!< 0x00000001 */
# define GPIO_CTL1_MD8_1 (0x2U << GPIO_CTL1_MD8_Pos) /*!< 0x00000002 */
# define GPIO_CTL1_MD9_Pos (4U)
# define GPIO_CTL1_MD9_Msk (0x3U << GPIO_CTL1_MD9_Pos) /*!< 0x00000030 */
# define GPIO_CTL1_MD9 GPIO_CTL1_MD9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
# define GPIO_CTL1_MD9_0 (0x1U << GPIO_CTL1_MD9_Pos) /*!< 0x00000010 */
# define GPIO_CTL1_MD9_1 (0x2U << GPIO_CTL1_MD9_Pos) /*!< 0x00000020 */
# define GPIO_CTL1_MD10_Pos (8U)
# define GPIO_CTL1_MD10_Msk (0x3U << GPIO_CTL1_MD10_Pos) /*!< 0x00000300 */
# define GPIO_CTL1_MD10 GPIO_CTL1_MD10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
# define GPIO_CTL1_MD10_0 (0x1U << GPIO_CTL1_MD10_Pos) /*!< 0x00000100 */
# define GPIO_CTL1_MD10_1 (0x2U << GPIO_CTL1_MD10_Pos) /*!< 0x00000200 */
# define GPIO_CTL1_MD11_Pos (12U)
# define GPIO_CTL1_MD11_Msk (0x3U << GPIO_CTL1_MD11_Pos) /*!< 0x00003000 */
# define GPIO_CTL1_MD11 GPIO_CTL1_MD11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
# define GPIO_CTL1_MD11_0 (0x1U << GPIO_CTL1_MD11_Pos) /*!< 0x00001000 */
# define GPIO_CTL1_MD11_1 (0x2U << GPIO_CTL1_MD11_Pos) /*!< 0x00002000 */
# define GPIO_CTL1_MD12_Pos (16U)
# define GPIO_CTL1_MD12_Msk (0x3U << GPIO_CTL1_MD12_Pos) /*!< 0x00030000 */
# define GPIO_CTL1_MD12 GPIO_CTL1_MD12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
# define GPIO_CTL1_MD12_0 (0x1U << GPIO_CTL1_MD12_Pos) /*!< 0x00010000 */
# define GPIO_CTL1_MD12_1 (0x2U << GPIO_CTL1_MD12_Pos) /*!< 0x00020000 */
# define GPIO_CTL1_MD13_Pos (20U)
# define GPIO_CTL1_MD13_Msk (0x3U << GPIO_CTL1_MD13_Pos) /*!< 0x00300000 */
# define GPIO_CTL1_MD13 GPIO_CTL1_MD13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
# define GPIO_CTL1_MD13_0 (0x1U << GPIO_CTL1_MD13_Pos) /*!< 0x00100000 */
# define GPIO_CTL1_MD13_1 (0x2U << GPIO_CTL1_MD13_Pos) /*!< 0x00200000 */
# define GPIO_CTL1_MD14_Pos (24U)
# define GPIO_CTL1_MD14_Msk (0x3U << GPIO_CTL1_MD14_Pos) /*!< 0x03000000 */
# define GPIO_CTL1_MD14 GPIO_CTL1_MD14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
# define GPIO_CTL1_MD14_0 (0x1U << GPIO_CTL1_MD14_Pos) /*!< 0x01000000 */
# define GPIO_CTL1_MD14_1 (0x2U << GPIO_CTL1_MD14_Pos) /*!< 0x02000000 */
# define GPIO_CTL1_MD15_Pos (28U)
# define GPIO_CTL1_MD15_Msk (0x3U << GPIO_CTL1_MD15_Pos) /*!< 0x30000000 */
# define GPIO_CTL1_MD15 GPIO_CTL1_MD15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
# define GPIO_CTL1_MD15_0 (0x1U << GPIO_CTL1_MD15_Pos) /*!< 0x10000000 */
# define GPIO_CTL1_MD15_1 (0x2U << GPIO_CTL1_MD15_Pos) /*!< 0x20000000 */
# define GPIO_CTL1_CNF_Pos (2U)
# define GPIO_CTL1_CNF_Msk (0x33333333U << GPIO_CTL1_CNF_Pos) /*!< 0xCCCCCCCC */
# define GPIO_CTL1_CNF GPIO_CTL1_CNF_Msk /*!< Port x configuration bits */
# define GPIO_CTL1_CTL8_Pos (2U)
# define GPIO_CTL1_CTL8_Msk (0x3U << GPIO_CTL1_CTL8_Pos) /*!< 0x0000000C */
# define GPIO_CTL1_CTL8 GPIO_CTL1_CTL8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
# define GPIO_CTL1_CTL8_0 (0x1U << GPIO_CTL1_CTL8_Pos) /*!< 0x00000004 */
# define GPIO_CTL1_CTL8_1 (0x2U << GPIO_CTL1_CTL8_Pos) /*!< 0x00000008 */
# define GPIO_CTL1_CTL9_Pos (6U)
# define GPIO_CTL1_CTL9_Msk (0x3U << GPIO_CTL1_CTL9_Pos) /*!< 0x000000C0 */
# define GPIO_CTL1_CTL9 GPIO_CTL1_CTL9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
# define GPIO_CTL1_CTL9_0 (0x1U << GPIO_CTL1_CTL9_Pos) /*!< 0x00000040 */
# define GPIO_CTL1_CTL9_1 (0x2U << GPIO_CTL1_CTL9_Pos) /*!< 0x00000080 */
# define GPIO_CTL1_CTL10_Pos (10U)
# define GPIO_CTL1_CTL10_Msk (0x3U << GPIO_CTL1_CTL10_Pos) /*!< 0x00000C00 */
# define GPIO_CTL1_CTL10 GPIO_CTL1_CTL10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
# define GPIO_CTL1_CTL10_0 (0x1U << GPIO_CTL1_CTL10_Pos) /*!< 0x00000400 */
# define GPIO_CTL1_CTL10_1 (0x2U << GPIO_CTL1_CTL10_Pos) /*!< 0x00000800 */
# define GPIO_CTL1_CTL11_Pos (14U)
# define GPIO_CTL1_CTL11_Msk (0x3U << GPIO_CTL1_CTL11_Pos) /*!< 0x0000C000 */
# define GPIO_CTL1_CTL11 GPIO_CTL1_CTL11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
# define GPIO_CTL1_CTL11_0 (0x1U << GPIO_CTL1_CTL11_Pos) /*!< 0x00004000 */
# define GPIO_CTL1_CTL11_1 (0x2U << GPIO_CTL1_CTL11_Pos) /*!< 0x00008000 */
# define GPIO_CTL1_CTL12_Pos (18U)
# define GPIO_CTL1_CTL12_Msk (0x3U << GPIO_CTL1_CTL12_Pos) /*!< 0x000C0000 */
# define GPIO_CTL1_CTL12 GPIO_CTL1_CTL12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
# define GPIO_CTL1_CTL12_0 (0x1U << GPIO_CTL1_CTL12_Pos) /*!< 0x00040000 */
# define GPIO_CTL1_CTL12_1 (0x2U << GPIO_CTL1_CTL12_Pos) /*!< 0x00080000 */
# define GPIO_CTL1_CTL13_Pos (22U)
# define GPIO_CTL1_CTL13_Msk (0x3U << GPIO_CTL1_CTL13_Pos) /*!< 0x00C00000 */
# define GPIO_CTL1_CTL13 GPIO_CTL1_CTL13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
# define GPIO_CTL1_CTL13_0 (0x1U << GPIO_CTL1_CTL13_Pos) /*!< 0x00400000 */
# define GPIO_CTL1_CTL13_1 (0x2U << GPIO_CTL1_CTL13_Pos) /*!< 0x00800000 */
# define GPIO_CTL1_CTL14_Pos (26U)
# define GPIO_CTL1_CTL14_Msk (0x3U << GPIO_CTL1_CTL14_Pos) /*!< 0x0C000000 */
# define GPIO_CTL1_CTL14 GPIO_CTL1_CTL14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
# define GPIO_CTL1_CTL14_0 (0x1U << GPIO_CTL1_CTL14_Pos) /*!< 0x04000000 */
# define GPIO_CTL1_CTL14_1 (0x2U << GPIO_CTL1_CTL14_Pos) /*!< 0x08000000 */
# define GPIO_CTL1_CTL15_Pos (30U)
# define GPIO_CTL1_CTL15_Msk (0x3U << GPIO_CTL1_CTL15_Pos) /*!< 0xC0000000 */
# define GPIO_CTL1_CTL15 GPIO_CTL1_CTL15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
# define GPIO_CTL1_CTL15_0 (0x1U << GPIO_CTL1_CTL15_Pos) /*!< 0x40000000 */
# define GPIO_CTL1_CTL15_1 (0x2U << GPIO_CTL1_CTL15_Pos) /*!< 0x80000000 */
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/*!<****************** Bit definition for GPIO_IDR register *******************/
2021-03-22 06:19:35 -07:00
# define GPIO_ISTAT_ISTAT0_Pos (0U)
# define GPIO_ISTAT_ISTAT0_Msk (0x1U << GPIO_ISTAT_ISTAT0_Pos) /*!< 0x00000001 */
# define GPIO_ISTAT_ISTAT0 GPIO_ISTAT_ISTAT0_Msk /*!< Port input data, bit 0 */
# define GPIO_ISTAT_ISTAT1_Pos (1U)
# define GPIO_ISTAT_ISTAT1_Msk (0x1U << GPIO_ISTAT_ISTAT1_Pos) /*!< 0x00000002 */
# define GPIO_ISTAT_ISTAT1 GPIO_ISTAT_ISTAT1_Msk /*!< Port input data, bit 1 */
# define GPIO_ISTAT_ISTAT2_Pos (2U)
# define GPIO_ISTAT_ISTAT2_Msk (0x1U << GPIO_ISTAT_ISTAT2_Pos) /*!< 0x00000004 */
# define GPIO_ISTAT_ISTAT2 GPIO_ISTAT_ISTAT2_Msk /*!< Port input data, bit 2 */
# define GPIO_ISTAT_ISTAT3_Pos (3U)
# define GPIO_ISTAT_ISTAT3_Msk (0x1U << GPIO_ISTAT_ISTAT3_Pos) /*!< 0x00000008 */
# define GPIO_ISTAT_ISTAT3 GPIO_ISTAT_ISTAT3_Msk /*!< Port input data, bit 3 */
# define GPIO_ISTAT_ISTAT4_Pos (4U)
# define GPIO_ISTAT_ISTAT4_Msk (0x1U << GPIO_ISTAT_ISTAT4_Pos) /*!< 0x00000010 */
# define GPIO_ISTAT_ISTAT4 GPIO_ISTAT_ISTAT4_Msk /*!< Port input data, bit 4 */
# define GPIO_ISTAT_ISTAT5_Pos (5U)
# define GPIO_ISTAT_ISTAT5_Msk (0x1U << GPIO_ISTAT_ISTAT5_Pos) /*!< 0x00000020 */
# define GPIO_ISTAT_ISTAT5 GPIO_ISTAT_ISTAT5_Msk /*!< Port input data, bit 5 */
# define GPIO_ISTAT_ISTAT6_Pos (6U)
# define GPIO_ISTAT_ISTAT6_Msk (0x1U << GPIO_ISTAT_ISTAT6_Pos) /*!< 0x00000040 */
# define GPIO_ISTAT_ISTAT6 GPIO_ISTAT_ISTAT6_Msk /*!< Port input data, bit 6 */
# define GPIO_ISTAT_ISTAT7_Pos (7U)
# define GPIO_ISTAT_ISTAT7_Msk (0x1U << GPIO_ISTAT_ISTAT7_Pos) /*!< 0x00000080 */
# define GPIO_ISTAT_ISTAT7 GPIO_ISTAT_ISTAT7_Msk /*!< Port input data, bit 7 */
# define GPIO_ISTAT_ISTAT8_Pos (8U)
# define GPIO_ISTAT_ISTAT8_Msk (0x1U << GPIO_ISTAT_ISTAT8_Pos) /*!< 0x00000100 */
# define GPIO_ISTAT_ISTAT8 GPIO_ISTAT_ISTAT8_Msk /*!< Port input data, bit 8 */
# define GPIO_ISTAT_ISTAT9_Pos (9U)
# define GPIO_ISTAT_ISTAT9_Msk (0x1U << GPIO_ISTAT_ISTAT9_Pos) /*!< 0x00000200 */
# define GPIO_ISTAT_ISTAT9 GPIO_ISTAT_ISTAT9_Msk /*!< Port input data, bit 9 */
# define GPIO_ISTAT_ISTAT10_Pos (10U)
# define GPIO_ISTAT_ISTAT10_Msk (0x1U << GPIO_ISTAT_ISTAT10_Pos) /*!< 0x00000400 */
# define GPIO_ISTAT_ISTAT10 GPIO_ISTAT_ISTAT10_Msk /*!< Port input data, bit 10 */
# define GPIO_ISTAT_ISTAT11_Pos (11U)
# define GPIO_ISTAT_ISTAT11_Msk (0x1U << GPIO_ISTAT_ISTAT11_Pos) /*!< 0x00000800 */
# define GPIO_ISTAT_ISTAT11 GPIO_ISTAT_ISTAT11_Msk /*!< Port input data, bit 11 */
# define GPIO_ISTAT_ISTAT12_Pos (12U)
# define GPIO_ISTAT_ISTAT12_Msk (0x1U << GPIO_ISTAT_ISTAT12_Pos) /*!< 0x00001000 */
# define GPIO_ISTAT_ISTAT12 GPIO_ISTAT_ISTAT12_Msk /*!< Port input data, bit 12 */
# define GPIO_ISTAT_ISTAT13_Pos (13U)
# define GPIO_ISTAT_ISTAT13_Msk (0x1U << GPIO_ISTAT_ISTAT13_Pos) /*!< 0x00002000 */
# define GPIO_ISTAT_ISTAT13 GPIO_ISTAT_ISTAT13_Msk /*!< Port input data, bit 13 */
# define GPIO_ISTAT_ISTAT14_Pos (14U)
# define GPIO_ISTAT_ISTAT14_Msk (0x1U << GPIO_ISTAT_ISTAT14_Pos) /*!< 0x00004000 */
# define GPIO_ISTAT_ISTAT14 GPIO_ISTAT_ISTAT14_Msk /*!< Port input data, bit 14 */
# define GPIO_ISTAT_ISTAT15_Pos (15U)
# define GPIO_ISTAT_ISTAT15_Msk (0x1U << GPIO_ISTAT_ISTAT15_Pos) /*!< 0x00008000 */
# define GPIO_ISTAT_ISTAT15 GPIO_ISTAT_ISTAT15_Msk /*!< Port input data, bit 15 */
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/******************* Bit definition for GPIO_ODR register *******************/
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# define GPIO_OCTL_OCTL0_Pos (0U)
# define GPIO_OCTL_OCTL0_Msk (0x1U << GPIO_OCTL_OCTL0_Pos) /*!< 0x00000001 */
# define GPIO_OCTL_OCTL0 GPIO_OCTL_OCTL0_Msk /*!< Port output data, bit 0 */
# define GPIO_OCTL_OCTL1_Pos (1U)
# define GPIO_OCTL_OCTL1_Msk (0x1U << GPIO_OCTL_OCTL1_Pos) /*!< 0x00000002 */
# define GPIO_OCTL_OCTL1 GPIO_OCTL_OCTL1_Msk /*!< Port output data, bit 1 */
# define GPIO_OCTL_OCTL2_Pos (2U)
# define GPIO_OCTL_OCTL2_Msk (0x1U << GPIO_OCTL_OCTL2_Pos) /*!< 0x00000004 */
# define GPIO_OCTL_OCTL2 GPIO_OCTL_OCTL2_Msk /*!< Port output data, bit 2 */
# define GPIO_OCTL_OCTL3_Pos (3U)
# define GPIO_OCTL_OCTL3_Msk (0x1U << GPIO_OCTL_OCTL3_Pos) /*!< 0x00000008 */
# define GPIO_OCTL_OCTL3 GPIO_OCTL_OCTL3_Msk /*!< Port output data, bit 3 */
# define GPIO_OCTL_OCTL4_Pos (4U)
# define GPIO_OCTL_OCTL4_Msk (0x1U << GPIO_OCTL_OCTL4_Pos) /*!< 0x00000010 */
# define GPIO_OCTL_OCTL4 GPIO_OCTL_OCTL4_Msk /*!< Port output data, bit 4 */
# define GPIO_OCTL_OCTL5_Pos (5U)
# define GPIO_OCTL_OCTL5_Msk (0x1U << GPIO_OCTL_OCTL5_Pos) /*!< 0x00000020 */
# define GPIO_OCTL_OCTL5 GPIO_OCTL_OCTL5_Msk /*!< Port output data, bit 5 */
# define GPIO_OCTL_OCTL6_Pos (6U)
# define GPIO_OCTL_OCTL6_Msk (0x1U << GPIO_OCTL_OCTL6_Pos) /*!< 0x00000040 */
# define GPIO_OCTL_OCTL6 GPIO_OCTL_OCTL6_Msk /*!< Port output data, bit 6 */
# define GPIO_OCTL_OCTL7_Pos (7U)
# define GPIO_OCTL_OCTL7_Msk (0x1U << GPIO_OCTL_OCTL7_Pos) /*!< 0x00000080 */
# define GPIO_OCTL_OCTL7 GPIO_OCTL_OCTL7_Msk /*!< Port output data, bit 7 */
# define GPIO_OCTL_OCTL8_Pos (8U)
# define GPIO_OCTL_OCTL8_Msk (0x1U << GPIO_OCTL_OCTL8_Pos) /*!< 0x00000100 */
# define GPIO_OCTL_OCTL8 GPIO_OCTL_OCTL8_Msk /*!< Port output data, bit 8 */
# define GPIO_OCTL_OCTL9_Pos (9U)
# define GPIO_OCTL_OCTL9_Msk (0x1U << GPIO_OCTL_OCTL9_Pos) /*!< 0x00000200 */
# define GPIO_OCTL_OCTL9 GPIO_OCTL_OCTL9_Msk /*!< Port output data, bit 9 */
# define GPIO_OCTL_OCTL10_Pos (10U)
# define GPIO_OCTL_OCTL10_Msk (0x1U << GPIO_OCTL_OCTL10_Pos) /*!< 0x00000400 */
# define GPIO_OCTL_OCTL10 GPIO_OCTL_OCTL10_Msk /*!< Port output data, bit 10 */
# define GPIO_OCTL_OCTL11_Pos (11U)
# define GPIO_OCTL_OCTL11_Msk (0x1U << GPIO_OCTL_OCTL11_Pos) /*!< 0x00000800 */
# define GPIO_OCTL_OCTL11 GPIO_OCTL_OCTL11_Msk /*!< Port output data, bit 11 */
# define GPIO_OCTL_OCTL12_Pos (12U)
# define GPIO_OCTL_OCTL12_Msk (0x1U << GPIO_OCTL_OCTL12_Pos) /*!< 0x00001000 */
# define GPIO_OCTL_OCTL12 GPIO_OCTL_OCTL12_Msk /*!< Port output data, bit 12 */
# define GPIO_OCTL_OCTL13_Pos (13U)
# define GPIO_OCTL_OCTL13_Msk (0x1U << GPIO_OCTL_OCTL13_Pos) /*!< 0x00002000 */
# define GPIO_OCTL_OCTL13 GPIO_OCTL_OCTL13_Msk /*!< Port output data, bit 13 */
# define GPIO_OCTL_OCTL14_Pos (14U)
# define GPIO_OCTL_OCTL14_Msk (0x1U << GPIO_OCTL_OCTL14_Pos) /*!< 0x00004000 */
# define GPIO_OCTL_OCTL14 GPIO_OCTL_OCTL14_Msk /*!< Port output data, bit 14 */
# define GPIO_OCTL_OCTL15_Pos (15U)
# define GPIO_OCTL_OCTL15_Msk (0x1U << GPIO_OCTL_OCTL15_Pos) /*!< 0x00008000 */
# define GPIO_OCTL_OCTL15 GPIO_OCTL_OCTL15_Msk /*!< Port output data, bit 15 */
/****************** Bit definition for GPIO_BOP register *******************/
# define GPIO_BOP_BOP0_Pos (0U)
# define GPIO_BOP_BOP0_Msk (0x1U << GPIO_BOP_BOP0_Pos) /*!< 0x00000001 */
# define GPIO_BOP_BOP0 GPIO_BOP_BOP0_Msk /*!< Port x Set bit 0 */
# define GPIO_BOP_BOP1_Pos (1U)
# define GPIO_BOP_BOP1_Msk (0x1U << GPIO_BOP_BOP1_Pos) /*!< 0x00000002 */
# define GPIO_BOP_BOP1 GPIO_BOP_BOP1_Msk /*!< Port x Set bit 1 */
# define GPIO_BOP_BOP2_Pos (2U)
# define GPIO_BOP_BOP2_Msk (0x1U << GPIO_BOP_BOP2_Pos) /*!< 0x00000004 */
# define GPIO_BOP_BOP2 GPIO_BOP_BOP2_Msk /*!< Port x Set bit 2 */
# define GPIO_BOP_BOP3_Pos (3U)
# define GPIO_BOP_BOP3_Msk (0x1U << GPIO_BOP_BOP3_Pos) /*!< 0x00000008 */
# define GPIO_BOP_BOP3 GPIO_BOP_BOP3_Msk /*!< Port x Set bit 3 */
# define GPIO_BOP_BOP4_Pos (4U)
# define GPIO_BOP_BOP4_Msk (0x1U << GPIO_BOP_BOP4_Pos) /*!< 0x00000010 */
# define GPIO_BOP_BOP4 GPIO_BOP_BOP4_Msk /*!< Port x Set bit 4 */
# define GPIO_BOP_BOP5_Pos (5U)
# define GPIO_BOP_BOP5_Msk (0x1U << GPIO_BOP_BOP5_Pos) /*!< 0x00000020 */
# define GPIO_BOP_BOP5 GPIO_BOP_BOP5_Msk /*!< Port x Set bit 5 */
# define GPIO_BOP_BOP6_Pos (6U)
# define GPIO_BOP_BOP6_Msk (0x1U << GPIO_BOP_BOP6_Pos) /*!< 0x00000040 */
# define GPIO_BOP_BOP6 GPIO_BOP_BOP6_Msk /*!< Port x Set bit 6 */
# define GPIO_BOP_BOP7_Pos (7U)
# define GPIO_BOP_BOP7_Msk (0x1U << GPIO_BOP_BOP7_Pos) /*!< 0x00000080 */
# define GPIO_BOP_BOP7 GPIO_BOP_BOP7_Msk /*!< Port x Set bit 7 */
# define GPIO_BOP_BOP8_Pos (8U)
# define GPIO_BOP_BOP8_Msk (0x1U << GPIO_BOP_BOP8_Pos) /*!< 0x00000100 */
# define GPIO_BOP_BOP8 GPIO_BOP_BOP8_Msk /*!< Port x Set bit 8 */
# define GPIO_BOP_BOP9_Pos (9U)
# define GPIO_BOP_BOP9_Msk (0x1U << GPIO_BOP_BOP9_Pos) /*!< 0x00000200 */
# define GPIO_BOP_BOP9 GPIO_BOP_BOP9_Msk /*!< Port x Set bit 9 */
# define GPIO_BOP_BOP10_Pos (10U)
# define GPIO_BOP_BOP10_Msk (0x1U << GPIO_BOP_BOP10_Pos) /*!< 0x00000400 */
# define GPIO_BOP_BOP10 GPIO_BOP_BOP10_Msk /*!< Port x Set bit 10 */
# define GPIO_BOP_BOP11_Pos (11U)
# define GPIO_BOP_BOP11_Msk (0x1U << GPIO_BOP_BOP11_Pos) /*!< 0x00000800 */
# define GPIO_BOP_BOP11 GPIO_BOP_BOP11_Msk /*!< Port x Set bit 11 */
# define GPIO_BOP_BOP12_Pos (12U)
# define GPIO_BOP_BOP12_Msk (0x1U << GPIO_BOP_BOP12_Pos) /*!< 0x00001000 */
# define GPIO_BOP_BOP12 GPIO_BOP_BOP12_Msk /*!< Port x Set bit 12 */
# define GPIO_BOP_BOP13_Pos (13U)
# define GPIO_BOP_BOP13_Msk (0x1U << GPIO_BOP_BOP13_Pos) /*!< 0x00002000 */
# define GPIO_BOP_BOP13 GPIO_BOP_BOP13_Msk /*!< Port x Set bit 13 */
# define GPIO_BOP_BOP14_Pos (14U)
# define GPIO_BOP_BOP14_Msk (0x1U << GPIO_BOP_BOP14_Pos) /*!< 0x00004000 */
# define GPIO_BOP_BOP14 GPIO_BOP_BOP14_Msk /*!< Port x Set bit 14 */
# define GPIO_BOP_BOP15_Pos (15U)
# define GPIO_BOP_BOP15_Msk (0x1U << GPIO_BOP_BOP15_Pos) /*!< 0x00008000 */
# define GPIO_BOP_BOP15 GPIO_BOP_BOP15_Msk /*!< Port x Set bit 15 */
# define GPIO_BOP_CR0_Pos (16U)
# define GPIO_BOP_CR0_Msk (0x1U << GPIO_BOP_CR0_Pos) /*!< 0x00010000 */
# define GPIO_BOP_CR0 GPIO_BOP_CR0_Msk /*!< Port x Reset bit 0 */
# define GPIO_BOP_CR1_Pos (17U)
# define GPIO_BOP_CR1_Msk (0x1U << GPIO_BOP_CR1_Pos) /*!< 0x00020000 */
# define GPIO_BOP_CR1 GPIO_BOP_CR1_Msk /*!< Port x Reset bit 1 */
# define GPIO_BOP_CR2_Pos (18U)
# define GPIO_BOP_CR2_Msk (0x1U << GPIO_BOP_CR2_Pos) /*!< 0x00040000 */
# define GPIO_BOP_CR2 GPIO_BOP_CR2_Msk /*!< Port x Reset bit 2 */
# define GPIO_BOP_CR3_Pos (19U)
# define GPIO_BOP_CR3_Msk (0x1U << GPIO_BOP_CR3_Pos) /*!< 0x00080000 */
# define GPIO_BOP_CR3 GPIO_BOP_CR3_Msk /*!< Port x Reset bit 3 */
# define GPIO_BOP_CR4_Pos (20U)
# define GPIO_BOP_CR4_Msk (0x1U << GPIO_BOP_CR4_Pos) /*!< 0x00100000 */
# define GPIO_BOP_CR4 GPIO_BOP_CR4_Msk /*!< Port x Reset bit 4 */
# define GPIO_BOP_CR5_Pos (21U)
# define GPIO_BOP_CR5_Msk (0x1U << GPIO_BOP_CR5_Pos) /*!< 0x00200000 */
# define GPIO_BOP_CR5 GPIO_BOP_CR5_Msk /*!< Port x Reset bit 5 */
# define GPIO_BOP_CR6_Pos (22U)
# define GPIO_BOP_CR6_Msk (0x1U << GPIO_BOP_CR6_Pos) /*!< 0x00400000 */
# define GPIO_BOP_CR6 GPIO_BOP_CR6_Msk /*!< Port x Reset bit 6 */
# define GPIO_BOP_CR7_Pos (23U)
# define GPIO_BOP_CR7_Msk (0x1U << GPIO_BOP_CR7_Pos) /*!< 0x00800000 */
# define GPIO_BOP_CR7 GPIO_BOP_CR7_Msk /*!< Port x Reset bit 7 */
# define GPIO_BOP_CR8_Pos (24U)
# define GPIO_BOP_CR8_Msk (0x1U << GPIO_BOP_CR8_Pos) /*!< 0x01000000 */
# define GPIO_BOP_CR8 GPIO_BOP_CR8_Msk /*!< Port x Reset bit 8 */
# define GPIO_BOP_CR9_Pos (25U)
# define GPIO_BOP_CR9_Msk (0x1U << GPIO_BOP_CR9_Pos) /*!< 0x02000000 */
# define GPIO_BOP_CR9 GPIO_BOP_CR9_Msk /*!< Port x Reset bit 9 */
# define GPIO_BOP_CR10_Pos (26U)
# define GPIO_BOP_CR10_Msk (0x1U << GPIO_BOP_CR10_Pos) /*!< 0x04000000 */
# define GPIO_BOP_CR10 GPIO_BOP_CR10_Msk /*!< Port x Reset bit 10 */
# define GPIO_BOP_CR11_Pos (27U)
# define GPIO_BOP_CR11_Msk (0x1U << GPIO_BOP_CR11_Pos) /*!< 0x08000000 */
# define GPIO_BOP_CR11 GPIO_BOP_CR11_Msk /*!< Port x Reset bit 11 */
# define GPIO_BOP_CR12_Pos (28U)
# define GPIO_BOP_CR12_Msk (0x1U << GPIO_BOP_CR12_Pos) /*!< 0x10000000 */
# define GPIO_BOP_CR12 GPIO_BOP_CR12_Msk /*!< Port x Reset bit 12 */
# define GPIO_BOP_CR13_Pos (29U)
# define GPIO_BOP_CR13_Msk (0x1U << GPIO_BOP_CR13_Pos) /*!< 0x20000000 */
# define GPIO_BOP_CR13 GPIO_BOP_CR13_Msk /*!< Port x Reset bit 13 */
# define GPIO_BOP_CR14_Pos (30U)
# define GPIO_BOP_CR14_Msk (0x1U << GPIO_BOP_CR14_Pos) /*!< 0x40000000 */
# define GPIO_BOP_CR14 GPIO_BOP_CR14_Msk /*!< Port x Reset bit 14 */
# define GPIO_BOP_CR15_Pos (31U)
# define GPIO_BOP_CR15_Msk (0x1U << GPIO_BOP_CR15_Pos) /*!< 0x80000000 */
# define GPIO_BOP_CR15 GPIO_BOP_CR15_Msk /*!< Port x Reset bit 15 */
/******************* Bit definition for GPIO_BC register *******************/
# define GPIO_BC_CR0_Pos (0U)
# define GPIO_BC_CR0_Msk (0x1U << GPIO_BC_CR0_Pos) /*!< 0x00000001 */
# define GPIO_BC_CR0 GPIO_BC_CR0_Msk /*!< Port x Reset bit 0 */
# define GPIO_BC_CR1_Pos (1U)
# define GPIO_BC_CR1_Msk (0x1U << GPIO_BC_CR1_Pos) /*!< 0x00000002 */
# define GPIO_BC_CR1 GPIO_BC_CR1_Msk /*!< Port x Reset bit 1 */
# define GPIO_BC_CR2_Pos (2U)
# define GPIO_BC_CR2_Msk (0x1U << GPIO_BC_CR2_Pos) /*!< 0x00000004 */
# define GPIO_BC_CR2 GPIO_BC_CR2_Msk /*!< Port x Reset bit 2 */
# define GPIO_BC_CR3_Pos (3U)
# define GPIO_BC_CR3_Msk (0x1U << GPIO_BC_CR3_Pos) /*!< 0x00000008 */
# define GPIO_BC_CR3 GPIO_BC_CR3_Msk /*!< Port x Reset bit 3 */
# define GPIO_BC_CR4_Pos (4U)
# define GPIO_BC_CR4_Msk (0x1U << GPIO_BC_CR4_Pos) /*!< 0x00000010 */
# define GPIO_BC_CR4 GPIO_BC_CR4_Msk /*!< Port x Reset bit 4 */
# define GPIO_BC_CR5_Pos (5U)
# define GPIO_BC_CR5_Msk (0x1U << GPIO_BC_CR5_Pos) /*!< 0x00000020 */
# define GPIO_BC_CR5 GPIO_BC_CR5_Msk /*!< Port x Reset bit 5 */
# define GPIO_BC_CR6_Pos (6U)
# define GPIO_BC_CR6_Msk (0x1U << GPIO_BC_CR6_Pos) /*!< 0x00000040 */
# define GPIO_BC_CR6 GPIO_BC_CR6_Msk /*!< Port x Reset bit 6 */
# define GPIO_BC_CR7_Pos (7U)
# define GPIO_BC_CR7_Msk (0x1U << GPIO_BC_CR7_Pos) /*!< 0x00000080 */
# define GPIO_BC_CR7 GPIO_BC_CR7_Msk /*!< Port x Reset bit 7 */
# define GPIO_BC_CR8_Pos (8U)
# define GPIO_BC_CR8_Msk (0x1U << GPIO_BC_CR8_Pos) /*!< 0x00000100 */
# define GPIO_BC_CR8 GPIO_BC_CR8_Msk /*!< Port x Reset bit 8 */
# define GPIO_BC_CR9_Pos (9U)
# define GPIO_BC_CR9_Msk (0x1U << GPIO_BC_CR9_Pos) /*!< 0x00000200 */
# define GPIO_BC_CR9 GPIO_BC_CR9_Msk /*!< Port x Reset bit 9 */
# define GPIO_BC_CR10_Pos (10U)
# define GPIO_BC_CR10_Msk (0x1U << GPIO_BC_CR10_Pos) /*!< 0x00000400 */
# define GPIO_BC_CR10 GPIO_BC_CR10_Msk /*!< Port x Reset bit 10 */
# define GPIO_BC_CR11_Pos (11U)
# define GPIO_BC_CR11_Msk (0x1U << GPIO_BC_CR11_Pos) /*!< 0x00000800 */
# define GPIO_BC_CR11 GPIO_BC_CR11_Msk /*!< Port x Reset bit 11 */
# define GPIO_BC_CR12_Pos (12U)
# define GPIO_BC_CR12_Msk (0x1U << GPIO_BC_CR12_Pos) /*!< 0x00001000 */
# define GPIO_BC_CR12 GPIO_BC_CR12_Msk /*!< Port x Reset bit 12 */
# define GPIO_BC_CR13_Pos (13U)
# define GPIO_BC_CR13_Msk (0x1U << GPIO_BC_CR13_Pos) /*!< 0x00002000 */
# define GPIO_BC_CR13 GPIO_BC_CR13_Msk /*!< Port x Reset bit 13 */
# define GPIO_BC_CR14_Pos (14U)
# define GPIO_BC_CR14_Msk (0x1U << GPIO_BC_CR14_Pos) /*!< 0x00004000 */
# define GPIO_BC_CR14 GPIO_BC_CR14_Msk /*!< Port x Reset bit 14 */
# define GPIO_BC_CR15_Pos (15U)
# define GPIO_BC_CR15_Msk (0x1U << GPIO_BC_CR15_Pos) /*!< 0x00008000 */
# define GPIO_BC_CR15 GPIO_BC_CR15_Msk /*!< Port x Reset bit 15 */
/****************** Bit definition for GPIO_LOCK register *******************/
# define GPIO_LOCK_LK0_Pos (0U)
# define GPIO_LOCK_LK0_Msk (0x1U << GPIO_LOCK_LK0_Pos) /*!< 0x00000001 */
# define GPIO_LOCK_LK0 GPIO_LOCK_LK0_Msk /*!< Port x Lock bit 0 */
# define GPIO_LOCK_LK1_Pos (1U)
# define GPIO_LOCK_LK1_Msk (0x1U << GPIO_LOCK_LK1_Pos) /*!< 0x00000002 */
# define GPIO_LOCK_LK1 GPIO_LOCK_LK1_Msk /*!< Port x Lock bit 1 */
# define GPIO_LOCK_LK2_Pos (2U)
# define GPIO_LOCK_LK2_Msk (0x1U << GPIO_LOCK_LK2_Pos) /*!< 0x00000004 */
# define GPIO_LOCK_LK2 GPIO_LOCK_LK2_Msk /*!< Port x Lock bit 2 */
# define GPIO_LOCK_LK3_Pos (3U)
# define GPIO_LOCK_LK3_Msk (0x1U << GPIO_LOCK_LK3_Pos) /*!< 0x00000008 */
# define GPIO_LOCK_LK3 GPIO_LOCK_LK3_Msk /*!< Port x Lock bit 3 */
# define GPIO_LOCK_LK4_Pos (4U)
# define GPIO_LOCK_LK4_Msk (0x1U << GPIO_LOCK_LK4_Pos) /*!< 0x00000010 */
# define GPIO_LOCK_LK4 GPIO_LOCK_LK4_Msk /*!< Port x Lock bit 4 */
# define GPIO_LOCK_LK5_Pos (5U)
# define GPIO_LOCK_LK5_Msk (0x1U << GPIO_LOCK_LK5_Pos) /*!< 0x00000020 */
# define GPIO_LOCK_LK5 GPIO_LOCK_LK5_Msk /*!< Port x Lock bit 5 */
# define GPIO_LOCK_LK6_Pos (6U)
# define GPIO_LOCK_LK6_Msk (0x1U << GPIO_LOCK_LK6_Pos) /*!< 0x00000040 */
# define GPIO_LOCK_LK6 GPIO_LOCK_LK6_Msk /*!< Port x Lock bit 6 */
# define GPIO_LOCK_LK7_Pos (7U)
# define GPIO_LOCK_LK7_Msk (0x1U << GPIO_LOCK_LK7_Pos) /*!< 0x00000080 */
# define GPIO_LOCK_LK7 GPIO_LOCK_LK7_Msk /*!< Port x Lock bit 7 */
# define GPIO_LOCK_LK8_Pos (8U)
# define GPIO_LOCK_LK8_Msk (0x1U << GPIO_LOCK_LK8_Pos) /*!< 0x00000100 */
# define GPIO_LOCK_LK8 GPIO_LOCK_LK8_Msk /*!< Port x Lock bit 8 */
# define GPIO_LOCK_LK9_Pos (9U)
# define GPIO_LOCK_LK9_Msk (0x1U << GPIO_LOCK_LK9_Pos) /*!< 0x00000200 */
# define GPIO_LOCK_LK9 GPIO_LOCK_LK9_Msk /*!< Port x Lock bit 9 */
# define GPIO_LOCK_LK10_Pos (10U)
# define GPIO_LOCK_LK10_Msk (0x1U << GPIO_LOCK_LK10_Pos) /*!< 0x00000400 */
# define GPIO_LOCK_LK10 GPIO_LOCK_LK10_Msk /*!< Port x Lock bit 10 */
# define GPIO_LOCK_LK11_Pos (11U)
# define GPIO_LOCK_LK11_Msk (0x1U << GPIO_LOCK_LK11_Pos) /*!< 0x00000800 */
# define GPIO_LOCK_LK11 GPIO_LOCK_LK11_Msk /*!< Port x Lock bit 11 */
# define GPIO_LOCK_LK12_Pos (12U)
# define GPIO_LOCK_LK12_Msk (0x1U << GPIO_LOCK_LK12_Pos) /*!< 0x00001000 */
# define GPIO_LOCK_LK12 GPIO_LOCK_LK12_Msk /*!< Port x Lock bit 12 */
# define GPIO_LOCK_LK13_Pos (13U)
# define GPIO_LOCK_LK13_Msk (0x1U << GPIO_LOCK_LK13_Pos) /*!< 0x00002000 */
# define GPIO_LOCK_LK13 GPIO_LOCK_LK13_Msk /*!< Port x Lock bit 13 */
# define GPIO_LOCK_LK14_Pos (14U)
# define GPIO_LOCK_LK14_Msk (0x1U << GPIO_LOCK_LK14_Pos) /*!< 0x00004000 */
# define GPIO_LOCK_LK14 GPIO_LOCK_LK14_Msk /*!< Port x Lock bit 14 */
# define GPIO_LOCK_LK15_Pos (15U)
# define GPIO_LOCK_LK15_Msk (0x1U << GPIO_LOCK_LK15_Pos) /*!< 0x00008000 */
# define GPIO_LOCK_LK15 GPIO_LOCK_LK15_Msk /*!< Port x Lock bit 15 */
# define GPIO_LOCK_LKK_Pos (16U)
# define GPIO_LOCK_LKK_Msk (0x1U << GPIO_LOCK_LKK_Pos) /*!< 0x00010000 */
# define GPIO_LOCK_LKK GPIO_LOCK_LKK_Msk /*!< Lock key */
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/*----------------------------------------------------------------------------*/
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/****************** Bit definition for AFIO_EC register *******************/
# define AFIO_EC_PIN_Pos (0U)
# define AFIO_EC_PIN_Msk (0xFU << AFIO_EC_PIN_Pos) /*!< 0x0000000F */
# define AFIO_EC_PIN AFIO_EC_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */
# define AFIO_EC_PIN_0 (0x1U << AFIO_EC_PIN_Pos) /*!< 0x00000001 */
# define AFIO_EC_PIN_1 (0x2U << AFIO_EC_PIN_Pos) /*!< 0x00000002 */
# define AFIO_EC_PIN_2 (0x4U << AFIO_EC_PIN_Pos) /*!< 0x00000004 */
# define AFIO_EC_PIN_3 (0x8U << AFIO_EC_PIN_Pos) /*!< 0x00000008 */
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/*!< PIN configuration */
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# define AFIO_EC_PIN_PX0 0x00000000U /*!< Pin 0 selected */
# define AFIO_EC_PIN_PX1_Pos (0U)
# define AFIO_EC_PIN_PX1_Msk (0x1U << AFIO_EC_PIN_PX1_Pos) /*!< 0x00000001 */
# define AFIO_EC_PIN_PX1 AFIO_EC_PIN_PX1_Msk /*!< Pin 1 selected */
# define AFIO_EC_PIN_PX2_Pos (1U)
# define AFIO_EC_PIN_PX2_Msk (0x1U << AFIO_EC_PIN_PX2_Pos) /*!< 0x00000002 */
# define AFIO_EC_PIN_PX2 AFIO_EC_PIN_PX2_Msk /*!< Pin 2 selected */
# define AFIO_EC_PIN_PX3_Pos (0U)
# define AFIO_EC_PIN_PX3_Msk (0x3U << AFIO_EC_PIN_PX3_Pos) /*!< 0x00000003 */
# define AFIO_EC_PIN_PX3 AFIO_EC_PIN_PX3_Msk /*!< Pin 3 selected */
# define AFIO_EC_PIN_PX4_Pos (2U)
# define AFIO_EC_PIN_PX4_Msk (0x1U << AFIO_EC_PIN_PX4_Pos) /*!< 0x00000004 */
# define AFIO_EC_PIN_PX4 AFIO_EC_PIN_PX4_Msk /*!< Pin 4 selected */
# define AFIO_EC_PIN_PX5_Pos (0U)
# define AFIO_EC_PIN_PX5_Msk (0x5U << AFIO_EC_PIN_PX5_Pos) /*!< 0x00000005 */
# define AFIO_EC_PIN_PX5 AFIO_EC_PIN_PX5_Msk /*!< Pin 5 selected */
# define AFIO_EC_PIN_PX6_Pos (1U)
# define AFIO_EC_PIN_PX6_Msk (0x3U << AFIO_EC_PIN_PX6_Pos) /*!< 0x00000006 */
# define AFIO_EC_PIN_PX6 AFIO_EC_PIN_PX6_Msk /*!< Pin 6 selected */
# define AFIO_EC_PIN_PX7_Pos (0U)
# define AFIO_EC_PIN_PX7_Msk (0x7U << AFIO_EC_PIN_PX7_Pos) /*!< 0x00000007 */
# define AFIO_EC_PIN_PX7 AFIO_EC_PIN_PX7_Msk /*!< Pin 7 selected */
# define AFIO_EC_PIN_PX8_Pos (3U)
# define AFIO_EC_PIN_PX8_Msk (0x1U << AFIO_EC_PIN_PX8_Pos) /*!< 0x00000008 */
# define AFIO_EC_PIN_PX8 AFIO_EC_PIN_PX8_Msk /*!< Pin 8 selected */
# define AFIO_EC_PIN_PX9_Pos (0U)
# define AFIO_EC_PIN_PX9_Msk (0x9U << AFIO_EC_PIN_PX9_Pos) /*!< 0x00000009 */
# define AFIO_EC_PIN_PX9 AFIO_EC_PIN_PX9_Msk /*!< Pin 9 selected */
# define AFIO_EC_PIN_PX10_Pos (1U)
# define AFIO_EC_PIN_PX10_Msk (0x5U << AFIO_EC_PIN_PX10_Pos) /*!< 0x0000000A */
# define AFIO_EC_PIN_PX10 AFIO_EC_PIN_PX10_Msk /*!< Pin 10 selected */
# define AFIO_EC_PIN_PX11_Pos (0U)
# define AFIO_EC_PIN_PX11_Msk (0xBU << AFIO_EC_PIN_PX11_Pos) /*!< 0x0000000B */
# define AFIO_EC_PIN_PX11 AFIO_EC_PIN_PX11_Msk /*!< Pin 11 selected */
# define AFIO_EC_PIN_PX12_Pos (2U)
# define AFIO_EC_PIN_PX12_Msk (0x3U << AFIO_EC_PIN_PX12_Pos) /*!< 0x0000000C */
# define AFIO_EC_PIN_PX12 AFIO_EC_PIN_PX12_Msk /*!< Pin 12 selected */
# define AFIO_EC_PIN_PX13_Pos (0U)
# define AFIO_EC_PIN_PX13_Msk (0xDU << AFIO_EC_PIN_PX13_Pos) /*!< 0x0000000D */
# define AFIO_EC_PIN_PX13 AFIO_EC_PIN_PX13_Msk /*!< Pin 13 selected */
# define AFIO_EC_PIN_PX14_Pos (1U)
# define AFIO_EC_PIN_PX14_Msk (0x7U << AFIO_EC_PIN_PX14_Pos) /*!< 0x0000000E */
# define AFIO_EC_PIN_PX14 AFIO_EC_PIN_PX14_Msk /*!< Pin 14 selected */
# define AFIO_EC_PIN_PX15_Pos (0U)
# define AFIO_EC_PIN_PX15_Msk (0xFU << AFIO_EC_PIN_PX15_Pos) /*!< 0x0000000F */
# define AFIO_EC_PIN_PX15 AFIO_EC_PIN_PX15_Msk /*!< Pin 15 selected */
# define AFIO_EC_PORT_Pos (4U)
# define AFIO_EC_PORT_Msk (0x7U << AFIO_EC_PORT_Pos) /*!< 0x00000070 */
# define AFIO_EC_PORT AFIO_EC_PORT_Msk /*!< PORT[2:0] bits (Port selection) */
# define AFIO_EC_PORT_0 (0x1U << AFIO_EC_PORT_Pos) /*!< 0x00000010 */
# define AFIO_EC_PORT_1 (0x2U << AFIO_EC_PORT_Pos) /*!< 0x00000020 */
# define AFIO_EC_PORT_2 (0x4U << AFIO_EC_PORT_Pos) /*!< 0x00000040 */
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/*!< PORT configuration */
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# define AFIO_EC_PORT_PA 0x00000000 /*!< Port A selected */
# define AFIO_EC_PORT_PB_Pos (4U)
# define AFIO_EC_PORT_PB_Msk (0x1U << AFIO_EC_PORT_PB_Pos) /*!< 0x00000010 */
# define AFIO_EC_PORT_PB AFIO_EC_PORT_PB_Msk /*!< Port B selected */
# define AFIO_EC_PORT_PC_Pos (5U)
# define AFIO_EC_PORT_PC_Msk (0x1U << AFIO_EC_PORT_PC_Pos) /*!< 0x00000020 */
# define AFIO_EC_PORT_PC AFIO_EC_PORT_PC_Msk /*!< Port C selected */
# define AFIO_EC_PORT_PD_Pos (4U)
# define AFIO_EC_PORT_PD_Msk (0x3U << AFIO_EC_PORT_PD_Pos) /*!< 0x00000030 */
# define AFIO_EC_PORT_PD AFIO_EC_PORT_PD_Msk /*!< Port D selected */
# define AFIO_EC_PORT_PE_Pos (6U)
# define AFIO_EC_PORT_PE_Msk (0x1U << AFIO_EC_PORT_PE_Pos) /*!< 0x00000040 */
# define AFIO_EC_PORT_PE AFIO_EC_PORT_PE_Msk /*!< Port E selected */
# define AFIO_EC_EOE_Pos (7U)
# define AFIO_EC_EOE_Msk (0x1U << AFIO_EC_EOE_Pos) /*!< 0x00000080 */
# define AFIO_EC_EOE AFIO_EC_EOE_Msk /*!< Event Output Enable */
/****************** Bit definition for AFIO_PCF0 register *******************/
# define AFIO_PCF0_SPI0_REMAP_Pos (0U)
# define AFIO_PCF0_SPI0_REMAP_Msk (0x1U << AFIO_PCF0_SPI0_REMAP_Pos) /*!< 0x00000001 */
# define AFIO_PCF0_SPI0_REMAP AFIO_PCF0_SPI0_REMAP_Msk /*!< SPI1 remapping */
# define AFIO_PCF0_I2C0_REMAP_Pos (1U)
# define AFIO_PCF0_I2C0_REMAP_Msk (0x1U << AFIO_PCF0_I2C0_REMAP_Pos) /*!< 0x00000002 */
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# define AFIO_PCF0_I2C0_REMAP AFIO_PCF0_I2C0_REMAP_Msk /*!< I2C0 remapping */
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# define AFIO_PCF0_USART0_REMAP_Pos (2U)
# define AFIO_PCF0_USART0_REMAP_Msk (0x1U << AFIO_PCF0_USART0_REMAP_Pos) /*!< 0x00000004 */
# define AFIO_PCF0_USART0_REMAP AFIO_PCF0_USART0_REMAP_Msk /*!< USART1 remapping */
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# define AFIO_PCF0_USART1_REMAP_Pos (3U)
# define AFIO_PCF0_USART1_REMAP_Msk (0x1U << AFIO_PCF0_USART1_REMAP_Pos) /*!< 0x00000008 */
# define AFIO_PCF0_USART1_REMAP AFIO_PCF0_USART1_REMAP_Msk /*!< USART2 remapping */
# define AFIO_PCF0_USART2_REMAP_Pos (4U)
# define AFIO_PCF0_USART2_REMAP_Msk (0x3U << AFIO_PCF0_USART2_REMAP_Pos) /*!< 0x00000030 */
# define AFIO_PCF0_USART2_REMAP AFIO_PCF0_USART2_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
# define AFIO_PCF0_USART2_REMAP_0 (0x1U << AFIO_PCF0_USART2_REMAP_Pos) /*!< 0x00000010 */
# define AFIO_PCF0_USART2_REMAP_1 (0x2U << AFIO_PCF0_USART2_REMAP_Pos) /*!< 0x00000020 */
/* USART3_REMAP configuration */
# define AFIO_PCF0_USART2_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
# define AFIO_PCF0_USART2_REMAP_PARTIALREMAP_Pos (4U)
# define AFIO_PCF0_USART2_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_PCF0_USART2_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
# define AFIO_PCF0_USART2_REMAP_PARTIALREMAP AFIO_PCF0_USART2_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
# define AFIO_PCF0_USART2_REMAP_FULLREMAP_Pos (4U)
# define AFIO_PCF0_USART2_REMAP_FULLREMAP_Msk (0x3U << AFIO_PCF0_USART2_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */
# define AFIO_PCF0_USART2_REMAP_FULLREMAP AFIO_PCF0_USART2_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
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# define AFIO_PCF0_TIMER0_REMAP_Pos (6U)
# define AFIO_PCF0_TIMER0_REMAP_Msk (0x3U << AFIO_PCF0_TIMER0_REMAP_Pos) /*!< 0x000000C0 */
# define AFIO_PCF0_TIMER0_REMAP AFIO_PCF0_TIMER0_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
# define AFIO_PCF0_TIMER0_REMAP_0 (0x1U << AFIO_PCF0_TIMER0_REMAP_Pos) /*!< 0x00000040 */
# define AFIO_PCF0_TIMER0_REMAP_1 (0x2U << AFIO_PCF0_TIMER0_REMAP_Pos) /*!< 0x00000080 */
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/*!< TIM1_REMAP configuration */
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# define AFIO_PCF0_TIMER0_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
# define AFIO_PCF0_TIMER0_REMAP_PARTIALREMAP_Pos (6U)
# define AFIO_PCF0_TIMER0_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_PCF0_TIMER0_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
# define AFIO_PCF0_TIMER0_REMAP_PARTIALREMAP AFIO_PCF0_TIMER0_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
# define AFIO_PCF0_TIMER0_REMAP_FULLREMAP_Pos (6U)
# define AFIO_PCF0_TIMER0_REMAP_FULLREMAP_Msk (0x3U << AFIO_PCF0_TIMER0_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */
# define AFIO_PCF0_TIMER0_REMAP_FULLREMAP AFIO_PCF0_TIMER0_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
# define AFIO_PCF0_TIMER1_REMAP_Pos (8U)
# define AFIO_PCF0_TIMER1_REMAP_Msk (0x3U << AFIO_PCF0_TIMER1_REMAP_Pos) /*!< 0x00000300 */
# define AFIO_PCF0_TIMER1_REMAP AFIO_PCF0_TIMER1_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
# define AFIO_PCF0_TIMER1_REMAP_0 (0x1U << AFIO_PCF0_TIMER1_REMAP_Pos) /*!< 0x00000100 */
# define AFIO_PCF0_TIMER1_REMAP_1 (0x2U << AFIO_PCF0_TIMER1_REMAP_Pos) /*!< 0x00000200 */
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/*!< TIM2_REMAP configuration */
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# define AFIO_PCF0_TIMER1_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
# define AFIO_PCF0_TIMER1_REMAP_PARTIALREMAP1_Pos (8U)
# define AFIO_PCF0_TIMER1_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_PCF0_TIMER1_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
# define AFIO_PCF0_TIMER1_REMAP_PARTIALREMAP1 AFIO_PCF0_TIMER1_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
# define AFIO_PCF0_TIMER1_REMAP_PARTIALREMAP2_Pos (9U)
# define AFIO_PCF0_TIMER1_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_PCF0_TIMER1_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */
# define AFIO_PCF0_TIMER1_REMAP_PARTIALREMAP2 AFIO_PCF0_TIMER1_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
# define AFIO_PCF0_TIMER1_REMAP_FULLREMAP_Pos (8U)
# define AFIO_PCF0_TIMER1_REMAP_FULLREMAP_Msk (0x3U << AFIO_PCF0_TIMER1_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */
# define AFIO_PCF0_TIMER1_REMAP_FULLREMAP AFIO_PCF0_TIMER1_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
# define AFIO_PCF0_TIMER2_REMAP_Pos (10U)
# define AFIO_PCF0_TIMER2_REMAP_Msk (0x3U << AFIO_PCF0_TIMER2_REMAP_Pos) /*!< 0x00000C00 */
# define AFIO_PCF0_TIMER2_REMAP AFIO_PCF0_TIMER2_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
# define AFIO_PCF0_TIMER2_REMAP_0 (0x1U << AFIO_PCF0_TIMER2_REMAP_Pos) /*!< 0x00000400 */
# define AFIO_PCF0_TIMER2_REMAP_1 (0x2U << AFIO_PCF0_TIMER2_REMAP_Pos) /*!< 0x00000800 */
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/*!< TIM3_REMAP configuration */
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# define AFIO_PCF0_TIMER2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
# define AFIO_PCF0_TIMER2_REMAP_PARTIALREMAP_Pos (11U)
# define AFIO_PCF0_TIMER2_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_PCF0_TIMER2_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
# define AFIO_PCF0_TIMER2_REMAP_PARTIALREMAP AFIO_PCF0_TIMER2_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
# define AFIO_PCF0_TIMER2_REMAP_FULLREMAP_Pos (10U)
# define AFIO_PCF0_TIMER2_REMAP_FULLREMAP_Msk (0x3U << AFIO_PCF0_TIMER2_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */
# define AFIO_PCF0_TIMER2_REMAP_FULLREMAP AFIO_PCF0_TIMER2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
# define AFIO_PCF0_TIMER3_REMAP_Pos (12U)
# define AFIO_PCF0_TIMER3_REMAP_Msk (0x1U << AFIO_PCF0_TIMER3_REMAP_Pos) /*!< 0x00001000 */
# define AFIO_PCF0_TIMER3_REMAP AFIO_PCF0_TIMER3_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */
# define AFIO_PCF0_CAN0_REMAP_Pos (13U)
# define AFIO_PCF0_CAN0_REMAP_Msk (0x3U << AFIO_PCF0_CAN0_REMAP_Pos) /*!< 0x00006000 */
# define AFIO_PCF0_CAN0_REMAP AFIO_PCF0_CAN0_REMAP_Msk /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
# define AFIO_PCF0_CAN0_REMAP_0 (0x1U << AFIO_PCF0_CAN0_REMAP_Pos) /*!< 0x00002000 */
# define AFIO_PCF0_CAN0_REMAP_1 (0x2U << AFIO_PCF0_CAN0_REMAP_Pos) /*!< 0x00004000 */
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/*!< CAN_REMAP configuration */
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# define AFIO_PCF0_CAN0_REMAP_REMAP1 0x00000000U /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
# define AFIO_PCF0_CAN0_REMAP_REMAP2_Pos (14U)
# define AFIO_PCF0_CAN0_REMAP_REMAP2_Msk (0x1U << AFIO_PCF0_CAN0_REMAP_REMAP2_Pos) /*!< 0x00004000 */
# define AFIO_PCF0_CAN0_REMAP_REMAP2 AFIO_PCF0_CAN0_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
# define AFIO_PCF0_CAN0_REMAP_REMAP3_Pos (13U)
# define AFIO_PCF0_CAN0_REMAP_REMAP3_Msk (0x3U << AFIO_PCF0_CAN0_REMAP_REMAP3_Pos) /*!< 0x00006000 */
# define AFIO_PCF0_CAN0_REMAP_REMAP3 AFIO_PCF0_CAN0_REMAP_REMAP3_Msk /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
# define AFIO_PCF0_PD01_REMAP_Pos (15U)
# define AFIO_PCF0_PD01_REMAP_Msk (0x1U << AFIO_PCF0_PD01_REMAP_Pos) /*!< 0x00008000 */
# define AFIO_PCF0_PD01_REMAP AFIO_PCF0_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
# define AFIO_PCF0_TIM4CH3_IREMAP_Pos (16U)
# define AFIO_PCF0_TIM4CH3_IREMAP_Msk (0x1U << AFIO_PCF0_TIM4CH3_IREMAP_Pos) /*!< 0x00010000 */
# define AFIO_PCF0_TIM4CH3_IREMAP AFIO_PCF0_TIM4CH3_IREMAP_Msk /*!< TIM5 Channel4 Internal Remap */
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/*!< SWJ_CFG configuration */
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# define AFIO_PCF0_SWJ_CFG_Pos (24U)
# define AFIO_PCF0_SWJ_CFG_Msk (0x7U << AFIO_PCF0_SWJ_CFG_Pos) /*!< 0x07000000 */
# define AFIO_PCF0_SWJ_CFG AFIO_PCF0_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
# define AFIO_PCF0_SWJ_CFG_0 (0x1U << AFIO_PCF0_SWJ_CFG_Pos) /*!< 0x01000000 */
# define AFIO_PCF0_SWJ_CFG_1 (0x2U << AFIO_PCF0_SWJ_CFG_Pos) /*!< 0x02000000 */
# define AFIO_PCF0_SWJ_CFG_2 (0x4U << AFIO_PCF0_SWJ_CFG_Pos) /*!< 0x04000000 */
# define AFIO_PCF0_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
# define AFIO_PCF0_SWJ_CFG_NOJNTRST_Pos (24U)
# define AFIO_PCF0_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_PCF0_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
# define AFIO_PCF0_SWJ_CFG_NOJNTRST AFIO_PCF0_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
# define AFIO_PCF0_SWJ_CFG_JTAGDISABLE_Pos (25U)
# define AFIO_PCF0_SWJ_CFG_JTAGDISABLE_Msk (0x1U << AFIO_PCF0_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */
# define AFIO_PCF0_SWJ_CFG_JTAGDISABLE AFIO_PCF0_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */
# define AFIO_PCF0_SWJ_CFG_DISABLE_Pos (26U)
# define AFIO_PCF0_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_PCF0_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */
# define AFIO_PCF0_SWJ_CFG_DISABLE AFIO_PCF0_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */
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/*!< CAN2_REMAP configuration */
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# define AFIO_PCF0_CAN1_REMAP_Pos (22U)
# define AFIO_PCF0_CAN1_REMAP_Msk (0x1U << AFIO_PCF0_CAN1_REMAP_Pos) /*!< 0x00400000 */
# define AFIO_PCF0_CAN1_REMAP AFIO_PCF0_CAN1_REMAP_Msk /*!< CAN2_REMAP bit (CAN2 I/O remapping) */
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/*!< SPI3_REMAP configuration */
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# define AFIO_PCF0_SPI2_REMAP_Pos (28U)
# define AFIO_PCF0_SPI2_REMAP_Msk (0x1U << AFIO_PCF0_SPI2_REMAP_Pos) /*!< 0x10000000 */
# define AFIO_PCF0_SPI2_REMAP AFIO_PCF0_SPI2_REMAP_Msk /*!< SPI3_REMAP bit (SPI3 remapping) */
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/*!< TIM2ITR1_IREMAP configuration */
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# define AFIO_PCF0_TIM1ITR1_IREMAP_Pos (29U)
# define AFIO_PCF0_TIM1ITR1_IREMAP_Msk (0x1U << AFIO_PCF0_TIM1ITR1_IREMAP_Pos) /*!< 0x20000000 */
# define AFIO_PCF0_TIM1ITR1_IREMAP AFIO_PCF0_TIM1ITR1_IREMAP_Msk /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */
/***************** Bit definition for AFIO_EXTISS0 register *****************/
# define AFIO_EXTISS0_EXTI0_SS_Pos (0U)
# define AFIO_EXTISS0_EXTI0_SS_Msk (0xFU << AFIO_EXTISS0_EXTI0_SS_Pos) /*!< 0x0000000F */
# define AFIO_EXTISS0_EXTI0_SS AFIO_EXTISS0_EXTI0_SS_Msk /*!< EXTI 0 configuration */
# define AFIO_EXTISS0_EXTI1_SS_Pos (4U)
# define AFIO_EXTISS0_EXTI1_SS_Msk (0xFU << AFIO_EXTISS0_EXTI1_SS_Pos) /*!< 0x000000F0 */
# define AFIO_EXTISS0_EXTI1_SS AFIO_EXTISS0_EXTI1_SS_Msk /*!< EXTI 1 configuration */
# define AFIO_EXTISS0_EXTI2_SS_Pos (8U)
# define AFIO_EXTISS0_EXTI2_SS_Msk (0xFU << AFIO_EXTISS0_EXTI2_SS_Pos) /*!< 0x00000F00 */
# define AFIO_EXTISS0_EXTI2_SS AFIO_EXTISS0_EXTI2_SS_Msk /*!< EXTI 2 configuration */
# define AFIO_EXTISS0_EXTI3_SS_Pos (12U)
# define AFIO_EXTISS0_EXTI3_SS_Msk (0xFU << AFIO_EXTISS0_EXTI3_SS_Pos) /*!< 0x0000F000 */
# define AFIO_EXTISS0_EXTI3_SS AFIO_EXTISS0_EXTI3_SS_Msk /*!< EXTI 3 configuration */
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/*!< EXTI0 configuration */
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# define AFIO_EXTISS0_EXTI0_SS_PA 0x00000000U /*!< PA[0] pin */
# define AFIO_EXTISS0_EXTI0_SS_PB_Pos (0U)
# define AFIO_EXTISS0_EXTI0_SS_PB_Msk (0x1U << AFIO_EXTISS0_EXTI0_SS_PB_Pos) /*!< 0x00000001 */
# define AFIO_EXTISS0_EXTI0_SS_PB AFIO_EXTISS0_EXTI0_SS_PB_Msk /*!< PB[0] pin */
# define AFIO_EXTISS0_EXTI0_SS_PC_Pos (1U)
# define AFIO_EXTISS0_EXTI0_SS_PC_Msk (0x1U << AFIO_EXTISS0_EXTI0_SS_PC_Pos) /*!< 0x00000002 */
# define AFIO_EXTISS0_EXTI0_SS_PC AFIO_EXTISS0_EXTI0_SS_PC_Msk /*!< PC[0] pin */
# define AFIO_EXTISS0_EXTI0_SS_PD_Pos (0U)
# define AFIO_EXTISS0_EXTI0_SS_PD_Msk (0x3U << AFIO_EXTISS0_EXTI0_SS_PD_Pos) /*!< 0x00000003 */
# define AFIO_EXTISS0_EXTI0_SS_PD AFIO_EXTISS0_EXTI0_SS_PD_Msk /*!< PD[0] pin */
# define AFIO_EXTISS0_EXTI0_SS_PE_Pos (2U)
# define AFIO_EXTISS0_EXTI0_SS_PE_Msk (0x1U << AFIO_EXTISS0_EXTI0_SS_PE_Pos) /*!< 0x00000004 */
# define AFIO_EXTISS0_EXTI0_SS_PE AFIO_EXTISS0_EXTI0_SS_PE_Msk /*!< PE[0] pin */
# define AFIO_EXTISS0_EXTI0_SS_PF_Pos (0U)
# define AFIO_EXTISS0_EXTI0_SS_PF_Msk (0x5U << AFIO_EXTISS0_EXTI0_SS_PF_Pos) /*!< 0x00000005 */
# define AFIO_EXTISS0_EXTI0_SS_PF AFIO_EXTISS0_EXTI0_SS_PF_Msk /*!< PF[0] pin */
# define AFIO_EXTISS0_EXTI0_SS_PG_Pos (1U)
# define AFIO_EXTISS0_EXTI0_SS_PG_Msk (0x3U << AFIO_EXTISS0_EXTI0_SS_PG_Pos) /*!< 0x00000006 */
# define AFIO_EXTISS0_EXTI0_SS_PG AFIO_EXTISS0_EXTI0_SS_PG_Msk /*!< PG[0] pin */
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/*!< EXTI1 configuration */
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# define AFIO_EXTISS0_EXTI1_SS_PA 0x00000000U /*!< PA[1] pin */
# define AFIO_EXTISS0_EXTI1_SS_PB_Pos (4U)
# define AFIO_EXTISS0_EXTI1_SS_PB_Msk (0x1U << AFIO_EXTISS0_EXTI1_SS_PB_Pos) /*!< 0x00000010 */
# define AFIO_EXTISS0_EXTI1_SS_PB AFIO_EXTISS0_EXTI1_SS_PB_Msk /*!< PB[1] pin */
# define AFIO_EXTISS0_EXTI1_SS_PC_Pos (5U)
# define AFIO_EXTISS0_EXTI1_SS_PC_Msk (0x1U << AFIO_EXTISS0_EXTI1_SS_PC_Pos) /*!< 0x00000020 */
# define AFIO_EXTISS0_EXTI1_SS_PC AFIO_EXTISS0_EXTI1_SS_PC_Msk /*!< PC[1] pin */
# define AFIO_EXTISS0_EXTI1_SS_PD_Pos (4U)
# define AFIO_EXTISS0_EXTI1_SS_PD_Msk (0x3U << AFIO_EXTISS0_EXTI1_SS_PD_Pos) /*!< 0x00000030 */
# define AFIO_EXTISS0_EXTI1_SS_PD AFIO_EXTISS0_EXTI1_SS_PD_Msk /*!< PD[1] pin */
# define AFIO_EXTISS0_EXTI1_SS_PE_Pos (6U)
# define AFIO_EXTISS0_EXTI1_SS_PE_Msk (0x1U << AFIO_EXTISS0_EXTI1_SS_PE_Pos) /*!< 0x00000040 */
# define AFIO_EXTISS0_EXTI1_SS_PE AFIO_EXTISS0_EXTI1_SS_PE_Msk /*!< PE[1] pin */
# define AFIO_EXTISS0_EXTI1_SS_PF_Pos (4U)
# define AFIO_EXTISS0_EXTI1_SS_PF_Msk (0x5U << AFIO_EXTISS0_EXTI1_SS_PF_Pos) /*!< 0x00000050 */
# define AFIO_EXTISS0_EXTI1_SS_PF AFIO_EXTISS0_EXTI1_SS_PF_Msk /*!< PF[1] pin */
# define AFIO_EXTISS0_EXTI1_SS_PG_Pos (5U)
# define AFIO_EXTISS0_EXTI1_SS_PG_Msk (0x3U << AFIO_EXTISS0_EXTI1_SS_PG_Pos) /*!< 0x00000060 */
# define AFIO_EXTISS0_EXTI1_SS_PG AFIO_EXTISS0_EXTI1_SS_PG_Msk /*!< PG[1] pin */
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/*!< EXTI2 configuration */
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# define AFIO_EXTISS0_EXTI2_SS_PA 0x00000000U /*!< PA[2] pin */
# define AFIO_EXTISS0_EXTI2_SS_PB_Pos (8U)
# define AFIO_EXTISS0_EXTI2_SS_PB_Msk (0x1U << AFIO_EXTISS0_EXTI2_SS_PB_Pos) /*!< 0x00000100 */
# define AFIO_EXTISS0_EXTI2_SS_PB AFIO_EXTISS0_EXTI2_SS_PB_Msk /*!< PB[2] pin */
# define AFIO_EXTISS0_EXTI2_SS_PC_Pos (9U)
# define AFIO_EXTISS0_EXTI2_SS_PC_Msk (0x1U << AFIO_EXTISS0_EXTI2_SS_PC_Pos) /*!< 0x00000200 */
# define AFIO_EXTISS0_EXTI2_SS_PC AFIO_EXTISS0_EXTI2_SS_PC_Msk /*!< PC[2] pin */
# define AFIO_EXTISS0_EXTI2_SS_PD_Pos (8U)
# define AFIO_EXTISS0_EXTI2_SS_PD_Msk (0x3U << AFIO_EXTISS0_EXTI2_SS_PD_Pos) /*!< 0x00000300 */
# define AFIO_EXTISS0_EXTI2_SS_PD AFIO_EXTISS0_EXTI2_SS_PD_Msk /*!< PD[2] pin */
# define AFIO_EXTISS0_EXTI2_SS_PE_Pos (10U)
# define AFIO_EXTISS0_EXTI2_SS_PE_Msk (0x1U << AFIO_EXTISS0_EXTI2_SS_PE_Pos) /*!< 0x00000400 */
# define AFIO_EXTISS0_EXTI2_SS_PE AFIO_EXTISS0_EXTI2_SS_PE_Msk /*!< PE[2] pin */
# define AFIO_EXTISS0_EXTI2_SS_PF_Pos (8U)
# define AFIO_EXTISS0_EXTI2_SS_PF_Msk (0x5U << AFIO_EXTISS0_EXTI2_SS_PF_Pos) /*!< 0x00000500 */
# define AFIO_EXTISS0_EXTI2_SS_PF AFIO_EXTISS0_EXTI2_SS_PF_Msk /*!< PF[2] pin */
# define AFIO_EXTISS0_EXTI2_SS_PG_Pos (9U)
# define AFIO_EXTISS0_EXTI2_SS_PG_Msk (0x3U << AFIO_EXTISS0_EXTI2_SS_PG_Pos) /*!< 0x00000600 */
# define AFIO_EXTISS0_EXTI2_SS_PG AFIO_EXTISS0_EXTI2_SS_PG_Msk /*!< PG[2] pin */
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/*!< EXTI3 configuration */
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# define AFIO_EXTISS0_EXTI3_SS_PA 0x00000000U /*!< PA[3] pin */
# define AFIO_EXTISS0_EXTI3_SS_PB_Pos (12U)
# define AFIO_EXTISS0_EXTI3_SS_PB_Msk (0x1U << AFIO_EXTISS0_EXTI3_SS_PB_Pos) /*!< 0x00001000 */
# define AFIO_EXTISS0_EXTI3_SS_PB AFIO_EXTISS0_EXTI3_SS_PB_Msk /*!< PB[3] pin */
# define AFIO_EXTISS0_EXTI3_SS_PC_Pos (13U)
# define AFIO_EXTISS0_EXTI3_SS_PC_Msk (0x1U << AFIO_EXTISS0_EXTI3_SS_PC_Pos) /*!< 0x00002000 */
# define AFIO_EXTISS0_EXTI3_SS_PC AFIO_EXTISS0_EXTI3_SS_PC_Msk /*!< PC[3] pin */
# define AFIO_EXTISS0_EXTI3_SS_PD_Pos (12U)
# define AFIO_EXTISS0_EXTI3_SS_PD_Msk (0x3U << AFIO_EXTISS0_EXTI3_SS_PD_Pos) /*!< 0x00003000 */
# define AFIO_EXTISS0_EXTI3_SS_PD AFIO_EXTISS0_EXTI3_SS_PD_Msk /*!< PD[3] pin */
# define AFIO_EXTISS0_EXTI3_SS_PE_Pos (14U)
# define AFIO_EXTISS0_EXTI3_SS_PE_Msk (0x1U << AFIO_EXTISS0_EXTI3_SS_PE_Pos) /*!< 0x00004000 */
# define AFIO_EXTISS0_EXTI3_SS_PE AFIO_EXTISS0_EXTI3_SS_PE_Msk /*!< PE[3] pin */
# define AFIO_EXTISS0_EXTI3_SS_PF_Pos (12U)
# define AFIO_EXTISS0_EXTI3_SS_PF_Msk (0x5U << AFIO_EXTISS0_EXTI3_SS_PF_Pos) /*!< 0x00005000 */
# define AFIO_EXTISS0_EXTI3_SS_PF AFIO_EXTISS0_EXTI3_SS_PF_Msk /*!< PF[3] pin */
# define AFIO_EXTISS0_EXTI3_SS_PG_Pos (13U)
# define AFIO_EXTISS0_EXTI3_SS_PG_Msk (0x3U << AFIO_EXTISS0_EXTI3_SS_PG_Pos) /*!< 0x00006000 */
# define AFIO_EXTISS0_EXTI3_SS_PG AFIO_EXTISS0_EXTI3_SS_PG_Msk /*!< PG[3] pin */
/***************** Bit definition for AFIO_EXTISS1 register *****************/
# define AFIO_EXTISS1_EXTI4_SS_Pos (0U)
# define AFIO_EXTISS1_EXTI4_SS_Msk (0xFU << AFIO_EXTISS1_EXTI4_SS_Pos) /*!< 0x0000000F */
# define AFIO_EXTISS1_EXTI4_SS AFIO_EXTISS1_EXTI4_SS_Msk /*!< EXTI 4 configuration */
# define AFIO_EXTISS1_EXTI5_SS_Pos (4U)
# define AFIO_EXTISS1_EXTI5_SS_Msk (0xFU << AFIO_EXTISS1_EXTI5_SS_Pos) /*!< 0x000000F0 */
# define AFIO_EXTISS1_EXTI5_SS AFIO_EXTISS1_EXTI5_SS_Msk /*!< EXTI 5 configuration */
# define AFIO_EXTISS1_EXTI6_SS_Pos (8U)
# define AFIO_EXTISS1_EXTI6_SS_Msk (0xFU << AFIO_EXTISS1_EXTI6_SS_Pos) /*!< 0x00000F00 */
# define AFIO_EXTISS1_EXTI6_SS AFIO_EXTISS1_EXTI6_SS_Msk /*!< EXTI 6 configuration */
# define AFIO_EXTISS1_EXTI7_SS_Pos (12U)
# define AFIO_EXTISS1_EXTI7_SS_Msk (0xFU << AFIO_EXTISS1_EXTI7_SS_Pos) /*!< 0x0000F000 */
# define AFIO_EXTISS1_EXTI7_SS AFIO_EXTISS1_EXTI7_SS_Msk /*!< EXTI 7 configuration */
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/*!< EXTI4 configuration */
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# define AFIO_EXTISS1_EXTI4_SS_PA 0x00000000U /*!< PA[4] pin */
# define AFIO_EXTISS1_EXTI4_SS_PB_Pos (0U)
# define AFIO_EXTISS1_EXTI4_SS_PB_Msk (0x1U << AFIO_EXTISS1_EXTI4_SS_PB_Pos) /*!< 0x00000001 */
# define AFIO_EXTISS1_EXTI4_SS_PB AFIO_EXTISS1_EXTI4_SS_PB_Msk /*!< PB[4] pin */
# define AFIO_EXTISS1_EXTI4_SS_PC_Pos (1U)
# define AFIO_EXTISS1_EXTI4_SS_PC_Msk (0x1U << AFIO_EXTISS1_EXTI4_SS_PC_Pos) /*!< 0x00000002 */
# define AFIO_EXTISS1_EXTI4_SS_PC AFIO_EXTISS1_EXTI4_SS_PC_Msk /*!< PC[4] pin */
# define AFIO_EXTISS1_EXTI4_SS_PD_Pos (0U)
# define AFIO_EXTISS1_EXTI4_SS_PD_Msk (0x3U << AFIO_EXTISS1_EXTI4_SS_PD_Pos) /*!< 0x00000003 */
# define AFIO_EXTISS1_EXTI4_SS_PD AFIO_EXTISS1_EXTI4_SS_PD_Msk /*!< PD[4] pin */
# define AFIO_EXTISS1_EXTI4_SS_PE_Pos (2U)
# define AFIO_EXTISS1_EXTI4_SS_PE_Msk (0x1U << AFIO_EXTISS1_EXTI4_SS_PE_Pos) /*!< 0x00000004 */
# define AFIO_EXTISS1_EXTI4_SS_PE AFIO_EXTISS1_EXTI4_SS_PE_Msk /*!< PE[4] pin */
# define AFIO_EXTISS1_EXTI4_SS_PF_Pos (0U)
# define AFIO_EXTISS1_EXTI4_SS_PF_Msk (0x5U << AFIO_EXTISS1_EXTI4_SS_PF_Pos) /*!< 0x00000005 */
# define AFIO_EXTISS1_EXTI4_SS_PF AFIO_EXTISS1_EXTI4_SS_PF_Msk /*!< PF[4] pin */
# define AFIO_EXTISS1_EXTI4_SS_PG_Pos (1U)
# define AFIO_EXTISS1_EXTI4_SS_PG_Msk (0x3U << AFIO_EXTISS1_EXTI4_SS_PG_Pos) /*!< 0x00000006 */
# define AFIO_EXTISS1_EXTI4_SS_PG AFIO_EXTISS1_EXTI4_SS_PG_Msk /*!< PG[4] pin */
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/* EXTI5 configuration */
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# define AFIO_EXTISS1_EXTI5_SS_PA 0x00000000U /*!< PA[5] pin */
# define AFIO_EXTISS1_EXTI5_SS_PB_Pos (4U)
# define AFIO_EXTISS1_EXTI5_SS_PB_Msk (0x1U << AFIO_EXTISS1_EXTI5_SS_PB_Pos) /*!< 0x00000010 */
# define AFIO_EXTISS1_EXTI5_SS_PB AFIO_EXTISS1_EXTI5_SS_PB_Msk /*!< PB[5] pin */
# define AFIO_EXTISS1_EXTI5_SS_PC_Pos (5U)
# define AFIO_EXTISS1_EXTI5_SS_PC_Msk (0x1U << AFIO_EXTISS1_EXTI5_SS_PC_Pos) /*!< 0x00000020 */
# define AFIO_EXTISS1_EXTI5_SS_PC AFIO_EXTISS1_EXTI5_SS_PC_Msk /*!< PC[5] pin */
# define AFIO_EXTISS1_EXTI5_SS_PD_Pos (4U)
# define AFIO_EXTISS1_EXTI5_SS_PD_Msk (0x3U << AFIO_EXTISS1_EXTI5_SS_PD_Pos) /*!< 0x00000030 */
# define AFIO_EXTISS1_EXTI5_SS_PD AFIO_EXTISS1_EXTI5_SS_PD_Msk /*!< PD[5] pin */
# define AFIO_EXTISS1_EXTI5_SS_PE_Pos (6U)
# define AFIO_EXTISS1_EXTI5_SS_PE_Msk (0x1U << AFIO_EXTISS1_EXTI5_SS_PE_Pos) /*!< 0x00000040 */
# define AFIO_EXTISS1_EXTI5_SS_PE AFIO_EXTISS1_EXTI5_SS_PE_Msk /*!< PE[5] pin */
# define AFIO_EXTISS1_EXTI5_SS_PF_Pos (4U)
# define AFIO_EXTISS1_EXTI5_SS_PF_Msk (0x5U << AFIO_EXTISS1_EXTI5_SS_PF_Pos) /*!< 0x00000050 */
# define AFIO_EXTISS1_EXTI5_SS_PF AFIO_EXTISS1_EXTI5_SS_PF_Msk /*!< PF[5] pin */
# define AFIO_EXTISS1_EXTI5_SS_PG_Pos (5U)
# define AFIO_EXTISS1_EXTI5_SS_PG_Msk (0x3U << AFIO_EXTISS1_EXTI5_SS_PG_Pos) /*!< 0x00000060 */
# define AFIO_EXTISS1_EXTI5_SS_PG AFIO_EXTISS1_EXTI5_SS_PG_Msk /*!< PG[5] pin */
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/*!< EXTI6 configuration */
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# define AFIO_EXTISS1_EXTI6_SS_PA 0x00000000U /*!< PA[6] pin */
# define AFIO_EXTISS1_EXTI6_SS_PB_Pos (8U)
# define AFIO_EXTISS1_EXTI6_SS_PB_Msk (0x1U << AFIO_EXTISS1_EXTI6_SS_PB_Pos) /*!< 0x00000100 */
# define AFIO_EXTISS1_EXTI6_SS_PB AFIO_EXTISS1_EXTI6_SS_PB_Msk /*!< PB[6] pin */
# define AFIO_EXTISS1_EXTI6_SS_PC_Pos (9U)
# define AFIO_EXTISS1_EXTI6_SS_PC_Msk (0x1U << AFIO_EXTISS1_EXTI6_SS_PC_Pos) /*!< 0x00000200 */
# define AFIO_EXTISS1_EXTI6_SS_PC AFIO_EXTISS1_EXTI6_SS_PC_Msk /*!< PC[6] pin */
# define AFIO_EXTISS1_EXTI6_SS_PD_Pos (8U)
# define AFIO_EXTISS1_EXTI6_SS_PD_Msk (0x3U << AFIO_EXTISS1_EXTI6_SS_PD_Pos) /*!< 0x00000300 */
# define AFIO_EXTISS1_EXTI6_SS_PD AFIO_EXTISS1_EXTI6_SS_PD_Msk /*!< PD[6] pin */
# define AFIO_EXTISS1_EXTI6_SS_PE_Pos (10U)
# define AFIO_EXTISS1_EXTI6_SS_PE_Msk (0x1U << AFIO_EXTISS1_EXTI6_SS_PE_Pos) /*!< 0x00000400 */
# define AFIO_EXTISS1_EXTI6_SS_PE AFIO_EXTISS1_EXTI6_SS_PE_Msk /*!< PE[6] pin */
# define AFIO_EXTISS1_EXTI6_SS_PF_Pos (8U)
# define AFIO_EXTISS1_EXTI6_SS_PF_Msk (0x5U << AFIO_EXTISS1_EXTI6_SS_PF_Pos) /*!< 0x00000500 */
# define AFIO_EXTISS1_EXTI6_SS_PF AFIO_EXTISS1_EXTI6_SS_PF_Msk /*!< PF[6] pin */
# define AFIO_EXTISS1_EXTI6_SS_PG_Pos (9U)
# define AFIO_EXTISS1_EXTI6_SS_PG_Msk (0x3U << AFIO_EXTISS1_EXTI6_SS_PG_Pos) /*!< 0x00000600 */
# define AFIO_EXTISS1_EXTI6_SS_PG AFIO_EXTISS1_EXTI6_SS_PG_Msk /*!< PG[6] pin */
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/*!< EXTI7 configuration */
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# define AFIO_EXTISS1_EXTI7_SS_PA 0x00000000U /*!< PA[7] pin */
# define AFIO_EXTISS1_EXTI7_SS_PB_Pos (12U)
# define AFIO_EXTISS1_EXTI7_SS_PB_Msk (0x1U << AFIO_EXTISS1_EXTI7_SS_PB_Pos) /*!< 0x00001000 */
# define AFIO_EXTISS1_EXTI7_SS_PB AFIO_EXTISS1_EXTI7_SS_PB_Msk /*!< PB[7] pin */
# define AFIO_EXTISS1_EXTI7_SS_PC_Pos (13U)
# define AFIO_EXTISS1_EXTI7_SS_PC_Msk (0x1U << AFIO_EXTISS1_EXTI7_SS_PC_Pos) /*!< 0x00002000 */
# define AFIO_EXTISS1_EXTI7_SS_PC AFIO_EXTISS1_EXTI7_SS_PC_Msk /*!< PC[7] pin */
# define AFIO_EXTISS1_EXTI7_SS_PD_Pos (12U)
# define AFIO_EXTISS1_EXTI7_SS_PD_Msk (0x3U << AFIO_EXTISS1_EXTI7_SS_PD_Pos) /*!< 0x00003000 */
# define AFIO_EXTISS1_EXTI7_SS_PD AFIO_EXTISS1_EXTI7_SS_PD_Msk /*!< PD[7] pin */
# define AFIO_EXTISS1_EXTI7_SS_PE_Pos (14U)
# define AFIO_EXTISS1_EXTI7_SS_PE_Msk (0x1U << AFIO_EXTISS1_EXTI7_SS_PE_Pos) /*!< 0x00004000 */
# define AFIO_EXTISS1_EXTI7_SS_PE AFIO_EXTISS1_EXTI7_SS_PE_Msk /*!< PE[7] pin */
# define AFIO_EXTISS1_EXTI7_SS_PF_Pos (12U)
# define AFIO_EXTISS1_EXTI7_SS_PF_Msk (0x5U << AFIO_EXTISS1_EXTI7_SS_PF_Pos) /*!< 0x00005000 */
# define AFIO_EXTISS1_EXTI7_SS_PF AFIO_EXTISS1_EXTI7_SS_PF_Msk /*!< PF[7] pin */
# define AFIO_EXTISS1_EXTI7_SS_PG_Pos (13U)
# define AFIO_EXTISS1_EXTI7_SS_PG_Msk (0x3U << AFIO_EXTISS1_EXTI7_SS_PG_Pos) /*!< 0x00006000 */
# define AFIO_EXTISS1_EXTI7_SS_PG AFIO_EXTISS1_EXTI7_SS_PG_Msk /*!< PG[7] pin */
/***************** Bit definition for AFIO_EXTISS2 register *****************/
# define AFIO_EXTISS2_EXTI8_SS_Pos (0U)
# define AFIO_EXTISS2_EXTI8_SS_Msk (0xFU << AFIO_EXTISS2_EXTI8_SS_Pos) /*!< 0x0000000F */
# define AFIO_EXTISS2_EXTI8_SS AFIO_EXTISS2_EXTI8_SS_Msk /*!< EXTI 8 configuration */
# define AFIO_EXTISS2_EXTI9_SS_Pos (4U)
# define AFIO_EXTISS2_EXTI9_SS_Msk (0xFU << AFIO_EXTISS2_EXTI9_SS_Pos) /*!< 0x000000F0 */
# define AFIO_EXTISS2_EXTI9_SS AFIO_EXTISS2_EXTI9_SS_Msk /*!< EXTI 9 configuration */
# define AFIO_EXTISS2_EXTI10_SS_Pos (8U)
# define AFIO_EXTISS2_EXTI10_SS_Msk (0xFU << AFIO_EXTISS2_EXTI10_SS_Pos) /*!< 0x00000F00 */
# define AFIO_EXTISS2_EXTI10_SS AFIO_EXTISS2_EXTI10_SS_Msk /*!< EXTI 10 configuration */
# define AFIO_EXTISS2_EXTI11_SS_Pos (12U)
# define AFIO_EXTISS2_EXTI11_SS_Msk (0xFU << AFIO_EXTISS2_EXTI11_SS_Pos) /*!< 0x0000F000 */
# define AFIO_EXTISS2_EXTI11_SS AFIO_EXTISS2_EXTI11_SS_Msk /*!< EXTI 11 configuration */
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/*!< EXTI8 configuration */
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# define AFIO_EXTISS2_EXTI8_SS_PA 0x00000000U /*!< PA[8] pin */
# define AFIO_EXTISS2_EXTI8_SS_PB_Pos (0U)
# define AFIO_EXTISS2_EXTI8_SS_PB_Msk (0x1U << AFIO_EXTISS2_EXTI8_SS_PB_Pos) /*!< 0x00000001 */
# define AFIO_EXTISS2_EXTI8_SS_PB AFIO_EXTISS2_EXTI8_SS_PB_Msk /*!< PB[8] pin */
# define AFIO_EXTISS2_EXTI8_SS_PC_Pos (1U)
# define AFIO_EXTISS2_EXTI8_SS_PC_Msk (0x1U << AFIO_EXTISS2_EXTI8_SS_PC_Pos) /*!< 0x00000002 */
# define AFIO_EXTISS2_EXTI8_SS_PC AFIO_EXTISS2_EXTI8_SS_PC_Msk /*!< PC[8] pin */
# define AFIO_EXTISS2_EXTI8_SS_PD_Pos (0U)
# define AFIO_EXTISS2_EXTI8_SS_PD_Msk (0x3U << AFIO_EXTISS2_EXTI8_SS_PD_Pos) /*!< 0x00000003 */
# define AFIO_EXTISS2_EXTI8_SS_PD AFIO_EXTISS2_EXTI8_SS_PD_Msk /*!< PD[8] pin */
# define AFIO_EXTISS2_EXTI8_SS_PE_Pos (2U)
# define AFIO_EXTISS2_EXTI8_SS_PE_Msk (0x1U << AFIO_EXTISS2_EXTI8_SS_PE_Pos) /*!< 0x00000004 */
# define AFIO_EXTISS2_EXTI8_SS_PE AFIO_EXTISS2_EXTI8_SS_PE_Msk /*!< PE[8] pin */
# define AFIO_EXTISS2_EXTI8_SS_PF_Pos (0U)
# define AFIO_EXTISS2_EXTI8_SS_PF_Msk (0x5U << AFIO_EXTISS2_EXTI8_SS_PF_Pos) /*!< 0x00000005 */
# define AFIO_EXTISS2_EXTI8_SS_PF AFIO_EXTISS2_EXTI8_SS_PF_Msk /*!< PF[8] pin */
# define AFIO_EXTISS2_EXTI8_SS_PG_Pos (1U)
# define AFIO_EXTISS2_EXTI8_SS_PG_Msk (0x3U << AFIO_EXTISS2_EXTI8_SS_PG_Pos) /*!< 0x00000006 */
# define AFIO_EXTISS2_EXTI8_SS_PG AFIO_EXTISS2_EXTI8_SS_PG_Msk /*!< PG[8] pin */
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/*!< EXTI9 configuration */
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# define AFIO_EXTISS2_EXTI9_SS_PA 0x00000000U /*!< PA[9] pin */
# define AFIO_EXTISS2_EXTI9_SS_PB_Pos (4U)
# define AFIO_EXTISS2_EXTI9_SS_PB_Msk (0x1U << AFIO_EXTISS2_EXTI9_SS_PB_Pos) /*!< 0x00000010 */
# define AFIO_EXTISS2_EXTI9_SS_PB AFIO_EXTISS2_EXTI9_SS_PB_Msk /*!< PB[9] pin */
# define AFIO_EXTISS2_EXTI9_SS_PC_Pos (5U)
# define AFIO_EXTISS2_EXTI9_SS_PC_Msk (0x1U << AFIO_EXTISS2_EXTI9_SS_PC_Pos) /*!< 0x00000020 */
# define AFIO_EXTISS2_EXTI9_SS_PC AFIO_EXTISS2_EXTI9_SS_PC_Msk /*!< PC[9] pin */
# define AFIO_EXTISS2_EXTI9_SS_PD_Pos (4U)
# define AFIO_EXTISS2_EXTI9_SS_PD_Msk (0x3U << AFIO_EXTISS2_EXTI9_SS_PD_Pos) /*!< 0x00000030 */
# define AFIO_EXTISS2_EXTI9_SS_PD AFIO_EXTISS2_EXTI9_SS_PD_Msk /*!< PD[9] pin */
# define AFIO_EXTISS2_EXTI9_SS_PE_Pos (6U)
# define AFIO_EXTISS2_EXTI9_SS_PE_Msk (0x1U << AFIO_EXTISS2_EXTI9_SS_PE_Pos) /*!< 0x00000040 */
# define AFIO_EXTISS2_EXTI9_SS_PE AFIO_EXTISS2_EXTI9_SS_PE_Msk /*!< PE[9] pin */
# define AFIO_EXTISS2_EXTI9_SS_PF_Pos (4U)
# define AFIO_EXTISS2_EXTI9_SS_PF_Msk (0x5U << AFIO_EXTISS2_EXTI9_SS_PF_Pos) /*!< 0x00000050 */
# define AFIO_EXTISS2_EXTI9_SS_PF AFIO_EXTISS2_EXTI9_SS_PF_Msk /*!< PF[9] pin */
# define AFIO_EXTISS2_EXTI9_SS_PG_Pos (5U)
# define AFIO_EXTISS2_EXTI9_SS_PG_Msk (0x3U << AFIO_EXTISS2_EXTI9_SS_PG_Pos) /*!< 0x00000060 */
# define AFIO_EXTISS2_EXTI9_SS_PG AFIO_EXTISS2_EXTI9_SS_PG_Msk /*!< PG[9] pin */
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/*!< EXTI10 configuration */
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# define AFIO_EXTISS2_EXTI10_SS_PA 0x00000000U /*!< PA[10] pin */
# define AFIO_EXTISS2_EXTI10_SS_PB_Pos (8U)
# define AFIO_EXTISS2_EXTI10_SS_PB_Msk (0x1U << AFIO_EXTISS2_EXTI10_SS_PB_Pos) /*!< 0x00000100 */
# define AFIO_EXTISS2_EXTI10_SS_PB AFIO_EXTISS2_EXTI10_SS_PB_Msk /*!< PB[10] pin */
# define AFIO_EXTISS2_EXTI10_SS_PC_Pos (9U)
# define AFIO_EXTISS2_EXTI10_SS_PC_Msk (0x1U << AFIO_EXTISS2_EXTI10_SS_PC_Pos) /*!< 0x00000200 */
# define AFIO_EXTISS2_EXTI10_SS_PC AFIO_EXTISS2_EXTI10_SS_PC_Msk /*!< PC[10] pin */
# define AFIO_EXTISS2_EXTI10_SS_PD_Pos (8U)
# define AFIO_EXTISS2_EXTI10_SS_PD_Msk (0x3U << AFIO_EXTISS2_EXTI10_SS_PD_Pos) /*!< 0x00000300 */
# define AFIO_EXTISS2_EXTI10_SS_PD AFIO_EXTISS2_EXTI10_SS_PD_Msk /*!< PD[10] pin */
# define AFIO_EXTISS2_EXTI10_SS_PE_Pos (10U)
# define AFIO_EXTISS2_EXTI10_SS_PE_Msk (0x1U << AFIO_EXTISS2_EXTI10_SS_PE_Pos) /*!< 0x00000400 */
# define AFIO_EXTISS2_EXTI10_SS_PE AFIO_EXTISS2_EXTI10_SS_PE_Msk /*!< PE[10] pin */
# define AFIO_EXTISS2_EXTI10_SS_PF_Pos (8U)
# define AFIO_EXTISS2_EXTI10_SS_PF_Msk (0x5U << AFIO_EXTISS2_EXTI10_SS_PF_Pos) /*!< 0x00000500 */
# define AFIO_EXTISS2_EXTI10_SS_PF AFIO_EXTISS2_EXTI10_SS_PF_Msk /*!< PF[10] pin */
# define AFIO_EXTISS2_EXTI10_SS_PG_Pos (9U)
# define AFIO_EXTISS2_EXTI10_SS_PG_Msk (0x3U << AFIO_EXTISS2_EXTI10_SS_PG_Pos) /*!< 0x00000600 */
# define AFIO_EXTISS2_EXTI10_SS_PG AFIO_EXTISS2_EXTI10_SS_PG_Msk /*!< PG[10] pin */
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/*!< EXTI11 configuration */
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# define AFIO_EXTISS2_EXTI11_SS_PA 0x00000000U /*!< PA[11] pin */
# define AFIO_EXTISS2_EXTI11_SS_PB_Pos (12U)
# define AFIO_EXTISS2_EXTI11_SS_PB_Msk (0x1U << AFIO_EXTISS2_EXTI11_SS_PB_Pos) /*!< 0x00001000 */
# define AFIO_EXTISS2_EXTI11_SS_PB AFIO_EXTISS2_EXTI11_SS_PB_Msk /*!< PB[11] pin */
# define AFIO_EXTISS2_EXTI11_SS_PC_Pos (13U)
# define AFIO_EXTISS2_EXTI11_SS_PC_Msk (0x1U << AFIO_EXTISS2_EXTI11_SS_PC_Pos) /*!< 0x00002000 */
# define AFIO_EXTISS2_EXTI11_SS_PC AFIO_EXTISS2_EXTI11_SS_PC_Msk /*!< PC[11] pin */
# define AFIO_EXTISS2_EXTI11_SS_PD_Pos (12U)
# define AFIO_EXTISS2_EXTI11_SS_PD_Msk (0x3U << AFIO_EXTISS2_EXTI11_SS_PD_Pos) /*!< 0x00003000 */
# define AFIO_EXTISS2_EXTI11_SS_PD AFIO_EXTISS2_EXTI11_SS_PD_Msk /*!< PD[11] pin */
# define AFIO_EXTISS2_EXTI11_SS_PE_Pos (14U)
# define AFIO_EXTISS2_EXTI11_SS_PE_Msk (0x1U << AFIO_EXTISS2_EXTI11_SS_PE_Pos) /*!< 0x00004000 */
# define AFIO_EXTISS2_EXTI11_SS_PE AFIO_EXTISS2_EXTI11_SS_PE_Msk /*!< PE[11] pin */
# define AFIO_EXTISS2_EXTI11_SS_PF_Pos (12U)
# define AFIO_EXTISS2_EXTI11_SS_PF_Msk (0x5U << AFIO_EXTISS2_EXTI11_SS_PF_Pos) /*!< 0x00005000 */
# define AFIO_EXTISS2_EXTI11_SS_PF AFIO_EXTISS2_EXTI11_SS_PF_Msk /*!< PF[11] pin */
# define AFIO_EXTISS2_EXTI11_SS_PG_Pos (13U)
# define AFIO_EXTISS2_EXTI11_SS_PG_Msk (0x3U << AFIO_EXTISS2_EXTI11_SS_PG_Pos) /*!< 0x00006000 */
# define AFIO_EXTISS2_EXTI11_SS_PG AFIO_EXTISS2_EXTI11_SS_PG_Msk /*!< PG[11] pin */
/***************** Bit definition for AFIO_EXTISS3 register *****************/
# define AFIO_EXTISS3_EXTI12_SS_Pos (0U)
# define AFIO_EXTISS3_EXTI12_SS_Msk (0xFU << AFIO_EXTISS3_EXTI12_SS_Pos) /*!< 0x0000000F */
# define AFIO_EXTISS3_EXTI12_SS AFIO_EXTISS3_EXTI12_SS_Msk /*!< EXTI 12 configuration */
# define AFIO_EXTISS3_EXTI13_SS_Pos (4U)
# define AFIO_EXTISS3_EXTI13_SS_Msk (0xFU << AFIO_EXTISS3_EXTI13_SS_Pos) /*!< 0x000000F0 */
# define AFIO_EXTISS3_EXTI13_SS AFIO_EXTISS3_EXTI13_SS_Msk /*!< EXTI 13 configuration */
# define AFIO_EXTISS3_EXTI14_SS_Pos (8U)
# define AFIO_EXTISS3_EXTI14_SS_Msk (0xFU << AFIO_EXTISS3_EXTI14_SS_Pos) /*!< 0x00000F00 */
# define AFIO_EXTISS3_EXTI14_SS AFIO_EXTISS3_EXTI14_SS_Msk /*!< EXTI 14 configuration */
# define AFIO_EXTISS3_EXTI15_SS_Pos (12U)
# define AFIO_EXTISS3_EXTI15_SS_Msk (0xFU << AFIO_EXTISS3_EXTI15_SS_Pos) /*!< 0x0000F000 */
# define AFIO_EXTISS3_EXTI15_SS AFIO_EXTISS3_EXTI15_SS_Msk /*!< EXTI 15 configuration */
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/* EXTI12 configuration */
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# define AFIO_EXTISS3_EXTI12_SS_PA 0x00000000U /*!< PA[12] pin */
# define AFIO_EXTISS3_EXTI12_SS_PB_Pos (0U)
# define AFIO_EXTISS3_EXTI12_SS_PB_Msk (0x1U << AFIO_EXTISS3_EXTI12_SS_PB_Pos) /*!< 0x00000001 */
# define AFIO_EXTISS3_EXTI12_SS_PB AFIO_EXTISS3_EXTI12_SS_PB_Msk /*!< PB[12] pin */
# define AFIO_EXTISS3_EXTI12_SS_PC_Pos (1U)
# define AFIO_EXTISS3_EXTI12_SS_PC_Msk (0x1U << AFIO_EXTISS3_EXTI12_SS_PC_Pos) /*!< 0x00000002 */
# define AFIO_EXTISS3_EXTI12_SS_PC AFIO_EXTISS3_EXTI12_SS_PC_Msk /*!< PC[12] pin */
# define AFIO_EXTISS3_EXTI12_SS_PD_Pos (0U)
# define AFIO_EXTISS3_EXTI12_SS_PD_Msk (0x3U << AFIO_EXTISS3_EXTI12_SS_PD_Pos) /*!< 0x00000003 */
# define AFIO_EXTISS3_EXTI12_SS_PD AFIO_EXTISS3_EXTI12_SS_PD_Msk /*!< PD[12] pin */
# define AFIO_EXTISS3_EXTI12_SS_PE_Pos (2U)
# define AFIO_EXTISS3_EXTI12_SS_PE_Msk (0x1U << AFIO_EXTISS3_EXTI12_SS_PE_Pos) /*!< 0x00000004 */
# define AFIO_EXTISS3_EXTI12_SS_PE AFIO_EXTISS3_EXTI12_SS_PE_Msk /*!< PE[12] pin */
# define AFIO_EXTISS3_EXTI12_SS_PF_Pos (0U)
# define AFIO_EXTISS3_EXTI12_SS_PF_Msk (0x5U << AFIO_EXTISS3_EXTI12_SS_PF_Pos) /*!< 0x00000005 */
# define AFIO_EXTISS3_EXTI12_SS_PF AFIO_EXTISS3_EXTI12_SS_PF_Msk /*!< PF[12] pin */
# define AFIO_EXTISS3_EXTI12_SS_PG_Pos (1U)
# define AFIO_EXTISS3_EXTI12_SS_PG_Msk (0x3U << AFIO_EXTISS3_EXTI12_SS_PG_Pos) /*!< 0x00000006 */
# define AFIO_EXTISS3_EXTI12_SS_PG AFIO_EXTISS3_EXTI12_SS_PG_Msk /*!< PG[12] pin */
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/* EXTI13 configuration */
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# define AFIO_EXTISS3_EXTI13_SS_PA 0x00000000U /*!< PA[13] pin */
# define AFIO_EXTISS3_EXTI13_SS_PB_Pos (4U)
# define AFIO_EXTISS3_EXTI13_SS_PB_Msk (0x1U << AFIO_EXTISS3_EXTI13_SS_PB_Pos) /*!< 0x00000010 */
# define AFIO_EXTISS3_EXTI13_SS_PB AFIO_EXTISS3_EXTI13_SS_PB_Msk /*!< PB[13] pin */
# define AFIO_EXTISS3_EXTI13_SS_PC_Pos (5U)
# define AFIO_EXTISS3_EXTI13_SS_PC_Msk (0x1U << AFIO_EXTISS3_EXTI13_SS_PC_Pos) /*!< 0x00000020 */
# define AFIO_EXTISS3_EXTI13_SS_PC AFIO_EXTISS3_EXTI13_SS_PC_Msk /*!< PC[13] pin */
# define AFIO_EXTISS3_EXTI13_SS_PD_Pos (4U)
# define AFIO_EXTISS3_EXTI13_SS_PD_Msk (0x3U << AFIO_EXTISS3_EXTI13_SS_PD_Pos) /*!< 0x00000030 */
# define AFIO_EXTISS3_EXTI13_SS_PD AFIO_EXTISS3_EXTI13_SS_PD_Msk /*!< PD[13] pin */
# define AFIO_EXTISS3_EXTI13_SS_PE_Pos (6U)
# define AFIO_EXTISS3_EXTI13_SS_PE_Msk (0x1U << AFIO_EXTISS3_EXTI13_SS_PE_Pos) /*!< 0x00000040 */
# define AFIO_EXTISS3_EXTI13_SS_PE AFIO_EXTISS3_EXTI13_SS_PE_Msk /*!< PE[13] pin */
# define AFIO_EXTISS3_EXTI13_SS_PF_Pos (4U)
# define AFIO_EXTISS3_EXTI13_SS_PF_Msk (0x5U << AFIO_EXTISS3_EXTI13_SS_PF_Pos) /*!< 0x00000050 */
# define AFIO_EXTISS3_EXTI13_SS_PF AFIO_EXTISS3_EXTI13_SS_PF_Msk /*!< PF[13] pin */
# define AFIO_EXTISS3_EXTI13_SS_PG_Pos (5U)
# define AFIO_EXTISS3_EXTI13_SS_PG_Msk (0x3U << AFIO_EXTISS3_EXTI13_SS_PG_Pos) /*!< 0x00000060 */
# define AFIO_EXTISS3_EXTI13_SS_PG AFIO_EXTISS3_EXTI13_SS_PG_Msk /*!< PG[13] pin */
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/*!< EXTI14 configuration */
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# define AFIO_EXTISS3_EXTI14_SS_PA 0x00000000U /*!< PA[14] pin */
# define AFIO_EXTISS3_EXTI14_SS_PB_Pos (8U)
# define AFIO_EXTISS3_EXTI14_SS_PB_Msk (0x1U << AFIO_EXTISS3_EXTI14_SS_PB_Pos) /*!< 0x00000100 */
# define AFIO_EXTISS3_EXTI14_SS_PB AFIO_EXTISS3_EXTI14_SS_PB_Msk /*!< PB[14] pin */
# define AFIO_EXTISS3_EXTI14_SS_PC_Pos (9U)
# define AFIO_EXTISS3_EXTI14_SS_PC_Msk (0x1U << AFIO_EXTISS3_EXTI14_SS_PC_Pos) /*!< 0x00000200 */
# define AFIO_EXTISS3_EXTI14_SS_PC AFIO_EXTISS3_EXTI14_SS_PC_Msk /*!< PC[14] pin */
# define AFIO_EXTISS3_EXTI14_SS_PD_Pos (8U)
# define AFIO_EXTISS3_EXTI14_SS_PD_Msk (0x3U << AFIO_EXTISS3_EXTI14_SS_PD_Pos) /*!< 0x00000300 */
# define AFIO_EXTISS3_EXTI14_SS_PD AFIO_EXTISS3_EXTI14_SS_PD_Msk /*!< PD[14] pin */
# define AFIO_EXTISS3_EXTI14_SS_PE_Pos (10U)
# define AFIO_EXTISS3_EXTI14_SS_PE_Msk (0x1U << AFIO_EXTISS3_EXTI14_SS_PE_Pos) /*!< 0x00000400 */
# define AFIO_EXTISS3_EXTI14_SS_PE AFIO_EXTISS3_EXTI14_SS_PE_Msk /*!< PE[14] pin */
# define AFIO_EXTISS3_EXTI14_SS_PF_Pos (8U)
# define AFIO_EXTISS3_EXTI14_SS_PF_Msk (0x5U << AFIO_EXTISS3_EXTI14_SS_PF_Pos) /*!< 0x00000500 */
# define AFIO_EXTISS3_EXTI14_SS_PF AFIO_EXTISS3_EXTI14_SS_PF_Msk /*!< PF[14] pin */
# define AFIO_EXTISS3_EXTI14_SS_PG_Pos (9U)
# define AFIO_EXTISS3_EXTI14_SS_PG_Msk (0x3U << AFIO_EXTISS3_EXTI14_SS_PG_Pos) /*!< 0x00000600 */
# define AFIO_EXTISS3_EXTI14_SS_PG AFIO_EXTISS3_EXTI14_SS_PG_Msk /*!< PG[14] pin */
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/*!< EXTI15 configuration */
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# define AFIO_EXTISS3_EXTI15_SS_PA 0x00000000U /*!< PA[15] pin */
# define AFIO_EXTISS3_EXTI15_SS_PB_Pos (12U)
# define AFIO_EXTISS3_EXTI15_SS_PB_Msk (0x1U << AFIO_EXTISS3_EXTI15_SS_PB_Pos) /*!< 0x00001000 */
# define AFIO_EXTISS3_EXTI15_SS_PB AFIO_EXTISS3_EXTI15_SS_PB_Msk /*!< PB[15] pin */
# define AFIO_EXTISS3_EXTI15_SS_PC_Pos (13U)
# define AFIO_EXTISS3_EXTI15_SS_PC_Msk (0x1U << AFIO_EXTISS3_EXTI15_SS_PC_Pos) /*!< 0x00002000 */
# define AFIO_EXTISS3_EXTI15_SS_PC AFIO_EXTISS3_EXTI15_SS_PC_Msk /*!< PC[15] pin */
# define AFIO_EXTISS3_EXTI15_SS_PD_Pos (12U)
# define AFIO_EXTISS3_EXTI15_SS_PD_Msk (0x3U << AFIO_EXTISS3_EXTI15_SS_PD_Pos) /*!< 0x00003000 */
# define AFIO_EXTISS3_EXTI15_SS_PD AFIO_EXTISS3_EXTI15_SS_PD_Msk /*!< PD[15] pin */
# define AFIO_EXTISS3_EXTI15_SS_PE_Pos (14U)
# define AFIO_EXTISS3_EXTI15_SS_PE_Msk (0x1U << AFIO_EXTISS3_EXTI15_SS_PE_Pos) /*!< 0x00004000 */
# define AFIO_EXTISS3_EXTI15_SS_PE AFIO_EXTISS3_EXTI15_SS_PE_Msk /*!< PE[15] pin */
# define AFIO_EXTISS3_EXTI15_SS_PF_Pos (12U)
# define AFIO_EXTISS3_EXTI15_SS_PF_Msk (0x5U << AFIO_EXTISS3_EXTI15_SS_PF_Pos) /*!< 0x00005000 */
# define AFIO_EXTISS3_EXTI15_SS_PF AFIO_EXTISS3_EXTI15_SS_PF_Msk /*!< PF[15] pin */
# define AFIO_EXTISS3_EXTI15_SS_PG_Pos (13U)
# define AFIO_EXTISS3_EXTI15_SS_PG_Msk (0x3U << AFIO_EXTISS3_EXTI15_SS_PG_Pos) /*!< 0x00006000 */
# define AFIO_EXTISS3_EXTI15_SS_PG AFIO_EXTISS3_EXTI15_SS_PG_Msk /*!< PG[15] pin */
/****************** Bit definition for AFIO_PCF1 register ******************/
# define AFIO_PCF1_EXMC_NADV_REMAP_Pos (10U)
# define AFIO_PCF1_EXMC_NADV_REMAP_Msk (0x1U << AFIO_PCF1_EXMC_NADV_REMAP_Pos) /*!< 0x00000400 */
# define AFIO_PCF1_EXMC_NADV_REMAP AFIO_PCF1_EXMC_NADV_REMAP_Msk /*!< FSMC NADV remapping */
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/******************************************************************************/
/* */
/* External Interrupt/Event Controller */
/* */
/******************************************************************************/
/******************* Bit definition for EXTI_IMR register *******************/
# define EXTI_IMR_MR0_Pos (0U)
# define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
# define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
# define EXTI_IMR_MR1_Pos (1U)
# define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
# define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
# define EXTI_IMR_MR2_Pos (2U)
# define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
# define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
# define EXTI_IMR_MR3_Pos (3U)
# define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
# define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
# define EXTI_IMR_MR4_Pos (4U)
# define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
# define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
# define EXTI_IMR_MR5_Pos (5U)
# define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
# define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
# define EXTI_IMR_MR6_Pos (6U)
# define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
# define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
# define EXTI_IMR_MR7_Pos (7U)
# define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
# define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
# define EXTI_IMR_MR8_Pos (8U)
# define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
# define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
# define EXTI_IMR_MR9_Pos (9U)
# define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
# define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
# define EXTI_IMR_MR10_Pos (10U)
# define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
# define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
# define EXTI_IMR_MR11_Pos (11U)
# define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
# define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
# define EXTI_IMR_MR12_Pos (12U)
# define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
# define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
# define EXTI_IMR_MR13_Pos (13U)
# define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
# define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
# define EXTI_IMR_MR14_Pos (14U)
# define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
# define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
# define EXTI_IMR_MR15_Pos (15U)
# define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
# define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
# define EXTI_IMR_MR16_Pos (16U)
# define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
# define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
# define EXTI_IMR_MR17_Pos (17U)
# define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
# define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
# define EXTI_IMR_MR18_Pos (18U)
# define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
# define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
# define EXTI_IMR_MR19_Pos (19U)
# define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
# define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
/* References Defines */
# define EXTI_IMR_IM0 EXTI_IMR_MR0
# define EXTI_IMR_IM1 EXTI_IMR_MR1
# define EXTI_IMR_IM2 EXTI_IMR_MR2
# define EXTI_IMR_IM3 EXTI_IMR_MR3
# define EXTI_IMR_IM4 EXTI_IMR_MR4
# define EXTI_IMR_IM5 EXTI_IMR_MR5
# define EXTI_IMR_IM6 EXTI_IMR_MR6
# define EXTI_IMR_IM7 EXTI_IMR_MR7
# define EXTI_IMR_IM8 EXTI_IMR_MR8
# define EXTI_IMR_IM9 EXTI_IMR_MR9
# define EXTI_IMR_IM10 EXTI_IMR_MR10
# define EXTI_IMR_IM11 EXTI_IMR_MR11
# define EXTI_IMR_IM12 EXTI_IMR_MR12
# define EXTI_IMR_IM13 EXTI_IMR_MR13
# define EXTI_IMR_IM14 EXTI_IMR_MR14
# define EXTI_IMR_IM15 EXTI_IMR_MR15
# define EXTI_IMR_IM16 EXTI_IMR_MR16
# define EXTI_IMR_IM17 EXTI_IMR_MR17
# define EXTI_IMR_IM18 EXTI_IMR_MR18
# define EXTI_IMR_IM19 EXTI_IMR_MR19
# define EXTI_IMR_IM 0x000FFFFFU /*!< Interrupt Mask All */
/******************* Bit definition for EXTI_EMR register *******************/
# define EXTI_EMR_MR0_Pos (0U)
# define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
# define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
# define EXTI_EMR_MR1_Pos (1U)
# define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
# define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
# define EXTI_EMR_MR2_Pos (2U)
# define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
# define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
# define EXTI_EMR_MR3_Pos (3U)
# define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
# define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
# define EXTI_EMR_MR4_Pos (4U)
# define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
# define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
# define EXTI_EMR_MR5_Pos (5U)
# define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
# define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
# define EXTI_EMR_MR6_Pos (6U)
# define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
# define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
# define EXTI_EMR_MR7_Pos (7U)
# define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
# define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
# define EXTI_EMR_MR8_Pos (8U)
# define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
# define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
# define EXTI_EMR_MR9_Pos (9U)
# define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
# define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
# define EXTI_EMR_MR10_Pos (10U)
# define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
# define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
# define EXTI_EMR_MR11_Pos (11U)
# define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
# define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
# define EXTI_EMR_MR12_Pos (12U)
# define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
# define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
# define EXTI_EMR_MR13_Pos (13U)
# define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
# define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
# define EXTI_EMR_MR14_Pos (14U)
# define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
# define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
# define EXTI_EMR_MR15_Pos (15U)
# define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
# define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
# define EXTI_EMR_MR16_Pos (16U)
# define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
# define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
# define EXTI_EMR_MR17_Pos (17U)
# define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
# define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
# define EXTI_EMR_MR18_Pos (18U)
# define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
# define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
# define EXTI_EMR_MR19_Pos (19U)
# define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
# define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
/* References Defines */
# define EXTI_EMR_EM0 EXTI_EMR_MR0
# define EXTI_EMR_EM1 EXTI_EMR_MR1
# define EXTI_EMR_EM2 EXTI_EMR_MR2
# define EXTI_EMR_EM3 EXTI_EMR_MR3
# define EXTI_EMR_EM4 EXTI_EMR_MR4
# define EXTI_EMR_EM5 EXTI_EMR_MR5
# define EXTI_EMR_EM6 EXTI_EMR_MR6
# define EXTI_EMR_EM7 EXTI_EMR_MR7
# define EXTI_EMR_EM8 EXTI_EMR_MR8
# define EXTI_EMR_EM9 EXTI_EMR_MR9
# define EXTI_EMR_EM10 EXTI_EMR_MR10
# define EXTI_EMR_EM11 EXTI_EMR_MR11
# define EXTI_EMR_EM12 EXTI_EMR_MR12
# define EXTI_EMR_EM13 EXTI_EMR_MR13
# define EXTI_EMR_EM14 EXTI_EMR_MR14
# define EXTI_EMR_EM15 EXTI_EMR_MR15
# define EXTI_EMR_EM16 EXTI_EMR_MR16
# define EXTI_EMR_EM17 EXTI_EMR_MR17
# define EXTI_EMR_EM18 EXTI_EMR_MR18
# define EXTI_EMR_EM19 EXTI_EMR_MR19
/****************** Bit definition for EXTI_RTSR register *******************/
# define EXTI_RTSR_TR0_Pos (0U)
# define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
# define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
# define EXTI_RTSR_TR1_Pos (1U)
# define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
# define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
# define EXTI_RTSR_TR2_Pos (2U)
# define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
# define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
# define EXTI_RTSR_TR3_Pos (3U)
# define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
# define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
# define EXTI_RTSR_TR4_Pos (4U)
# define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
# define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
# define EXTI_RTSR_TR5_Pos (5U)
# define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
# define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
# define EXTI_RTSR_TR6_Pos (6U)
# define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
# define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
# define EXTI_RTSR_TR7_Pos (7U)
# define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
# define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
# define EXTI_RTSR_TR8_Pos (8U)
# define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
# define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
# define EXTI_RTSR_TR9_Pos (9U)
# define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
# define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
# define EXTI_RTSR_TR10_Pos (10U)
# define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
# define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
# define EXTI_RTSR_TR11_Pos (11U)
# define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
# define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
# define EXTI_RTSR_TR12_Pos (12U)
# define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
# define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
# define EXTI_RTSR_TR13_Pos (13U)
# define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
# define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
# define EXTI_RTSR_TR14_Pos (14U)
# define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
# define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
# define EXTI_RTSR_TR15_Pos (15U)
# define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
# define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
# define EXTI_RTSR_TR16_Pos (16U)
# define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
# define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
# define EXTI_RTSR_TR17_Pos (17U)
# define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
# define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
# define EXTI_RTSR_TR18_Pos (18U)
# define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
# define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
# define EXTI_RTSR_TR19_Pos (19U)
# define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
# define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
/* References Defines */
# define EXTI_RTSR_RT0 EXTI_RTSR_TR0
# define EXTI_RTSR_RT1 EXTI_RTSR_TR1
# define EXTI_RTSR_RT2 EXTI_RTSR_TR2
# define EXTI_RTSR_RT3 EXTI_RTSR_TR3
# define EXTI_RTSR_RT4 EXTI_RTSR_TR4
# define EXTI_RTSR_RT5 EXTI_RTSR_TR5
# define EXTI_RTSR_RT6 EXTI_RTSR_TR6
# define EXTI_RTSR_RT7 EXTI_RTSR_TR7
# define EXTI_RTSR_RT8 EXTI_RTSR_TR8
# define EXTI_RTSR_RT9 EXTI_RTSR_TR9
# define EXTI_RTSR_RT10 EXTI_RTSR_TR10
# define EXTI_RTSR_RT11 EXTI_RTSR_TR11
# define EXTI_RTSR_RT12 EXTI_RTSR_TR12
# define EXTI_RTSR_RT13 EXTI_RTSR_TR13
# define EXTI_RTSR_RT14 EXTI_RTSR_TR14
# define EXTI_RTSR_RT15 EXTI_RTSR_TR15
# define EXTI_RTSR_RT16 EXTI_RTSR_TR16
# define EXTI_RTSR_RT17 EXTI_RTSR_TR17
# define EXTI_RTSR_RT18 EXTI_RTSR_TR18
# define EXTI_RTSR_RT19 EXTI_RTSR_TR19
/****************** Bit definition for EXTI_FTSR register *******************/
# define EXTI_FTSR_TR0_Pos (0U)
# define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
# define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
# define EXTI_FTSR_TR1_Pos (1U)
# define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
# define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
# define EXTI_FTSR_TR2_Pos (2U)
# define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
# define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
# define EXTI_FTSR_TR3_Pos (3U)
# define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
# define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
# define EXTI_FTSR_TR4_Pos (4U)
# define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
# define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
# define EXTI_FTSR_TR5_Pos (5U)
# define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
# define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
# define EXTI_FTSR_TR6_Pos (6U)
# define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
# define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
# define EXTI_FTSR_TR7_Pos (7U)
# define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
# define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
# define EXTI_FTSR_TR8_Pos (8U)
# define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
# define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
# define EXTI_FTSR_TR9_Pos (9U)
# define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
# define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
# define EXTI_FTSR_TR10_Pos (10U)
# define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
# define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
# define EXTI_FTSR_TR11_Pos (11U)
# define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
# define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
# define EXTI_FTSR_TR12_Pos (12U)
# define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
# define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
# define EXTI_FTSR_TR13_Pos (13U)
# define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
# define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
# define EXTI_FTSR_TR14_Pos (14U)
# define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
# define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
# define EXTI_FTSR_TR15_Pos (15U)
# define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
# define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
# define EXTI_FTSR_TR16_Pos (16U)
# define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
# define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
# define EXTI_FTSR_TR17_Pos (17U)
# define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
# define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
# define EXTI_FTSR_TR18_Pos (18U)
# define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
# define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
# define EXTI_FTSR_TR19_Pos (19U)
# define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
# define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
/* References Defines */
# define EXTI_FTSR_FT0 EXTI_FTSR_TR0
# define EXTI_FTSR_FT1 EXTI_FTSR_TR1
# define EXTI_FTSR_FT2 EXTI_FTSR_TR2
# define EXTI_FTSR_FT3 EXTI_FTSR_TR3
# define EXTI_FTSR_FT4 EXTI_FTSR_TR4
# define EXTI_FTSR_FT5 EXTI_FTSR_TR5
# define EXTI_FTSR_FT6 EXTI_FTSR_TR6
# define EXTI_FTSR_FT7 EXTI_FTSR_TR7
# define EXTI_FTSR_FT8 EXTI_FTSR_TR8
# define EXTI_FTSR_FT9 EXTI_FTSR_TR9
# define EXTI_FTSR_FT10 EXTI_FTSR_TR10
# define EXTI_FTSR_FT11 EXTI_FTSR_TR11
# define EXTI_FTSR_FT12 EXTI_FTSR_TR12
# define EXTI_FTSR_FT13 EXTI_FTSR_TR13
# define EXTI_FTSR_FT14 EXTI_FTSR_TR14
# define EXTI_FTSR_FT15 EXTI_FTSR_TR15
# define EXTI_FTSR_FT16 EXTI_FTSR_TR16
# define EXTI_FTSR_FT17 EXTI_FTSR_TR17
# define EXTI_FTSR_FT18 EXTI_FTSR_TR18
# define EXTI_FTSR_FT19 EXTI_FTSR_TR19
/****************** Bit definition for EXTI_SWIER register ******************/
# define EXTI_SWIER_SWIER0_Pos (0U)
# define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
# define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
# define EXTI_SWIER_SWIER1_Pos (1U)
# define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
# define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
# define EXTI_SWIER_SWIER2_Pos (2U)
# define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
# define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
# define EXTI_SWIER_SWIER3_Pos (3U)
# define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
# define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
# define EXTI_SWIER_SWIER4_Pos (4U)
# define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
# define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
# define EXTI_SWIER_SWIER5_Pos (5U)
# define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
# define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
# define EXTI_SWIER_SWIER6_Pos (6U)
# define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
# define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
# define EXTI_SWIER_SWIER7_Pos (7U)
# define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
# define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
# define EXTI_SWIER_SWIER8_Pos (8U)
# define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
# define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
# define EXTI_SWIER_SWIER9_Pos (9U)
# define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
# define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
# define EXTI_SWIER_SWIER10_Pos (10U)
# define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
# define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
# define EXTI_SWIER_SWIER11_Pos (11U)
# define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
# define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
# define EXTI_SWIER_SWIER12_Pos (12U)
# define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
# define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
# define EXTI_SWIER_SWIER13_Pos (13U)
# define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
# define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
# define EXTI_SWIER_SWIER14_Pos (14U)
# define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
# define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
# define EXTI_SWIER_SWIER15_Pos (15U)
# define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
# define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
# define EXTI_SWIER_SWIER16_Pos (16U)
# define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
# define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
# define EXTI_SWIER_SWIER17_Pos (17U)
# define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
# define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
# define EXTI_SWIER_SWIER18_Pos (18U)
# define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
# define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
# define EXTI_SWIER_SWIER19_Pos (19U)
# define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
# define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
/* References Defines */
# define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
# define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
# define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
# define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
# define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
# define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
# define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
# define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
# define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
# define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
# define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
# define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
# define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
# define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
# define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
# define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
# define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
# define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
# define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
# define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
/******************* Bit definition for EXTI_PR register ********************/
# define EXTI_PR_PR0_Pos (0U)
# define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
# define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
# define EXTI_PR_PR1_Pos (1U)
# define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
# define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
# define EXTI_PR_PR2_Pos (2U)
# define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
# define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
# define EXTI_PR_PR3_Pos (3U)
# define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
# define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
# define EXTI_PR_PR4_Pos (4U)
# define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
# define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
# define EXTI_PR_PR5_Pos (5U)
# define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
# define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
# define EXTI_PR_PR6_Pos (6U)
# define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
# define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
# define EXTI_PR_PR7_Pos (7U)
# define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
# define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
# define EXTI_PR_PR8_Pos (8U)
# define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
# define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
# define EXTI_PR_PR9_Pos (9U)
# define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
# define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
# define EXTI_PR_PR10_Pos (10U)
# define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
# define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
# define EXTI_PR_PR11_Pos (11U)
# define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
# define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
# define EXTI_PR_PR12_Pos (12U)
# define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
# define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
# define EXTI_PR_PR13_Pos (13U)
# define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
# define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
# define EXTI_PR_PR14_Pos (14U)
# define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
# define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
# define EXTI_PR_PR15_Pos (15U)
# define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
# define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
# define EXTI_PR_PR16_Pos (16U)
# define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
# define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
# define EXTI_PR_PR17_Pos (17U)
# define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
# define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
# define EXTI_PR_PR18_Pos (18U)
# define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
# define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
# define EXTI_PR_PR19_Pos (19U)
# define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
# define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
/* References Defines */
# define EXTI_PR_PIF0 EXTI_PR_PR0
# define EXTI_PR_PIF1 EXTI_PR_PR1
# define EXTI_PR_PIF2 EXTI_PR_PR2
# define EXTI_PR_PIF3 EXTI_PR_PR3
# define EXTI_PR_PIF4 EXTI_PR_PR4
# define EXTI_PR_PIF5 EXTI_PR_PR5
# define EXTI_PR_PIF6 EXTI_PR_PR6
# define EXTI_PR_PIF7 EXTI_PR_PR7
# define EXTI_PR_PIF8 EXTI_PR_PR8
# define EXTI_PR_PIF9 EXTI_PR_PR9
# define EXTI_PR_PIF10 EXTI_PR_PR10
# define EXTI_PR_PIF11 EXTI_PR_PR11
# define EXTI_PR_PIF12 EXTI_PR_PR12
# define EXTI_PR_PIF13 EXTI_PR_PR13
# define EXTI_PR_PIF14 EXTI_PR_PR14
# define EXTI_PR_PIF15 EXTI_PR_PR15
# define EXTI_PR_PIF16 EXTI_PR_PR16
# define EXTI_PR_PIF17 EXTI_PR_PR17
# define EXTI_PR_PIF18 EXTI_PR_PR18
# define EXTI_PR_PIF19 EXTI_PR_PR19
/******************************************************************************/
/* */
/* DMA Controller */
/* */
/******************************************************************************/
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/******************* Bit definition for DMA_INTF register ********************/
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# define DMA_INTF_GIF0_Pos (0U)
# define DMA_INTF_GIF0_Msk (0x1U << DMA_INTF_GIF0_Pos) /*!< 0x00000001 */
# define DMA_INTF_GIF0 DMA_INTF_GIF0_Msk /*!< Channel 1 Global interrupt flag */
# define DMA_INTF_FTFIF0_Pos (1U)
# define DMA_INTF_FTFIF0_Msk (0x1U << DMA_INTF_FTFIF0_Pos) /*!< 0x00000002 */
# define DMA_INTF_FTFIF0 DMA_INTF_FTFIF0_Msk /*!< Channel 1 Full Transfer finish flag */
# define DMA_INTF_HTFIF0_Pos (2U)
# define DMA_INTF_HTFIF0_Msk (0x1U << DMA_INTF_HTFIF0_Pos) /*!< 0x00000004 */
# define DMA_INTF_HTFIF0 DMA_INTF_HTFIF0_Msk /*!< Channel 1 Half Transfer flag */
# define DMA_INTF_ERRIF0_Pos (3U)
# define DMA_INTF_ERRIF0_Msk (0x1U << DMA_INTF_ERRIF0_Pos) /*!< 0x00000008 */
# define DMA_INTF_ERRIF0 DMA_INTF_ERRIF0_Msk /*!< Channel 1 Transfer Error flag */
# define DMA_INTF_GIF1_Pos (4U)
# define DMA_INTF_GIF1_Msk (0x1U << DMA_INTF_GIF1_Pos) /*!< 0x00000010 */
# define DMA_INTF_GIF1 DMA_INTF_GIF1_Msk /*!< Channel 2 Global interrupt flag */
# define DMA_INTF_FTFIF1_Pos (5U)
# define DMA_INTF_FTFIF1_Msk (0x1U << DMA_INTF_FTFIF1_Pos) /*!< 0x00000020 */
# define DMA_INTF_FTFIF1 DMA_INTF_FTFIF1_Msk /*!< Channel 2 Full Transfer finish flag */
# define DMA_INTF_HTFIF1_Pos (6U)
# define DMA_INTF_HTFIF1_Msk (0x1U << DMA_INTF_HTFIF1_Pos) /*!< 0x00000040 */
# define DMA_INTF_HTFIF1 DMA_INTF_HTFIF1_Msk /*!< Channel 2 Half Transfer flag */
# define DMA_INTF_ERRIF1_Pos (7U)
# define DMA_INTF_ERRIF1_Msk (0x1U << DMA_INTF_ERRIF1_Pos) /*!< 0x00000080 */
# define DMA_INTF_ERRIF1 DMA_INTF_ERRIF1_Msk /*!< Channel 2 Transfer Error flag */
# define DMA_INTF_GIF2_Pos (8U)
# define DMA_INTF_GIF2_Msk (0x1U << DMA_INTF_GIF2_Pos) /*!< 0x00000100 */
# define DMA_INTF_GIF2 DMA_INTF_GIF2_Msk /*!< Channel 3 Global interrupt flag */
# define DMA_INTF_FTFIF2_Pos (9U)
# define DMA_INTF_FTFIF2_Msk (0x1U << DMA_INTF_FTFIF2_Pos) /*!< 0x00000200 */
# define DMA_INTF_FTFIF2 DMA_INTF_FTFIF2_Msk /*!< Channel 3 Full Transfer finish flag */
# define DMA_INTF_HTFIF2_Pos (10U)
# define DMA_INTF_HTFIF2_Msk (0x1U << DMA_INTF_HTFIF2_Pos) /*!< 0x00000400 */
# define DMA_INTF_HTFIF2 DMA_INTF_HTFIF2_Msk /*!< Channel 3 Half Transfer flag */
# define DMA_INTF_ERRIF2_Pos (11U)
# define DMA_INTF_ERRIF2_Msk (0x1U << DMA_INTF_ERRIF2_Pos) /*!< 0x00000800 */
# define DMA_INTF_ERRIF2 DMA_INTF_ERRIF2_Msk /*!< Channel 3 Transfer Error flag */
# define DMA_INTF_GIF3_Pos (12U)
# define DMA_INTF_GIF3_Msk (0x1U << DMA_INTF_GIF3_Pos) /*!< 0x00001000 */
# define DMA_INTF_GIF3 DMA_INTF_GIF3_Msk /*!< Channel 4 Global interrupt flag */
# define DMA_INTF_FTFIF3_Pos (13U)
# define DMA_INTF_FTFIF3_Msk (0x1U << DMA_INTF_FTFIF3_Pos) /*!< 0x00002000 */
# define DMA_INTF_FTFIF3 DMA_INTF_FTFIF3_Msk /*!< Channel 4 Full Transfer finish flag */
# define DMA_INTF_HTFIF3_Pos (14U)
# define DMA_INTF_HTFIF3_Msk (0x1U << DMA_INTF_HTFIF3_Pos) /*!< 0x00004000 */
# define DMA_INTF_HTFIF3 DMA_INTF_HTFIF3_Msk /*!< Channel 4 Half Transfer flag */
# define DMA_INTF_ERRIF3_Pos (15U)
# define DMA_INTF_ERRIF3_Msk (0x1U << DMA_INTF_ERRIF3_Pos) /*!< 0x00008000 */
# define DMA_INTF_ERRIF3 DMA_INTF_ERRIF3_Msk /*!< Channel 4 Transfer Error flag */
# define DMA_INTF_GIF4_Pos (16U)
# define DMA_INTF_GIF4_Msk (0x1U << DMA_INTF_GIF4_Pos) /*!< 0x00010000 */
# define DMA_INTF_GIF4 DMA_INTF_GIF4_Msk /*!< Channel 5 Global interrupt flag */
# define DMA_INTF_FTFIF4_Pos (17U)
# define DMA_INTF_FTFIF4_Msk (0x1U << DMA_INTF_FTFIF4_Pos) /*!< 0x00020000 */
# define DMA_INTF_FTFIF4 DMA_INTF_FTFIF4_Msk /*!< Channel 5 Full Transfer finish flag */
# define DMA_INTF_HTFIF4_Pos (18U)
# define DMA_INTF_HTFIF4_Msk (0x1U << DMA_INTF_HTFIF4_Pos) /*!< 0x00040000 */
# define DMA_INTF_HTFIF4 DMA_INTF_HTFIF4_Msk /*!< Channel 5 Half Transfer flag */
# define DMA_INTF_ERRIF4_Pos (19U)
# define DMA_INTF_ERRIF4_Msk (0x1U << DMA_INTF_ERRIF4_Pos) /*!< 0x00080000 */
# define DMA_INTF_ERRIF4 DMA_INTF_ERRIF4_Msk /*!< Channel 5 Transfer Error flag */
# define DMA_INTF_GIF5_Pos (20U)
# define DMA_INTF_GIF5_Msk (0x1U << DMA_INTF_GIF5_Pos) /*!< 0x00100000 */
# define DMA_INTF_GIF5 DMA_INTF_GIF5_Msk /*!< Channel 6 Global interrupt flag */
# define DMA_INTF_FTFIF5_Pos (21U)
# define DMA_INTF_FTFIF5_Msk (0x1U << DMA_INTF_FTFIF5_Pos) /*!< 0x00200000 */
# define DMA_INTF_FTFIF5 DMA_INTF_FTFIF5_Msk /*!< Channel 6 Full Transfer finish flag */
# define DMA_INTF_HTFIF5_Pos (22U)
# define DMA_INTF_HTFIF5_Msk (0x1U << DMA_INTF_HTFIF5_Pos) /*!< 0x00400000 */
# define DMA_INTF_HTFIF5 DMA_INTF_HTFIF5_Msk /*!< Channel 6 Half Transfer flag */
# define DMA_INTF_ERRIF5_Pos (23U)
# define DMA_INTF_ERRIF5_Msk (0x1U << DMA_INTF_ERRIF5_Pos) /*!< 0x00800000 */
# define DMA_INTF_ERRIF5 DMA_INTF_ERRIF5_Msk /*!< Channel 6 Transfer Error flag */
# define DMA_INTF_GIF6_Pos (24U)
# define DMA_INTF_GIF6_Msk (0x1U << DMA_INTF_GIF6_Pos) /*!< 0x01000000 */
# define DMA_INTF_GIF6 DMA_INTF_GIF6_Msk /*!< Channel 7 Global interrupt flag */
# define DMA_INTF_FTFIF6_Pos (25U)
# define DMA_INTF_FTFIF6_Msk (0x1U << DMA_INTF_FTFIF6_Pos) /*!< 0x02000000 */
# define DMA_INTF_FTFIF6 DMA_INTF_FTFIF6_Msk /*!< Channel 7 Full Transfer finish flag */
# define DMA_INTF_HTFIF6_Pos (26U)
# define DMA_INTF_HTFIF6_Msk (0x1U << DMA_INTF_HTFIF6_Pos) /*!< 0x04000000 */
# define DMA_INTF_HTFIF6 DMA_INTF_HTFIF6_Msk /*!< Channel 7 Half Transfer flag */
# define DMA_INTF_ERRIF6_Pos (27U)
# define DMA_INTF_ERRIF6_Msk (0x1U << DMA_INTF_ERRIF6_Pos) /*!< 0x08000000 */
# define DMA_INTF_ERRIF6 DMA_INTF_ERRIF6_Msk /*!< Channel 7 Transfer Error flag */
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/******************* Bit definition for DMA_INTC register *******************/
# define DMA_INTC_GIFC0_Pos (0U)
# define DMA_INTC_GIFC0_Msk (0x1U << DMA_INTC_GIFC0_Pos) /*!< 0x00000001 */
# define DMA_INTC_GIFC0 DMA_INTC_GIFC0_Msk /*!< Channel 1 Global interrupt clear */
# define DMA_INTC_FTFIFC0_Pos (1U)
# define DMA_INTC_FTFIFC0_Msk (0x1U << DMA_INTC_FTFIFC0_Pos) /*!< 0x00000002 */
# define DMA_INTC_FTFIFC0 DMA_INTC_FTFIFC0_Msk /*!< Channel 1 Transfer Complete clear */
# define DMA_INTC_HTFIFC0_Pos (2U)
# define DMA_INTC_HTFIFC0_Msk (0x1U << DMA_INTC_HTFIFC0_Pos) /*!< 0x00000004 */
# define DMA_INTC_HTFIFC0 DMA_INTC_HTFIFC0_Msk /*!< Channel 1 Half Transfer clear */
# define DMA_INTC_ERRIFC0_Pos (3U)
# define DMA_INTC_ERRIFC0_Msk (0x1U << DMA_INTC_ERRIFC0_Pos) /*!< 0x00000008 */
# define DMA_INTC_ERRIFC0 DMA_INTC_ERRIFC0_Msk /*!< Channel 1 Transfer Error clear */
# define DMA_INTC_GIFC1_Pos (4U)
# define DMA_INTC_GIFC1_Msk (0x1U << DMA_INTC_GIFC1_Pos) /*!< 0x00000010 */
# define DMA_INTC_GIFC1 DMA_INTC_GIFC1_Msk /*!< Channel 2 Global interrupt clear */
# define DMA_INTC_FTFIFC1_Pos (5U)
# define DMA_INTC_FTFIFC1_Msk (0x1U << DMA_INTC_FTFIFC1_Pos) /*!< 0x00000020 */
# define DMA_INTC_FTFIFC1 DMA_INTC_FTFIFC1_Msk /*!< Channel 2 Transfer Complete clear */
# define DMA_INTC_HTFIFC1_Pos (6U)
# define DMA_INTC_HTFIFC1_Msk (0x1U << DMA_INTC_HTFIFC1_Pos) /*!< 0x00000040 */
# define DMA_INTC_HTFIFC1 DMA_INTC_HTFIFC1_Msk /*!< Channel 2 Half Transfer clear */
# define DMA_INTC_ERRIFC1_Pos (7U)
# define DMA_INTC_ERRIFC1_Msk (0x1U << DMA_INTC_ERRIFC1_Pos) /*!< 0x00000080 */
# define DMA_INTC_ERRIFC1 DMA_INTC_ERRIFC1_Msk /*!< Channel 2 Transfer Error clear */
# define DMA_INTC_GIFC2_Pos (8U)
# define DMA_INTC_GIFC2_Msk (0x1U << DMA_INTC_GIFC2_Pos) /*!< 0x00000100 */
# define DMA_INTC_GIFC2 DMA_INTC_GIFC2_Msk /*!< Channel 3 Global interrupt clear */
# define DMA_INTC_FTFIFC2_Pos (9U)
# define DMA_INTC_FTFIFC2_Msk (0x1U << DMA_INTC_FTFIFC2_Pos) /*!< 0x00000200 */
# define DMA_INTC_FTFIFC2 DMA_INTC_FTFIFC2_Msk /*!< Channel 3 Transfer Complete clear */
# define DMA_INTC_HTFIFC2_Pos (10U)
# define DMA_INTC_HTFIFC2_Msk (0x1U << DMA_INTC_HTFIFC2_Pos) /*!< 0x00000400 */
# define DMA_INTC_HTFIFC2 DMA_INTC_HTFIFC2_Msk /*!< Channel 3 Half Transfer clear */
# define DMA_INTC_ERRIFC2_Pos (11U)
# define DMA_INTC_ERRIFC2_Msk (0x1U << DMA_INTC_ERRIFC2_Pos) /*!< 0x00000800 */
# define DMA_INTC_ERRIFC2 DMA_INTC_ERRIFC2_Msk /*!< Channel 3 Transfer Error clear */
# define DMA_INTC_GIFC3_Pos (12U)
# define DMA_INTC_GIFC3_Msk (0x1U << DMA_INTC_GIFC3_Pos) /*!< 0x00001000 */
# define DMA_INTC_GIFC3 DMA_INTC_GIFC3_Msk /*!< Channel 4 Global interrupt clear */
# define DMA_INTC_FTFIFC3_Pos (13U)
# define DMA_INTC_FTFIFC3_Msk (0x1U << DMA_INTC_FTFIFC3_Pos) /*!< 0x00002000 */
# define DMA_INTC_FTFIFC3 DMA_INTC_FTFIFC3_Msk /*!< Channel 4 Transfer Complete clear */
# define DMA_INTC_HTFIFC3_Pos (14U)
# define DMA_INTC_HTFIFC3_Msk (0x1U << DMA_INTC_HTFIFC3_Pos) /*!< 0x00004000 */
# define DMA_INTC_HTFIFC3 DMA_INTC_HTFIFC3_Msk /*!< Channel 4 Half Transfer clear */
# define DMA_INTC_ERRIFC3_Pos (15U)
# define DMA_INTC_ERRIFC3_Msk (0x1U << DMA_INTC_ERRIFC3_Pos) /*!< 0x00008000 */
# define DMA_INTC_ERRIFC3 DMA_INTC_ERRIFC3_Msk /*!< Channel 4 Transfer Error clear */
# define DMA_INTC_GIFC4_Pos (16U)
# define DMA_INTC_GIFC4_Msk (0x1U << DMA_INTC_GIFC4_Pos) /*!< 0x00010000 */
# define DMA_INTC_GIFC4 DMA_INTC_GIFC4_Msk /*!< Channel 5 Global interrupt clear */
# define DMA_INTC_FTFIFC4_Pos (17U)
# define DMA_INTC_FTFIFC4_Msk (0x1U << DMA_INTC_FTFIFC4_Pos) /*!< 0x00020000 */
# define DMA_INTC_FTFIFC4 DMA_INTC_FTFIFC4_Msk /*!< Channel 5 Transfer Complete clear */
# define DMA_INTC_HTFIFC4_Pos (18U)
# define DMA_INTC_HTFIFC4_Msk (0x1U << DMA_INTC_HTFIFC4_Pos) /*!< 0x00040000 */
# define DMA_INTC_HTFIFC4 DMA_INTC_HTFIFC4_Msk /*!< Channel 5 Half Transfer clear */
# define DMA_INTC_ERRIFC4_Pos (19U)
# define DMA_INTC_ERRIFC4_Msk (0x1U << DMA_INTC_ERRIFC4_Pos) /*!< 0x00080000 */
# define DMA_INTC_ERRIFC4 DMA_INTC_ERRIFC4_Msk /*!< Channel 5 Transfer Error clear */
# define DMA_INTC_GIFC5_Pos (20U)
# define DMA_INTC_GIFC5_Msk (0x1U << DMA_INTC_GIFC5_Pos) /*!< 0x00100000 */
# define DMA_INTC_GIFC5 DMA_INTC_GIFC5_Msk /*!< Channel 6 Global interrupt clear */
# define DMA_INTC_FTFIFC5_Pos (21U)
# define DMA_INTC_FTFIFC5_Msk (0x1U << DMA_INTC_FTFIFC5_Pos) /*!< 0x00200000 */
# define DMA_INTC_FTFIFC5 DMA_INTC_FTFIFC5_Msk /*!< Channel 6 Transfer Complete clear */
# define DMA_INTC_HTFIFC5_Pos (22U)
# define DMA_INTC_HTFIFC5_Msk (0x1U << DMA_INTC_HTFIFC5_Pos) /*!< 0x00400000 */
# define DMA_INTC_HTFIFC5 DMA_INTC_HTFIFC5_Msk /*!< Channel 6 Half Transfer clear */
# define DMA_INTC_ERRIFC5_Pos (23U)
# define DMA_INTC_ERRIFC5_Msk (0x1U << DMA_INTC_ERRIFC5_Pos) /*!< 0x00800000 */
# define DMA_INTC_ERRIFC5 DMA_INTC_ERRIFC5_Msk /*!< Channel 6 Transfer Error clear */
# define DMA_INTC_GIFC6_Pos (24U)
# define DMA_INTC_GIFC6_Msk (0x1U << DMA_INTC_GIFC6_Pos) /*!< 0x01000000 */
# define DMA_INTC_GIFC6 DMA_INTC_GIFC6_Msk /*!< Channel 7 Global interrupt clear */
# define DMA_INTC_FTFIFC6_Pos (25U)
# define DMA_INTC_FTFIFC6_Msk (0x1U << DMA_INTC_FTFIFC6_Pos) /*!< 0x02000000 */
# define DMA_INTC_FTFIFC6 DMA_INTC_FTFIFC6_Msk /*!< Channel 7 Transfer Complete clear */
# define DMA_INTC_HTFIFC6_Pos (26U)
# define DMA_INTC_HTFIFC6_Msk (0x1U << DMA_INTC_HTFIFC6_Pos) /*!< 0x04000000 */
# define DMA_INTC_HTFIFC6 DMA_INTC_HTFIFC6_Msk /*!< Channel 7 Half Transfer clear */
# define DMA_INTC_ERRIFC6_Pos (27U)
# define DMA_INTC_ERRIFC6_Msk (0x1U << DMA_INTC_ERRIFC6_Pos) /*!< 0x08000000 */
# define DMA_INTC_ERRIFC6 DMA_INTC_ERRIFC6_Msk /*!< Channel 7 Transfer Error clear */
/******************* Bit definition for DMA_CTL register *******************/
# define DMA_CTL_CHEN_Pos (0U)
# define DMA_CTL_CHEN_Msk (0x1U << DMA_CTL_CHEN_Pos) /*!< 0x00000001 */
# define DMA_CTL_CHEN DMA_CTL_CHEN_Msk /*!< Channel enable */
# define DMA_CTL_FTFIE_Pos (1U)
# define DMA_CTL_FTFIE_Msk (0x1U << DMA_CTL_FTFIE_Pos) /*!< 0x00000002 */
# define DMA_CTL_FTFIE DMA_CTL_FTFIE_Msk /*!< Transfer complete interrupt enable */
# define DMA_CTL_HTFIE_Pos (2U)
# define DMA_CTL_HTFIE_Msk (0x1U << DMA_CTL_HTFIE_Pos) /*!< 0x00000004 */
# define DMA_CTL_HTFIE DMA_CTL_HTFIE_Msk /*!< Half Transfer interrupt enable */
# define DMA_CTL_ERRIE_Pos (3U)
# define DMA_CTL_ERRIE_Msk (0x1U << DMA_CTL_ERRIE_Pos) /*!< 0x00000008 */
# define DMA_CTL_ERRIE DMA_CTL_ERRIE_Msk /*!< Transfer error interrupt enable */
# define DMA_CTL_DIR_Pos (4U)
# define DMA_CTL_DIR_Msk (0x1U << DMA_CTL_DIR_Pos) /*!< 0x00000010 */
# define DMA_CTL_DIR DMA_CTL_DIR_Msk /*!< Data transfer direction */
# define DMA_CTL_CMEN_Pos (5U)
# define DMA_CTL_CMEN_Msk (0x1U << DMA_CTL_CMEN_Pos) /*!< 0x00000020 */
# define DMA_CTL_CMEN DMA_CTL_CMEN_Msk /*!< Circular mode */
# define DMA_CTL_PNAGA_Pos (6U)
# define DMA_CTL_PNAGA_Msk (0x1U << DMA_CTL_PNAGA_Pos) /*!< 0x00000040 */
# define DMA_CTL_PNAGA DMA_CTL_PNAGA_Msk /*!< Peripheral increment mode */
# define DMA_CTL_MNAGA_Pos (7U)
# define DMA_CTL_MNAGA_Msk (0x1U << DMA_CTL_MNAGA_Pos) /*!< 0x00000080 */
# define DMA_CTL_MNAGA DMA_CTL_MNAGA_Msk /*!< Memory increment mode */
# define DMA_CTL_PWIDTH_Pos (8U)
# define DMA_CTL_PWIDTH_Msk (0x3U << DMA_CTL_PWIDTH_Pos) /*!< 0x00000300 */
# define DMA_CTL_PWIDTH DMA_CTL_PWIDTH_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
# define DMA_CTL_PWIDTH_0 (0x1U << DMA_CTL_PWIDTH_Pos) /*!< 0x00000100 */
# define DMA_CTL_PWIDTH_1 (0x2U << DMA_CTL_PWIDTH_Pos) /*!< 0x00000200 */
# define DMA_CTL_MWIDTH_Pos (10U)
# define DMA_CTL_MWIDTH_Msk (0x3U << DMA_CTL_MWIDTH_Pos) /*!< 0x00000C00 */
# define DMA_CTL_MWIDTH DMA_CTL_MWIDTH_Msk /*!< MSIZE[1:0] bits (Memory size) */
# define DMA_CTL_MWIDTH_0 (0x1U << DMA_CTL_MWIDTH_Pos) /*!< 0x00000400 */
# define DMA_CTL_MWIDTH_1 (0x2U << DMA_CTL_MWIDTH_Pos) /*!< 0x00000800 */
# define DMA_CTL_PRIO_Pos (12U)
# define DMA_CTL_PRIO_Msk (0x3U << DMA_CTL_PRIO_Pos) /*!< 0x00003000 */
# define DMA_CTL_PRIO DMA_CTL_PRIO_Msk /*!< PL[1:0] bits(Channel Priority level) */
# define DMA_CTL_PRIO_0 (0x1U << DMA_CTL_PRIO_Pos) /*!< 0x00001000 */
# define DMA_CTL_PRIO_1 (0x2U << DMA_CTL_PRIO_Pos) /*!< 0x00002000 */
# define DMA_CTL_M2M_Pos (14U)
# define DMA_CTL_M2M_Msk (0x1U << DMA_CTL_M2M_Pos) /*!< 0x00004000 */
# define DMA_CTL_M2M DMA_CTL_M2M_Msk /*!< Memory to memory mode */
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/****************** Bit definition for DMA_CNT register ******************/
# define DMA_CNT_CNT_Pos (0U)
# define DMA_CNT_CNT_Msk (0xFFFFU << DMA_CNT_CNT_Pos) /*!< 0x0000FFFF */
# define DMA_CNT_CNT DMA_CNT_CNT_Msk /*!< Number of data to Transfer */
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/****************** Bit definition for DMA_PADDR register *******************/
# define DMA_PADDR_PADDR_Pos (0U)
# define DMA_PADDR_PADDR_Msk (0xFFFFFFFFU << DMA_PADDR_PADDR_Pos) /*!< 0xFFFFFFFF */
# define DMA_PADDR_PADDR DMA_PADDR_PADDR_Msk /*!< Peripheral Address */
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/****************** Bit definition for DMA_MADDR register *******************/
# define DMA_MADDR_MADDR_Pos (0U)
# define DMA_MADDR_MADDR_Msk (0xFFFFFFFFU << DMA_MADDR_MADDR_Pos) /*!< 0xFFFFFFFF */
# define DMA_MADDR_MADDR DMA_MADDR_MADDR_Msk /*!< Memory Address */
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/******************************************************************************/
/* */
/* Analog to Digital Converter (ADC) */
/* */
/******************************************************************************/
/*
* @ brief Specific device feature definitions ( not present on all devices in the STM32F1 family )
*/
# define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
/******************** Bit definition for ADC_SR register ********************/
# define ADC_SR_AWD_Pos (0U)
# define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
# define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */
# define ADC_SR_EOS_Pos (1U)
# define ADC_SR_EOS_Msk (0x1U << ADC_SR_EOS_Pos) /*!< 0x00000002 */
# define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
# define ADC_SR_JEOS_Pos (2U)
# define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */
# define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
# define ADC_SR_JSTRT_Pos (3U)
# define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
# define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */
# define ADC_SR_STRT_Pos (4U)
# define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
# define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */
/* Legacy defines */
# define ADC_SR_EOC (ADC_SR_EOS)
# define ADC_SR_JEOC (ADC_SR_JEOS)
/******************* Bit definition for ADC_CR1 register ********************/
# define ADC_CR1_AWDCH_Pos (0U)
# define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
# define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
# define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
# define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
# define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
# define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
# define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
# define ADC_CR1_EOSIE_Pos (5U)
# define ADC_CR1_EOSIE_Msk (0x1U << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */
# define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
# define ADC_CR1_AWDIE_Pos (6U)
# define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
# define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */
# define ADC_CR1_JEOSIE_Pos (7U)
# define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */
# define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
# define ADC_CR1_SCAN_Pos (8U)
# define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
# define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */
# define ADC_CR1_AWDSGL_Pos (9U)
# define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
# define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
# define ADC_CR1_JAUTO_Pos (10U)
# define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
# define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
# define ADC_CR1_DISCEN_Pos (11U)
# define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
# define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
# define ADC_CR1_JDISCEN_Pos (12U)
# define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
# define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
# define ADC_CR1_DISCNUM_Pos (13U)
# define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
# define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
# define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
# define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
# define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
# define ADC_CR1_DUALMOD_Pos (16U)
# define ADC_CR1_DUALMOD_Msk (0xFU << ADC_CR1_DUALMOD_Pos) /*!< 0x000F0000 */
# define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk /*!< ADC multimode mode selection */
# define ADC_CR1_DUALMOD_0 (0x1U << ADC_CR1_DUALMOD_Pos) /*!< 0x00010000 */
# define ADC_CR1_DUALMOD_1 (0x2U << ADC_CR1_DUALMOD_Pos) /*!< 0x00020000 */
# define ADC_CR1_DUALMOD_2 (0x4U << ADC_CR1_DUALMOD_Pos) /*!< 0x00040000 */
# define ADC_CR1_DUALMOD_3 (0x8U << ADC_CR1_DUALMOD_Pos) /*!< 0x00080000 */
# define ADC_CR1_JAWDEN_Pos (22U)
# define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
# define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
# define ADC_CR1_AWDEN_Pos (23U)
# define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
# define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
/* Legacy defines */
# define ADC_CR1_EOCIE (ADC_CR1_EOSIE)
# define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
/******************* Bit definition for ADC_CR2 register ********************/
# define ADC_CR2_ADON_Pos (0U)
# define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
# define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */
# define ADC_CR2_CONT_Pos (1U)
# define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
# define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */
# define ADC_CR2_CAL_Pos (2U)
# define ADC_CR2_CAL_Msk (0x1U << ADC_CR2_CAL_Pos) /*!< 0x00000004 */
# define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */
# define ADC_CR2_RSTCAL_Pos (3U)
# define ADC_CR2_RSTCAL_Msk (0x1U << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */
# define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */
# define ADC_CR2_DMA_Pos (8U)
# define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
# define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
# define ADC_CR2_ALIGN_Pos (11U)
# define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
# define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
# define ADC_CR2_JEXTSEL_Pos (12U)
# define ADC_CR2_JEXTSEL_Msk (0x7U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */
# define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */
# define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */
# define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */
# define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */
# define ADC_CR2_JEXTTRIG_Pos (15U)
# define ADC_CR2_JEXTTRIG_Msk (0x1U << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */
# define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */
# define ADC_CR2_EXTSEL_Pos (17U)
# define ADC_CR2_EXTSEL_Msk (0x7U << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */
# define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */
# define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */
# define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */
# define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */
# define ADC_CR2_EXTTRIG_Pos (20U)
# define ADC_CR2_EXTTRIG_Msk (0x1U << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */
# define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */
# define ADC_CR2_JSWSTART_Pos (21U)
# define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */
# define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */
# define ADC_CR2_SWSTART_Pos (22U)
# define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */
# define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */
# define ADC_CR2_TSVREFE_Pos (23U)
# define ADC_CR2_TSVREFE_Msk (0x1U << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */
# define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */
/****************** Bit definition for ADC_SMPR1 register *******************/
# define ADC_SMPR1_SMP10_Pos (0U)
# define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
# define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */
# define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
# define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
# define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
# define ADC_SMPR1_SMP11_Pos (3U)
# define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
# define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */
# define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
# define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
# define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
# define ADC_SMPR1_SMP12_Pos (6U)
# define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
# define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */
# define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
# define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
# define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
# define ADC_SMPR1_SMP13_Pos (9U)
# define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
# define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */
# define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
# define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
# define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
# define ADC_SMPR1_SMP14_Pos (12U)
# define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
# define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */
# define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
# define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
# define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
# define ADC_SMPR1_SMP15_Pos (15U)
# define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
# define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */
# define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
# define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
# define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
# define ADC_SMPR1_SMP16_Pos (18U)
# define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
# define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */
# define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
# define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
# define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
# define ADC_SMPR1_SMP17_Pos (21U)
# define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
# define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */
# define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
# define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
# define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
/****************** Bit definition for ADC_SMPR2 register *******************/
# define ADC_SMPR2_SMP0_Pos (0U)
# define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
# define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */
# define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
# define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
# define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
# define ADC_SMPR2_SMP1_Pos (3U)
# define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
# define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */
# define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
# define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
# define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
# define ADC_SMPR2_SMP2_Pos (6U)
# define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
# define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */
# define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
# define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
# define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
# define ADC_SMPR2_SMP3_Pos (9U)
# define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
# define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */
# define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
# define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
# define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
# define ADC_SMPR2_SMP4_Pos (12U)
# define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
# define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */
# define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
# define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
# define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
# define ADC_SMPR2_SMP5_Pos (15U)
# define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
# define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */
# define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
# define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
# define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
# define ADC_SMPR2_SMP6_Pos (18U)
# define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
# define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */
# define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
# define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
# define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
# define ADC_SMPR2_SMP7_Pos (21U)
# define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
# define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */
# define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
# define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
# define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
# define ADC_SMPR2_SMP8_Pos (24U)
# define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
# define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */
# define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
# define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
# define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
# define ADC_SMPR2_SMP9_Pos (27U)
# define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
# define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */
# define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
# define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
# define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
/****************** Bit definition for ADC_JOFR1 register *******************/
# define ADC_JOFR1_JOFFSET1_Pos (0U)
# define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
# define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */
/****************** Bit definition for ADC_JOFR2 register *******************/
# define ADC_JOFR2_JOFFSET2_Pos (0U)
# define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
# define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */
/****************** Bit definition for ADC_JOFR3 register *******************/
# define ADC_JOFR3_JOFFSET3_Pos (0U)
# define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
# define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */
/****************** Bit definition for ADC_JOFR4 register *******************/
# define ADC_JOFR4_JOFFSET4_Pos (0U)
# define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
# define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */
/******************* Bit definition for ADC_HTR register ********************/
# define ADC_HTR_HT_Pos (0U)
# define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
# define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */
/******************* Bit definition for ADC_LTR register ********************/
# define ADC_LTR_LT_Pos (0U)
# define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
# define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */
/******************* Bit definition for ADC_SQR1 register *******************/
# define ADC_SQR1_SQ13_Pos (0U)
# define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
# define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
# define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
# define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
# define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
# define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
# define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
# define ADC_SQR1_SQ14_Pos (5U)
# define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
# define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
# define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
# define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
# define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
# define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
# define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
# define ADC_SQR1_SQ15_Pos (10U)
# define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
# define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
# define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
# define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
# define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
# define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
# define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
# define ADC_SQR1_SQ16_Pos (15U)
# define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
# define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
# define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
# define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
# define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
# define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
# define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
# define ADC_SQR1_L_Pos (20U)
# define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
# define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
# define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
# define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
# define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
# define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
/******************* Bit definition for ADC_SQR2 register *******************/
# define ADC_SQR2_SQ7_Pos (0U)
# define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
# define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
# define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
# define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
# define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
# define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
# define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
# define ADC_SQR2_SQ8_Pos (5U)
# define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
# define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
# define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
# define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
# define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
# define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
# define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
# define ADC_SQR2_SQ9_Pos (10U)
# define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
# define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
# define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
# define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
# define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
# define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
# define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
# define ADC_SQR2_SQ10_Pos (15U)
# define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
# define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
# define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
# define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
# define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
# define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
# define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
# define ADC_SQR2_SQ11_Pos (20U)
# define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
# define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */
# define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
# define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
# define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
# define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
# define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
# define ADC_SQR2_SQ12_Pos (25U)
# define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
# define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
# define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
# define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
# define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
# define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
# define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
/******************* Bit definition for ADC_SQR3 register *******************/
# define ADC_SQR3_SQ1_Pos (0U)
# define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
# define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
# define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
# define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
# define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
# define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
# define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
# define ADC_SQR3_SQ2_Pos (5U)
# define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
# define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
# define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
# define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
# define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
# define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
# define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
# define ADC_SQR3_SQ3_Pos (10U)
# define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
# define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
# define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
# define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
# define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
# define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
# define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
# define ADC_SQR3_SQ4_Pos (15U)
# define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
# define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
# define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
# define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
# define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
# define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
# define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
# define ADC_SQR3_SQ5_Pos (20U)
# define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
# define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
# define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
# define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
# define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
# define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
# define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
# define ADC_SQR3_SQ6_Pos (25U)
# define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
# define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
# define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
# define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
# define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
# define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
# define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
/******************* Bit definition for ADC_JSQR register *******************/
# define ADC_JSQR_JSQ1_Pos (0U)
# define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
# define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
# define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
# define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
# define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
# define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
# define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
# define ADC_JSQR_JSQ2_Pos (5U)
# define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
# define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
# define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
# define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
# define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
# define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
# define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
# define ADC_JSQR_JSQ3_Pos (10U)
# define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
# define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
# define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
# define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
# define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
# define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
# define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
# define ADC_JSQR_JSQ4_Pos (15U)
# define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
# define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
# define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
# define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
# define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
# define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
# define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
# define ADC_JSQR_JL_Pos (20U)
# define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
# define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
# define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
# define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
/******************* Bit definition for ADC_JDR1 register *******************/
# define ADC_JDR1_JDATA_Pos (0U)
# define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
# define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
/******************* Bit definition for ADC_JDR2 register *******************/
# define ADC_JDR2_JDATA_Pos (0U)
# define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
# define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
/******************* Bit definition for ADC_JDR3 register *******************/
# define ADC_JDR3_JDATA_Pos (0U)
# define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
# define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
/******************* Bit definition for ADC_JDR4 register *******************/
# define ADC_JDR4_JDATA_Pos (0U)
# define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
# define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
/******************** Bit definition for ADC_DR register ********************/
# define ADC_DR_DATA_Pos (0U)
# define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
# define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
# define ADC_DR_ADC2DATA_Pos (16U)
# define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
# define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */
/******************************************************************************/
/* */
/* Digital to Analog Converter */
/* */
/******************************************************************************/
2021-03-29 03:09:57 -07:00
/******************** Bit definition for DAC_CTL register ********************/
# define DAC_CTL_DEN0_Pos (0U)
# define DAC_CTL_DEN0_Msk (0x1U << DAC_CTL_DEN0_Pos) /*!< 0x00000001 */
# define DAC_CTL_DEN0 DAC_CTL_DEN0_Msk /*!< DAC channel1 enable */
# define DAC_CTL_DBOFF0_Pos (1U)
# define DAC_CTL_DBOFF0_Msk (0x1U << DAC_CTL_DBOFF0_Pos) /*!< 0x00000002 */
# define DAC_CTL_DBOFF0 DAC_CTL_DBOFF0_Msk /*!< DAC channel1 output buffer disable */
# define DAC_CTL_DTEN0_Pos (2U)
# define DAC_CTL_DTEN0_Msk (0x1U << DAC_CTL_DTEN0_Pos) /*!< 0x00000004 */
# define DAC_CTL_DTEN0 DAC_CTL_DTEN0_Msk /*!< DAC channel1 Trigger enable */
# define DAC_CTL_DTSEL0_Pos (3U)
# define DAC_CTL_DTSEL0_Msk (0x7U << DAC_CTL_DTSEL0_Pos) /*!< 0x00000038 */
# define DAC_CTL_DTSEL0 DAC_CTL_DTSEL0_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
# define DAC_CTL_DTSEL0_0 (0x1U << DAC_CTL_DTSEL0_Pos) /*!< 0x00000008 */
# define DAC_CTL_DTSEL0_1 (0x2U << DAC_CTL_DTSEL0_Pos) /*!< 0x00000010 */
# define DAC_CTL_DTSEL0_2 (0x4U << DAC_CTL_DTSEL0_Pos) /*!< 0x00000020 */
# define DAC_CTL_DWM0_Pos (6U)
# define DAC_CTL_DWM0_Msk (0x3U << DAC_CTL_DWM0_Pos) /*!< 0x000000C0 */
# define DAC_CTL_DWM0 DAC_CTL_DWM0_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
# define DAC_CTL_DWM0_0 (0x1U << DAC_CTL_DWM0_Pos) /*!< 0x00000040 */
# define DAC_CTL_DWM0_1 (0x2U << DAC_CTL_DWM0_Pos) /*!< 0x00000080 */
# define DAC_CTL_DWBW0_Pos (8U)
# define DAC_CTL_DWBW0_Msk (0xFU << DAC_CTL_DWBW0_Pos) /*!< 0x00000F00 */
# define DAC_CTL_DWBW0 DAC_CTL_DWBW0_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
# define DAC_CTL_DWBW0_0 (0x1U << DAC_CTL_DWBW0_Pos) /*!< 0x00000100 */
# define DAC_CTL_DWBW0_1 (0x2U << DAC_CTL_DWBW0_Pos) /*!< 0x00000200 */
# define DAC_CTL_DWBW0_2 (0x4U << DAC_CTL_DWBW0_Pos) /*!< 0x00000400 */
# define DAC_CTL_DWBW0_3 (0x8U << DAC_CTL_DWBW0_Pos) /*!< 0x00000800 */
# define DAC_CTL_DDMAEN0_Pos (12U)
# define DAC_CTL_DDMAEN0_Msk (0x1U << DAC_CTL_DDMAEN0_Pos) /*!< 0x00001000 */
# define DAC_CTL_DDMAEN0 DAC_CTL_DDMAEN0_Msk /*!< DAC channel1 DMA enable */
# define DAC_CTL_DEN1_Pos (16U)
# define DAC_CTL_DEN1_Msk (0x1U << DAC_CTL_DEN1_Pos) /*!< 0x00010000 */
# define DAC_CTL_DEN1 DAC_CTL_DEN1_Msk /*!< DAC channel2 enable */
# define DAC_CTL_DBOFF1_Pos (17U)
# define DAC_CTL_DBOFF1_Msk (0x1U << DAC_CTL_DBOFF1_Pos) /*!< 0x00020000 */
# define DAC_CTL_DBOFF1 DAC_CTL_DBOFF1_Msk /*!< DAC channel2 output buffer disable */
# define DAC_CTL_DTEN1_Pos (18U)
# define DAC_CTL_DTEN1_Msk (0x1U << DAC_CTL_DTEN1_Pos) /*!< 0x00040000 */
# define DAC_CTL_DTEN1 DAC_CTL_DTEN1_Msk /*!< DAC channel2 Trigger enable */
# define DAC_CTL_DTSEL1_Pos (19U)
# define DAC_CTL_DTSEL1_Msk (0x7U << DAC_CTL_DTSEL1_Pos) /*!< 0x00380000 */
# define DAC_CTL_DTSEL1 DAC_CTL_DTSEL1_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
# define DAC_CTL_DTSEL1_0 (0x1U << DAC_CTL_DTSEL1_Pos) /*!< 0x00080000 */
# define DAC_CTL_DTSEL1_1 (0x2U << DAC_CTL_DTSEL1_Pos) /*!< 0x00100000 */
# define DAC_CTL_DTSEL1_2 (0x4U << DAC_CTL_DTSEL1_Pos) /*!< 0x00200000 */
# define DAC_CTL_DWM1_Pos (22U)
# define DAC_CTL_DWM1_Msk (0x3U << DAC_CTL_DWM1_Pos) /*!< 0x00C00000 */
# define DAC_CTL_DWM1 DAC_CTL_DWM1_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
# define DAC_CTL_DWM1_0 (0x1U << DAC_CTL_DWM1_Pos) /*!< 0x00400000 */
# define DAC_CTL_DWM1_1 (0x2U << DAC_CTL_DWM1_Pos) /*!< 0x00800000 */
# define DAC_CTL_DWBW1_Pos (24U)
# define DAC_CTL_DWBW1_Msk (0xFU << DAC_CTL_DWBW1_Pos) /*!< 0x0F000000 */
# define DAC_CTL_DWBW1 DAC_CTL_DWBW1_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
# define DAC_CTL_DWBW1_0 (0x1U << DAC_CTL_DWBW1_Pos) /*!< 0x01000000 */
# define DAC_CTL_DWBW1_1 (0x2U << DAC_CTL_DWBW1_Pos) /*!< 0x02000000 */
# define DAC_CTL_DWBW1_2 (0x4U << DAC_CTL_DWBW1_Pos) /*!< 0x04000000 */
# define DAC_CTL_DWBW1_3 (0x8U << DAC_CTL_DWBW1_Pos) /*!< 0x08000000 */
# define DAC_CTL_DDMAEN1_Pos (28U)
# define DAC_CTL_DDMAEN1_Msk (0x1U << DAC_CTL_DDMAEN1_Pos) /*!< 0x10000000 */
# define DAC_CTL_DDMAEN1 DAC_CTL_DDMAEN1_Msk /*!< DAC channel2 DMA enabled */
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/***************** Bit definition for DAC_SWT register ******************/
# define DAC_SWT_SWTR0_Pos (0U)
# define DAC_SWT_SWTR0_Msk (0x1U << DAC_SWT_SWTR0_Pos) /*!< 0x00000001 */
# define DAC_SWT_SWTR0 DAC_SWT_SWTR0_Msk /*!< DAC channel1 software trigger */
# define DAC_SWT_SWTR1_Pos (1U)
# define DAC_SWT_SWTR1_Msk (0x1U << DAC_SWT_SWTR1_Pos) /*!< 0x00000002 */
# define DAC_SWT_SWTR1 DAC_SWT_SWTR1_Msk /*!< DAC channel2 software trigger */
/***************** Bit definition for DAC_DAC0_R12DH register ******************/
# define DAC_DAC0_R12DH_DAC0_DH_Pos (0U)
# define DAC_DAC0_R12DH_DAC0_DH_Msk (0xFFFU << DAC_DAC0_R12DH_DAC0_DH_Pos) /*!< 0x00000FFF */
# define DAC_DAC0_R12DH_DAC0_DH DAC_DAC0_R12DH_DAC0_DH_Msk /*!< DAC channel1 12-bit Right aligned data */
/***************** Bit definition for DAC_DAC0_L12DH register ******************/
# define DAC_DAC0_L12DH_DAC0_DH_Pos (4U)
# define DAC_DAC0_L12DH_DAC0_DH_Msk (0xFFFU << DAC_DAC0_L12DH_DAC0_DH_Pos) /*!< 0x0000FFF0 */
# define DAC_DAC0_L12DH_DAC0_DH DAC_DAC0_L12DH_DAC0_DH_Msk /*!< DAC channel1 12-bit Left aligned data */
/****************** Bit definition for DAC_DAC0_R8DH register ******************/
# define DAC_DAC0_R8DH_DAC0_DH_Pos (0U)
# define DAC_DAC0_R8DH_DAC0_DH_Msk (0xFFU << DAC_DAC0_R8DH_DAC0_DH_Pos) /*!< 0x000000FF */
# define DAC_DAC0_R8DH_DAC0_DH DAC_DAC0_R8DH_DAC0_DH_Msk /*!< DAC channel1 8-bit Right aligned data */
/***************** Bit definition for DAC_DAC1_R12DH register ******************/
# define DAC_DAC1_R12DH_DAC1_DH_Pos (0U)
# define DAC_DAC1_R12DH_DAC1_DH_Msk (0xFFFU << DAC_DAC1_R12DH_DAC1_DH_Pos) /*!< 0x00000FFF */
# define DAC_DAC1_R12DH_DAC1_DH DAC_DAC1_R12DH_DAC1_DH_Msk /*!< DAC channel2 12-bit Right aligned data */
/***************** Bit definition for DAC_DAC1_L12DH register ******************/
# define DAC_DAC1_L12DH_DAC1_DH_Pos (4U)
# define DAC_DAC1_L12DH_DAC1_DH_Msk (0xFFFU << DAC_DAC1_L12DH_DAC1_DH_Pos) /*!< 0x0000FFF0 */
# define DAC_DAC1_L12DH_DAC1_DH DAC_DAC1_L12DH_DAC1_DH_Msk /*!< DAC channel2 12-bit Left aligned data */
/****************** Bit definition for DAC_DAC1_R8DH register ******************/
# define DAC_DAC1_R8DH_DAC1_DH_Pos (0U)
# define DAC_DAC1_R8DH_DAC1_DH_Msk (0xFFU << DAC_DAC1_R8DH_DAC1_DH_Pos) /*!< 0x000000FF */
# define DAC_DAC1_R8DH_DAC1_DH DAC_DAC1_R8DH_DAC1_DH_Msk /*!< DAC channel2 8-bit Right aligned data */
/***************** Bit definition for DAC_DACC_R12DH register ******************/
# define DAC_DACC_R12DH_DAC0_DH_Pos (0U)
# define DAC_DACC_R12DH_DAC0_DH_Msk (0xFFFU << DAC_DACC_R12DH_DAC0_DH_Pos) /*!< 0x00000FFF */
# define DAC_DACC_R12DH_DAC0_DH DAC_DACC_R12DH_DAC0_DH_Msk /*!< DAC channel1 12-bit Right aligned data */
# define DAC_DACC_R12DH_DAC1_DH_Pos (16U)
# define DAC_DACC_R12DH_DAC1_DH_Msk (0xFFFU << DAC_DACC_R12DH_DAC1_DH_Pos) /*!< 0x0FFF0000 */
# define DAC_DACC_R12DH_DAC1_DH DAC_DACC_R12DH_DAC1_DH_Msk /*!< DAC channel2 12-bit Right aligned data */
/***************** Bit definition for DAC_DACC_L12DH register ******************/
# define DAC_DACC_L12DH_DAC0_DH_Pos (4U)
# define DAC_DACC_L12DH_DAC0_DH_Msk (0xFFFU << DAC_DACC_L12DH_DAC0_DH_Pos) /*!< 0x0000FFF0 */
# define DAC_DACC_L12DH_DAC0_DH DAC_DACC_L12DH_DAC0_DH_Msk /*!< DAC channel1 12-bit Left aligned data */
# define DAC_DACC_L12DH_DAC1_DH_Pos (20U)
# define DAC_DACC_L12DH_DAC1_DH_Msk (0xFFFU << DAC_DACC_L12DH_DAC1_DH_Pos) /*!< 0xFFF00000 */
# define DAC_DACC_L12DH_DAC1_DH DAC_DACC_L12DH_DAC1_DH_Msk /*!< DAC channel2 12-bit Left aligned data */
/****************** Bit definition for DAC_DACC_R8DH register ******************/
# define DAC_DACC_R8DH_DAC0_DH_Pos (0U)
# define DAC_DACC_R8DH_DAC0_DH_Msk (0xFFU << DAC_DACC_R8DH_DAC0_DH_Pos) /*!< 0x000000FF */
# define DAC_DACC_R8DH_DAC0_DH DAC_DACC_R8DH_DAC0_DH_Msk /*!< DAC channel1 8-bit Right aligned data */
# define DAC_DACC_R8DH_DAC1_DH_Pos (8U)
# define DAC_DACC_R8DH_DAC1_DH_Msk (0xFFU << DAC_DACC_R8DH_DAC1_DH_Pos) /*!< 0x0000FF00 */
# define DAC_DACC_R8DH_DAC1_DH DAC_DACC_R8DH_DAC1_DH_Msk /*!< DAC channel2 8-bit Right aligned data */
/******************* Bit definition for DAC_DAC0_DO register *******************/
# define DAC_DAC0_DO_DAC0_DO_Pos (0U)
# define DAC_DAC0_DO_DAC0_DO_Msk (0xFFFU << DAC_DAC0_DO_DAC0_DO_Pos) /*!< 0x00000FFF */
# define DAC_DAC0_DO_DAC0_DO DAC_DAC0_DO_DAC0_DO_Msk /*!< DAC channel1 data output */
/******************* Bit definition for DAC_DAC1_DO register *******************/
# define DAC_DAC1_DO_DAC1_DO_Pos (0U)
# define DAC_DAC1_DO_DAC1_DO_Msk (0xFFFU << DAC_DAC1_DO_DAC1_DO_Pos) /*!< 0x00000FFF */
# define DAC_DAC1_DO_DAC1_DO DAC_DAC1_DO_DAC1_DO_Msk /*!< DAC channel2 data output */
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/*****************************************************************************/
/* */
/* Timers (TIM) */
/* */
/*****************************************************************************/
/******************* Bit definition for TIM_CR1 register *******************/
# define TIM_CR1_CEN_Pos (0U)
# define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
# define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
# define TIM_CR1_UDIS_Pos (1U)
# define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
# define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
# define TIM_CR1_URS_Pos (2U)
# define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
# define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
# define TIM_CR1_OPM_Pos (3U)
# define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
# define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
# define TIM_CR1_DIR_Pos (4U)
# define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
# define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
# define TIM_CR1_CMS_Pos (5U)
# define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
# define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
# define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
# define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
# define TIM_CR1_ARPE_Pos (7U)
# define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
# define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
# define TIM_CR1_CKD_Pos (8U)
# define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
# define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
# define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
# define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
/******************* Bit definition for TIM_CR2 register *******************/
# define TIM_CR2_CCPC_Pos (0U)
# define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
# define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
# define TIM_CR2_CCUS_Pos (2U)
# define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
# define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
# define TIM_CR2_CCDS_Pos (3U)
# define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
# define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
# define TIM_CR2_MMS_Pos (4U)
# define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
# define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
# define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
# define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
# define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
# define TIM_CR2_TI1S_Pos (7U)
# define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
# define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
# define TIM_CR2_OIS1_Pos (8U)
# define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
# define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
# define TIM_CR2_OIS1N_Pos (9U)
# define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
# define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
# define TIM_CR2_OIS2_Pos (10U)
# define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
# define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
# define TIM_CR2_OIS2N_Pos (11U)
# define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
# define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
# define TIM_CR2_OIS3_Pos (12U)
# define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
# define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
# define TIM_CR2_OIS3N_Pos (13U)
# define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
# define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
# define TIM_CR2_OIS4_Pos (14U)
# define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
# define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
/******************* Bit definition for TIM_SMCR register ******************/
# define TIM_SMCR_SMS_Pos (0U)
# define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
# define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
# define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
# define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
# define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
# define TIM_SMCR_TS_Pos (4U)
# define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
# define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
# define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
# define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
# define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
# define TIM_SMCR_MSM_Pos (7U)
# define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
# define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
# define TIM_SMCR_ETF_Pos (8U)
# define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
# define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
# define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
# define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
# define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
# define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
# define TIM_SMCR_ETPS_Pos (12U)
# define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
# define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
# define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
# define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
# define TIM_SMCR_ECE_Pos (14U)
# define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
# define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
# define TIM_SMCR_ETP_Pos (15U)
# define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
# define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
/******************* Bit definition for TIM_DIER register ******************/
# define TIM_DIER_UIE_Pos (0U)
# define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
# define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
# define TIM_DIER_CC1IE_Pos (1U)
# define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
# define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
# define TIM_DIER_CC2IE_Pos (2U)
# define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
# define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
# define TIM_DIER_CC3IE_Pos (3U)
# define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
# define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
# define TIM_DIER_CC4IE_Pos (4U)
# define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
# define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
# define TIM_DIER_COMIE_Pos (5U)
# define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
# define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
# define TIM_DIER_TIE_Pos (6U)
# define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
# define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
# define TIM_DIER_BIE_Pos (7U)
# define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
# define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
# define TIM_DIER_UDE_Pos (8U)
# define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
# define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
# define TIM_DIER_CC1DE_Pos (9U)
# define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
# define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
# define TIM_DIER_CC2DE_Pos (10U)
# define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
# define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
# define TIM_DIER_CC3DE_Pos (11U)
# define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
# define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
# define TIM_DIER_CC4DE_Pos (12U)
# define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
# define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
# define TIM_DIER_COMDE_Pos (13U)
# define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
# define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
# define TIM_DIER_TDE_Pos (14U)
# define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
# define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
/******************** Bit definition for TIM_SR register *******************/
# define TIM_SR_UIF_Pos (0U)
# define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
# define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
# define TIM_SR_CC1IF_Pos (1U)
# define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
# define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
# define TIM_SR_CC2IF_Pos (2U)
# define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
# define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
# define TIM_SR_CC3IF_Pos (3U)
# define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
# define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
# define TIM_SR_CC4IF_Pos (4U)
# define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
# define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
# define TIM_SR_COMIF_Pos (5U)
# define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
# define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
# define TIM_SR_TIF_Pos (6U)
# define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
# define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
# define TIM_SR_BIF_Pos (7U)
# define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
# define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
# define TIM_SR_CC1OF_Pos (9U)
# define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
# define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
# define TIM_SR_CC2OF_Pos (10U)
# define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
# define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
# define TIM_SR_CC3OF_Pos (11U)
# define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
# define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
# define TIM_SR_CC4OF_Pos (12U)
# define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
# define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
/******************* Bit definition for TIM_EGR register *******************/
# define TIM_EGR_UG_Pos (0U)
# define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
# define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
# define TIM_EGR_CC1G_Pos (1U)
# define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
# define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
# define TIM_EGR_CC2G_Pos (2U)
# define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
# define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
# define TIM_EGR_CC3G_Pos (3U)
# define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
# define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
# define TIM_EGR_CC4G_Pos (4U)
# define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
# define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
# define TIM_EGR_COMG_Pos (5U)
# define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
# define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
# define TIM_EGR_TG_Pos (6U)
# define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
# define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
# define TIM_EGR_BG_Pos (7U)
# define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
# define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
/****************** Bit definition for TIM_CCMR1 register ******************/
# define TIM_CCMR1_CC1S_Pos (0U)
# define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
# define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
# define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
# define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
# define TIM_CCMR1_OC1FE_Pos (2U)
# define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
# define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
# define TIM_CCMR1_OC1PE_Pos (3U)
# define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
# define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
# define TIM_CCMR1_OC1M_Pos (4U)
# define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
# define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
# define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
# define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
# define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
# define TIM_CCMR1_OC1CE_Pos (7U)
# define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
# define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
# define TIM_CCMR1_CC2S_Pos (8U)
# define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
# define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
# define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
# define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
# define TIM_CCMR1_OC2FE_Pos (10U)
# define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
# define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
# define TIM_CCMR1_OC2PE_Pos (11U)
# define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
# define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
# define TIM_CCMR1_OC2M_Pos (12U)
# define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
# define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
# define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
# define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
# define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
# define TIM_CCMR1_OC2CE_Pos (15U)
# define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
# define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
/*---------------------------------------------------------------------------*/
# define TIM_CCMR1_IC1PSC_Pos (2U)
# define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
# define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
# define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
# define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
# define TIM_CCMR1_IC1F_Pos (4U)
# define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
# define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
# define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
# define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
# define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
# define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
# define TIM_CCMR1_IC2PSC_Pos (10U)
# define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
# define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
# define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
# define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
# define TIM_CCMR1_IC2F_Pos (12U)
# define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
# define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
# define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
# define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
# define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
# define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
/****************** Bit definition for TIM_CCMR2 register ******************/
# define TIM_CCMR2_CC3S_Pos (0U)
# define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
# define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
# define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
# define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
# define TIM_CCMR2_OC3FE_Pos (2U)
# define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
# define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
# define TIM_CCMR2_OC3PE_Pos (3U)
# define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
# define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
# define TIM_CCMR2_OC3M_Pos (4U)
# define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
# define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
# define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
# define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
# define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
# define TIM_CCMR2_OC3CE_Pos (7U)
# define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
# define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
# define TIM_CCMR2_CC4S_Pos (8U)
# define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
# define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
# define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
# define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
# define TIM_CCMR2_OC4FE_Pos (10U)
# define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
# define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
# define TIM_CCMR2_OC4PE_Pos (11U)
# define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
# define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
# define TIM_CCMR2_OC4M_Pos (12U)
# define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
# define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
# define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
# define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
# define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
# define TIM_CCMR2_OC4CE_Pos (15U)
# define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
# define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
/*---------------------------------------------------------------------------*/
# define TIM_CCMR2_IC3PSC_Pos (2U)
# define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
# define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
# define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
# define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
# define TIM_CCMR2_IC3F_Pos (4U)
# define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
# define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
# define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
# define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
# define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
# define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
# define TIM_CCMR2_IC4PSC_Pos (10U)
# define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
# define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
# define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
# define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
# define TIM_CCMR2_IC4F_Pos (12U)
# define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
# define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
# define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
# define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
# define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
# define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
/******************* Bit definition for TIM_CCER register ******************/
# define TIM_CCER_CC1E_Pos (0U)
# define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
# define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
# define TIM_CCER_CC1P_Pos (1U)
# define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
# define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
# define TIM_CCER_CC1NE_Pos (2U)
# define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
# define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
# define TIM_CCER_CC1NP_Pos (3U)
# define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
# define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
# define TIM_CCER_CC2E_Pos (4U)
# define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
# define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
# define TIM_CCER_CC2P_Pos (5U)
# define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
# define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
# define TIM_CCER_CC2NE_Pos (6U)
# define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
# define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
# define TIM_CCER_CC2NP_Pos (7U)
# define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
# define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
# define TIM_CCER_CC3E_Pos (8U)
# define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
# define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
# define TIM_CCER_CC3P_Pos (9U)
# define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
# define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
# define TIM_CCER_CC3NE_Pos (10U)
# define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
# define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
# define TIM_CCER_CC3NP_Pos (11U)
# define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
# define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
# define TIM_CCER_CC4E_Pos (12U)
# define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
# define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
# define TIM_CCER_CC4P_Pos (13U)
# define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
# define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
/******************* Bit definition for TIM_CNT register *******************/
# define TIM_CNT_CNT_Pos (0U)
# define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
# define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
/******************* Bit definition for TIM_PSC register *******************/
# define TIM_PSC_PSC_Pos (0U)
# define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
# define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
/******************* Bit definition for TIM_ARR register *******************/
# define TIM_ARR_ARR_Pos (0U)
# define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
# define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
/******************* Bit definition for TIM_RCR register *******************/
# define TIM_RCR_REP_Pos (0U)
# define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
# define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
/******************* Bit definition for TIM_CCR1 register ******************/
# define TIM_CCR1_CCR1_Pos (0U)
# define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
# define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
/******************* Bit definition for TIM_CCR2 register ******************/
# define TIM_CCR2_CCR2_Pos (0U)
# define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
# define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
/******************* Bit definition for TIM_CCR3 register ******************/
# define TIM_CCR3_CCR3_Pos (0U)
# define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
# define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
/******************* Bit definition for TIM_CCR4 register ******************/
# define TIM_CCR4_CCR4_Pos (0U)
# define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
# define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
/******************* Bit definition for TIM_BDTR register ******************/
# define TIM_BDTR_DTG_Pos (0U)
# define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
# define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
# define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
# define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
# define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
# define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
# define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
# define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
# define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
# define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
# define TIM_BDTR_LOCK_Pos (8U)
# define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
# define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
# define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
# define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
# define TIM_BDTR_OSSI_Pos (10U)
# define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
# define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
# define TIM_BDTR_OSSR_Pos (11U)
# define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
# define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
# define TIM_BDTR_BKE_Pos (12U)
# define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
# define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
# define TIM_BDTR_BKP_Pos (13U)
# define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
# define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
# define TIM_BDTR_AOE_Pos (14U)
# define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
# define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
# define TIM_BDTR_MOE_Pos (15U)
# define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
# define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
/******************* Bit definition for TIM_DCR register *******************/
# define TIM_DCR_DBA_Pos (0U)
# define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
# define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
# define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
# define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
# define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
# define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
# define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
# define TIM_DCR_DBL_Pos (8U)
# define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
# define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
# define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
# define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
# define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
# define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
# define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
/******************* Bit definition for TIM_DMAR register ******************/
# define TIM_DMAR_DMAB_Pos (0U)
# define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
# define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
/******************************************************************************/
/* */
/* Real-Time Clock */
/* */
/******************************************************************************/
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/******************* Bit definition for RTC_INTEN register ********************/
# define RTC_INTEN_SCIE_Pos (0U)
# define RTC_INTEN_SCIE_Msk (0x1U << RTC_INTEN_SCIE_Pos) /*!< 0x00000001 */
# define RTC_INTEN_SCIE RTC_INTEN_SCIE_Msk /*!< Second Interrupt Enable */
# define RTC_INTEN_ALRMIE_Pos (1U)
# define RTC_INTEN_ALRMIE_Msk (0x1U << RTC_INTEN_ALRMIE_Pos) /*!< 0x00000002 */
# define RTC_INTEN_ALRMIE RTC_INTEN_ALRMIE_Msk /*!< Alarm Interrupt Enable */
# define RTC_INTEN_OVIE_Pos (2U)
# define RTC_INTEN_OVIE_Msk (0x1U << RTC_INTEN_OVIE_Pos) /*!< 0x00000004 */
# define RTC_INTEN_OVIE RTC_INTEN_OVIE_Msk /*!< OverfloW Interrupt Enable */
/******************* Bit definition for RTC_CTL register ********************/
# define RTC_CTL_SCIF_Pos (0U)
# define RTC_CTL_SCIF_Msk (0x1U << RTC_CTL_SCIF_Pos) /*!< 0x00000001 */
# define RTC_CTL_SCIF RTC_CTL_SCIF_Msk /*!< Second Flag */
# define RTC_CTL_ALRMIF_Pos (1U)
# define RTC_CTL_ALRMIF_Msk (0x1U << RTC_CTL_ALRMIF_Pos) /*!< 0x00000002 */
# define RTC_CTL_ALRMIF RTC_CTL_ALRMIF_Msk /*!< Alarm Flag */
# define RTC_CTL_OVIF_Pos (2U)
# define RTC_CTL_OVIF_Msk (0x1U << RTC_CTL_OVIF_Pos) /*!< 0x00000004 */
# define RTC_CTL_OVIF RTC_CTL_OVIF_Msk /*!< OverfloW Flag */
# define RTC_CTL_RSYNF_Pos (3U)
# define RTC_CTL_RSYNF_Msk (0x1U << RTC_CTL_RSYNF_Pos) /*!< 0x00000008 */
# define RTC_CTL_RSYNF RTC_CTL_RSYNF_Msk /*!< Registers Synchronized Flag */
# define RTC_CTL_CMF_Pos (4U)
# define RTC_CTL_CMF_Msk (0x1U << RTC_CTL_CMF_Pos) /*!< 0x00000010 */
# define RTC_CTL_CMF RTC_CTL_CMF_Msk /*!< Configuration Flag */
# define RTC_CTL_LWOFF_Pos (5U)
# define RTC_CTL_LWOFF_Msk (0x1U << RTC_CTL_LWOFF_Pos) /*!< 0x00000020 */
# define RTC_CTL_LWOFF RTC_CTL_LWOFF_Msk /*!< RTC operation OFF */
/******************* Bit definition for RTC_PSCH register *******************/
# define RTC_PSCH_PSC_Pos (0U)
# define RTC_PSCH_PSC_Msk (0xFU << RTC_PSCH_PSC_Pos) /*!< 0x0000000F */
# define RTC_PSCH_PSC RTC_PSCH_PSC_Msk /*!< RTC Prescaler Reload Value High */
/******************* Bit definition for RTC_PSCL register *******************/
# define RTC_PSCL_PSC_Pos (0U)
# define RTC_PSCL_PSC_Msk (0xFFFFU << RTC_PSCL_PSC_Pos) /*!< 0x0000FFFF */
# define RTC_PSCL_PSC RTC_PSCL_PSC_Msk /*!< RTC Prescaler Reload Value Low */
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/******************* Bit definition for RTC_DIVH register *******************/
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# define RTC_DIVH_DIV_Pos (0U)
# define RTC_DIVH_DIV_Msk (0xFU << RTC_DIVH_DIV_Pos) /*!< 0x0000000F */
# define RTC_DIVH_RTC_DIV RTC_DIVH_DIV_Msk /*!< RTC Clock Divider High */
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/******************* Bit definition for RTC_DIVL register *******************/
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# define RTC_DIVL_DIV_Pos (0U)
# define RTC_DIVL_DIV_Msk (0xFFFFU << RTC_DIVL_DIV_Pos) /*!< 0x0000FFFF */
# define RTC_DIVL_RTC_DIV RTC_DIVL_DIV_Msk /*!< RTC Clock Divider Low */
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/******************* Bit definition for RTC_CNTH register *******************/
# define RTC_CNTH_RTC_CNT_Pos (0U)
# define RTC_CNTH_RTC_CNT_Msk (0xFFFFU << RTC_CNTH_RTC_CNT_Pos) /*!< 0x0000FFFF */
# define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /*!< RTC Counter High */
/******************* Bit definition for RTC_CNTL register *******************/
# define RTC_CNTL_RTC_CNT_Pos (0U)
# define RTC_CNTL_RTC_CNT_Msk (0xFFFFU << RTC_CNTL_RTC_CNT_Pos) /*!< 0x0000FFFF */
# define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /*!< RTC Counter Low */
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/******************* Bit definition for RTC_ALRMH register *******************/
# define RTC_ALRMH_RTC_ALRM_Pos (0U)
# define RTC_ALRMH_RTC_ALRM_Msk (0xFFFFU << RTC_ALRMH_RTC_ALRM_Pos) /*!< 0x0000FFFF */
# define RTC_ALRMH_RTC_ALRM RTC_ALRMH_RTC_ALRM_Msk /*!< RTC Alarm High */
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/******************* Bit definition for RTC_ALRML register *******************/
# define RTC_ALRML_RTC_ALRM_Pos (0U)
# define RTC_ALRML_RTC_ALRM_Msk (0xFFFFU << RTC_ALRML_RTC_ALRM_Pos) /*!< 0x0000FFFF */
# define RTC_ALRML_RTC_ALRM RTC_ALRML_RTC_ALRM_Msk /*!< RTC Alarm Low */
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/******************************************************************************/
/* */
/* Independent WATCHDOG (IWDG) */
/* */
/******************************************************************************/
/******************* Bit definition for IWDG_KR register ********************/
# define IWDG_KR_KEY_Pos (0U)
# define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
# define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
/******************* Bit definition for IWDG_PR register ********************/
# define IWDG_PR_PR_Pos (0U)
# define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
# define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
# define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
# define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
# define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
/******************* Bit definition for IWDG_RLR register *******************/
# define IWDG_RLR_RL_Pos (0U)
# define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
# define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
/******************* Bit definition for IWDG_SR register ********************/
# define IWDG_SR_PVU_Pos (0U)
# define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
# define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
# define IWDG_SR_RVU_Pos (1U)
# define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
# define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
/******************************************************************************/
/* */
/* Window WATCHDOG (WWDG) */
/* */
/******************************************************************************/
/******************* Bit definition for WWDG_CR register ********************/
# define WWDG_CR_T_Pos (0U)
# define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
# define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
# define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
# define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
# define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
# define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
# define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
# define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
# define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
/* Legacy defines */
# define WWDG_CR_T0 WWDG_CR_T_0
# define WWDG_CR_T1 WWDG_CR_T_1
# define WWDG_CR_T2 WWDG_CR_T_2
# define WWDG_CR_T3 WWDG_CR_T_3
# define WWDG_CR_T4 WWDG_CR_T_4
# define WWDG_CR_T5 WWDG_CR_T_5
# define WWDG_CR_T6 WWDG_CR_T_6
# define WWDG_CR_WDGA_Pos (7U)
# define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
# define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
/******************* Bit definition for WWDG_CFR register *******************/
# define WWDG_CFR_W_Pos (0U)
# define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
# define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
# define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
# define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
# define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
# define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
# define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
# define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
# define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
/* Legacy defines */
# define WWDG_CFR_W0 WWDG_CFR_W_0
# define WWDG_CFR_W1 WWDG_CFR_W_1
# define WWDG_CFR_W2 WWDG_CFR_W_2
# define WWDG_CFR_W3 WWDG_CFR_W_3
# define WWDG_CFR_W4 WWDG_CFR_W_4
# define WWDG_CFR_W5 WWDG_CFR_W_5
# define WWDG_CFR_W6 WWDG_CFR_W_6
# define WWDG_CFR_WDGTB_Pos (7U)
# define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
# define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
# define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
# define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
/* Legacy defines */
# define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
# define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
# define WWDG_CFR_EWI_Pos (9U)
# define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
# define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
/******************* Bit definition for WWDG_SR register ********************/
# define WWDG_SR_EWIF_Pos (0U)
# define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
# define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
/******************************************************************************/
/* */
/* Controller Area Network */
/* */
/******************************************************************************/
/*!< CAN control and status registers */
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/******************* Bit definition for CAN_CTL register ********************/
# define CAN_CTL_IWMOD_Pos (0U)
# define CAN_CTL_IWMOD_Msk (0x1U << CAN_CTL_IWMOD_Pos) /*!< 0x00000001 */
# define CAN_CTL_IWMOD CAN_CTL_IWMOD_Msk /*!< Initialization Request */
# define CAN_CTL_SLPWMOD_Pos (1U)
# define CAN_CTL_SLPWMOD_Msk (0x1U << CAN_CTL_SLPWMOD_Pos) /*!< 0x00000002 */
# define CAN_CTL_SLPWMOD CAN_CTL_SLPWMOD_Msk /*!< Sleep Mode Request */
# define CAN_CTL_TFO_Pos (2U)
# define CAN_CTL_TFO_Msk (0x1U << CAN_CTL_TFO_Pos) /*!< 0x00000004 */
# define CAN_CTL_TFO CAN_CTL_TFO_Msk /*!< Transmit FIFO Priority */
# define CAN_CTL_RFOD_Pos (3U)
# define CAN_CTL_RFOD_Msk (0x1U << CAN_CTL_RFOD_Pos) /*!< 0x00000008 */
# define CAN_CTL_RFOD CAN_CTL_RFOD_Msk /*!< Receive FIFO Locked Mode */
# define CAN_CTL_ARD_Pos (4U)
# define CAN_CTL_ARD_Msk (0x1U << CAN_CTL_ARD_Pos) /*!< 0x00000010 */
# define CAN_CTL_ARD CAN_CTL_ARD_Msk /*!< No Automatic Retransmission */
# define CAN_CTL_AWU_Pos (5U)
# define CAN_CTL_AWU_Msk (0x1U << CAN_CTL_AWU_Pos) /*!< 0x00000020 */
# define CAN_CTL_AWU CAN_CTL_AWU_Msk /*!< Automatic Wakeup Mode */
# define CAN_CTL_ABOR_Pos (6U)
# define CAN_CTL_ABOR_Msk (0x1U << CAN_CTL_ABOR_Pos) /*!< 0x00000040 */
# define CAN_CTL_ABOR CAN_CTL_ABOR_Msk /*!< Automatic Bus-Off Management */
# define CAN_CTL_TTC_Pos (7U)
# define CAN_CTL_TTC_Msk (0x1U << CAN_CTL_TTC_Pos) /*!< 0x00000080 */
# define CAN_CTL_TTC CAN_CTL_TTC_Msk /*!< Time Triggered Communication Mode */
# define CAN_CTL_SWRST_Pos (15U)
# define CAN_CTL_SWRST_Msk (0x1U << CAN_CTL_SWRST_Pos) /*!< 0x00008000 */
# define CAN_CTL_SWRST CAN_CTL_SWRST_Msk /*!< CAN software master reset */
# define CAN_CTL_DFZ_Pos (16U)
# define CAN_CTL_DFZ_Msk (0x1U << CAN_CTL_DFZ_Pos) /*!< 0x00010000 */
# define CAN_CTL_DFZ CAN_CTL_DFZ_Msk /*!< CAN Debug freeze */
/******************* Bit definition for CAN_STAT register ********************/
# define CAN_STAT_IWS_Pos (0U)
# define CAN_STAT_IWS_Msk (0x1U << CAN_STAT_IWS_Pos) /*!< 0x00000001 */
# define CAN_STAT_IWS CAN_STAT_IWS_Msk /*!< Initialization Acknowledge */
# define CAN_STAT_SLPWS_Pos (1U)
# define CAN_STAT_SLPWS_Msk (0x1U << CAN_STAT_SLPWS_Pos) /*!< 0x00000002 */
# define CAN_STAT_SLPWS CAN_STAT_SLPWS_Msk /*!< Sleep Acknowledge */
# define CAN_STAT_ERRIF_Pos (2U)
# define CAN_STAT_ERRIF_Msk (0x1U << CAN_STAT_ERRIF_Pos) /*!< 0x00000004 */
# define CAN_STAT_ERRIF CAN_STAT_ERRIF_Msk /*!< Error Interrupt */
# define CAN_STAT_WUIF_Pos (3U)
# define CAN_STAT_WUIF_Msk (0x1U << CAN_STAT_WUIF_Pos) /*!< 0x00000008 */
# define CAN_STAT_WUIF CAN_STAT_WUIF_Msk /*!< Wakeup Interrupt */
# define CAN_STAT_SLPWSI_Pos (4U)
# define CAN_STAT_SLPWSI_Msk (0x1U << CAN_STAT_SLPWSI_Pos) /*!< 0x00000010 */
# define CAN_STAT_SLPWSI CAN_STAT_SLPWSI_Msk /*!< Sleep Acknowledge Interrupt */
# define CAN_STAT_TS_Pos (8U)
# define CAN_STAT_TS_Msk (0x1U << CAN_STAT_TS_Pos) /*!< 0x00000100 */
# define CAN_STAT_TS CAN_STAT_TS_Msk /*!< Transmit Mode */
# define CAN_STAT_RS_Pos (9U)
# define CAN_STAT_RS_Msk (0x1U << CAN_STAT_RS_Pos) /*!< 0x00000200 */
# define CAN_STAT_RS CAN_STAT_RS_Msk /*!< Receive Mode */
# define CAN_STAT_LASTRX_Pos (10U)
# define CAN_STAT_LASTRX_Msk (0x1U << CAN_STAT_LASTRX_Pos) /*!< 0x00000400 */
# define CAN_STAT_LASTRX CAN_STAT_LASTRX_Msk /*!< Last Sample Point */
# define CAN_STAT_RXL_Pos (11U)
# define CAN_STAT_RXL_Msk (0x1U << CAN_STAT_RXL_Pos) /*!< 0x00000800 */
# define CAN_STAT_RXL CAN_STAT_RXL_Msk /*!< CAN Rx Signal */
/******************* Bit definition for CAN_TSTAT register ********************/
# define CAN_TSTAT_MTF0_Pos (0U)
# define CAN_TSTAT_MTF0_Msk (0x1U << CAN_TSTAT_MTF0_Pos) /*!< 0x00000001 */
# define CAN_TSTAT_MTF0 CAN_TSTAT_MTF0_Msk /*!< Request Completed Mailbox0 */
# define CAN_TSTAT_MTFNERR0_Pos (1U)
# define CAN_TSTAT_MTFNERR0_Msk (0x1U << CAN_TSTAT_MTFNERR0_Pos) /*!< 0x00000002 */
# define CAN_TSTAT_MTFNERR0 CAN_TSTAT_MTFNERR0_Msk /*!< Transmission OK of Mailbox0 */
# define CAN_TSTAT_MAL0_Pos (2U)
# define CAN_TSTAT_MAL0_Msk (0x1U << CAN_TSTAT_MAL0_Pos) /*!< 0x00000004 */
# define CAN_TSTAT_MAL0 CAN_TSTAT_MAL0_Msk /*!< Arbitration Lost for Mailbox0 */
# define CAN_TSTAT_MTE0_Pos (3U)
# define CAN_TSTAT_MTE0_Msk (0x1U << CAN_TSTAT_MTE0_Pos) /*!< 0x00000008 */
# define CAN_TSTAT_MTE0 CAN_TSTAT_MTE0_Msk /*!< Transmission Error of Mailbox0 */
# define CAN_TSTAT_MST0_Pos (7U)
# define CAN_TSTAT_MST0_Msk (0x1U << CAN_TSTAT_MST0_Pos) /*!< 0x00000080 */
# define CAN_TSTAT_MST0 CAN_TSTAT_MST0_Msk /*!< Abort Request for Mailbox0 */
# define CAN_TSTAT_MTF1_Pos (8U)
# define CAN_TSTAT_MTF1_Msk (0x1U << CAN_TSTAT_MTF1_Pos) /*!< 0x00000100 */
# define CAN_TSTAT_MTF1 CAN_TSTAT_MTF1_Msk /*!< Request Completed Mailbox1 */
# define CAN_TSTAT_MTFNERR1_Pos (9U)
# define CAN_TSTAT_MTFNERR1_Msk (0x1U << CAN_TSTAT_MTFNERR1_Pos) /*!< 0x00000200 */
# define CAN_TSTAT_MTFNERR1 CAN_TSTAT_MTFNERR1_Msk /*!< Transmission OK of Mailbox1 */
# define CAN_TSTAT_MAL1_Pos (10U)
# define CAN_TSTAT_MAL1_Msk (0x1U << CAN_TSTAT_MAL1_Pos) /*!< 0x00000400 */
# define CAN_TSTAT_MAL1 CAN_TSTAT_MAL1_Msk /*!< Arbitration Lost for Mailbox1 */
# define CAN_TSTAT_MTE1_Pos (11U)
# define CAN_TSTAT_MTE1_Msk (0x1U << CAN_TSTAT_MTE1_Pos) /*!< 0x00000800 */
# define CAN_TSTAT_MTE1 CAN_TSTAT_MTE1_Msk /*!< Transmission Error of Mailbox1 */
# define CAN_TSTAT_MST1_Pos (15U)
# define CAN_TSTAT_MST1_Msk (0x1U << CAN_TSTAT_MST1_Pos) /*!< 0x00008000 */
# define CAN_TSTAT_MST1 CAN_TSTAT_MST1_Msk /*!< Abort Request for Mailbox 1 */
# define CAN_TSTAT_MTF2_Pos (16U)
# define CAN_TSTAT_MTF2_Msk (0x1U << CAN_TSTAT_MTF2_Pos) /*!< 0x00010000 */
# define CAN_TSTAT_MTF2 CAN_TSTAT_MTF2_Msk /*!< Request Completed Mailbox2 */
# define CAN_TSTAT_MTFNERR2_Pos (17U)
# define CAN_TSTAT_MTFNERR2_Msk (0x1U << CAN_TSTAT_MTFNERR2_Pos) /*!< 0x00020000 */
# define CAN_TSTAT_MTFNERR2 CAN_TSTAT_MTFNERR2_Msk /*!< Transmission OK of Mailbox 2 */
# define CAN_TSTAT_MAL2_Pos (18U)
# define CAN_TSTAT_MAL2_Msk (0x1U << CAN_TSTAT_MAL2_Pos) /*!< 0x00040000 */
# define CAN_TSTAT_MAL2 CAN_TSTAT_MAL2_Msk /*!< Arbitration Lost for mailbox 2 */
# define CAN_TSTAT_MTE2_Pos (19U)
# define CAN_TSTAT_MTE2_Msk (0x1U << CAN_TSTAT_MTE2_Pos) /*!< 0x00080000 */
# define CAN_TSTAT_MTE2 CAN_TSTAT_MTE2_Msk /*!< Transmission Error of Mailbox 2 */
# define CAN_TSTAT_MST2_Pos (23U)
# define CAN_TSTAT_MST2_Msk (0x1U << CAN_TSTAT_MST2_Pos) /*!< 0x00800000 */
# define CAN_TSTAT_MST2 CAN_TSTAT_MST2_Msk /*!< Abort Request for Mailbox 2 */
# define CAN_TSTAT_NUM_Pos (24U)
# define CAN_TSTAT_NUM_Msk (0x3U << CAN_TSTAT_NUM_Pos) /*!< 0x03000000 */
# define CAN_TSTAT_NUM CAN_TSTAT_NUM_Msk /*!< Mailbox Code */
# define CAN_TSTAT_TME_Pos (26U)
# define CAN_TSTAT_TME_Msk (0x7U << CAN_TSTAT_TME_Pos) /*!< 0x1C000000 */
# define CAN_TSTAT_TME CAN_TSTAT_TME_Msk /*!< TME[2:0] bits */
# define CAN_TSTAT_TME0_Pos (26U)
# define CAN_TSTAT_TME0_Msk (0x1U << CAN_TSTAT_TME0_Pos) /*!< 0x04000000 */
# define CAN_TSTAT_TME0 CAN_TSTAT_TME0_Msk /*!< Transmit Mailbox 0 Empty */
# define CAN_TSTAT_TME1_Pos (27U)
# define CAN_TSTAT_TME1_Msk (0x1U << CAN_TSTAT_TME1_Pos) /*!< 0x08000000 */
# define CAN_TSTAT_TME1 CAN_TSTAT_TME1_Msk /*!< Transmit Mailbox 1 Empty */
# define CAN_TSTAT_TME2_Pos (28U)
# define CAN_TSTAT_TME2_Msk (0x1U << CAN_TSTAT_TME2_Pos) /*!< 0x10000000 */
# define CAN_TSTAT_TME2 CAN_TSTAT_TME2_Msk /*!< Transmit Mailbox 2 Empty */
# define CAN_TSTAT_TMLS_Pos (29U)
# define CAN_TSTAT_TMLS_Msk (0x7U << CAN_TSTAT_TMLS_Pos) /*!< 0xE0000000 */
# define CAN_TSTAT_TMLS CAN_TSTAT_TMLS_Msk /*!< LOW[2:0] bits */
# define CAN_TSTAT_TMLS0_Pos (29U)
# define CAN_TSTAT_TMLS0_Msk (0x1U << CAN_TSTAT_TMLS0_Pos) /*!< 0x20000000 */
# define CAN_TSTAT_TMLS0 CAN_TSTAT_TMLS0_Msk /*!< Lowest Priority Flag for Mailbox 0 */
# define CAN_TSTAT_TMLS1_Pos (30U)
# define CAN_TSTAT_TMLS1_Msk (0x1U << CAN_TSTAT_TMLS1_Pos) /*!< 0x40000000 */
# define CAN_TSTAT_TMLS1 CAN_TSTAT_TMLS1_Msk /*!< Lowest Priority Flag for Mailbox 1 */
# define CAN_TSTAT_TMLS2_Pos (31U)
# define CAN_TSTAT_TMLS2_Msk (0x1U << CAN_TSTAT_TMLS2_Pos) /*!< 0x80000000 */
# define CAN_TSTAT_TMLS2 CAN_TSTAT_TMLS2_Msk /*!< Lowest Priority Flag for Mailbox 2 */
/******************* Bit definition for CAN_RFIFO0 register *******************/
# define CAN_RFIFO0_RFL0_Pos (0U)
# define CAN_RFIFO0_RFL0_Msk (0x3U << CAN_RFIFO0_RFL0_Pos) /*!< 0x00000003 */
# define CAN_RFIFO0_RFL0 CAN_RFIFO0_RFL0_Msk /*!< FIFO 0 Message Pending */
# define CAN_RFIFO0_RFF0_Pos (3U)
# define CAN_RFIFO0_RFF0_Msk (0x1U << CAN_RFIFO0_RFF0_Pos) /*!< 0x00000008 */
# define CAN_RFIFO0_RFF0 CAN_RFIFO0_RFF0_Msk /*!< FIFO 0 Full */
# define CAN_RFIFO0_RFO0_Pos (4U)
# define CAN_RFIFO0_RFO0_Msk (0x1U << CAN_RFIFO0_RFO0_Pos) /*!< 0x00000010 */
# define CAN_RFIFO0_RFO0 CAN_RFIFO0_RFO0_Msk /*!< FIFO 0 Overrun */
# define CAN_RFIFO0_RFD0_Pos (5U)
# define CAN_RFIFO0_RFD0_Msk (0x1U << CAN_RFIFO0_RFD0_Pos) /*!< 0x00000020 */
# define CAN_RFIFO0_RFD0 CAN_RFIFO0_RFD0_Msk /*!< Release FIFO 0 Output Mailbox */
/******************* Bit definition for CAN_RFIFO1 register *******************/
# define CAN_RFIFO1_RFL1_Pos (0U)
# define CAN_RFIFO1_RFL1_Msk (0x3U << CAN_RFIFO1_RFL1_Pos) /*!< 0x00000003 */
# define CAN_RFIFO1_RFL1 CAN_RFIFO1_RFL1_Msk /*!< FIFO 1 Message Pending */
# define CAN_RFIFO1_RFF1_Pos (3U)
# define CAN_RFIFO1_RFF1_Msk (0x1U << CAN_RFIFO1_RFF1_Pos) /*!< 0x00000008 */
# define CAN_RFIFO1_RFF1 CAN_RFIFO1_RFF1_Msk /*!< FIFO 1 Full */
# define CAN_RFIFO1_RFO1_Pos (4U)
# define CAN_RFIFO1_RFO1_Msk (0x1U << CAN_RFIFO1_RFO1_Pos) /*!< 0x00000010 */
# define CAN_RFIFO1_RFO1 CAN_RFIFO1_RFO1_Msk /*!< FIFO 1 Overrun */
# define CAN_RFIFO1_RFD1_Pos (5U)
# define CAN_RFIFO1_RFD1_Msk (0x1U << CAN_RFIFO1_RFD1_Pos) /*!< 0x00000020 */
# define CAN_RFIFO1_RFD1 CAN_RFIFO1_RFD1_Msk /*!< Release FIFO 1 Output Mailbox */
/******************** Bit definition for CAN_INTEN register *******************/
# define CAN_INTEN_TMEIE_Pos (0U)
# define CAN_INTEN_TMEIE_Msk (0x1U << CAN_INTEN_TMEIE_Pos) /*!< 0x00000001 */
# define CAN_INTEN_TMEIE CAN_INTEN_TMEIE_Msk /*!< Transmit Mailbox Empty Interrupt Enable */
# define CAN_INTEN_RFNEIE0_Pos (1U)
# define CAN_INTEN_RFNEIE0_Msk (0x1U << CAN_INTEN_RFNEIE0_Pos) /*!< 0x00000002 */
# define CAN_INTEN_RFNEIE0 CAN_INTEN_RFNEIE0_Msk /*!< FIFO Message Pending Interrupt Enable */
# define CAN_INTEN_RFFIE0_Pos (2U)
# define CAN_INTEN_RFFIE0_Msk (0x1U << CAN_INTEN_RFFIE0_Pos) /*!< 0x00000004 */
# define CAN_INTEN_RFFIE0 CAN_INTEN_RFFIE0_Msk /*!< FIFO Full Interrupt Enable */
# define CAN_INTEN_RFOIE0_Pos (3U)
# define CAN_INTEN_RFOIE0_Msk (0x1U << CAN_INTEN_RFOIE0_Pos) /*!< 0x00000008 */
# define CAN_INTEN_RFOIE0 CAN_INTEN_RFOIE0_Msk /*!< FIFO Overrun Interrupt Enable */
# define CAN_INTEN_RFNEIE1_Pos (4U)
# define CAN_INTEN_RFNEIE1_Msk (0x1U << CAN_INTEN_RFNEIE1_Pos) /*!< 0x00000010 */
# define CAN_INTEN_RFNEIE1 CAN_INTEN_RFNEIE1_Msk /*!< FIFO Message Pending Interrupt Enable */
# define CAN_INTEN_RFFIE1_Pos (5U)
# define CAN_INTEN_RFFIE1_Msk (0x1U << CAN_INTEN_RFFIE1_Pos) /*!< 0x00000020 */
# define CAN_INTEN_RFFIE1 CAN_INTEN_RFFIE1_Msk /*!< FIFO Full Interrupt Enable */
# define CAN_INTEN_RFOIE1_Pos (6U)
# define CAN_INTEN_RFOIE1_Msk (0x1U << CAN_INTEN_RFOIE1_Pos) /*!< 0x00000040 */
# define CAN_INTEN_RFOIE1 CAN_INTEN_RFOIE1_Msk /*!< FIFO Overrun Interrupt Enable */
# define CAN_INTEN_WERRIE_Pos (8U)
# define CAN_INTEN_WERRIE_Msk (0x1U << CAN_INTEN_WERRIE_Pos) /*!< 0x00000100 */
# define CAN_INTEN_WERRIE CAN_INTEN_WERRIE_Msk /*!< Error Warning Interrupt Enable */
# define CAN_INTEN_PERRIE_Pos (9U)
# define CAN_INTEN_PERRIE_Msk (0x1U << CAN_INTEN_PERRIE_Pos) /*!< 0x00000200 */
# define CAN_INTEN_PERRIE CAN_INTEN_PERRIE_Msk /*!< Error Passive Interrupt Enable */
# define CAN_INTEN_BOIE_Pos (10U)
# define CAN_INTEN_BOIE_Msk (0x1U << CAN_INTEN_BOIE_Pos) /*!< 0x00000400 */
# define CAN_INTEN_BOIE CAN_INTEN_BOIE_Msk /*!< Bus-Off Interrupt Enable */
# define CAN_INTEN_ERRNIE_Pos (11U)
# define CAN_INTEN_ERRNIE_Msk (0x1U << CAN_INTEN_ERRNIE_Pos) /*!< 0x00000800 */
# define CAN_INTEN_ERRNIE CAN_INTEN_ERRNIE_Msk /*!< Last Error Code Interrupt Enable */
# define CAN_INTEN_ERRIE_Pos (15U)
# define CAN_INTEN_ERRIE_Msk (0x1U << CAN_INTEN_ERRIE_Pos) /*!< 0x00008000 */
# define CAN_INTEN_ERRIE CAN_INTEN_ERRIE_Msk /*!< Error Interrupt Enable */
# define CAN_INTEN_WIE_Pos (16U)
# define CAN_INTEN_WIE_Msk (0x1U << CAN_INTEN_WIE_Pos) /*!< 0x00010000 */
# define CAN_INTEN_WIE CAN_INTEN_WIE_Msk /*!< Wakeup Interrupt Enable */
# define CAN_INTEN_SLPWIE_Pos (17U)
# define CAN_INTEN_SLPWIE_Msk (0x1U << CAN_INTEN_SLPWIE_Pos) /*!< 0x00020000 */
# define CAN_INTEN_SLPWIE CAN_INTEN_SLPWIE_Msk /*!< Sleep Interrupt Enable */
/******************** Bit definition for CAN_ERR register *******************/
# define CAN_ERR_WERR_Pos (0U)
# define CAN_ERR_WERR_Msk (0x1U << CAN_ERR_WERR_Pos) /*!< 0x00000001 */
# define CAN_ERR_WERR CAN_ERR_WERR_Msk /*!< Error Warning Flag */
# define CAN_ERR_PERR_Pos (1U)
# define CAN_ERR_PERR_Msk (0x1U << CAN_ERR_PERR_Pos) /*!< 0x00000002 */
# define CAN_ERR_PERR CAN_ERR_PERR_Msk /*!< Error Passive Flag */
# define CAN_ERR_BOERR_Pos (2U)
# define CAN_ERR_BOERR_Msk (0x1U << CAN_ERR_BOERR_Pos) /*!< 0x00000004 */
# define CAN_ERR_BOERR CAN_ERR_BOERR_Msk /*!< Bus-Off Flag */
# define CAN_ERR_ERRN_Pos (4U)
# define CAN_ERR_ERRN_Msk (0x7U << CAN_ERR_ERRN_Pos) /*!< 0x00000070 */
# define CAN_ERR_ERRN CAN_ERR_ERRN_Msk /*!< LEC[2:0] bits (Last Error Code) */
# define CAN_ERR_ERRN_0 (0x1U << CAN_ERR_ERRN_Pos) /*!< 0x00000010 */
# define CAN_ERR_ERRN_1 (0x2U << CAN_ERR_ERRN_Pos) /*!< 0x00000020 */
# define CAN_ERR_ERRN_2 (0x4U << CAN_ERR_ERRN_Pos) /*!< 0x00000040 */
# define CAN_ERR_TECNT_Pos (16U)
# define CAN_ERR_TECNT_Msk (0xFFU << CAN_ERR_TECNT_Pos) /*!< 0x00FF0000 */
# define CAN_ERR_TECNT CAN_ERR_TECNT_Msk /*!< Least significant byte of the 9-bit Transmit Error Counter */
# define CAN_ERR_RECNT_Pos (24U)
# define CAN_ERR_RECNT_Msk (0xFFU << CAN_ERR_RECNT_Pos) /*!< 0xFF000000 */
# define CAN_ERR_RECNT CAN_ERR_RECNT_Msk /*!< Receive Error Counter */
/******************* Bit definition for CAN_BT register ********************/
# define CAN_BT_BAUDPSC_Pos (0U)
# define CAN_BT_BAUDPSC_Msk (0x3FFU << CAN_BT_BAUDPSC_Pos) /*!< 0x000003FF */
# define CAN_BT_BAUDPSC CAN_BT_BAUDPSC_Msk /*!<Baud Rate Prescaler */
# define CAN_BT_BS1_Pos (16U)
# define CAN_BT_BS1_Msk (0xFU << CAN_BT_BS1_Pos) /*!< 0x000F0000 */
# define CAN_BT_BS1 CAN_BT_BS1_Msk /*!<Time Segment 1 */
# define CAN_BT_BS1_0 (0x1U << CAN_BT_BS1_Pos) /*!< 0x00010000 */
# define CAN_BT_BS1_1 (0x2U << CAN_BT_BS1_Pos) /*!< 0x00020000 */
# define CAN_BT_BS1_2 (0x4U << CAN_BT_BS1_Pos) /*!< 0x00040000 */
# define CAN_BT_BS1_3 (0x8U << CAN_BT_BS1_Pos) /*!< 0x00080000 */
# define CAN_BT_BS2_Pos (20U)
# define CAN_BT_BS2_Msk (0x7U << CAN_BT_BS2_Pos) /*!< 0x00700000 */
# define CAN_BT_BS2 CAN_BT_BS2_Msk /*!<Time Segment 2 */
# define CAN_BT_BS2_0 (0x1U << CAN_BT_BS2_Pos) /*!< 0x00100000 */
# define CAN_BT_BS2_1 (0x2U << CAN_BT_BS2_Pos) /*!< 0x00200000 */
# define CAN_BT_BS2_2 (0x4U << CAN_BT_BS2_Pos) /*!< 0x00400000 */
# define CAN_BT_SJW_Pos (24U)
# define CAN_BT_SJW_Msk (0x3U << CAN_BT_SJW_Pos) /*!< 0x03000000 */
# define CAN_BT_SJW CAN_BT_SJW_Msk /*!<Resynchronization Jump Width */
# define CAN_BT_SJW_0 (0x1U << CAN_BT_SJW_Pos) /*!< 0x01000000 */
# define CAN_BT_SJW_1 (0x2U << CAN_BT_SJW_Pos) /*!< 0x02000000 */
# define CAN_BT_LCMOD_Pos (30U)
# define CAN_BT_LCMOD_Msk (0x1U << CAN_BT_LCMOD_Pos) /*!< 0x40000000 */
# define CAN_BT_LCMOD CAN_BT_LCMOD_Msk /*!<Loop Back Mode (Debug) */
# define CAN_BT_SCMOD_Pos (31U)
# define CAN_BT_SCMOD_Msk (0x1U << CAN_BT_SCMOD_Pos) /*!< 0x80000000 */
# define CAN_BT_SCMOD CAN_BT_SCMOD_Msk /*!<Silent Mode */
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/*!< Mailbox registers */
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/****************** Bit definition for CAN_TMI0 register ********************/
# define CAN_TMI0_TEN_Pos (0U)
# define CAN_TMI0_TEN_Msk (0x1U << CAN_TMI0_TEN_Pos) /*!< 0x00000001 */
# define CAN_TMI0_TEN CAN_TMI0_TEN_Msk /*!< Transmit Mailbox Request */
# define CAN_TMI0_FT_Pos (1U)
# define CAN_TMI0_FT_Msk (0x1U << CAN_TMI0_FT_Pos) /*!< 0x00000002 */
# define CAN_TMI0_FT CAN_TMI0_FT_Msk /*!< Remote Transmission Request */
# define CAN_TMI0_FF_Pos (2U)
# define CAN_TMI0_FF_Msk (0x1U << CAN_TMI0_FF_Pos) /*!< 0x00000004 */
# define CAN_TMI0_FF CAN_TMI0_FF_Msk /*!< Identifier Extension */
# define CAN_TMI0_EFID_Pos (3U)
# define CAN_TMI0_EFID_Msk (0x3FFFFU << CAN_TMI0_EFID_Pos) /*!< 0x001FFFF8 */
# define CAN_TMI0_EFID CAN_TMI0_EFID_Msk /*!< Extended Identifier */
# define CAN_TMI0_SFID_Pos (21U)
# define CAN_TMI0_SFID_Msk (0x7FFU << CAN_TMI0_SFID_Pos) /*!< 0xFFE00000 */
# define CAN_TMI0_SFID CAN_TMI0_SFID_Msk /*!< Standard Identifier or Extended Identifier */
/****************** Bit definition for CAN_TMP0 register *******************/
# define CAN_TMP0_DLENC_Pos (0U)
# define CAN_TMP0_DLENC_Msk (0xFU << CAN_TMP0_DLENC_Pos) /*!< 0x0000000F */
# define CAN_TMP0_DLENC CAN_TMP0_DLENC_Msk /*!< Data Length Code */
# define CAN_TMP0_TSEN_Pos (8U)
# define CAN_TMP0_TSEN_Msk (0x1U << CAN_TMP0_TSEN_Pos) /*!< 0x00000100 */
# define CAN_TMP0_TSEN CAN_TMP0_TSEN_Msk /*!< Transmit Global Time */
# define CAN_TMP0_TS_Pos (16U)
# define CAN_TMP0_TS_Msk (0xFFFFU << CAN_TMP0_TS_Pos) /*!< 0xFFFF0000 */
# define CAN_TMP0_TS CAN_TMP0_TS_Msk /*!< Message Time Stamp */
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/****************** Bit definition for CAN_TMDATA00 register *******************/
# define CAN_TMDATA00_DB0_Pos (0U)
# define CAN_TMDATA00_DB0_Msk (0xFFU << CAN_TMDATA00_DB0_Pos) /*!< 0x000000FF */
# define CAN_TMDATA00_DB0 CAN_TMDATA00_DB0_Msk /*!< Data byte 0 */
# define CAN_TMDATA00_DB1_Pos (8U)
# define CAN_TMDATA00_DB1_Msk (0xFFU << CAN_TMDATA00_DB1_Pos) /*!< 0x0000FF00 */
# define CAN_TMDATA00_DB1 CAN_TMDATA00_DB1_Msk /*!< Data byte 1 */
# define CAN_TMDATA00_DB2_Pos (16U)
# define CAN_TMDATA00_DB2_Msk (0xFFU << CAN_TMDATA00_DB2_Pos) /*!< 0x00FF0000 */
# define CAN_TMDATA00_DB2 CAN_TMDATA00_DB2_Msk /*!< Data byte 2 */
# define CAN_TMDATA00_DB3_Pos (24U)
# define CAN_TMDATA00_DB3_Msk (0xFFU << CAN_TMDATA00_DB3_Pos) /*!< 0xFF000000 */
# define CAN_TMDATA00_DB3 CAN_TMDATA00_DB3_Msk /*!< Data byte 3 */
/****************** Bit definition for CAN_TMDATA10 register *******************/
# define CAN_TMDATA10_DB4_Pos (0U)
# define CAN_TMDATA10_DB4_Msk (0xFFU << CAN_TMDATA10_DB4_Pos) /*!< 0x000000FF */
# define CAN_TMDATA10_DB4 CAN_TMDATA10_DB4_Msk /*!< Data byte 4 */
# define CAN_TMDATA10_DB5_Pos (8U)
# define CAN_TMDATA10_DB5_Msk (0xFFU << CAN_TMDATA10_DB5_Pos) /*!< 0x0000FF00 */
# define CAN_TMDATA10_DB5 CAN_TMDATA10_DB5_Msk /*!< Data byte 5 */
# define CAN_TMDATA10_DB6_Pos (16U)
# define CAN_TMDATA10_DB6_Msk (0xFFU << CAN_TMDATA10_DB6_Pos) /*!< 0x00FF0000 */
# define CAN_TMDATA10_DB6 CAN_TMDATA10_DB6_Msk /*!< Data byte 6 */
# define CAN_TMDATA10_DB7_Pos (24U)
# define CAN_TMDATA10_DB7_Msk (0xFFU << CAN_TMDATA10_DB7_Pos) /*!< 0xFF000000 */
# define CAN_TMDATA10_DB7 CAN_TMDATA10_DB7_Msk /*!< Data byte 7 */
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/******************* Bit definition for CAN_TMI0 register *******************/
# define CAN_TMI0_TEN_Pos (0U)
# define CAN_TMI0_TEN_Msk (0x1U << CAN_TMI0_TEN_Pos) /*!< 0x00000001 */
# define CAN_TMI0_TEN CAN_TMI0_TEN_Msk /*!< Transmit Mailbox Request */
# define CAN_TMI0_FT_Pos (1U)
# define CAN_TMI0_FT_Msk (0x1U << CAN_TMI0_FT_Pos) /*!< 0x00000002 */
# define CAN_TMI0_FT CAN_TMI0_FT_Msk /*!< Remote Transmission Request */
# define CAN_TMI0_FF_Pos (2U)
# define CAN_TMI0_FF_Msk (0x1U << CAN_TMI0_FF_Pos) /*!< 0x00000004 */
# define CAN_TMI0_FF CAN_TMI0_FF_Msk /*!< Identifier Extension */
# define CAN_TMI0_EFID_Pos (3U)
# define CAN_TMI0_EFID_Msk (0x3FFFFU << CAN_TMI0_EFID_Pos) /*!< 0x001FFFF8 */
# define CAN_TMI0_EFID CAN_TMI0_EFID_Msk /*!< Extended Identifier */
# define CAN_TMI0_SFID_Pos (21U)
# define CAN_TMI0_SFID_Msk (0x7FFU << CAN_TMI0_SFID_Pos) /*!< 0xFFE00000 */
# define CAN_TMI0_SFID CAN_TMI0_SFID_Msk /*!< Standard Identifier or Extended Identifier */
/******************* Bit definition for CAN_TMP1 register ******************/
# define CAN_TMP1_DLENC_Pos (0U)
# define CAN_TMP1_DLENC_Msk (0xFU << CAN_TMP1_DLENC_Pos) /*!< 0x0000000F */
# define CAN_TMP1_DLENC CAN_TMP1_DLENC_Msk /*!< Data Length Code */
# define CAN_TMP1_TSEN_Pos (8U)
# define CAN_TMP1_TSEN_Msk (0x1U << CAN_TMP1_TSEN_Pos) /*!< 0x00000100 */
# define CAN_TMP1_TSEN CAN_TMP1_TSEN_Msk /*!< Transmit Global Time */
# define CAN_TMP1_TS_Pos (16U)
# define CAN_TMP1_TS_Msk (0xFFFFU << CAN_TMP1_TS_Pos) /*!< 0xFFFF0000 */
# define CAN_TMP1_TS CAN_TMP1_TS_Msk /*!< Message Time Stamp */
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/******************* Bit definition for CAN_TMDATA00 register ******************/
# define CAN_TMDATA00_DB0_Pos (0U)
# define CAN_TMDATA00_DB0_Msk (0xFFU << CAN_TMDATA00_DB0_Pos) /*!< 0x000000FF */
# define CAN_TMDATA00_DB0 CAN_TMDATA00_DB0_Msk /*!< Data byte 0 */
# define CAN_TMDATA00_DB1_Pos (8U)
# define CAN_TMDATA00_DB1_Msk (0xFFU << CAN_TMDATA00_DB1_Pos) /*!< 0x0000FF00 */
# define CAN_TMDATA00_DB1 CAN_TMDATA00_DB1_Msk /*!< Data byte 1 */
# define CAN_TMDATA00_DB2_Pos (16U)
# define CAN_TMDATA00_DB2_Msk (0xFFU << CAN_TMDATA00_DB2_Pos) /*!< 0x00FF0000 */
# define CAN_TMDATA00_DB2 CAN_TMDATA00_DB2_Msk /*!< Data byte 2 */
# define CAN_TMDATA00_DB3_Pos (24U)
# define CAN_TMDATA00_DB3_Msk (0xFFU << CAN_TMDATA00_DB3_Pos) /*!< 0xFF000000 */
# define CAN_TMDATA00_DB3 CAN_TMDATA00_DB3_Msk /*!< Data byte 3 */
/******************* Bit definition for CAN_TMDATA11 register ******************/
# define CAN_TMDATA11_DB4_Pos (0U)
# define CAN_TMDATA11_DB4_Msk (0xFFU << CAN_TMDATA11_DB4_Pos) /*!< 0x000000FF */
# define CAN_TMDATA11_DB4 CAN_TMDATA11_DB4_Msk /*!< Data byte 4 */
# define CAN_TMDATA11_DB5_Pos (8U)
# define CAN_TMDATA11_DB5_Msk (0xFFU << CAN_TMDATA11_DB5_Pos) /*!< 0x0000FF00 */
# define CAN_TMDATA11_DB5 CAN_TMDATA11_DB5_Msk /*!< Data byte 5 */
# define CAN_TMDATA11_DB6_Pos (16U)
# define CAN_TMDATA11_DB6_Msk (0xFFU << CAN_TMDATA11_DB6_Pos) /*!< 0x00FF0000 */
# define CAN_TMDATA11_DB6 CAN_TMDATA11_DB6_Msk /*!< Data byte 6 */
# define CAN_TMDATA11_DB7_Pos (24U)
# define CAN_TMDATA11_DB7_Msk (0xFFU << CAN_TMDATA11_DB7_Pos) /*!< 0xFF000000 */
# define CAN_TMDATA11_DB7 CAN_TMDATA11_DB7_Msk /*!< Data byte 7 */
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/******************* Bit definition for CAN_TMI2 register *******************/
# define CAN_TMI2_TEN_Pos (0U)
# define CAN_TMI2_TEN_Msk (0x1U << CAN_TMI2_TEN_Pos) /*!< 0x00000001 */
# define CAN_TMI2_TEN CAN_TMI2_TEN_Msk /*!< Transmit Mailbox Request */
# define CAN_TMI2_FT_Pos (1U)
# define CAN_TMI2_FT_Msk (0x1U << CAN_TMI2_FT_Pos) /*!< 0x00000002 */
# define CAN_TMI2_FT CAN_TMI2_FT_Msk /*!< Remote Transmission Request */
# define CAN_TMI2_FF_Pos (2U)
# define CAN_TMI2_FF_Msk (0x1U << CAN_TMI2_FF_Pos) /*!< 0x00000004 */
# define CAN_TMI2_FF CAN_TMI2_FF_Msk /*!< Identifier Extension */
# define CAN_TMI2_EFID_Pos (3U)
# define CAN_TMI2_EFID_Msk (0x3FFFFU << CAN_TMI2_EFID_Pos) /*!< 0x001FFFF8 */
# define CAN_TMI2_EFID CAN_TMI2_EFID_Msk /*!< Extended identifier */
# define CAN_TMI2_SFID_Pos (21U)
# define CAN_TMI2_SFID_Msk (0x7FFU << CAN_TMI2_SFID_Pos) /*!< 0xFFE00000 */
# define CAN_TMI2_SFID CAN_TMI2_SFID_Msk /*!< Standard Identifier or Extended Identifier */
/******************* Bit definition for CAN_TMP2 register ******************/
# define CAN_TMP2_DLENC_Pos (0U)
# define CAN_TMP2_DLENC_Msk (0xFU << CAN_TMP2_DLENC_Pos) /*!< 0x0000000F */
# define CAN_TMP2_DLENC CAN_TMP2_DLENC_Msk /*!< Data Length Code */
# define CAN_TMP2_TSEN_Pos (8U)
# define CAN_TMP2_TSEN_Msk (0x1U << CAN_TMP2_TSEN_Pos) /*!< 0x00000100 */
# define CAN_TMP2_TSEN CAN_TMP2_TSEN_Msk /*!< Transmit Global Time */
# define CAN_TMP2_TS_Pos (16U)
# define CAN_TMP2_TS_Msk (0xFFFFU << CAN_TMP2_TS_Pos) /*!< 0xFFFF0000 */
# define CAN_TMP2_TS CAN_TMP2_TS_Msk /*!< Message Time Stamp */
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/******************* Bit definition for CAN_TMDATA02 register ******************/
# define CAN_TMDATA02_DB0_Pos (0U)
# define CAN_TMDATA02_DB0_Msk (0xFFU << CAN_TMDATA02_DB0_Pos) /*!< 0x000000FF */
# define CAN_TMDATA02_DB0 CAN_TMDATA02_DB0_Msk /*!< Data byte 0 */
# define CAN_TMDATA02_DB1_Pos (8U)
# define CAN_TMDATA02_DB1_Msk (0xFFU << CAN_TMDATA02_DB1_Pos) /*!< 0x0000FF00 */
# define CAN_TMDATA02_DB1 CAN_TMDATA02_DB1_Msk /*!< Data byte 1 */
# define CAN_TMDATA02_DB2_Pos (16U)
# define CAN_TMDATA02_DB2_Msk (0xFFU << CAN_TMDATA02_DB2_Pos) /*!< 0x00FF0000 */
# define CAN_TMDATA02_DB2 CAN_TMDATA02_DB2_Msk /*!< Data byte 2 */
# define CAN_TMDATA02_DB3_Pos (24U)
# define CAN_TMDATA02_DB3_Msk (0xFFU << CAN_TMDATA02_DB3_Pos) /*!< 0xFF000000 */
# define CAN_TMDATA02_DB3 CAN_TMDATA02_DB3_Msk /*!< Data byte 3 */
/******************* Bit definition for CAN_TMDATA12 register ******************/
# define CAN_TMDATA12_DB4_Pos (0U)
# define CAN_TMDATA12_DB4_Msk (0xFFU << CAN_TMDATA12_DB4_Pos) /*!< 0x000000FF */
# define CAN_TMDATA12_DB4 CAN_TMDATA12_DB4_Msk /*!< Data byte 4 */
# define CAN_TMDATA12_DB5_Pos (8U)
# define CAN_TMDATA12_DB5_Msk (0xFFU << CAN_TMDATA12_DB5_Pos) /*!< 0x0000FF00 */
# define CAN_TMDATA12_DB5 CAN_TMDATA12_DB5_Msk /*!< Data byte 5 */
# define CAN_TMDATA12_DB6_Pos (16U)
# define CAN_TMDATA12_DB6_Msk (0xFFU << CAN_TMDATA12_DB6_Pos) /*!< 0x00FF0000 */
# define CAN_TMDATA12_DB6 CAN_TMDATA12_DB6_Msk /*!< Data byte 6 */
# define CAN_TMDATA12_DB7_Pos (24U)
# define CAN_TMDATA12_DB7_Msk (0xFFU << CAN_TMDATA12_DB7_Pos) /*!< 0xFF000000 */
# define CAN_TMDATA12_DB7 CAN_TMDATA12_DB7_Msk /*!< Data byte 7 */
/******************* Bit definition for CAN_RFIFOMI0 register *******************/
# define CAN_RFIFOMI0_FT_Pos (1U)
# define CAN_RFIFOMI0_FT_Msk (0x1U << CAN_RFIFOMI0_FT_Pos) /*!< 0x00000002 */
# define CAN_RFIFOMI0_FT CAN_RFIFOMI0_FT_Msk /*!< Remote Transmission Request */
# define CAN_RFIFOMI0_FF_Pos (2U)
# define CAN_RFIFOMI0_FF_Msk (0x1U << CAN_RFIFOMI0_FF_Pos) /*!< 0x00000004 */
# define CAN_RFIFOMI0_FF CAN_RFIFOMI0_FF_Msk /*!< Identifier Extension */
# define CAN_RFIFOMI0_EFID_Pos (3U)
# define CAN_RFIFOMI0_EFID_Msk (0x3FFFFU << CAN_RFIFOMI0_EFID_Pos) /*!< 0x001FFFF8 */
# define CAN_RFIFOMI0_EFID CAN_RFIFOMI0_EFID_Msk /*!< Extended Identifier */
# define CAN_RFIFOMI0_SFID_Pos (21U)
# define CAN_RFIFOMI0_SFID_Msk (0x7FFU << CAN_RFIFOMI0_SFID_Pos) /*!< 0xFFE00000 */
# define CAN_RFIFOMI0_SFID CAN_RFIFOMI0_SFID_Msk /*!< Standard Identifier or Extended Identifier */
/******************* Bit definition for CAN_RFIFOMP0 register ******************/
# define CAN_RFIFOMP0_DLENC_Pos (0U)
# define CAN_RFIFOMP0_DLENC_Msk (0xFU << CAN_RFIFOMP0_DLENC_Pos) /*!< 0x0000000F */
# define CAN_RFIFOMP0_DLENC CAN_RFIFOMP0_DLENC_Msk /*!< Data Length Code */
# define CAN_RFIFOMP0_FI_Pos (8U)
# define CAN_RFIFOMP0_FI_Msk (0xFFU << CAN_RFIFOMP0_FI_Pos) /*!< 0x0000FF00 */
# define CAN_RFIFOMP0_FI CAN_RFIFOMP0_FI_Msk /*!< Filter Match Index */
# define CAN_RFIFOMP0_TS_Pos (16U)
# define CAN_RFIFOMP0_TS_Msk (0xFFFFU << CAN_RFIFOMP0_TS_Pos) /*!< 0xFFFF0000 */
# define CAN_RFIFOMP0_TS CAN_RFIFOMP0_TS_Msk /*!< Message Time Stamp */
/******************* Bit definition for CAN_RFIFOMDATA00 register ******************/
# define CAN_RFIFOMDATA00_DB0_Pos (0U)
# define CAN_RFIFOMDATA00_DB0_Msk (0xFFU << CAN_RFIFOMDATA00_DB0_Pos) /*!< 0x000000FF */
# define CAN_RFIFOMDATA00_DB0 CAN_RFIFOMDATA00_DB0_Msk /*!< Data byte 0 */
# define CAN_RFIFOMDATA00_DB1_Pos (8U)
# define CAN_RFIFOMDATA00_DB1_Msk (0xFFU << CAN_RFIFOMDATA00_DB1_Pos) /*!< 0x0000FF00 */
# define CAN_RFIFOMDATA00_DB1 CAN_RFIFOMDATA00_DB1_Msk /*!< Data byte 1 */
# define CAN_RFIFOMDATA00_DB2_Pos (16U)
# define CAN_RFIFOMDATA00_DB2_Msk (0xFFU << CAN_RFIFOMDATA00_DB2_Pos) /*!< 0x00FF0000 */
# define CAN_RFIFOMDATA00_DB2 CAN_RFIFOMDATA00_DB2_Msk /*!< Data byte 2 */
# define CAN_RFIFOMDATA00_DB3_Pos (24U)
# define CAN_RFIFOMDATA00_DB3_Msk (0xFFU << CAN_RFIFOMDATA00_DB3_Pos) /*!< 0xFF000000 */
# define CAN_RFIFOMDATA00_DB3 CAN_RFIFOMDATA00_DB3_Msk /*!< Data byte 3 */
/******************* Bit definition for CAN_RFIFOMDATA10 register ******************/
# define CAN_RFIFOMDATA10_DB4_Pos (0U)
# define CAN_RFIFOMDATA10_DB4_Msk (0xFFU << CAN_RFIFOMDATA10_DB4_Pos) /*!< 0x000000FF */
# define CAN_RFIFOMDATA10_DB4 CAN_RFIFOMDATA10_DB4_Msk /*!< Data byte 4 */
# define CAN_RFIFOMDATA10_DB5_Pos (8U)
# define CAN_RFIFOMDATA10_DB5_Msk (0xFFU << CAN_RFIFOMDATA10_DB5_Pos) /*!< 0x0000FF00 */
# define CAN_RFIFOMDATA10_DB5 CAN_RFIFOMDATA10_DB5_Msk /*!< Data byte 5 */
# define CAN_RFIFOMDATA10_DB6_Pos (16U)
# define CAN_RFIFOMDATA10_DB6_Msk (0xFFU << CAN_RFIFOMDATA10_DB6_Pos) /*!< 0x00FF0000 */
# define CAN_RFIFOMDATA10_DB6 CAN_RFIFOMDATA10_DB6_Msk /*!< Data byte 6 */
# define CAN_RFIFOMDATA10_DB7_Pos (24U)
# define CAN_RFIFOMDATA10_DB7_Msk (0xFFU << CAN_RFIFOMDATA10_DB7_Pos) /*!< 0xFF000000 */
# define CAN_RFIFOMDATA10_DB7 CAN_RFIFOMDATA10_DB7_Msk /*!< Data byte 7 */
/******************* Bit definition for CAN_RFIFOMI1 register *******************/
# define CAN_RFIFOMI1_FT_Pos (1U)
# define CAN_RFIFOMI1_FT_Msk (0x1U << CAN_RFIFOMI1_FT_Pos) /*!< 0x00000002 */
# define CAN_RFIFOMI1_FT CAN_RFIFOMI1_FT_Msk /*!< Remote Transmission Request */
# define CAN_RFIFOMI1_FF_Pos (2U)
# define CAN_RFIFOMI1_FF_Msk (0x1U << CAN_RFIFOMI1_FF_Pos) /*!< 0x00000004 */
# define CAN_RFIFOMI1_FF CAN_RFIFOMI1_FF_Msk /*!< Identifier Extension */
# define CAN_RFIFOMI1_EFID_Pos (3U)
# define CAN_RFIFOMI1_EFID_Msk (0x3FFFFU << CAN_RFIFOMI1_EFID_Pos) /*!< 0x001FFFF8 */
# define CAN_RFIFOMI1_EFID CAN_RFIFOMI1_EFID_Msk /*!< Extended identifier */
# define CAN_RFIFOMI1_SFID_Pos (21U)
# define CAN_RFIFOMI1_SFID_Msk (0x7FFU << CAN_RFIFOMI1_SFID_Pos) /*!< 0xFFE00000 */
# define CAN_RFIFOMI1_SFID CAN_RFIFOMI1_SFID_Msk /*!< Standard Identifier or Extended Identifier */
/******************* Bit definition for CAN_RFIFOMP1 register ******************/
# define CAN_RFIFOMP1_DLENC_Pos (0U)
# define CAN_RFIFOMP1_DLENC_Msk (0xFU << CAN_RFIFOMP1_DLENC_Pos) /*!< 0x0000000F */
# define CAN_RFIFOMP1_DLENC CAN_RFIFOMP1_DLENC_Msk /*!< Data Length Code */
# define CAN_RFIFOMP1_FI_Pos (8U)
# define CAN_RFIFOMP1_FI_Msk (0xFFU << CAN_RFIFOMP1_FI_Pos) /*!< 0x0000FF00 */
# define CAN_RFIFOMP1_FI CAN_RFIFOMP1_FI_Msk /*!< Filter Match Index */
# define CAN_RFIFOMP1_TS_Pos (16U)
# define CAN_RFIFOMP1_TS_Msk (0xFFFFU << CAN_RFIFOMP1_TS_Pos) /*!< 0xFFFF0000 */
# define CAN_RFIFOMP1_TS CAN_RFIFOMP1_TS_Msk /*!< Message Time Stamp */
/******************* Bit definition for CAN_RFIFOMDATA01 register ******************/
# define CAN_RFIFOMDATA01_DB0_Pos (0U)
# define CAN_RFIFOMDATA01_DB0_Msk (0xFFU << CAN_RFIFOMDATA01_DB0_Pos) /*!< 0x000000FF */
# define CAN_RFIFOMDATA01_DB0 CAN_RFIFOMDATA01_DB0_Msk /*!< Data byte 0 */
# define CAN_RFIFOMDATA01_DB1_Pos (8U)
# define CAN_RFIFOMDATA01_DB1_Msk (0xFFU << CAN_RFIFOMDATA01_DB1_Pos) /*!< 0x0000FF00 */
# define CAN_RFIFOMDATA01_DB1 CAN_RFIFOMDATA01_DB1_Msk /*!< Data byte 1 */
# define CAN_RFIFOMDATA01_DB2_Pos (16U)
# define CAN_RFIFOMDATA01_DB2_Msk (0xFFU << CAN_RFIFOMDATA01_DB2_Pos) /*!< 0x00FF0000 */
# define CAN_RFIFOMDATA01_DB2 CAN_RFIFOMDATA01_DB2_Msk /*!< Data byte 2 */
# define CAN_RFIFOMDATA01_DB3_Pos (24U)
# define CAN_RFIFOMDATA01_DB3_Msk (0xFFU << CAN_RFIFOMDATA01_DB3_Pos) /*!< 0xFF000000 */
# define CAN_RFIFOMDATA01_DB3 CAN_RFIFOMDATA01_DB3_Msk /*!< Data byte 3 */
/******************* Bit definition for CAN_RFIFOMDATA11 register ******************/
# define CAN_RFIFOMDATA11_DB4_Pos (0U)
# define CAN_RFIFOMDATA11_DB4_Msk (0xFFU << CAN_RFIFOMDATA11_DB4_Pos) /*!< 0x000000FF */
# define CAN_RFIFOMDATA11_DB4 CAN_RFIFOMDATA11_DB4_Msk /*!< Data byte 4 */
# define CAN_RFIFOMDATA11_DB5_Pos (8U)
# define CAN_RFIFOMDATA11_DB5_Msk (0xFFU << CAN_RFIFOMDATA11_DB5_Pos) /*!< 0x0000FF00 */
# define CAN_RFIFOMDATA11_DB5 CAN_RFIFOMDATA11_DB5_Msk /*!< Data byte 5 */
# define CAN_RFIFOMDATA11_DB6_Pos (16U)
# define CAN_RFIFOMDATA11_DB6_Msk (0xFFU << CAN_RFIFOMDATA11_DB6_Pos) /*!< 0x00FF0000 */
# define CAN_RFIFOMDATA11_DB6 CAN_RFIFOMDATA11_DB6_Msk /*!< Data byte 6 */
# define CAN_RFIFOMDATA11_DB7_Pos (24U)
# define CAN_RFIFOMDATA11_DB7_Msk (0xFFU << CAN_RFIFOMDATA11_DB7_Pos) /*!< 0xFF000000 */
# define CAN_RFIFOMDATA11_DB7 CAN_RFIFOMDATA11_DB7_Msk /*!< Data byte 7 */
2021-03-19 10:05:24 -07:00
/*!< CAN filter registers */
2021-03-26 07:28:37 -07:00
/******************* Bit definition for CAN_FCTL register ********************/
# define CAN_FCTL_FLD_Pos (0U)
# define CAN_FCTL_FLD_Msk (0x1U << CAN_FCTL_FLD_Pos) /*!< 0x00000001 */
# define CAN_FCTL_FLD CAN_FCTL_FLD_Msk /*!< Filter Init Mode */
# define CAN_FCTL_HBC1F_Pos (8U)
# define CAN_FCTL_HBC1F_Msk (0x3FU << CAN_FCTL_HBC1F_Pos) /*!< 0x00003F00 */
# define CAN_FCTL_HBC1F CAN_FCTL_HBC1F_Msk /*!< CAN2 start bank */
/******************* Bit definition for CAN_FMCFG register *******************/
# define CAN_FMCFG_FMOD_Pos (0U)
# define CAN_FMCFG_FMOD_Msk (0x3FFFU << CAN_FMCFG_FMOD_Pos) /*!< 0x00003FFF */
# define CAN_FMCFG_FMOD CAN_FMCFG_FMOD_Msk /*!< Filter Mode */
# define CAN_FMCFG_FMOD0_Pos (0U)
# define CAN_FMCFG_FMOD0_Msk (0x1U << CAN_FMCFG_FMOD0_Pos) /*!< 0x00000001 */
# define CAN_FMCFG_FMOD0 CAN_FMCFG_FMOD0_Msk /*!< Filter Init Mode for filter 0 */
# define CAN_FMCFG_FMOD1_Pos (1U)
# define CAN_FMCFG_FMOD1_Msk (0x1U << CAN_FMCFG_FMOD1_Pos) /*!< 0x00000002 */
# define CAN_FMCFG_FMOD1 CAN_FMCFG_FMOD1_Msk /*!< Filter Init Mode for filter 1 */
# define CAN_FMCFG_FMOD2_Pos (2U)
# define CAN_FMCFG_FMOD2_Msk (0x1U << CAN_FMCFG_FMOD2_Pos) /*!< 0x00000004 */
# define CAN_FMCFG_FMOD2 CAN_FMCFG_FMOD2_Msk /*!< Filter Init Mode for filter 2 */
# define CAN_FMCFG_FMOD3_Pos (3U)
# define CAN_FMCFG_FMOD3_Msk (0x1U << CAN_FMCFG_FMOD3_Pos) /*!< 0x00000008 */
# define CAN_FMCFG_FMOD3 CAN_FMCFG_FMOD3_Msk /*!< Filter Init Mode for filter 3 */
# define CAN_FMCFG_FMOD4_Pos (4U)
# define CAN_FMCFG_FMOD4_Msk (0x1U << CAN_FMCFG_FMOD4_Pos) /*!< 0x00000010 */
# define CAN_FMCFG_FMOD4 CAN_FMCFG_FMOD4_Msk /*!< Filter Init Mode for filter 4 */
# define CAN_FMCFG_FMOD5_Pos (5U)
# define CAN_FMCFG_FMOD5_Msk (0x1U << CAN_FMCFG_FMOD5_Pos) /*!< 0x00000020 */
# define CAN_FMCFG_FMOD5 CAN_FMCFG_FMOD5_Msk /*!< Filter Init Mode for filter 5 */
# define CAN_FMCFG_FMOD6_Pos (6U)
# define CAN_FMCFG_FMOD6_Msk (0x1U << CAN_FMCFG_FMOD6_Pos) /*!< 0x00000040 */
# define CAN_FMCFG_FMOD6 CAN_FMCFG_FMOD6_Msk /*!< Filter Init Mode for filter 6 */
# define CAN_FMCFG_FMOD7_Pos (7U)
# define CAN_FMCFG_FMOD7_Msk (0x1U << CAN_FMCFG_FMOD7_Pos) /*!< 0x00000080 */
# define CAN_FMCFG_FMOD7 CAN_FMCFG_FMOD7_Msk /*!< Filter Init Mode for filter 7 */
# define CAN_FMCFG_FMOD8_Pos (8U)
# define CAN_FMCFG_FMOD8_Msk (0x1U << CAN_FMCFG_FMOD8_Pos) /*!< 0x00000100 */
# define CAN_FMCFG_FMOD8 CAN_FMCFG_FMOD8_Msk /*!< Filter Init Mode for filter 8 */
# define CAN_FMCFG_FMOD9_Pos (9U)
# define CAN_FMCFG_FMOD9_Msk (0x1U << CAN_FMCFG_FMOD9_Pos) /*!< 0x00000200 */
# define CAN_FMCFG_FMOD9 CAN_FMCFG_FMOD9_Msk /*!< Filter Init Mode for filter 9 */
# define CAN_FMCFG_FMOD10_Pos (10U)
# define CAN_FMCFG_FMOD10_Msk (0x1U << CAN_FMCFG_FMOD10_Pos) /*!< 0x00000400 */
# define CAN_FMCFG_FMOD10 CAN_FMCFG_FMOD10_Msk /*!< Filter Init Mode for filter 10 */
# define CAN_FMCFG_FMOD11_Pos (11U)
# define CAN_FMCFG_FMOD11_Msk (0x1U << CAN_FMCFG_FMOD11_Pos) /*!< 0x00000800 */
# define CAN_FMCFG_FMOD11 CAN_FMCFG_FMOD11_Msk /*!< Filter Init Mode for filter 11 */
# define CAN_FMCFG_FMOD12_Pos (12U)
# define CAN_FMCFG_FMOD12_Msk (0x1U << CAN_FMCFG_FMOD12_Pos) /*!< 0x00001000 */
# define CAN_FMCFG_FMOD12 CAN_FMCFG_FMOD12_Msk /*!< Filter Init Mode for filter 12 */
# define CAN_FMCFG_FMOD13_Pos (13U)
# define CAN_FMCFG_FMOD13_Msk (0x1U << CAN_FMCFG_FMOD13_Pos) /*!< 0x00002000 */
# define CAN_FMCFG_FMOD13 CAN_FMCFG_FMOD13_Msk /*!< Filter Init Mode for filter 13 */
# define CAN_FMCFG_FMOD14_Pos (14U)
# define CAN_FMCFG_FMOD14_Msk (0x1U << CAN_FMCFG_FMOD14_Pos) /*!< 0x00004000 */
# define CAN_FMCFG_FMOD14 CAN_FMCFG_FMOD14_Msk /*!< Filter Init Mode for filter 14 */
# define CAN_FMCFG_FMOD15_Pos (15U)
# define CAN_FMCFG_FMOD15_Msk (0x1U << CAN_FMCFG_FMOD15_Pos) /*!< 0x00008000 */
# define CAN_FMCFG_FMOD15 CAN_FMCFG_FMOD15_Msk /*!< Filter Init Mode for filter 15 */
# define CAN_FMCFG_FMOD16_Pos (16U)
# define CAN_FMCFG_FMOD16_Msk (0x1U << CAN_FMCFG_FMOD16_Pos) /*!< 0x00010000 */
# define CAN_FMCFG_FMOD16 CAN_FMCFG_FMOD16_Msk /*!< Filter Init Mode for filter 16 */
# define CAN_FMCFG_FMOD17_Pos (17U)
# define CAN_FMCFG_FMOD17_Msk (0x1U << CAN_FMCFG_FMOD17_Pos) /*!< 0x00020000 */
# define CAN_FMCFG_FMOD17 CAN_FMCFG_FMOD17_Msk /*!< Filter Init Mode for filter 17 */
# define CAN_FMCFG_FMOD18_Pos (18U)
# define CAN_FMCFG_FMOD18_Msk (0x1U << CAN_FMCFG_FMOD18_Pos) /*!< 0x00040000 */
# define CAN_FMCFG_FMOD18 CAN_FMCFG_FMOD18_Msk /*!< Filter Init Mode for filter 18 */
# define CAN_FMCFG_FMOD19_Pos (19U)
# define CAN_FMCFG_FMOD19_Msk (0x1U << CAN_FMCFG_FMOD19_Pos) /*!< 0x00080000 */
# define CAN_FMCFG_FMOD19 CAN_FMCFG_FMOD19_Msk /*!< Filter Init Mode for filter 19 */
# define CAN_FMCFG_FMOD20_Pos (20U)
# define CAN_FMCFG_FMOD20_Msk (0x1U << CAN_FMCFG_FMOD20_Pos) /*!< 0x00100000 */
# define CAN_FMCFG_FMOD20 CAN_FMCFG_FMOD20_Msk /*!< Filter Init Mode for filter 20 */
# define CAN_FMCFG_FMOD21_Pos (21U)
# define CAN_FMCFG_FMOD21_Msk (0x1U << CAN_FMCFG_FMOD21_Pos) /*!< 0x00200000 */
# define CAN_FMCFG_FMOD21 CAN_FMCFG_FMOD21_Msk /*!< Filter Init Mode for filter 21 */
# define CAN_FMCFG_FMOD22_Pos (22U)
# define CAN_FMCFG_FMOD22_Msk (0x1U << CAN_FMCFG_FMOD22_Pos) /*!< 0x00400000 */
# define CAN_FMCFG_FMOD22 CAN_FMCFG_FMOD22_Msk /*!< Filter Init Mode for filter 22 */
# define CAN_FMCFG_FMOD23_Pos (23U)
# define CAN_FMCFG_FMOD23_Msk (0x1U << CAN_FMCFG_FMOD23_Pos) /*!< 0x00800000 */
# define CAN_FMCFG_FMOD23 CAN_FMCFG_FMOD23_Msk /*!< Filter Init Mode for filter 23 */
# define CAN_FMCFG_FMOD24_Pos (24U)
# define CAN_FMCFG_FMOD24_Msk (0x1U << CAN_FMCFG_FMOD24_Pos) /*!< 0x01000000 */
# define CAN_FMCFG_FMOD24 CAN_FMCFG_FMOD24_Msk /*!< Filter Init Mode for filter 24 */
# define CAN_FMCFG_FMOD25_Pos (25U)
# define CAN_FMCFG_FMOD25_Msk (0x1U << CAN_FMCFG_FMOD25_Pos) /*!< 0x02000000 */
# define CAN_FMCFG_FMOD25 CAN_FMCFG_FMOD25_Msk /*!< Filter Init Mode for filter 25 */
# define CAN_FMCFG_FMOD26_Pos (26U)
# define CAN_FMCFG_FMOD26_Msk (0x1U << CAN_FMCFG_FMOD26_Pos) /*!< 0x04000000 */
# define CAN_FMCFG_FMOD26 CAN_FMCFG_FMOD26_Msk /*!< Filter Init Mode for filter 26 */
# define CAN_FMCFG_FMOD27_Pos (27U)
# define CAN_FMCFG_FMOD27_Msk (0x1U << CAN_FMCFG_FMOD27_Pos) /*!< 0x08000000 */
# define CAN_FMCFG_FMOD27 CAN_FMCFG_FMOD27_Msk /*!< Filter Init Mode for filter 27 */
/******************* Bit definition for CAN_FSCFG register *******************/
# define CAN_FSCFG_FS_Pos (0U)
# define CAN_FSCFG_FS_Msk (0x3FFFU << CAN_FSCFG_FS_Pos) /*!< 0x00003FFF */
# define CAN_FSCFG_FS CAN_FSCFG_FS_Msk /*!< Filter Scale Configuration */
# define CAN_FSCFG_FS0_Pos (0U)
# define CAN_FSCFG_FS0_Msk (0x1U << CAN_FSCFG_FS0_Pos) /*!< 0x00000001 */
# define CAN_FSCFG_FS0 CAN_FSCFG_FS0_Msk /*!< Filter Scale Configuration for filter 0 */
# define CAN_FSCFG_FS1_Pos (1U)
# define CAN_FSCFG_FS1_Msk (0x1U << CAN_FSCFG_FS1_Pos) /*!< 0x00000002 */
# define CAN_FSCFG_FS1 CAN_FSCFG_FS1_Msk /*!< Filter Scale Configuration for filter 1 */
# define CAN_FSCFG_FS2_Pos (2U)
# define CAN_FSCFG_FS2_Msk (0x1U << CAN_FSCFG_FS2_Pos) /*!< 0x00000004 */
# define CAN_FSCFG_FS2 CAN_FSCFG_FS2_Msk /*!< Filter Scale Configuration for filter 2 */
# define CAN_FSCFG_FS3_Pos (3U)
# define CAN_FSCFG_FS3_Msk (0x1U << CAN_FSCFG_FS3_Pos) /*!< 0x00000008 */
# define CAN_FSCFG_FS3 CAN_FSCFG_FS3_Msk /*!< Filter Scale Configuration for filter 3 */
# define CAN_FSCFG_FS4_Pos (4U)
# define CAN_FSCFG_FS4_Msk (0x1U << CAN_FSCFG_FS4_Pos) /*!< 0x00000010 */
# define CAN_FSCFG_FS4 CAN_FSCFG_FS4_Msk /*!< Filter Scale Configuration for filter 4 */
# define CAN_FSCFG_FS5_Pos (5U)
# define CAN_FSCFG_FS5_Msk (0x1U << CAN_FSCFG_FS5_Pos) /*!< 0x00000020 */
# define CAN_FSCFG_FS5 CAN_FSCFG_FS5_Msk /*!< Filter Scale Configuration for filter 5 */
# define CAN_FSCFG_FS6_Pos (6U)
# define CAN_FSCFG_FS6_Msk (0x1U << CAN_FSCFG_FS6_Pos) /*!< 0x00000040 */
# define CAN_FSCFG_FS6 CAN_FSCFG_FS6_Msk /*!< Filter Scale Configuration for filter 6 */
# define CAN_FSCFG_FS7_Pos (7U)
# define CAN_FSCFG_FS7_Msk (0x1U << CAN_FSCFG_FS7_Pos) /*!< 0x00000080 */
# define CAN_FSCFG_FS7 CAN_FSCFG_FS7_Msk /*!< Filter Scale Configuration for filter 7 */
# define CAN_FSCFG_FS8_Pos (8U)
# define CAN_FSCFG_FS8_Msk (0x1U << CAN_FSCFG_FS8_Pos) /*!< 0x00000100 */
# define CAN_FSCFG_FS8 CAN_FSCFG_FS8_Msk /*!< Filter Scale Configuration for filter 8 */
# define CAN_FSCFG_FS9_Pos (9U)
# define CAN_FSCFG_FS9_Msk (0x1U << CAN_FSCFG_FS9_Pos) /*!< 0x00000200 */
# define CAN_FSCFG_FS9 CAN_FSCFG_FS9_Msk /*!< Filter Scale Configuration for filter 9 */
# define CAN_FSCFG_FS10_Pos (10U)
# define CAN_FSCFG_FS10_Msk (0x1U << CAN_FSCFG_FS10_Pos) /*!< 0x00000400 */
# define CAN_FSCFG_FS10 CAN_FSCFG_FS10_Msk /*!< Filter Scale Configuration for filter 10 */
# define CAN_FSCFG_FS11_Pos (11U)
# define CAN_FSCFG_FS11_Msk (0x1U << CAN_FSCFG_FS11_Pos) /*!< 0x00000800 */
# define CAN_FSCFG_FS11 CAN_FSCFG_FS11_Msk /*!< Filter Scale Configuration for filter 11 */
# define CAN_FSCFG_FS12_Pos (12U)
# define CAN_FSCFG_FS12_Msk (0x1U << CAN_FSCFG_FS12_Pos) /*!< 0x00001000 */
# define CAN_FSCFG_FS12 CAN_FSCFG_FS12_Msk /*!< Filter Scale Configuration for filter 12 */
# define CAN_FSCFG_FS13_Pos (13U)
# define CAN_FSCFG_FS13_Msk (0x1U << CAN_FSCFG_FS13_Pos) /*!< 0x00002000 */
# define CAN_FSCFG_FS13 CAN_FSCFG_FS13_Msk /*!< Filter Scale Configuration for filter 13 */
# define CAN_FSCFG_FS14_Pos (14U)
# define CAN_FSCFG_FS14_Msk (0x1U << CAN_FSCFG_FS14_Pos) /*!< 0x00004000 */
# define CAN_FSCFG_FS14 CAN_FSCFG_FS14_Msk /*!< Filter Scale Configuration for filter 14 */
# define CAN_FSCFG_FS15_Pos (15U)
# define CAN_FSCFG_FS15_Msk (0x1U << CAN_FSCFG_FS15_Pos) /*!< 0x00008000 */
# define CAN_FSCFG_FS15 CAN_FSCFG_FS15_Msk /*!< Filter Scale Configuration for filter 15 */
# define CAN_FSCFG_FS16_Pos (16U)
# define CAN_FSCFG_FS16_Msk (0x1U << CAN_FSCFG_FS16_Pos) /*!< 0x00010000 */
# define CAN_FSCFG_FS16 CAN_FSCFG_FS16_Msk /*!< Filter Scale Configuration for filter 16 */
# define CAN_FSCFG_FS17_Pos (17U)
# define CAN_FSCFG_FS17_Msk (0x1U << CAN_FSCFG_FS17_Pos) /*!< 0x00020000 */
# define CAN_FSCFG_FS17 CAN_FSCFG_FS17_Msk /*!< Filter Scale Configuration for filter 17 */
# define CAN_FSCFG_FS18_Pos (18U)
# define CAN_FSCFG_FS18_Msk (0x1U << CAN_FSCFG_FS18_Pos) /*!< 0x00040000 */
# define CAN_FSCFG_FS18 CAN_FSCFG_FS18_Msk /*!< Filter Scale Configuration for filter 18 */
# define CAN_FSCFG_FS19_Pos (19U)
# define CAN_FSCFG_FS19_Msk (0x1U << CAN_FSCFG_FS19_Pos) /*!< 0x00080000 */
# define CAN_FSCFG_FS19 CAN_FSCFG_FS19_Msk /*!< Filter Scale Configuration for filter 19 */
# define CAN_FSCFG_FS20_Pos (20U)
# define CAN_FSCFG_FS20_Msk (0x1U << CAN_FSCFG_FS20_Pos) /*!< 0x00100000 */
# define CAN_FSCFG_FS20 CAN_FSCFG_FS20_Msk /*!< Filter Scale Configuration for filter 20 */
# define CAN_FSCFG_FS21_Pos (21U)
# define CAN_FSCFG_FS21_Msk (0x1U << CAN_FSCFG_FS21_Pos) /*!< 0x00200000 */
# define CAN_FSCFG_FS21 CAN_FSCFG_FS21_Msk /*!< Filter Scale Configuration for filter 21 */
# define CAN_FSCFG_FS22_Pos (22U)
# define CAN_FSCFG_FS22_Msk (0x1U << CAN_FSCFG_FS22_Pos) /*!< 0x00400000 */
# define CAN_FSCFG_FS22 CAN_FSCFG_FS22_Msk /*!< Filter Scale Configuration for filter 22 */
# define CAN_FSCFG_FS23_Pos (23U)
# define CAN_FSCFG_FS23_Msk (0x1U << CAN_FSCFG_FS23_Pos) /*!< 0x00800000 */
# define CAN_FSCFG_FS23 CAN_FSCFG_FS23_Msk /*!< Filter Scale Configuration for filter 23 */
# define CAN_FSCFG_FS24_Pos (24U)
# define CAN_FSCFG_FS24_Msk (0x1U << CAN_FSCFG_FS24_Pos) /*!< 0x01000000 */
# define CAN_FSCFG_FS24 CAN_FSCFG_FS24_Msk /*!< Filter Scale Configuration for filter 24 */
# define CAN_FSCFG_FS25_Pos (25U)
# define CAN_FSCFG_FS25_Msk (0x1U << CAN_FSCFG_FS25_Pos) /*!< 0x02000000 */
# define CAN_FSCFG_FS25 CAN_FSCFG_FS25_Msk /*!< Filter Scale Configuration for filter 25 */
# define CAN_FSCFG_FS26_Pos (26U)
# define CAN_FSCFG_FS26_Msk (0x1U << CAN_FSCFG_FS26_Pos) /*!< 0x04000000 */
# define CAN_FSCFG_FS26 CAN_FSCFG_FS26_Msk /*!< Filter Scale Configuration for filter 26 */
# define CAN_FSCFG_FS27_Pos (27U)
# define CAN_FSCFG_FS27_Msk (0x1U << CAN_FSCFG_FS27_Pos) /*!< 0x08000000 */
# define CAN_FSCFG_FS27 CAN_FSCFG_FS27_Msk /*!< Filter Scale Configuration for filter 27 */
/****************** Bit definition for CAN_FAFIFO register *******************/
# define CAN_FAFIFO_FAF_Pos (0U)
# define CAN_FAFIFO_FAF_Msk (0x3FFFU << CAN_FAFIFO_FAF_Pos) /*!< 0x00003FFF */
# define CAN_FAFIFO_FAF CAN_FAFIFO_FAF_Msk /*!< Filter FIFO Assignment */
# define CAN_FAFIFO_FAF0_Pos (0U)
# define CAN_FAFIFO_FAF0_Msk (0x1U << CAN_FAFIFO_FAF0_Pos) /*!< 0x00000001 */
# define CAN_FAFIFO_FAF0 CAN_FAFIFO_FAF0_Msk /*!< Filter FIFO Assignment for filter 0 */
# define CAN_FAFIFO_FAF1_Pos (1U)
# define CAN_FAFIFO_FAF1_Msk (0x1U << CAN_FAFIFO_FAF1_Pos) /*!< 0x00000002 */
# define CAN_FAFIFO_FAF1 CAN_FAFIFO_FAF1_Msk /*!< Filter FIFO Assignment for filter 1 */
# define CAN_FAFIFO_FAF2_Pos (2U)
# define CAN_FAFIFO_FAF2_Msk (0x1U << CAN_FAFIFO_FAF2_Pos) /*!< 0x00000004 */
# define CAN_FAFIFO_FAF2 CAN_FAFIFO_FAF2_Msk /*!< Filter FIFO Assignment for filter 2 */
# define CAN_FAFIFO_FAF3_Pos (3U)
# define CAN_FAFIFO_FAF3_Msk (0x1U << CAN_FAFIFO_FAF3_Pos) /*!< 0x00000008 */
# define CAN_FAFIFO_FAF3 CAN_FAFIFO_FAF3_Msk /*!< Filter FIFO Assignment for filter 3 */
# define CAN_FAFIFO_FAF4_Pos (4U)
# define CAN_FAFIFO_FAF4_Msk (0x1U << CAN_FAFIFO_FAF4_Pos) /*!< 0x00000010 */
# define CAN_FAFIFO_FAF4 CAN_FAFIFO_FAF4_Msk /*!< Filter FIFO Assignment for filter 4 */
# define CAN_FAFIFO_FAF5_Pos (5U)
# define CAN_FAFIFO_FAF5_Msk (0x1U << CAN_FAFIFO_FAF5_Pos) /*!< 0x00000020 */
# define CAN_FAFIFO_FAF5 CAN_FAFIFO_FAF5_Msk /*!< Filter FIFO Assignment for filter 5 */
# define CAN_FAFIFO_FAF6_Pos (6U)
# define CAN_FAFIFO_FAF6_Msk (0x1U << CAN_FAFIFO_FAF6_Pos) /*!< 0x00000040 */
# define CAN_FAFIFO_FAF6 CAN_FAFIFO_FAF6_Msk /*!< Filter FIFO Assignment for filter 6 */
# define CAN_FAFIFO_FAF7_Pos (7U)
# define CAN_FAFIFO_FAF7_Msk (0x1U << CAN_FAFIFO_FAF7_Pos) /*!< 0x00000080 */
# define CAN_FAFIFO_FAF7 CAN_FAFIFO_FAF7_Msk /*!< Filter FIFO Assignment for filter 7 */
# define CAN_FAFIFO_FAF8_Pos (8U)
# define CAN_FAFIFO_FAF8_Msk (0x1U << CAN_FAFIFO_FAF8_Pos) /*!< 0x00000100 */
# define CAN_FAFIFO_FAF8 CAN_FAFIFO_FAF8_Msk /*!< Filter FIFO Assignment for filter 8 */
# define CAN_FAFIFO_FAF9_Pos (9U)
# define CAN_FAFIFO_FAF9_Msk (0x1U << CAN_FAFIFO_FAF9_Pos) /*!< 0x00000200 */
# define CAN_FAFIFO_FAF9 CAN_FAFIFO_FAF9_Msk /*!< Filter FIFO Assignment for filter 9 */
# define CAN_FAFIFO_FAF10_Pos (10U)
# define CAN_FAFIFO_FAF10_Msk (0x1U << CAN_FAFIFO_FAF10_Pos) /*!< 0x00000400 */
# define CAN_FAFIFO_FAF10 CAN_FAFIFO_FAF10_Msk /*!< Filter FIFO Assignment for filter 10 */
# define CAN_FAFIFO_FAF11_Pos (11U)
# define CAN_FAFIFO_FAF11_Msk (0x1U << CAN_FAFIFO_FAF11_Pos) /*!< 0x00000800 */
# define CAN_FAFIFO_FAF11 CAN_FAFIFO_FAF11_Msk /*!< Filter FIFO Assignment for filter 11 */
# define CAN_FAFIFO_FAF12_Pos (12U)
# define CAN_FAFIFO_FAF12_Msk (0x1U << CAN_FAFIFO_FAF12_Pos) /*!< 0x00001000 */
# define CAN_FAFIFO_FAF12 CAN_FAFIFO_FAF12_Msk /*!< Filter FIFO Assignment for filter 12 */
# define CAN_FAFIFO_FAF13_Pos (13U)
# define CAN_FAFIFO_FAF13_Msk (0x1U << CAN_FAFIFO_FAF13_Pos) /*!< 0x00002000 */
# define CAN_FAFIFO_FAF13 CAN_FAFIFO_FAF13_Msk /*!< Filter FIFO Assignment for filter 13 */
# define CAN_FAFIFO_FAF14_Pos (14U)
# define CAN_FAFIFO_FAF14_Msk (0x1U << CAN_FAFIFO_FAF14_Pos) /*!< 0x00004000 */
# define CAN_FAFIFO_FAF14 CAN_FAFIFO_FAF14_Msk /*!< Filter FIFO Assignment for filter 14 */
# define CAN_FAFIFO_FAF15_Pos (15U)
# define CAN_FAFIFO_FAF15_Msk (0x1U << CAN_FAFIFO_FAF15_Pos) /*!< 0x00008000 */
# define CAN_FAFIFO_FAF15 CAN_FAFIFO_FAF15_Msk /*!< Filter FIFO Assignment for filter 15 */
# define CAN_FAFIFO_FAF16_Pos (16U)
# define CAN_FAFIFO_FAF16_Msk (0x1U << CAN_FAFIFO_FAF16_Pos) /*!< 0x00010000 */
# define CAN_FAFIFO_FAF16 CAN_FAFIFO_FAF16_Msk /*!< Filter FIFO Assignment for filter 16 */
# define CAN_FAFIFO_FAF17_Pos (17U)
# define CAN_FAFIFO_FAF17_Msk (0x1U << CAN_FAFIFO_FAF17_Pos) /*!< 0x00020000 */
# define CAN_FAFIFO_FAF17 CAN_FAFIFO_FAF17_Msk /*!< Filter FIFO Assignment for filter 17 */
# define CAN_FAFIFO_FAF18_Pos (18U)
# define CAN_FAFIFO_FAF18_Msk (0x1U << CAN_FAFIFO_FAF18_Pos) /*!< 0x00040000 */
# define CAN_FAFIFO_FAF18 CAN_FAFIFO_FAF18_Msk /*!< Filter FIFO Assignment for filter 18 */
# define CAN_FAFIFO_FAF19_Pos (19U)
# define CAN_FAFIFO_FAF19_Msk (0x1U << CAN_FAFIFO_FAF19_Pos) /*!< 0x00080000 */
# define CAN_FAFIFO_FAF19 CAN_FAFIFO_FAF19_Msk /*!< Filter FIFO Assignment for filter 19 */
# define CAN_FAFIFO_FAF20_Pos (20U)
# define CAN_FAFIFO_FAF20_Msk (0x1U << CAN_FAFIFO_FAF20_Pos) /*!< 0x00100000 */
# define CAN_FAFIFO_FAF20 CAN_FAFIFO_FAF20_Msk /*!< Filter FIFO Assignment for filter 20 */
# define CAN_FAFIFO_FAF21_Pos (21U)
# define CAN_FAFIFO_FAF21_Msk (0x1U << CAN_FAFIFO_FAF21_Pos) /*!< 0x00200000 */
# define CAN_FAFIFO_FAF21 CAN_FAFIFO_FAF21_Msk /*!< Filter FIFO Assignment for filter 21 */
# define CAN_FAFIFO_FAF22_Pos (22U)
# define CAN_FAFIFO_FAF22_Msk (0x1U << CAN_FAFIFO_FAF22_Pos) /*!< 0x00400000 */
# define CAN_FAFIFO_FAF22 CAN_FAFIFO_FAF22_Msk /*!< Filter FIFO Assignment for filter 22 */
# define CAN_FAFIFO_FAF23_Pos (23U)
# define CAN_FAFIFO_FAF23_Msk (0x1U << CAN_FAFIFO_FAF23_Pos) /*!< 0x00800000 */
# define CAN_FAFIFO_FAF23 CAN_FAFIFO_FAF23_Msk /*!< Filter FIFO Assignment for filter 23 */
# define CAN_FAFIFO_FAF24_Pos (24U)
# define CAN_FAFIFO_FAF24_Msk (0x1U << CAN_FAFIFO_FAF24_Pos) /*!< 0x01000000 */
# define CAN_FAFIFO_FAF24 CAN_FAFIFO_FAF24_Msk /*!< Filter FIFO Assignment for filter 24 */
# define CAN_FAFIFO_FAF25_Pos (25U)
# define CAN_FAFIFO_FAF25_Msk (0x1U << CAN_FAFIFO_FAF25_Pos) /*!< 0x02000000 */
# define CAN_FAFIFO_FAF25 CAN_FAFIFO_FAF25_Msk /*!< Filter FIFO Assignment for filter 25 */
# define CAN_FAFIFO_FAF26_Pos (26U)
# define CAN_FAFIFO_FAF26_Msk (0x1U << CAN_FAFIFO_FAF26_Pos) /*!< 0x04000000 */
# define CAN_FAFIFO_FAF26 CAN_FAFIFO_FAF26_Msk /*!< Filter FIFO Assignment for filter 26 */
# define CAN_FAFIFO_FAF27_Pos (27U)
# define CAN_FAFIFO_FAF27_Msk (0x1U << CAN_FAFIFO_FAF27_Pos) /*!< 0x08000000 */
# define CAN_FAFIFO_FAF27 CAN_FAFIFO_FAF27_Msk /*!< Filter FIFO Assignment for filter 27 */
/******************* Bit definition for CAN_FW register *******************/
# define CAN_FW_FW_Pos (0U)
# define CAN_FW_FW_Msk (0x3FFFU << CAN_FW_FW_Pos) /*!< 0x00003FFF */
# define CAN_FW_FW CAN_FW_FW_Msk /*!< Filter Active */
# define CAN_FW_FW0_Pos (0U)
# define CAN_FW_FW0_Msk (0x1U << CAN_FW_FW0_Pos) /*!< 0x00000001 */
# define CAN_FW_FW0 CAN_FW_FW0_Msk /*!< Filter 0 Active */
# define CAN_FW_FW1_Pos (1U)
# define CAN_FW_FW1_Msk (0x1U << CAN_FW_FW1_Pos) /*!< 0x00000002 */
# define CAN_FW_FW1 CAN_FW_FW1_Msk /*!< Filter 1 Active */
# define CAN_FW_FW2_Pos (2U)
# define CAN_FW_FW2_Msk (0x1U << CAN_FW_FW2_Pos) /*!< 0x00000004 */
# define CAN_FW_FW2 CAN_FW_FW2_Msk /*!< Filter 2 Active */
# define CAN_FW_FW3_Pos (3U)
# define CAN_FW_FW3_Msk (0x1U << CAN_FW_FW3_Pos) /*!< 0x00000008 */
# define CAN_FW_FW3 CAN_FW_FW3_Msk /*!< Filter 3 Active */
# define CAN_FW_FW4_Pos (4U)
# define CAN_FW_FW4_Msk (0x1U << CAN_FW_FW4_Pos) /*!< 0x00000010 */
# define CAN_FW_FW4 CAN_FW_FW4_Msk /*!< Filter 4 Active */
# define CAN_FW_FW5_Pos (5U)
# define CAN_FW_FW5_Msk (0x1U << CAN_FW_FW5_Pos) /*!< 0x00000020 */
# define CAN_FW_FW5 CAN_FW_FW5_Msk /*!< Filter 5 Active */
# define CAN_FW_FW6_Pos (6U)
# define CAN_FW_FW6_Msk (0x1U << CAN_FW_FW6_Pos) /*!< 0x00000040 */
# define CAN_FW_FW6 CAN_FW_FW6_Msk /*!< Filter 6 Active */
# define CAN_FW_FW7_Pos (7U)
# define CAN_FW_FW7_Msk (0x1U << CAN_FW_FW7_Pos) /*!< 0x00000080 */
# define CAN_FW_FW7 CAN_FW_FW7_Msk /*!< Filter 7 Active */
# define CAN_FW_FW8_Pos (8U)
# define CAN_FW_FW8_Msk (0x1U << CAN_FW_FW8_Pos) /*!< 0x00000100 */
# define CAN_FW_FW8 CAN_FW_FW8_Msk /*!< Filter 8 Active */
# define CAN_FW_FW9_Pos (9U)
# define CAN_FW_FW9_Msk (0x1U << CAN_FW_FW9_Pos) /*!< 0x00000200 */
# define CAN_FW_FW9 CAN_FW_FW9_Msk /*!< Filter 9 Active */
# define CAN_FW_FW10_Pos (10U)
# define CAN_FW_FW10_Msk (0x1U << CAN_FW_FW10_Pos) /*!< 0x00000400 */
# define CAN_FW_FW10 CAN_FW_FW10_Msk /*!< Filter 10 Active */
# define CAN_FW_FW11_Pos (11U)
# define CAN_FW_FW11_Msk (0x1U << CAN_FW_FW11_Pos) /*!< 0x00000800 */
# define CAN_FW_FW11 CAN_FW_FW11_Msk /*!< Filter 11 Active */
# define CAN_FW_FW12_Pos (12U)
# define CAN_FW_FW12_Msk (0x1U << CAN_FW_FW12_Pos) /*!< 0x00001000 */
# define CAN_FW_FW12 CAN_FW_FW12_Msk /*!< Filter 12 Active */
# define CAN_FW_FW13_Pos (13U)
# define CAN_FW_FW13_Msk (0x1U << CAN_FW_FW13_Pos) /*!< 0x00002000 */
# define CAN_FW_FW13 CAN_FW_FW13_Msk /*!< Filter 13 Active */
# define CAN_FW_FW14_Pos (14U)
# define CAN_FW_FW14_Msk (0x1U << CAN_FW_FW14_Pos) /*!< 0x00004000 */
# define CAN_FW_FW14 CAN_FW_FW14_Msk /*!< Filter 14 Active */
# define CAN_FW_FW15_Pos (15U)
# define CAN_FW_FW15_Msk (0x1U << CAN_FW_FW15_Pos) /*!< 0x00008000 */
# define CAN_FW_FW15 CAN_FW_FW15_Msk /*!< Filter 15 Active */
# define CAN_FW_FW16_Pos (16U)
# define CAN_FW_FW16_Msk (0x1U << CAN_FW_FW16_Pos) /*!< 0x00010000 */
# define CAN_FW_FW16 CAN_FW_FW16_Msk /*!< Filter 16 Active */
# define CAN_FW_FW17_Pos (17U)
# define CAN_FW_FW17_Msk (0x1U << CAN_FW_FW17_Pos) /*!< 0x00020000 */
# define CAN_FW_FW17 CAN_FW_FW17_Msk /*!< Filter 17 Active */
# define CAN_FW_FW18_Pos (18U)
# define CAN_FW_FW18_Msk (0x1U << CAN_FW_FW18_Pos) /*!< 0x00040000 */
# define CAN_FW_FW18 CAN_FW_FW18_Msk /*!< Filter 18 Active */
# define CAN_FW_FW19_Pos (19U)
# define CAN_FW_FW19_Msk (0x1U << CAN_FW_FW19_Pos) /*!< 0x00080000 */
# define CAN_FW_FW19 CAN_FW_FW19_Msk /*!< Filter 19 Active */
# define CAN_FW_FW20_Pos (20U)
# define CAN_FW_FW20_Msk (0x1U << CAN_FW_FW20_Pos) /*!< 0x00100000 */
# define CAN_FW_FW20 CAN_FW_FW20_Msk /*!< Filter 20 Active */
# define CAN_FW_FW21_Pos (21U)
# define CAN_FW_FW21_Msk (0x1U << CAN_FW_FW21_Pos) /*!< 0x00200000 */
# define CAN_FW_FW21 CAN_FW_FW21_Msk /*!< Filter 21 Active */
# define CAN_FW_FW22_Pos (22U)
# define CAN_FW_FW22_Msk (0x1U << CAN_FW_FW22_Pos) /*!< 0x00400000 */
# define CAN_FW_FW22 CAN_FW_FW22_Msk /*!< Filter 22 Active */
# define CAN_FW_FW23_Pos (23U)
# define CAN_FW_FW23_Msk (0x1U << CAN_FW_FW23_Pos) /*!< 0x00800000 */
# define CAN_FW_FW23 CAN_FW_FW23_Msk /*!< Filter 23 Active */
# define CAN_FW_FW24_Pos (24U)
# define CAN_FW_FW24_Msk (0x1U << CAN_FW_FW24_Pos) /*!< 0x01000000 */
# define CAN_FW_FW24 CAN_FW_FW24_Msk /*!< Filter 24 Active */
# define CAN_FW_FW25_Pos (25U)
# define CAN_FW_FW25_Msk (0x1U << CAN_FW_FW25_Pos) /*!< 0x02000000 */
# define CAN_FW_FW25 CAN_FW_FW25_Msk /*!< Filter 25 Active */
# define CAN_FW_FW26_Pos (26U)
# define CAN_FW_FW26_Msk (0x1U << CAN_FW_FW26_Pos) /*!< 0x04000000 */
# define CAN_FW_FW26 CAN_FW_FW26_Msk /*!< Filter 26 Active */
# define CAN_FW_FW27_Pos (27U)
# define CAN_FW_FW27_Msk (0x1U << CAN_FW_FW27_Pos) /*!< 0x08000000 */
# define CAN_FW_FW27 CAN_FW_FW27_Msk /*!< Filter 27 Active */
2021-03-19 10:05:24 -07:00
/******************* Bit definition for CAN_F0R1 register *******************/
2021-03-26 07:28:37 -07:00
# define CAN_F0DATA0_FD0_Pos (0U)
# define CAN_F0DATA0_FD0_Msk (0x1U << CAN_F0DATA0_FD0_Pos) /*!< 0x00000001 */
# define CAN_F0DATA0_FD0 CAN_F0DATA0_FD0_Msk /*!< Filter bit 0 */
# define CAN_F0DATA0_FD1_Pos (1U)
# define CAN_F0DATA0_FD1_Msk (0x1U << CAN_F0DATA0_FD1_Pos) /*!< 0x00000002 */
# define CAN_F0DATA0_FD1 CAN_F0DATA0_FD1_Msk /*!< Filter bit 1 */
# define CAN_F0DATA0_FD2_Pos (2U)
# define CAN_F0DATA0_FD2_Msk (0x1U << CAN_F0DATA0_FD2_Pos) /*!< 0x00000004 */
# define CAN_F0DATA0_FD2 CAN_F0DATA0_FD2_Msk /*!< Filter bit 2 */
# define CAN_F0DATA0_FD3_Pos (3U)
# define CAN_F0DATA0_FD3_Msk (0x1U << CAN_F0DATA0_FD3_Pos) /*!< 0x00000008 */
# define CAN_F0DATA0_FD3 CAN_F0DATA0_FD3_Msk /*!< Filter bit 3 */
# define CAN_F0DATA0_FD4_Pos (4U)
# define CAN_F0DATA0_FD4_Msk (0x1U << CAN_F0DATA0_FD4_Pos) /*!< 0x00000010 */
# define CAN_F0DATA0_FD4 CAN_F0DATA0_FD4_Msk /*!< Filter bit 4 */
# define CAN_F0DATA0_FD5_Pos (5U)
# define CAN_F0DATA0_FD5_Msk (0x1U << CAN_F0DATA0_FD5_Pos) /*!< 0x00000020 */
# define CAN_F0DATA0_FD5 CAN_F0DATA0_FD5_Msk /*!< Filter bit 5 */
# define CAN_F0DATA0_FD6_Pos (6U)
# define CAN_F0DATA0_FD6_Msk (0x1U << CAN_F0DATA0_FD6_Pos) /*!< 0x00000040 */
# define CAN_F0DATA0_FD6 CAN_F0DATA0_FD6_Msk /*!< Filter bit 6 */
# define CAN_F0DATA0_FD7_Pos (7U)
# define CAN_F0DATA0_FD7_Msk (0x1U << CAN_F0DATA0_FD7_Pos) /*!< 0x00000080 */
# define CAN_F0DATA0_FD7 CAN_F0DATA0_FD7_Msk /*!< Filter bit 7 */
# define CAN_F0DATA0_FD8_Pos (8U)
# define CAN_F0DATA0_FD8_Msk (0x1U << CAN_F0DATA0_FD8_Pos) /*!< 0x00000100 */
# define CAN_F0DATA0_FD8 CAN_F0DATA0_FD8_Msk /*!< Filter bit 8 */
# define CAN_F0DATA0_FD9_Pos (9U)
# define CAN_F0DATA0_FD9_Msk (0x1U << CAN_F0DATA0_FD9_Pos) /*!< 0x00000200 */
# define CAN_F0DATA0_FD9 CAN_F0DATA0_FD9_Msk /*!< Filter bit 9 */
# define CAN_F0DATA0_FD10_Pos (10U)
# define CAN_F0DATA0_FD10_Msk (0x1U << CAN_F0DATA0_FD10_Pos) /*!< 0x00000400 */
# define CAN_F0DATA0_FD10 CAN_F0DATA0_FD10_Msk /*!< Filter bit 10 */
# define CAN_F0DATA0_FD11_Pos (11U)
# define CAN_F0DATA0_FD11_Msk (0x1U << CAN_F0DATA0_FD11_Pos) /*!< 0x00000800 */
# define CAN_F0DATA0_FD11 CAN_F0DATA0_FD11_Msk /*!< Filter bit 11 */
# define CAN_F0DATA0_FD12_Pos (12U)
# define CAN_F0DATA0_FD12_Msk (0x1U << CAN_F0DATA0_FD12_Pos) /*!< 0x00001000 */
# define CAN_F0DATA0_FD12 CAN_F0DATA0_FD12_Msk /*!< Filter bit 12 */
# define CAN_F0DATA0_FD13_Pos (13U)
# define CAN_F0DATA0_FD13_Msk (0x1U << CAN_F0DATA0_FD13_Pos) /*!< 0x00002000 */
# define CAN_F0DATA0_FD13 CAN_F0DATA0_FD13_Msk /*!< Filter bit 13 */
# define CAN_F0DATA0_FD14_Pos (14U)
# define CAN_F0DATA0_FD14_Msk (0x1U << CAN_F0DATA0_FD14_Pos) /*!< 0x00004000 */
# define CAN_F0DATA0_FD14 CAN_F0DATA0_FD14_Msk /*!< Filter bit 14 */
# define CAN_F0DATA0_FD15_Pos (15U)
# define CAN_F0DATA0_FD15_Msk (0x1U << CAN_F0DATA0_FD15_Pos) /*!< 0x00008000 */
# define CAN_F0DATA0_FD15 CAN_F0DATA0_FD15_Msk /*!< Filter bit 15 */
# define CAN_F0DATA0_FD16_Pos (16U)
# define CAN_F0DATA0_FD16_Msk (0x1U << CAN_F0DATA0_FD16_Pos) /*!< 0x00010000 */
# define CAN_F0DATA0_FD16 CAN_F0DATA0_FD16_Msk /*!< Filter bit 16 */
# define CAN_F0DATA0_FD17_Pos (17U)
# define CAN_F0DATA0_FD17_Msk (0x1U << CAN_F0DATA0_FD17_Pos) /*!< 0x00020000 */
# define CAN_F0DATA0_FD17 CAN_F0DATA0_FD17_Msk /*!< Filter bit 17 */
# define CAN_F0DATA0_FD18_Pos (18U)
# define CAN_F0DATA0_FD18_Msk (0x1U << CAN_F0DATA0_FD18_Pos) /*!< 0x00040000 */
# define CAN_F0DATA0_FD18 CAN_F0DATA0_FD18_Msk /*!< Filter bit 18 */
# define CAN_F0DATA0_FD19_Pos (19U)
# define CAN_F0DATA0_FD19_Msk (0x1U << CAN_F0DATA0_FD19_Pos) /*!< 0x00080000 */
# define CAN_F0DATA0_FD19 CAN_F0DATA0_FD19_Msk /*!< Filter bit 19 */
# define CAN_F0DATA0_FD20_Pos (20U)
# define CAN_F0DATA0_FD20_Msk (0x1U << CAN_F0DATA0_FD20_Pos) /*!< 0x00100000 */
# define CAN_F0DATA0_FD20 CAN_F0DATA0_FD20_Msk /*!< Filter bit 20 */
# define CAN_F0DATA0_FD21_Pos (21U)
# define CAN_F0DATA0_FD21_Msk (0x1U << CAN_F0DATA0_FD21_Pos) /*!< 0x00200000 */
# define CAN_F0DATA0_FD21 CAN_F0DATA0_FD21_Msk /*!< Filter bit 21 */
# define CAN_F0DATA0_FD22_Pos (22U)
# define CAN_F0DATA0_FD22_Msk (0x1U << CAN_F0DATA0_FD22_Pos) /*!< 0x00400000 */
# define CAN_F0DATA0_FD22 CAN_F0DATA0_FD22_Msk /*!< Filter bit 22 */
# define CAN_F0DATA0_FD23_Pos (23U)
# define CAN_F0DATA0_FD23_Msk (0x1U << CAN_F0DATA0_FD23_Pos) /*!< 0x00800000 */
# define CAN_F0DATA0_FD23 CAN_F0DATA0_FD23_Msk /*!< Filter bit 23 */
# define CAN_F0DATA0_FD24_Pos (24U)
# define CAN_F0DATA0_FD24_Msk (0x1U << CAN_F0DATA0_FD24_Pos) /*!< 0x01000000 */
# define CAN_F0DATA0_FD24 CAN_F0DATA0_FD24_Msk /*!< Filter bit 24 */
# define CAN_F0DATA0_FD25_Pos (25U)
# define CAN_F0DATA0_FD25_Msk (0x1U << CAN_F0DATA0_FD25_Pos) /*!< 0x02000000 */
# define CAN_F0DATA0_FD25 CAN_F0DATA0_FD25_Msk /*!< Filter bit 25 */
# define CAN_F0DATA0_FD26_Pos (26U)
# define CAN_F0DATA0_FD26_Msk (0x1U << CAN_F0DATA0_FD26_Pos) /*!< 0x04000000 */
# define CAN_F0DATA0_FD26 CAN_F0DATA0_FD26_Msk /*!< Filter bit 26 */
# define CAN_F0DATA0_FD27_Pos (27U)
# define CAN_F0DATA0_FD27_Msk (0x1U << CAN_F0DATA0_FD27_Pos) /*!< 0x08000000 */
# define CAN_F0DATA0_FD27 CAN_F0DATA0_FD27_Msk /*!< Filter bit 27 */
# define CAN_F0DATA0_FD28_Pos (28U)
# define CAN_F0DATA0_FD28_Msk (0x1U << CAN_F0DATA0_FD28_Pos) /*!< 0x10000000 */
# define CAN_F0DATA0_FD28 CAN_F0DATA0_FD28_Msk /*!< Filter bit 28 */
# define CAN_F0DATA0_FD29_Pos (29U)
# define CAN_F0DATA0_FD29_Msk (0x1U << CAN_F0DATA0_FD29_Pos) /*!< 0x20000000 */
# define CAN_F0DATA0_FD29 CAN_F0DATA0_FD29_Msk /*!< Filter bit 29 */
# define CAN_F0DATA0_FD30_Pos (30U)
# define CAN_F0DATA0_FD30_Msk (0x1U << CAN_F0DATA0_FD30_Pos) /*!< 0x40000000 */
# define CAN_F0DATA0_FD30 CAN_F0DATA0_FD30_Msk /*!< Filter bit 30 */
# define CAN_F0DATA0_FD31_Pos (31U)
# define CAN_F0DATA0_FD31_Msk (0x1U << CAN_F0DATA0_FD31_Pos) /*!< 0x80000000 */
# define CAN_F0DATA0_FD31 CAN_F0DATA0_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F1R1 register *******************/
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# define CAN_F1DATA0_FD0_Pos (0U)
# define CAN_F1DATA0_FD0_Msk (0x1U << CAN_F1DATA0_FD0_Pos) /*!< 0x00000001 */
# define CAN_F1DATA0_FD0 CAN_F1DATA0_FD0_Msk /*!< Filter bit 0 */
# define CAN_F1DATA0_FD1_Pos (1U)
# define CAN_F1DATA0_FD1_Msk (0x1U << CAN_F1DATA0_FD1_Pos) /*!< 0x00000002 */
# define CAN_F1DATA0_FD1 CAN_F1DATA0_FD1_Msk /*!< Filter bit 1 */
# define CAN_F1DATA0_FD2_Pos (2U)
# define CAN_F1DATA0_FD2_Msk (0x1U << CAN_F1DATA0_FD2_Pos) /*!< 0x00000004 */
# define CAN_F1DATA0_FD2 CAN_F1DATA0_FD2_Msk /*!< Filter bit 2 */
# define CAN_F1DATA0_FD3_Pos (3U)
# define CAN_F1DATA0_FD3_Msk (0x1U << CAN_F1DATA0_FD3_Pos) /*!< 0x00000008 */
# define CAN_F1DATA0_FD3 CAN_F1DATA0_FD3_Msk /*!< Filter bit 3 */
# define CAN_F1DATA0_FD4_Pos (4U)
# define CAN_F1DATA0_FD4_Msk (0x1U << CAN_F1DATA0_FD4_Pos) /*!< 0x00000010 */
# define CAN_F1DATA0_FD4 CAN_F1DATA0_FD4_Msk /*!< Filter bit 4 */
# define CAN_F1DATA0_FD5_Pos (5U)
# define CAN_F1DATA0_FD5_Msk (0x1U << CAN_F1DATA0_FD5_Pos) /*!< 0x00000020 */
# define CAN_F1DATA0_FD5 CAN_F1DATA0_FD5_Msk /*!< Filter bit 5 */
# define CAN_F1DATA0_FD6_Pos (6U)
# define CAN_F1DATA0_FD6_Msk (0x1U << CAN_F1DATA0_FD6_Pos) /*!< 0x00000040 */
# define CAN_F1DATA0_FD6 CAN_F1DATA0_FD6_Msk /*!< Filter bit 6 */
# define CAN_F1DATA0_FD7_Pos (7U)
# define CAN_F1DATA0_FD7_Msk (0x1U << CAN_F1DATA0_FD7_Pos) /*!< 0x00000080 */
# define CAN_F1DATA0_FD7 CAN_F1DATA0_FD7_Msk /*!< Filter bit 7 */
# define CAN_F1DATA0_FD8_Pos (8U)
# define CAN_F1DATA0_FD8_Msk (0x1U << CAN_F1DATA0_FD8_Pos) /*!< 0x00000100 */
# define CAN_F1DATA0_FD8 CAN_F1DATA0_FD8_Msk /*!< Filter bit 8 */
# define CAN_F1DATA0_FD9_Pos (9U)
# define CAN_F1DATA0_FD9_Msk (0x1U << CAN_F1DATA0_FD9_Pos) /*!< 0x00000200 */
# define CAN_F1DATA0_FD9 CAN_F1DATA0_FD9_Msk /*!< Filter bit 9 */
# define CAN_F1DATA0_FD10_Pos (10U)
# define CAN_F1DATA0_FD10_Msk (0x1U << CAN_F1DATA0_FD10_Pos) /*!< 0x00000400 */
# define CAN_F1DATA0_FD10 CAN_F1DATA0_FD10_Msk /*!< Filter bit 10 */
# define CAN_F1DATA0_FD11_Pos (11U)
# define CAN_F1DATA0_FD11_Msk (0x1U << CAN_F1DATA0_FD11_Pos) /*!< 0x00000800 */
# define CAN_F1DATA0_FD11 CAN_F1DATA0_FD11_Msk /*!< Filter bit 11 */
# define CAN_F1DATA0_FD12_Pos (12U)
# define CAN_F1DATA0_FD12_Msk (0x1U << CAN_F1DATA0_FD12_Pos) /*!< 0x00001000 */
# define CAN_F1DATA0_FD12 CAN_F1DATA0_FD12_Msk /*!< Filter bit 12 */
# define CAN_F1DATA0_FD13_Pos (13U)
# define CAN_F1DATA0_FD13_Msk (0x1U << CAN_F1DATA0_FD13_Pos) /*!< 0x00002000 */
# define CAN_F1DATA0_FD13 CAN_F1DATA0_FD13_Msk /*!< Filter bit 13 */
# define CAN_F1DATA0_FD14_Pos (14U)
# define CAN_F1DATA0_FD14_Msk (0x1U << CAN_F1DATA0_FD14_Pos) /*!< 0x00004000 */
# define CAN_F1DATA0_FD14 CAN_F1DATA0_FD14_Msk /*!< Filter bit 14 */
# define CAN_F1DATA0_FD15_Pos (15U)
# define CAN_F1DATA0_FD15_Msk (0x1U << CAN_F1DATA0_FD15_Pos) /*!< 0x00008000 */
# define CAN_F1DATA0_FD15 CAN_F1DATA0_FD15_Msk /*!< Filter bit 15 */
# define CAN_F1DATA0_FD16_Pos (16U)
# define CAN_F1DATA0_FD16_Msk (0x1U << CAN_F1DATA0_FD16_Pos) /*!< 0x00010000 */
# define CAN_F1DATA0_FD16 CAN_F1DATA0_FD16_Msk /*!< Filter bit 16 */
# define CAN_F1DATA0_FD17_Pos (17U)
# define CAN_F1DATA0_FD17_Msk (0x1U << CAN_F1DATA0_FD17_Pos) /*!< 0x00020000 */
# define CAN_F1DATA0_FD17 CAN_F1DATA0_FD17_Msk /*!< Filter bit 17 */
# define CAN_F1DATA0_FD18_Pos (18U)
# define CAN_F1DATA0_FD18_Msk (0x1U << CAN_F1DATA0_FD18_Pos) /*!< 0x00040000 */
# define CAN_F1DATA0_FD18 CAN_F1DATA0_FD18_Msk /*!< Filter bit 18 */
# define CAN_F1DATA0_FD19_Pos (19U)
# define CAN_F1DATA0_FD19_Msk (0x1U << CAN_F1DATA0_FD19_Pos) /*!< 0x00080000 */
# define CAN_F1DATA0_FD19 CAN_F1DATA0_FD19_Msk /*!< Filter bit 19 */
# define CAN_F1DATA0_FD20_Pos (20U)
# define CAN_F1DATA0_FD20_Msk (0x1U << CAN_F1DATA0_FD20_Pos) /*!< 0x00100000 */
# define CAN_F1DATA0_FD20 CAN_F1DATA0_FD20_Msk /*!< Filter bit 20 */
# define CAN_F1DATA0_FD21_Pos (21U)
# define CAN_F1DATA0_FD21_Msk (0x1U << CAN_F1DATA0_FD21_Pos) /*!< 0x00200000 */
# define CAN_F1DATA0_FD21 CAN_F1DATA0_FD21_Msk /*!< Filter bit 21 */
# define CAN_F1DATA0_FD22_Pos (22U)
# define CAN_F1DATA0_FD22_Msk (0x1U << CAN_F1DATA0_FD22_Pos) /*!< 0x00400000 */
# define CAN_F1DATA0_FD22 CAN_F1DATA0_FD22_Msk /*!< Filter bit 22 */
# define CAN_F1DATA0_FD23_Pos (23U)
# define CAN_F1DATA0_FD23_Msk (0x1U << CAN_F1DATA0_FD23_Pos) /*!< 0x00800000 */
# define CAN_F1DATA0_FD23 CAN_F1DATA0_FD23_Msk /*!< Filter bit 23 */
# define CAN_F1DATA0_FD24_Pos (24U)
# define CAN_F1DATA0_FD24_Msk (0x1U << CAN_F1DATA0_FD24_Pos) /*!< 0x01000000 */
# define CAN_F1DATA0_FD24 CAN_F1DATA0_FD24_Msk /*!< Filter bit 24 */
# define CAN_F1DATA0_FD25_Pos (25U)
# define CAN_F1DATA0_FD25_Msk (0x1U << CAN_F1DATA0_FD25_Pos) /*!< 0x02000000 */
# define CAN_F1DATA0_FD25 CAN_F1DATA0_FD25_Msk /*!< Filter bit 25 */
# define CAN_F1DATA0_FD26_Pos (26U)
# define CAN_F1DATA0_FD26_Msk (0x1U << CAN_F1DATA0_FD26_Pos) /*!< 0x04000000 */
# define CAN_F1DATA0_FD26 CAN_F1DATA0_FD26_Msk /*!< Filter bit 26 */
# define CAN_F1DATA0_FD27_Pos (27U)
# define CAN_F1DATA0_FD27_Msk (0x1U << CAN_F1DATA0_FD27_Pos) /*!< 0x08000000 */
# define CAN_F1DATA0_FD27 CAN_F1DATA0_FD27_Msk /*!< Filter bit 27 */
# define CAN_F1DATA0_FD28_Pos (28U)
# define CAN_F1DATA0_FD28_Msk (0x1U << CAN_F1DATA0_FD28_Pos) /*!< 0x10000000 */
# define CAN_F1DATA0_FD28 CAN_F1DATA0_FD28_Msk /*!< Filter bit 28 */
# define CAN_F1DATA0_FD29_Pos (29U)
# define CAN_F1DATA0_FD29_Msk (0x1U << CAN_F1DATA0_FD29_Pos) /*!< 0x20000000 */
# define CAN_F1DATA0_FD29 CAN_F1DATA0_FD29_Msk /*!< Filter bit 29 */
# define CAN_F1DATA0_FD30_Pos (30U)
# define CAN_F1DATA0_FD30_Msk (0x1U << CAN_F1DATA0_FD30_Pos) /*!< 0x40000000 */
# define CAN_F1DATA0_FD30 CAN_F1DATA0_FD30_Msk /*!< Filter bit 30 */
# define CAN_F1DATA0_FD31_Pos (31U)
# define CAN_F1DATA0_FD31_Msk (0x1U << CAN_F1DATA0_FD31_Pos) /*!< 0x80000000 */
# define CAN_F1DATA0_FD31 CAN_F1DATA0_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F2R1 register *******************/
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# define CAN_F2DATA0_FD0_Pos (0U)
# define CAN_F2DATA0_FD0_Msk (0x1U << CAN_F2DATA0_FD0_Pos) /*!< 0x00000001 */
# define CAN_F2DATA0_FD0 CAN_F2DATA0_FD0_Msk /*!< Filter bit 0 */
# define CAN_F2DATA0_FD1_Pos (1U)
# define CAN_F2DATA0_FD1_Msk (0x1U << CAN_F2DATA0_FD1_Pos) /*!< 0x00000002 */
# define CAN_F2DATA0_FD1 CAN_F2DATA0_FD1_Msk /*!< Filter bit 1 */
# define CAN_F2DATA0_FD2_Pos (2U)
# define CAN_F2DATA0_FD2_Msk (0x1U << CAN_F2DATA0_FD2_Pos) /*!< 0x00000004 */
# define CAN_F2DATA0_FD2 CAN_F2DATA0_FD2_Msk /*!< Filter bit 2 */
# define CAN_F2DATA0_FD3_Pos (3U)
# define CAN_F2DATA0_FD3_Msk (0x1U << CAN_F2DATA0_FD3_Pos) /*!< 0x00000008 */
# define CAN_F2DATA0_FD3 CAN_F2DATA0_FD3_Msk /*!< Filter bit 3 */
# define CAN_F2DATA0_FD4_Pos (4U)
# define CAN_F2DATA0_FD4_Msk (0x1U << CAN_F2DATA0_FD4_Pos) /*!< 0x00000010 */
# define CAN_F2DATA0_FD4 CAN_F2DATA0_FD4_Msk /*!< Filter bit 4 */
# define CAN_F2DATA0_FD5_Pos (5U)
# define CAN_F2DATA0_FD5_Msk (0x1U << CAN_F2DATA0_FD5_Pos) /*!< 0x00000020 */
# define CAN_F2DATA0_FD5 CAN_F2DATA0_FD5_Msk /*!< Filter bit 5 */
# define CAN_F2DATA0_FD6_Pos (6U)
# define CAN_F2DATA0_FD6_Msk (0x1U << CAN_F2DATA0_FD6_Pos) /*!< 0x00000040 */
# define CAN_F2DATA0_FD6 CAN_F2DATA0_FD6_Msk /*!< Filter bit 6 */
# define CAN_F2DATA0_FD7_Pos (7U)
# define CAN_F2DATA0_FD7_Msk (0x1U << CAN_F2DATA0_FD7_Pos) /*!< 0x00000080 */
# define CAN_F2DATA0_FD7 CAN_F2DATA0_FD7_Msk /*!< Filter bit 7 */
# define CAN_F2DATA0_FD8_Pos (8U)
# define CAN_F2DATA0_FD8_Msk (0x1U << CAN_F2DATA0_FD8_Pos) /*!< 0x00000100 */
# define CAN_F2DATA0_FD8 CAN_F2DATA0_FD8_Msk /*!< Filter bit 8 */
# define CAN_F2DATA0_FD9_Pos (9U)
# define CAN_F2DATA0_FD9_Msk (0x1U << CAN_F2DATA0_FD9_Pos) /*!< 0x00000200 */
# define CAN_F2DATA0_FD9 CAN_F2DATA0_FD9_Msk /*!< Filter bit 9 */
# define CAN_F2DATA0_FD10_Pos (10U)
# define CAN_F2DATA0_FD10_Msk (0x1U << CAN_F2DATA0_FD10_Pos) /*!< 0x00000400 */
# define CAN_F2DATA0_FD10 CAN_F2DATA0_FD10_Msk /*!< Filter bit 10 */
# define CAN_F2DATA0_FD11_Pos (11U)
# define CAN_F2DATA0_FD11_Msk (0x1U << CAN_F2DATA0_FD11_Pos) /*!< 0x00000800 */
# define CAN_F2DATA0_FD11 CAN_F2DATA0_FD11_Msk /*!< Filter bit 11 */
# define CAN_F2DATA0_FD12_Pos (12U)
# define CAN_F2DATA0_FD12_Msk (0x1U << CAN_F2DATA0_FD12_Pos) /*!< 0x00001000 */
# define CAN_F2DATA0_FD12 CAN_F2DATA0_FD12_Msk /*!< Filter bit 12 */
# define CAN_F2DATA0_FD13_Pos (13U)
# define CAN_F2DATA0_FD13_Msk (0x1U << CAN_F2DATA0_FD13_Pos) /*!< 0x00002000 */
# define CAN_F2DATA0_FD13 CAN_F2DATA0_FD13_Msk /*!< Filter bit 13 */
# define CAN_F2DATA0_FD14_Pos (14U)
# define CAN_F2DATA0_FD14_Msk (0x1U << CAN_F2DATA0_FD14_Pos) /*!< 0x00004000 */
# define CAN_F2DATA0_FD14 CAN_F2DATA0_FD14_Msk /*!< Filter bit 14 */
# define CAN_F2DATA0_FD15_Pos (15U)
# define CAN_F2DATA0_FD15_Msk (0x1U << CAN_F2DATA0_FD15_Pos) /*!< 0x00008000 */
# define CAN_F2DATA0_FD15 CAN_F2DATA0_FD15_Msk /*!< Filter bit 15 */
# define CAN_F2DATA0_FD16_Pos (16U)
# define CAN_F2DATA0_FD16_Msk (0x1U << CAN_F2DATA0_FD16_Pos) /*!< 0x00010000 */
# define CAN_F2DATA0_FD16 CAN_F2DATA0_FD16_Msk /*!< Filter bit 16 */
# define CAN_F2DATA0_FD17_Pos (17U)
# define CAN_F2DATA0_FD17_Msk (0x1U << CAN_F2DATA0_FD17_Pos) /*!< 0x00020000 */
# define CAN_F2DATA0_FD17 CAN_F2DATA0_FD17_Msk /*!< Filter bit 17 */
# define CAN_F2DATA0_FD18_Pos (18U)
# define CAN_F2DATA0_FD18_Msk (0x1U << CAN_F2DATA0_FD18_Pos) /*!< 0x00040000 */
# define CAN_F2DATA0_FD18 CAN_F2DATA0_FD18_Msk /*!< Filter bit 18 */
# define CAN_F2DATA0_FD19_Pos (19U)
# define CAN_F2DATA0_FD19_Msk (0x1U << CAN_F2DATA0_FD19_Pos) /*!< 0x00080000 */
# define CAN_F2DATA0_FD19 CAN_F2DATA0_FD19_Msk /*!< Filter bit 19 */
# define CAN_F2DATA0_FD20_Pos (20U)
# define CAN_F2DATA0_FD20_Msk (0x1U << CAN_F2DATA0_FD20_Pos) /*!< 0x00100000 */
# define CAN_F2DATA0_FD20 CAN_F2DATA0_FD20_Msk /*!< Filter bit 20 */
# define CAN_F2DATA0_FD21_Pos (21U)
# define CAN_F2DATA0_FD21_Msk (0x1U << CAN_F2DATA0_FD21_Pos) /*!< 0x00200000 */
# define CAN_F2DATA0_FD21 CAN_F2DATA0_FD21_Msk /*!< Filter bit 21 */
# define CAN_F2DATA0_FD22_Pos (22U)
# define CAN_F2DATA0_FD22_Msk (0x1U << CAN_F2DATA0_FD22_Pos) /*!< 0x00400000 */
# define CAN_F2DATA0_FD22 CAN_F2DATA0_FD22_Msk /*!< Filter bit 22 */
# define CAN_F2DATA0_FD23_Pos (23U)
# define CAN_F2DATA0_FD23_Msk (0x1U << CAN_F2DATA0_FD23_Pos) /*!< 0x00800000 */
# define CAN_F2DATA0_FD23 CAN_F2DATA0_FD23_Msk /*!< Filter bit 23 */
# define CAN_F2DATA0_FD24_Pos (24U)
# define CAN_F2DATA0_FD24_Msk (0x1U << CAN_F2DATA0_FD24_Pos) /*!< 0x01000000 */
# define CAN_F2DATA0_FD24 CAN_F2DATA0_FD24_Msk /*!< Filter bit 24 */
# define CAN_F2DATA0_FD25_Pos (25U)
# define CAN_F2DATA0_FD25_Msk (0x1U << CAN_F2DATA0_FD25_Pos) /*!< 0x02000000 */
# define CAN_F2DATA0_FD25 CAN_F2DATA0_FD25_Msk /*!< Filter bit 25 */
# define CAN_F2DATA0_FD26_Pos (26U)
# define CAN_F2DATA0_FD26_Msk (0x1U << CAN_F2DATA0_FD26_Pos) /*!< 0x04000000 */
# define CAN_F2DATA0_FD26 CAN_F2DATA0_FD26_Msk /*!< Filter bit 26 */
# define CAN_F2DATA0_FD27_Pos (27U)
# define CAN_F2DATA0_FD27_Msk (0x1U << CAN_F2DATA0_FD27_Pos) /*!< 0x08000000 */
# define CAN_F2DATA0_FD27 CAN_F2DATA0_FD27_Msk /*!< Filter bit 27 */
# define CAN_F2DATA0_FD28_Pos (28U)
# define CAN_F2DATA0_FD28_Msk (0x1U << CAN_F2DATA0_FD28_Pos) /*!< 0x10000000 */
# define CAN_F2DATA0_FD28 CAN_F2DATA0_FD28_Msk /*!< Filter bit 28 */
# define CAN_F2DATA0_FD29_Pos (29U)
# define CAN_F2DATA0_FD29_Msk (0x1U << CAN_F2DATA0_FD29_Pos) /*!< 0x20000000 */
# define CAN_F2DATA0_FD29 CAN_F2DATA0_FD29_Msk /*!< Filter bit 29 */
# define CAN_F2DATA0_FD30_Pos (30U)
# define CAN_F2DATA0_FD30_Msk (0x1U << CAN_F2DATA0_FD30_Pos) /*!< 0x40000000 */
# define CAN_F2DATA0_FD30 CAN_F2DATA0_FD30_Msk /*!< Filter bit 30 */
# define CAN_F2DATA0_FD31_Pos (31U)
# define CAN_F2DATA0_FD31_Msk (0x1U << CAN_F2DATA0_FD31_Pos) /*!< 0x80000000 */
# define CAN_F2DATA0_FD31 CAN_F2DATA0_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F3R1 register *******************/
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# define CAN_F3DATA0_FD0_Pos (0U)
# define CAN_F3DATA0_FD0_Msk (0x1U << CAN_F3DATA0_FD0_Pos) /*!< 0x00000001 */
# define CAN_F3DATA0_FD0 CAN_F3DATA0_FD0_Msk /*!< Filter bit 0 */
# define CAN_F3DATA0_FD1_Pos (1U)
# define CAN_F3DATA0_FD1_Msk (0x1U << CAN_F3DATA0_FD1_Pos) /*!< 0x00000002 */
# define CAN_F3DATA0_FD1 CAN_F3DATA0_FD1_Msk /*!< Filter bit 1 */
# define CAN_F3DATA0_FD2_Pos (2U)
# define CAN_F3DATA0_FD2_Msk (0x1U << CAN_F3DATA0_FD2_Pos) /*!< 0x00000004 */
# define CAN_F3DATA0_FD2 CAN_F3DATA0_FD2_Msk /*!< Filter bit 2 */
# define CAN_F3DATA0_FD3_Pos (3U)
# define CAN_F3DATA0_FD3_Msk (0x1U << CAN_F3DATA0_FD3_Pos) /*!< 0x00000008 */
# define CAN_F3DATA0_FD3 CAN_F3DATA0_FD3_Msk /*!< Filter bit 3 */
# define CAN_F3DATA0_FD4_Pos (4U)
# define CAN_F3DATA0_FD4_Msk (0x1U << CAN_F3DATA0_FD4_Pos) /*!< 0x00000010 */
# define CAN_F3DATA0_FD4 CAN_F3DATA0_FD4_Msk /*!< Filter bit 4 */
# define CAN_F3DATA0_FD5_Pos (5U)
# define CAN_F3DATA0_FD5_Msk (0x1U << CAN_F3DATA0_FD5_Pos) /*!< 0x00000020 */
# define CAN_F3DATA0_FD5 CAN_F3DATA0_FD5_Msk /*!< Filter bit 5 */
# define CAN_F3DATA0_FD6_Pos (6U)
# define CAN_F3DATA0_FD6_Msk (0x1U << CAN_F3DATA0_FD6_Pos) /*!< 0x00000040 */
# define CAN_F3DATA0_FD6 CAN_F3DATA0_FD6_Msk /*!< Filter bit 6 */
# define CAN_F3DATA0_FD7_Pos (7U)
# define CAN_F3DATA0_FD7_Msk (0x1U << CAN_F3DATA0_FD7_Pos) /*!< 0x00000080 */
# define CAN_F3DATA0_FD7 CAN_F3DATA0_FD7_Msk /*!< Filter bit 7 */
# define CAN_F3DATA0_FD8_Pos (8U)
# define CAN_F3DATA0_FD8_Msk (0x1U << CAN_F3DATA0_FD8_Pos) /*!< 0x00000100 */
# define CAN_F3DATA0_FD8 CAN_F3DATA0_FD8_Msk /*!< Filter bit 8 */
# define CAN_F3DATA0_FD9_Pos (9U)
# define CAN_F3DATA0_FD9_Msk (0x1U << CAN_F3DATA0_FD9_Pos) /*!< 0x00000200 */
# define CAN_F3DATA0_FD9 CAN_F3DATA0_FD9_Msk /*!< Filter bit 9 */
# define CAN_F3DATA0_FD10_Pos (10U)
# define CAN_F3DATA0_FD10_Msk (0x1U << CAN_F3DATA0_FD10_Pos) /*!< 0x00000400 */
# define CAN_F3DATA0_FD10 CAN_F3DATA0_FD10_Msk /*!< Filter bit 10 */
# define CAN_F3DATA0_FD11_Pos (11U)
# define CAN_F3DATA0_FD11_Msk (0x1U << CAN_F3DATA0_FD11_Pos) /*!< 0x00000800 */
# define CAN_F3DATA0_FD11 CAN_F3DATA0_FD11_Msk /*!< Filter bit 11 */
# define CAN_F3DATA0_FD12_Pos (12U)
# define CAN_F3DATA0_FD12_Msk (0x1U << CAN_F3DATA0_FD12_Pos) /*!< 0x00001000 */
# define CAN_F3DATA0_FD12 CAN_F3DATA0_FD12_Msk /*!< Filter bit 12 */
# define CAN_F3DATA0_FD13_Pos (13U)
# define CAN_F3DATA0_FD13_Msk (0x1U << CAN_F3DATA0_FD13_Pos) /*!< 0x00002000 */
# define CAN_F3DATA0_FD13 CAN_F3DATA0_FD13_Msk /*!< Filter bit 13 */
# define CAN_F3DATA0_FD14_Pos (14U)
# define CAN_F3DATA0_FD14_Msk (0x1U << CAN_F3DATA0_FD14_Pos) /*!< 0x00004000 */
# define CAN_F3DATA0_FD14 CAN_F3DATA0_FD14_Msk /*!< Filter bit 14 */
# define CAN_F3DATA0_FD15_Pos (15U)
# define CAN_F3DATA0_FD15_Msk (0x1U << CAN_F3DATA0_FD15_Pos) /*!< 0x00008000 */
# define CAN_F3DATA0_FD15 CAN_F3DATA0_FD15_Msk /*!< Filter bit 15 */
# define CAN_F3DATA0_FD16_Pos (16U)
# define CAN_F3DATA0_FD16_Msk (0x1U << CAN_F3DATA0_FD16_Pos) /*!< 0x00010000 */
# define CAN_F3DATA0_FD16 CAN_F3DATA0_FD16_Msk /*!< Filter bit 16 */
# define CAN_F3DATA0_FD17_Pos (17U)
# define CAN_F3DATA0_FD17_Msk (0x1U << CAN_F3DATA0_FD17_Pos) /*!< 0x00020000 */
# define CAN_F3DATA0_FD17 CAN_F3DATA0_FD17_Msk /*!< Filter bit 17 */
# define CAN_F3DATA0_FD18_Pos (18U)
# define CAN_F3DATA0_FD18_Msk (0x1U << CAN_F3DATA0_FD18_Pos) /*!< 0x00040000 */
# define CAN_F3DATA0_FD18 CAN_F3DATA0_FD18_Msk /*!< Filter bit 18 */
# define CAN_F3DATA0_FD19_Pos (19U)
# define CAN_F3DATA0_FD19_Msk (0x1U << CAN_F3DATA0_FD19_Pos) /*!< 0x00080000 */
# define CAN_F3DATA0_FD19 CAN_F3DATA0_FD19_Msk /*!< Filter bit 19 */
# define CAN_F3DATA0_FD20_Pos (20U)
# define CAN_F3DATA0_FD20_Msk (0x1U << CAN_F3DATA0_FD20_Pos) /*!< 0x00100000 */
# define CAN_F3DATA0_FD20 CAN_F3DATA0_FD20_Msk /*!< Filter bit 20 */
# define CAN_F3DATA0_FD21_Pos (21U)
# define CAN_F3DATA0_FD21_Msk (0x1U << CAN_F3DATA0_FD21_Pos) /*!< 0x00200000 */
# define CAN_F3DATA0_FD21 CAN_F3DATA0_FD21_Msk /*!< Filter bit 21 */
# define CAN_F3DATA0_FD22_Pos (22U)
# define CAN_F3DATA0_FD22_Msk (0x1U << CAN_F3DATA0_FD22_Pos) /*!< 0x00400000 */
# define CAN_F3DATA0_FD22 CAN_F3DATA0_FD22_Msk /*!< Filter bit 22 */
# define CAN_F3DATA0_FD23_Pos (23U)
# define CAN_F3DATA0_FD23_Msk (0x1U << CAN_F3DATA0_FD23_Pos) /*!< 0x00800000 */
# define CAN_F3DATA0_FD23 CAN_F3DATA0_FD23_Msk /*!< Filter bit 23 */
# define CAN_F3DATA0_FD24_Pos (24U)
# define CAN_F3DATA0_FD24_Msk (0x1U << CAN_F3DATA0_FD24_Pos) /*!< 0x01000000 */
# define CAN_F3DATA0_FD24 CAN_F3DATA0_FD24_Msk /*!< Filter bit 24 */
# define CAN_F3DATA0_FD25_Pos (25U)
# define CAN_F3DATA0_FD25_Msk (0x1U << CAN_F3DATA0_FD25_Pos) /*!< 0x02000000 */
# define CAN_F3DATA0_FD25 CAN_F3DATA0_FD25_Msk /*!< Filter bit 25 */
# define CAN_F3DATA0_FD26_Pos (26U)
# define CAN_F3DATA0_FD26_Msk (0x1U << CAN_F3DATA0_FD26_Pos) /*!< 0x04000000 */
# define CAN_F3DATA0_FD26 CAN_F3DATA0_FD26_Msk /*!< Filter bit 26 */
# define CAN_F3DATA0_FD27_Pos (27U)
# define CAN_F3DATA0_FD27_Msk (0x1U << CAN_F3DATA0_FD27_Pos) /*!< 0x08000000 */
# define CAN_F3DATA0_FD27 CAN_F3DATA0_FD27_Msk /*!< Filter bit 27 */
# define CAN_F3DATA0_FD28_Pos (28U)
# define CAN_F3DATA0_FD28_Msk (0x1U << CAN_F3DATA0_FD28_Pos) /*!< 0x10000000 */
# define CAN_F3DATA0_FD28 CAN_F3DATA0_FD28_Msk /*!< Filter bit 28 */
# define CAN_F3DATA0_FD29_Pos (29U)
# define CAN_F3DATA0_FD29_Msk (0x1U << CAN_F3DATA0_FD29_Pos) /*!< 0x20000000 */
# define CAN_F3DATA0_FD29 CAN_F3DATA0_FD29_Msk /*!< Filter bit 29 */
# define CAN_F3DATA0_FD30_Pos (30U)
# define CAN_F3DATA0_FD30_Msk (0x1U << CAN_F3DATA0_FD30_Pos) /*!< 0x40000000 */
# define CAN_F3DATA0_FD30 CAN_F3DATA0_FD30_Msk /*!< Filter bit 30 */
# define CAN_F3DATA0_FD31_Pos (31U)
# define CAN_F3DATA0_FD31_Msk (0x1U << CAN_F3DATA0_FD31_Pos) /*!< 0x80000000 */
# define CAN_F3DATA0_FD31 CAN_F3DATA0_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F4R1 register *******************/
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# define CAN_F4DATA0_FD0_Pos (0U)
# define CAN_F4DATA0_FD0_Msk (0x1U << CAN_F4DATA0_FD0_Pos) /*!< 0x00000001 */
# define CAN_F4DATA0_FD0 CAN_F4DATA0_FD0_Msk /*!< Filter bit 0 */
# define CAN_F4DATA0_FD1_Pos (1U)
# define CAN_F4DATA0_FD1_Msk (0x1U << CAN_F4DATA0_FD1_Pos) /*!< 0x00000002 */
# define CAN_F4DATA0_FD1 CAN_F4DATA0_FD1_Msk /*!< Filter bit 1 */
# define CAN_F4DATA0_FD2_Pos (2U)
# define CAN_F4DATA0_FD2_Msk (0x1U << CAN_F4DATA0_FD2_Pos) /*!< 0x00000004 */
# define CAN_F4DATA0_FD2 CAN_F4DATA0_FD2_Msk /*!< Filter bit 2 */
# define CAN_F4DATA0_FD3_Pos (3U)
# define CAN_F4DATA0_FD3_Msk (0x1U << CAN_F4DATA0_FD3_Pos) /*!< 0x00000008 */
# define CAN_F4DATA0_FD3 CAN_F4DATA0_FD3_Msk /*!< Filter bit 3 */
# define CAN_F4DATA0_FD4_Pos (4U)
# define CAN_F4DATA0_FD4_Msk (0x1U << CAN_F4DATA0_FD4_Pos) /*!< 0x00000010 */
# define CAN_F4DATA0_FD4 CAN_F4DATA0_FD4_Msk /*!< Filter bit 4 */
# define CAN_F4DATA0_FD5_Pos (5U)
# define CAN_F4DATA0_FD5_Msk (0x1U << CAN_F4DATA0_FD5_Pos) /*!< 0x00000020 */
# define CAN_F4DATA0_FD5 CAN_F4DATA0_FD5_Msk /*!< Filter bit 5 */
# define CAN_F4DATA0_FD6_Pos (6U)
# define CAN_F4DATA0_FD6_Msk (0x1U << CAN_F4DATA0_FD6_Pos) /*!< 0x00000040 */
# define CAN_F4DATA0_FD6 CAN_F4DATA0_FD6_Msk /*!< Filter bit 6 */
# define CAN_F4DATA0_FD7_Pos (7U)
# define CAN_F4DATA0_FD7_Msk (0x1U << CAN_F4DATA0_FD7_Pos) /*!< 0x00000080 */
# define CAN_F4DATA0_FD7 CAN_F4DATA0_FD7_Msk /*!< Filter bit 7 */
# define CAN_F4DATA0_FD8_Pos (8U)
# define CAN_F4DATA0_FD8_Msk (0x1U << CAN_F4DATA0_FD8_Pos) /*!< 0x00000100 */
# define CAN_F4DATA0_FD8 CAN_F4DATA0_FD8_Msk /*!< Filter bit 8 */
# define CAN_F4DATA0_FD9_Pos (9U)
# define CAN_F4DATA0_FD9_Msk (0x1U << CAN_F4DATA0_FD9_Pos) /*!< 0x00000200 */
# define CAN_F4DATA0_FD9 CAN_F4DATA0_FD9_Msk /*!< Filter bit 9 */
# define CAN_F4DATA0_FD10_Pos (10U)
# define CAN_F4DATA0_FD10_Msk (0x1U << CAN_F4DATA0_FD10_Pos) /*!< 0x00000400 */
# define CAN_F4DATA0_FD10 CAN_F4DATA0_FD10_Msk /*!< Filter bit 10 */
# define CAN_F4DATA0_FD11_Pos (11U)
# define CAN_F4DATA0_FD11_Msk (0x1U << CAN_F4DATA0_FD11_Pos) /*!< 0x00000800 */
# define CAN_F4DATA0_FD11 CAN_F4DATA0_FD11_Msk /*!< Filter bit 11 */
# define CAN_F4DATA0_FD12_Pos (12U)
# define CAN_F4DATA0_FD12_Msk (0x1U << CAN_F4DATA0_FD12_Pos) /*!< 0x00001000 */
# define CAN_F4DATA0_FD12 CAN_F4DATA0_FD12_Msk /*!< Filter bit 12 */
# define CAN_F4DATA0_FD13_Pos (13U)
# define CAN_F4DATA0_FD13_Msk (0x1U << CAN_F4DATA0_FD13_Pos) /*!< 0x00002000 */
# define CAN_F4DATA0_FD13 CAN_F4DATA0_FD13_Msk /*!< Filter bit 13 */
# define CAN_F4DATA0_FD14_Pos (14U)
# define CAN_F4DATA0_FD14_Msk (0x1U << CAN_F4DATA0_FD14_Pos) /*!< 0x00004000 */
# define CAN_F4DATA0_FD14 CAN_F4DATA0_FD14_Msk /*!< Filter bit 14 */
# define CAN_F4DATA0_FD15_Pos (15U)
# define CAN_F4DATA0_FD15_Msk (0x1U << CAN_F4DATA0_FD15_Pos) /*!< 0x00008000 */
# define CAN_F4DATA0_FD15 CAN_F4DATA0_FD15_Msk /*!< Filter bit 15 */
# define CAN_F4DATA0_FD16_Pos (16U)
# define CAN_F4DATA0_FD16_Msk (0x1U << CAN_F4DATA0_FD16_Pos) /*!< 0x00010000 */
# define CAN_F4DATA0_FD16 CAN_F4DATA0_FD16_Msk /*!< Filter bit 16 */
# define CAN_F4DATA0_FD17_Pos (17U)
# define CAN_F4DATA0_FD17_Msk (0x1U << CAN_F4DATA0_FD17_Pos) /*!< 0x00020000 */
# define CAN_F4DATA0_FD17 CAN_F4DATA0_FD17_Msk /*!< Filter bit 17 */
# define CAN_F4DATA0_FD18_Pos (18U)
# define CAN_F4DATA0_FD18_Msk (0x1U << CAN_F4DATA0_FD18_Pos) /*!< 0x00040000 */
# define CAN_F4DATA0_FD18 CAN_F4DATA0_FD18_Msk /*!< Filter bit 18 */
# define CAN_F4DATA0_FD19_Pos (19U)
# define CAN_F4DATA0_FD19_Msk (0x1U << CAN_F4DATA0_FD19_Pos) /*!< 0x00080000 */
# define CAN_F4DATA0_FD19 CAN_F4DATA0_FD19_Msk /*!< Filter bit 19 */
# define CAN_F4DATA0_FD20_Pos (20U)
# define CAN_F4DATA0_FD20_Msk (0x1U << CAN_F4DATA0_FD20_Pos) /*!< 0x00100000 */
# define CAN_F4DATA0_FD20 CAN_F4DATA0_FD20_Msk /*!< Filter bit 20 */
# define CAN_F4DATA0_FD21_Pos (21U)
# define CAN_F4DATA0_FD21_Msk (0x1U << CAN_F4DATA0_FD21_Pos) /*!< 0x00200000 */
# define CAN_F4DATA0_FD21 CAN_F4DATA0_FD21_Msk /*!< Filter bit 21 */
# define CAN_F4DATA0_FD22_Pos (22U)
# define CAN_F4DATA0_FD22_Msk (0x1U << CAN_F4DATA0_FD22_Pos) /*!< 0x00400000 */
# define CAN_F4DATA0_FD22 CAN_F4DATA0_FD22_Msk /*!< Filter bit 22 */
# define CAN_F4DATA0_FD23_Pos (23U)
# define CAN_F4DATA0_FD23_Msk (0x1U << CAN_F4DATA0_FD23_Pos) /*!< 0x00800000 */
# define CAN_F4DATA0_FD23 CAN_F4DATA0_FD23_Msk /*!< Filter bit 23 */
# define CAN_F4DATA0_FD24_Pos (24U)
# define CAN_F4DATA0_FD24_Msk (0x1U << CAN_F4DATA0_FD24_Pos) /*!< 0x01000000 */
# define CAN_F4DATA0_FD24 CAN_F4DATA0_FD24_Msk /*!< Filter bit 24 */
# define CAN_F4DATA0_FD25_Pos (25U)
# define CAN_F4DATA0_FD25_Msk (0x1U << CAN_F4DATA0_FD25_Pos) /*!< 0x02000000 */
# define CAN_F4DATA0_FD25 CAN_F4DATA0_FD25_Msk /*!< Filter bit 25 */
# define CAN_F4DATA0_FD26_Pos (26U)
# define CAN_F4DATA0_FD26_Msk (0x1U << CAN_F4DATA0_FD26_Pos) /*!< 0x04000000 */
# define CAN_F4DATA0_FD26 CAN_F4DATA0_FD26_Msk /*!< Filter bit 26 */
# define CAN_F4DATA0_FD27_Pos (27U)
# define CAN_F4DATA0_FD27_Msk (0x1U << CAN_F4DATA0_FD27_Pos) /*!< 0x08000000 */
# define CAN_F4DATA0_FD27 CAN_F4DATA0_FD27_Msk /*!< Filter bit 27 */
# define CAN_F4DATA0_FD28_Pos (28U)
# define CAN_F4DATA0_FD28_Msk (0x1U << CAN_F4DATA0_FD28_Pos) /*!< 0x10000000 */
# define CAN_F4DATA0_FD28 CAN_F4DATA0_FD28_Msk /*!< Filter bit 28 */
# define CAN_F4DATA0_FD29_Pos (29U)
# define CAN_F4DATA0_FD29_Msk (0x1U << CAN_F4DATA0_FD29_Pos) /*!< 0x20000000 */
# define CAN_F4DATA0_FD29 CAN_F4DATA0_FD29_Msk /*!< Filter bit 29 */
# define CAN_F4DATA0_FD30_Pos (30U)
# define CAN_F4DATA0_FD30_Msk (0x1U << CAN_F4DATA0_FD30_Pos) /*!< 0x40000000 */
# define CAN_F4DATA0_FD30 CAN_F4DATA0_FD30_Msk /*!< Filter bit 30 */
# define CAN_F4DATA0_FD31_Pos (31U)
# define CAN_F4DATA0_FD31_Msk (0x1U << CAN_F4DATA0_FD31_Pos) /*!< 0x80000000 */
# define CAN_F4DATA0_FD31 CAN_F4DATA0_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F5R1 register *******************/
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# define CAN_F5DATA0_FD0_Pos (0U)
# define CAN_F5DATA0_FD0_Msk (0x1U << CAN_F5DATA0_FD0_Pos) /*!< 0x00000001 */
# define CAN_F5DATA0_FD0 CAN_F5DATA0_FD0_Msk /*!< Filter bit 0 */
# define CAN_F5DATA0_FD1_Pos (1U)
# define CAN_F5DATA0_FD1_Msk (0x1U << CAN_F5DATA0_FD1_Pos) /*!< 0x00000002 */
# define CAN_F5DATA0_FD1 CAN_F5DATA0_FD1_Msk /*!< Filter bit 1 */
# define CAN_F5DATA0_FD2_Pos (2U)
# define CAN_F5DATA0_FD2_Msk (0x1U << CAN_F5DATA0_FD2_Pos) /*!< 0x00000004 */
# define CAN_F5DATA0_FD2 CAN_F5DATA0_FD2_Msk /*!< Filter bit 2 */
# define CAN_F5DATA0_FD3_Pos (3U)
# define CAN_F5DATA0_FD3_Msk (0x1U << CAN_F5DATA0_FD3_Pos) /*!< 0x00000008 */
# define CAN_F5DATA0_FD3 CAN_F5DATA0_FD3_Msk /*!< Filter bit 3 */
# define CAN_F5DATA0_FD4_Pos (4U)
# define CAN_F5DATA0_FD4_Msk (0x1U << CAN_F5DATA0_FD4_Pos) /*!< 0x00000010 */
# define CAN_F5DATA0_FD4 CAN_F5DATA0_FD4_Msk /*!< Filter bit 4 */
# define CAN_F5DATA0_FD5_Pos (5U)
# define CAN_F5DATA0_FD5_Msk (0x1U << CAN_F5DATA0_FD5_Pos) /*!< 0x00000020 */
# define CAN_F5DATA0_FD5 CAN_F5DATA0_FD5_Msk /*!< Filter bit 5 */
# define CAN_F5DATA0_FD6_Pos (6U)
# define CAN_F5DATA0_FD6_Msk (0x1U << CAN_F5DATA0_FD6_Pos) /*!< 0x00000040 */
# define CAN_F5DATA0_FD6 CAN_F5DATA0_FD6_Msk /*!< Filter bit 6 */
# define CAN_F5DATA0_FD7_Pos (7U)
# define CAN_F5DATA0_FD7_Msk (0x1U << CAN_F5DATA0_FD7_Pos) /*!< 0x00000080 */
# define CAN_F5DATA0_FD7 CAN_F5DATA0_FD7_Msk /*!< Filter bit 7 */
# define CAN_F5DATA0_FD8_Pos (8U)
# define CAN_F5DATA0_FD8_Msk (0x1U << CAN_F5DATA0_FD8_Pos) /*!< 0x00000100 */
# define CAN_F5DATA0_FD8 CAN_F5DATA0_FD8_Msk /*!< Filter bit 8 */
# define CAN_F5DATA0_FD9_Pos (9U)
# define CAN_F5DATA0_FD9_Msk (0x1U << CAN_F5DATA0_FD9_Pos) /*!< 0x00000200 */
# define CAN_F5DATA0_FD9 CAN_F5DATA0_FD9_Msk /*!< Filter bit 9 */
# define CAN_F5DATA0_FD10_Pos (10U)
# define CAN_F5DATA0_FD10_Msk (0x1U << CAN_F5DATA0_FD10_Pos) /*!< 0x00000400 */
# define CAN_F5DATA0_FD10 CAN_F5DATA0_FD10_Msk /*!< Filter bit 10 */
# define CAN_F5DATA0_FD11_Pos (11U)
# define CAN_F5DATA0_FD11_Msk (0x1U << CAN_F5DATA0_FD11_Pos) /*!< 0x00000800 */
# define CAN_F5DATA0_FD11 CAN_F5DATA0_FD11_Msk /*!< Filter bit 11 */
# define CAN_F5DATA0_FD12_Pos (12U)
# define CAN_F5DATA0_FD12_Msk (0x1U << CAN_F5DATA0_FD12_Pos) /*!< 0x00001000 */
# define CAN_F5DATA0_FD12 CAN_F5DATA0_FD12_Msk /*!< Filter bit 12 */
# define CAN_F5DATA0_FD13_Pos (13U)
# define CAN_F5DATA0_FD13_Msk (0x1U << CAN_F5DATA0_FD13_Pos) /*!< 0x00002000 */
# define CAN_F5DATA0_FD13 CAN_F5DATA0_FD13_Msk /*!< Filter bit 13 */
# define CAN_F5DATA0_FD14_Pos (14U)
# define CAN_F5DATA0_FD14_Msk (0x1U << CAN_F5DATA0_FD14_Pos) /*!< 0x00004000 */
# define CAN_F5DATA0_FD14 CAN_F5DATA0_FD14_Msk /*!< Filter bit 14 */
# define CAN_F5DATA0_FD15_Pos (15U)
# define CAN_F5DATA0_FD15_Msk (0x1U << CAN_F5DATA0_FD15_Pos) /*!< 0x00008000 */
# define CAN_F5DATA0_FD15 CAN_F5DATA0_FD15_Msk /*!< Filter bit 15 */
# define CAN_F5DATA0_FD16_Pos (16U)
# define CAN_F5DATA0_FD16_Msk (0x1U << CAN_F5DATA0_FD16_Pos) /*!< 0x00010000 */
# define CAN_F5DATA0_FD16 CAN_F5DATA0_FD16_Msk /*!< Filter bit 16 */
# define CAN_F5DATA0_FD17_Pos (17U)
# define CAN_F5DATA0_FD17_Msk (0x1U << CAN_F5DATA0_FD17_Pos) /*!< 0x00020000 */
# define CAN_F5DATA0_FD17 CAN_F5DATA0_FD17_Msk /*!< Filter bit 17 */
# define CAN_F5DATA0_FD18_Pos (18U)
# define CAN_F5DATA0_FD18_Msk (0x1U << CAN_F5DATA0_FD18_Pos) /*!< 0x00040000 */
# define CAN_F5DATA0_FD18 CAN_F5DATA0_FD18_Msk /*!< Filter bit 18 */
# define CAN_F5DATA0_FD19_Pos (19U)
# define CAN_F5DATA0_FD19_Msk (0x1U << CAN_F5DATA0_FD19_Pos) /*!< 0x00080000 */
# define CAN_F5DATA0_FD19 CAN_F5DATA0_FD19_Msk /*!< Filter bit 19 */
# define CAN_F5DATA0_FD20_Pos (20U)
# define CAN_F5DATA0_FD20_Msk (0x1U << CAN_F5DATA0_FD20_Pos) /*!< 0x00100000 */
# define CAN_F5DATA0_FD20 CAN_F5DATA0_FD20_Msk /*!< Filter bit 20 */
# define CAN_F5DATA0_FD21_Pos (21U)
# define CAN_F5DATA0_FD21_Msk (0x1U << CAN_F5DATA0_FD21_Pos) /*!< 0x00200000 */
# define CAN_F5DATA0_FD21 CAN_F5DATA0_FD21_Msk /*!< Filter bit 21 */
# define CAN_F5DATA0_FD22_Pos (22U)
# define CAN_F5DATA0_FD22_Msk (0x1U << CAN_F5DATA0_FD22_Pos) /*!< 0x00400000 */
# define CAN_F5DATA0_FD22 CAN_F5DATA0_FD22_Msk /*!< Filter bit 22 */
# define CAN_F5DATA0_FD23_Pos (23U)
# define CAN_F5DATA0_FD23_Msk (0x1U << CAN_F5DATA0_FD23_Pos) /*!< 0x00800000 */
# define CAN_F5DATA0_FD23 CAN_F5DATA0_FD23_Msk /*!< Filter bit 23 */
# define CAN_F5DATA0_FD24_Pos (24U)
# define CAN_F5DATA0_FD24_Msk (0x1U << CAN_F5DATA0_FD24_Pos) /*!< 0x01000000 */
# define CAN_F5DATA0_FD24 CAN_F5DATA0_FD24_Msk /*!< Filter bit 24 */
# define CAN_F5DATA0_FD25_Pos (25U)
# define CAN_F5DATA0_FD25_Msk (0x1U << CAN_F5DATA0_FD25_Pos) /*!< 0x02000000 */
# define CAN_F5DATA0_FD25 CAN_F5DATA0_FD25_Msk /*!< Filter bit 25 */
# define CAN_F5DATA0_FD26_Pos (26U)
# define CAN_F5DATA0_FD26_Msk (0x1U << CAN_F5DATA0_FD26_Pos) /*!< 0x04000000 */
# define CAN_F5DATA0_FD26 CAN_F5DATA0_FD26_Msk /*!< Filter bit 26 */
# define CAN_F5DATA0_FD27_Pos (27U)
# define CAN_F5DATA0_FD27_Msk (0x1U << CAN_F5DATA0_FD27_Pos) /*!< 0x08000000 */
# define CAN_F5DATA0_FD27 CAN_F5DATA0_FD27_Msk /*!< Filter bit 27 */
# define CAN_F5DATA0_FD28_Pos (28U)
# define CAN_F5DATA0_FD28_Msk (0x1U << CAN_F5DATA0_FD28_Pos) /*!< 0x10000000 */
# define CAN_F5DATA0_FD28 CAN_F5DATA0_FD28_Msk /*!< Filter bit 28 */
# define CAN_F5DATA0_FD29_Pos (29U)
# define CAN_F5DATA0_FD29_Msk (0x1U << CAN_F5DATA0_FD29_Pos) /*!< 0x20000000 */
# define CAN_F5DATA0_FD29 CAN_F5DATA0_FD29_Msk /*!< Filter bit 29 */
# define CAN_F5DATA0_FD30_Pos (30U)
# define CAN_F5DATA0_FD30_Msk (0x1U << CAN_F5DATA0_FD30_Pos) /*!< 0x40000000 */
# define CAN_F5DATA0_FD30 CAN_F5DATA0_FD30_Msk /*!< Filter bit 30 */
# define CAN_F5DATA0_FD31_Pos (31U)
# define CAN_F5DATA0_FD31_Msk (0x1U << CAN_F5DATA0_FD31_Pos) /*!< 0x80000000 */
# define CAN_F5DATA0_FD31 CAN_F5DATA0_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F6R1 register *******************/
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# define CAN_F6DATA0_FD0_Pos (0U)
# define CAN_F6DATA0_FD0_Msk (0x1U << CAN_F6DATA0_FD0_Pos) /*!< 0x00000001 */
# define CAN_F6DATA0_FD0 CAN_F6DATA0_FD0_Msk /*!< Filter bit 0 */
# define CAN_F6DATA0_FD1_Pos (1U)
# define CAN_F6DATA0_FD1_Msk (0x1U << CAN_F6DATA0_FD1_Pos) /*!< 0x00000002 */
# define CAN_F6DATA0_FD1 CAN_F6DATA0_FD1_Msk /*!< Filter bit 1 */
# define CAN_F6DATA0_FD2_Pos (2U)
# define CAN_F6DATA0_FD2_Msk (0x1U << CAN_F6DATA0_FD2_Pos) /*!< 0x00000004 */
# define CAN_F6DATA0_FD2 CAN_F6DATA0_FD2_Msk /*!< Filter bit 2 */
# define CAN_F6DATA0_FD3_Pos (3U)
# define CAN_F6DATA0_FD3_Msk (0x1U << CAN_F6DATA0_FD3_Pos) /*!< 0x00000008 */
# define CAN_F6DATA0_FD3 CAN_F6DATA0_FD3_Msk /*!< Filter bit 3 */
# define CAN_F6DATA0_FD4_Pos (4U)
# define CAN_F6DATA0_FD4_Msk (0x1U << CAN_F6DATA0_FD4_Pos) /*!< 0x00000010 */
# define CAN_F6DATA0_FD4 CAN_F6DATA0_FD4_Msk /*!< Filter bit 4 */
# define CAN_F6DATA0_FD5_Pos (5U)
# define CAN_F6DATA0_FD5_Msk (0x1U << CAN_F6DATA0_FD5_Pos) /*!< 0x00000020 */
# define CAN_F6DATA0_FD5 CAN_F6DATA0_FD5_Msk /*!< Filter bit 5 */
# define CAN_F6DATA0_FD6_Pos (6U)
# define CAN_F6DATA0_FD6_Msk (0x1U << CAN_F6DATA0_FD6_Pos) /*!< 0x00000040 */
# define CAN_F6DATA0_FD6 CAN_F6DATA0_FD6_Msk /*!< Filter bit 6 */
# define CAN_F6DATA0_FD7_Pos (7U)
# define CAN_F6DATA0_FD7_Msk (0x1U << CAN_F6DATA0_FD7_Pos) /*!< 0x00000080 */
# define CAN_F6DATA0_FD7 CAN_F6DATA0_FD7_Msk /*!< Filter bit 7 */
# define CAN_F6DATA0_FD8_Pos (8U)
# define CAN_F6DATA0_FD8_Msk (0x1U << CAN_F6DATA0_FD8_Pos) /*!< 0x00000100 */
# define CAN_F6DATA0_FD8 CAN_F6DATA0_FD8_Msk /*!< Filter bit 8 */
# define CAN_F6DATA0_FD9_Pos (9U)
# define CAN_F6DATA0_FD9_Msk (0x1U << CAN_F6DATA0_FD9_Pos) /*!< 0x00000200 */
# define CAN_F6DATA0_FD9 CAN_F6DATA0_FD9_Msk /*!< Filter bit 9 */
# define CAN_F6DATA0_FD10_Pos (10U)
# define CAN_F6DATA0_FD10_Msk (0x1U << CAN_F6DATA0_FD10_Pos) /*!< 0x00000400 */
# define CAN_F6DATA0_FD10 CAN_F6DATA0_FD10_Msk /*!< Filter bit 10 */
# define CAN_F6DATA0_FD11_Pos (11U)
# define CAN_F6DATA0_FD11_Msk (0x1U << CAN_F6DATA0_FD11_Pos) /*!< 0x00000800 */
# define CAN_F6DATA0_FD11 CAN_F6DATA0_FD11_Msk /*!< Filter bit 11 */
# define CAN_F6DATA0_FD12_Pos (12U)
# define CAN_F6DATA0_FD12_Msk (0x1U << CAN_F6DATA0_FD12_Pos) /*!< 0x00001000 */
# define CAN_F6DATA0_FD12 CAN_F6DATA0_FD12_Msk /*!< Filter bit 12 */
# define CAN_F6DATA0_FD13_Pos (13U)
# define CAN_F6DATA0_FD13_Msk (0x1U << CAN_F6DATA0_FD13_Pos) /*!< 0x00002000 */
# define CAN_F6DATA0_FD13 CAN_F6DATA0_FD13_Msk /*!< Filter bit 13 */
# define CAN_F6DATA0_FD14_Pos (14U)
# define CAN_F6DATA0_FD14_Msk (0x1U << CAN_F6DATA0_FD14_Pos) /*!< 0x00004000 */
# define CAN_F6DATA0_FD14 CAN_F6DATA0_FD14_Msk /*!< Filter bit 14 */
# define CAN_F6DATA0_FD15_Pos (15U)
# define CAN_F6DATA0_FD15_Msk (0x1U << CAN_F6DATA0_FD15_Pos) /*!< 0x00008000 */
# define CAN_F6DATA0_FD15 CAN_F6DATA0_FD15_Msk /*!< Filter bit 15 */
# define CAN_F6DATA0_FD16_Pos (16U)
# define CAN_F6DATA0_FD16_Msk (0x1U << CAN_F6DATA0_FD16_Pos) /*!< 0x00010000 */
# define CAN_F6DATA0_FD16 CAN_F6DATA0_FD16_Msk /*!< Filter bit 16 */
# define CAN_F6DATA0_FD17_Pos (17U)
# define CAN_F6DATA0_FD17_Msk (0x1U << CAN_F6DATA0_FD17_Pos) /*!< 0x00020000 */
# define CAN_F6DATA0_FD17 CAN_F6DATA0_FD17_Msk /*!< Filter bit 17 */
# define CAN_F6DATA0_FD18_Pos (18U)
# define CAN_F6DATA0_FD18_Msk (0x1U << CAN_F6DATA0_FD18_Pos) /*!< 0x00040000 */
# define CAN_F6DATA0_FD18 CAN_F6DATA0_FD18_Msk /*!< Filter bit 18 */
# define CAN_F6DATA0_FD19_Pos (19U)
# define CAN_F6DATA0_FD19_Msk (0x1U << CAN_F6DATA0_FD19_Pos) /*!< 0x00080000 */
# define CAN_F6DATA0_FD19 CAN_F6DATA0_FD19_Msk /*!< Filter bit 19 */
# define CAN_F6DATA0_FD20_Pos (20U)
# define CAN_F6DATA0_FD20_Msk (0x1U << CAN_F6DATA0_FD20_Pos) /*!< 0x00100000 */
# define CAN_F6DATA0_FD20 CAN_F6DATA0_FD20_Msk /*!< Filter bit 20 */
# define CAN_F6DATA0_FD21_Pos (21U)
# define CAN_F6DATA0_FD21_Msk (0x1U << CAN_F6DATA0_FD21_Pos) /*!< 0x00200000 */
# define CAN_F6DATA0_FD21 CAN_F6DATA0_FD21_Msk /*!< Filter bit 21 */
# define CAN_F6DATA0_FD22_Pos (22U)
# define CAN_F6DATA0_FD22_Msk (0x1U << CAN_F6DATA0_FD22_Pos) /*!< 0x00400000 */
# define CAN_F6DATA0_FD22 CAN_F6DATA0_FD22_Msk /*!< Filter bit 22 */
# define CAN_F6DATA0_FD23_Pos (23U)
# define CAN_F6DATA0_FD23_Msk (0x1U << CAN_F6DATA0_FD23_Pos) /*!< 0x00800000 */
# define CAN_F6DATA0_FD23 CAN_F6DATA0_FD23_Msk /*!< Filter bit 23 */
# define CAN_F6DATA0_FD24_Pos (24U)
# define CAN_F6DATA0_FD24_Msk (0x1U << CAN_F6DATA0_FD24_Pos) /*!< 0x01000000 */
# define CAN_F6DATA0_FD24 CAN_F6DATA0_FD24_Msk /*!< Filter bit 24 */
# define CAN_F6DATA0_FD25_Pos (25U)
# define CAN_F6DATA0_FD25_Msk (0x1U << CAN_F6DATA0_FD25_Pos) /*!< 0x02000000 */
# define CAN_F6DATA0_FD25 CAN_F6DATA0_FD25_Msk /*!< Filter bit 25 */
# define CAN_F6DATA0_FD26_Pos (26U)
# define CAN_F6DATA0_FD26_Msk (0x1U << CAN_F6DATA0_FD26_Pos) /*!< 0x04000000 */
# define CAN_F6DATA0_FD26 CAN_F6DATA0_FD26_Msk /*!< Filter bit 26 */
# define CAN_F6DATA0_FD27_Pos (27U)
# define CAN_F6DATA0_FD27_Msk (0x1U << CAN_F6DATA0_FD27_Pos) /*!< 0x08000000 */
# define CAN_F6DATA0_FD27 CAN_F6DATA0_FD27_Msk /*!< Filter bit 27 */
# define CAN_F6DATA0_FD28_Pos (28U)
# define CAN_F6DATA0_FD28_Msk (0x1U << CAN_F6DATA0_FD28_Pos) /*!< 0x10000000 */
# define CAN_F6DATA0_FD28 CAN_F6DATA0_FD28_Msk /*!< Filter bit 28 */
# define CAN_F6DATA0_FD29_Pos (29U)
# define CAN_F6DATA0_FD29_Msk (0x1U << CAN_F6DATA0_FD29_Pos) /*!< 0x20000000 */
# define CAN_F6DATA0_FD29 CAN_F6DATA0_FD29_Msk /*!< Filter bit 29 */
# define CAN_F6DATA0_FD30_Pos (30U)
# define CAN_F6DATA0_FD30_Msk (0x1U << CAN_F6DATA0_FD30_Pos) /*!< 0x40000000 */
# define CAN_F6DATA0_FD30 CAN_F6DATA0_FD30_Msk /*!< Filter bit 30 */
# define CAN_F6DATA0_FD31_Pos (31U)
# define CAN_F6DATA0_FD31_Msk (0x1U << CAN_F6DATA0_FD31_Pos) /*!< 0x80000000 */
# define CAN_F6DATA0_FD31 CAN_F6DATA0_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F7R1 register *******************/
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# define CAN_F7DATA0_FD0_Pos (0U)
# define CAN_F7DATA0_FD0_Msk (0x1U << CAN_F7DATA0_FD0_Pos) /*!< 0x00000001 */
# define CAN_F7DATA0_FD0 CAN_F7DATA0_FD0_Msk /*!< Filter bit 0 */
# define CAN_F7DATA0_FD1_Pos (1U)
# define CAN_F7DATA0_FD1_Msk (0x1U << CAN_F7DATA0_FD1_Pos) /*!< 0x00000002 */
# define CAN_F7DATA0_FD1 CAN_F7DATA0_FD1_Msk /*!< Filter bit 1 */
# define CAN_F7DATA0_FD2_Pos (2U)
# define CAN_F7DATA0_FD2_Msk (0x1U << CAN_F7DATA0_FD2_Pos) /*!< 0x00000004 */
# define CAN_F7DATA0_FD2 CAN_F7DATA0_FD2_Msk /*!< Filter bit 2 */
# define CAN_F7DATA0_FD3_Pos (3U)
# define CAN_F7DATA0_FD3_Msk (0x1U << CAN_F7DATA0_FD3_Pos) /*!< 0x00000008 */
# define CAN_F7DATA0_FD3 CAN_F7DATA0_FD3_Msk /*!< Filter bit 3 */
# define CAN_F7DATA0_FD4_Pos (4U)
# define CAN_F7DATA0_FD4_Msk (0x1U << CAN_F7DATA0_FD4_Pos) /*!< 0x00000010 */
# define CAN_F7DATA0_FD4 CAN_F7DATA0_FD4_Msk /*!< Filter bit 4 */
# define CAN_F7DATA0_FD5_Pos (5U)
# define CAN_F7DATA0_FD5_Msk (0x1U << CAN_F7DATA0_FD5_Pos) /*!< 0x00000020 */
# define CAN_F7DATA0_FD5 CAN_F7DATA0_FD5_Msk /*!< Filter bit 5 */
# define CAN_F7DATA0_FD6_Pos (6U)
# define CAN_F7DATA0_FD6_Msk (0x1U << CAN_F7DATA0_FD6_Pos) /*!< 0x00000040 */
# define CAN_F7DATA0_FD6 CAN_F7DATA0_FD6_Msk /*!< Filter bit 6 */
# define CAN_F7DATA0_FD7_Pos (7U)
# define CAN_F7DATA0_FD7_Msk (0x1U << CAN_F7DATA0_FD7_Pos) /*!< 0x00000080 */
# define CAN_F7DATA0_FD7 CAN_F7DATA0_FD7_Msk /*!< Filter bit 7 */
# define CAN_F7DATA0_FD8_Pos (8U)
# define CAN_F7DATA0_FD8_Msk (0x1U << CAN_F7DATA0_FD8_Pos) /*!< 0x00000100 */
# define CAN_F7DATA0_FD8 CAN_F7DATA0_FD8_Msk /*!< Filter bit 8 */
# define CAN_F7DATA0_FD9_Pos (9U)
# define CAN_F7DATA0_FD9_Msk (0x1U << CAN_F7DATA0_FD9_Pos) /*!< 0x00000200 */
# define CAN_F7DATA0_FD9 CAN_F7DATA0_FD9_Msk /*!< Filter bit 9 */
# define CAN_F7DATA0_FD10_Pos (10U)
# define CAN_F7DATA0_FD10_Msk (0x1U << CAN_F7DATA0_FD10_Pos) /*!< 0x00000400 */
# define CAN_F7DATA0_FD10 CAN_F7DATA0_FD10_Msk /*!< Filter bit 10 */
# define CAN_F7DATA0_FD11_Pos (11U)
# define CAN_F7DATA0_FD11_Msk (0x1U << CAN_F7DATA0_FD11_Pos) /*!< 0x00000800 */
# define CAN_F7DATA0_FD11 CAN_F7DATA0_FD11_Msk /*!< Filter bit 11 */
# define CAN_F7DATA0_FD12_Pos (12U)
# define CAN_F7DATA0_FD12_Msk (0x1U << CAN_F7DATA0_FD12_Pos) /*!< 0x00001000 */
# define CAN_F7DATA0_FD12 CAN_F7DATA0_FD12_Msk /*!< Filter bit 12 */
# define CAN_F7DATA0_FD13_Pos (13U)
# define CAN_F7DATA0_FD13_Msk (0x1U << CAN_F7DATA0_FD13_Pos) /*!< 0x00002000 */
# define CAN_F7DATA0_FD13 CAN_F7DATA0_FD13_Msk /*!< Filter bit 13 */
# define CAN_F7DATA0_FD14_Pos (14U)
# define CAN_F7DATA0_FD14_Msk (0x1U << CAN_F7DATA0_FD14_Pos) /*!< 0x00004000 */
# define CAN_F7DATA0_FD14 CAN_F7DATA0_FD14_Msk /*!< Filter bit 14 */
# define CAN_F7DATA0_FD15_Pos (15U)
# define CAN_F7DATA0_FD15_Msk (0x1U << CAN_F7DATA0_FD15_Pos) /*!< 0x00008000 */
# define CAN_F7DATA0_FD15 CAN_F7DATA0_FD15_Msk /*!< Filter bit 15 */
# define CAN_F7DATA0_FD16_Pos (16U)
# define CAN_F7DATA0_FD16_Msk (0x1U << CAN_F7DATA0_FD16_Pos) /*!< 0x00010000 */
# define CAN_F7DATA0_FD16 CAN_F7DATA0_FD16_Msk /*!< Filter bit 16 */
# define CAN_F7DATA0_FD17_Pos (17U)
# define CAN_F7DATA0_FD17_Msk (0x1U << CAN_F7DATA0_FD17_Pos) /*!< 0x00020000 */
# define CAN_F7DATA0_FD17 CAN_F7DATA0_FD17_Msk /*!< Filter bit 17 */
# define CAN_F7DATA0_FD18_Pos (18U)
# define CAN_F7DATA0_FD18_Msk (0x1U << CAN_F7DATA0_FD18_Pos) /*!< 0x00040000 */
# define CAN_F7DATA0_FD18 CAN_F7DATA0_FD18_Msk /*!< Filter bit 18 */
# define CAN_F7DATA0_FD19_Pos (19U)
# define CAN_F7DATA0_FD19_Msk (0x1U << CAN_F7DATA0_FD19_Pos) /*!< 0x00080000 */
# define CAN_F7DATA0_FD19 CAN_F7DATA0_FD19_Msk /*!< Filter bit 19 */
# define CAN_F7DATA0_FD20_Pos (20U)
# define CAN_F7DATA0_FD20_Msk (0x1U << CAN_F7DATA0_FD20_Pos) /*!< 0x00100000 */
# define CAN_F7DATA0_FD20 CAN_F7DATA0_FD20_Msk /*!< Filter bit 20 */
# define CAN_F7DATA0_FD21_Pos (21U)
# define CAN_F7DATA0_FD21_Msk (0x1U << CAN_F7DATA0_FD21_Pos) /*!< 0x00200000 */
# define CAN_F7DATA0_FD21 CAN_F7DATA0_FD21_Msk /*!< Filter bit 21 */
# define CAN_F7DATA0_FD22_Pos (22U)
# define CAN_F7DATA0_FD22_Msk (0x1U << CAN_F7DATA0_FD22_Pos) /*!< 0x00400000 */
# define CAN_F7DATA0_FD22 CAN_F7DATA0_FD22_Msk /*!< Filter bit 22 */
# define CAN_F7DATA0_FD23_Pos (23U)
# define CAN_F7DATA0_FD23_Msk (0x1U << CAN_F7DATA0_FD23_Pos) /*!< 0x00800000 */
# define CAN_F7DATA0_FD23 CAN_F7DATA0_FD23_Msk /*!< Filter bit 23 */
# define CAN_F7DATA0_FD24_Pos (24U)
# define CAN_F7DATA0_FD24_Msk (0x1U << CAN_F7DATA0_FD24_Pos) /*!< 0x01000000 */
# define CAN_F7DATA0_FD24 CAN_F7DATA0_FD24_Msk /*!< Filter bit 24 */
# define CAN_F7DATA0_FD25_Pos (25U)
# define CAN_F7DATA0_FD25_Msk (0x1U << CAN_F7DATA0_FD25_Pos) /*!< 0x02000000 */
# define CAN_F7DATA0_FD25 CAN_F7DATA0_FD25_Msk /*!< Filter bit 25 */
# define CAN_F7DATA0_FD26_Pos (26U)
# define CAN_F7DATA0_FD26_Msk (0x1U << CAN_F7DATA0_FD26_Pos) /*!< 0x04000000 */
# define CAN_F7DATA0_FD26 CAN_F7DATA0_FD26_Msk /*!< Filter bit 26 */
# define CAN_F7DATA0_FD27_Pos (27U)
# define CAN_F7DATA0_FD27_Msk (0x1U << CAN_F7DATA0_FD27_Pos) /*!< 0x08000000 */
# define CAN_F7DATA0_FD27 CAN_F7DATA0_FD27_Msk /*!< Filter bit 27 */
# define CAN_F7DATA0_FD28_Pos (28U)
# define CAN_F7DATA0_FD28_Msk (0x1U << CAN_F7DATA0_FD28_Pos) /*!< 0x10000000 */
# define CAN_F7DATA0_FD28 CAN_F7DATA0_FD28_Msk /*!< Filter bit 28 */
# define CAN_F7DATA0_FD29_Pos (29U)
# define CAN_F7DATA0_FD29_Msk (0x1U << CAN_F7DATA0_FD29_Pos) /*!< 0x20000000 */
# define CAN_F7DATA0_FD29 CAN_F7DATA0_FD29_Msk /*!< Filter bit 29 */
# define CAN_F7DATA0_FD30_Pos (30U)
# define CAN_F7DATA0_FD30_Msk (0x1U << CAN_F7DATA0_FD30_Pos) /*!< 0x40000000 */
# define CAN_F7DATA0_FD30 CAN_F7DATA0_FD30_Msk /*!< Filter bit 30 */
# define CAN_F7DATA0_FD31_Pos (31U)
# define CAN_F7DATA0_FD31_Msk (0x1U << CAN_F7DATA0_FD31_Pos) /*!< 0x80000000 */
# define CAN_F7DATA0_FD31 CAN_F7DATA0_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F8R1 register *******************/
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# define CAN_F8DATA0_FD0_Pos (0U)
# define CAN_F8DATA0_FD0_Msk (0x1U << CAN_F8DATA0_FD0_Pos) /*!< 0x00000001 */
# define CAN_F8DATA0_FD0 CAN_F8DATA0_FD0_Msk /*!< Filter bit 0 */
# define CAN_F8DATA0_FD1_Pos (1U)
# define CAN_F8DATA0_FD1_Msk (0x1U << CAN_F8DATA0_FD1_Pos) /*!< 0x00000002 */
# define CAN_F8DATA0_FD1 CAN_F8DATA0_FD1_Msk /*!< Filter bit 1 */
# define CAN_F8DATA0_FD2_Pos (2U)
# define CAN_F8DATA0_FD2_Msk (0x1U << CAN_F8DATA0_FD2_Pos) /*!< 0x00000004 */
# define CAN_F8DATA0_FD2 CAN_F8DATA0_FD2_Msk /*!< Filter bit 2 */
# define CAN_F8DATA0_FD3_Pos (3U)
# define CAN_F8DATA0_FD3_Msk (0x1U << CAN_F8DATA0_FD3_Pos) /*!< 0x00000008 */
# define CAN_F8DATA0_FD3 CAN_F8DATA0_FD3_Msk /*!< Filter bit 3 */
# define CAN_F8DATA0_FD4_Pos (4U)
# define CAN_F8DATA0_FD4_Msk (0x1U << CAN_F8DATA0_FD4_Pos) /*!< 0x00000010 */
# define CAN_F8DATA0_FD4 CAN_F8DATA0_FD4_Msk /*!< Filter bit 4 */
# define CAN_F8DATA0_FD5_Pos (5U)
# define CAN_F8DATA0_FD5_Msk (0x1U << CAN_F8DATA0_FD5_Pos) /*!< 0x00000020 */
# define CAN_F8DATA0_FD5 CAN_F8DATA0_FD5_Msk /*!< Filter bit 5 */
# define CAN_F8DATA0_FD6_Pos (6U)
# define CAN_F8DATA0_FD6_Msk (0x1U << CAN_F8DATA0_FD6_Pos) /*!< 0x00000040 */
# define CAN_F8DATA0_FD6 CAN_F8DATA0_FD6_Msk /*!< Filter bit 6 */
# define CAN_F8DATA0_FD7_Pos (7U)
# define CAN_F8DATA0_FD7_Msk (0x1U << CAN_F8DATA0_FD7_Pos) /*!< 0x00000080 */
# define CAN_F8DATA0_FD7 CAN_F8DATA0_FD7_Msk /*!< Filter bit 7 */
# define CAN_F8DATA0_FD8_Pos (8U)
# define CAN_F8DATA0_FD8_Msk (0x1U << CAN_F8DATA0_FD8_Pos) /*!< 0x00000100 */
# define CAN_F8DATA0_FD8 CAN_F8DATA0_FD8_Msk /*!< Filter bit 8 */
# define CAN_F8DATA0_FD9_Pos (9U)
# define CAN_F8DATA0_FD9_Msk (0x1U << CAN_F8DATA0_FD9_Pos) /*!< 0x00000200 */
# define CAN_F8DATA0_FD9 CAN_F8DATA0_FD9_Msk /*!< Filter bit 9 */
# define CAN_F8DATA0_FD10_Pos (10U)
# define CAN_F8DATA0_FD10_Msk (0x1U << CAN_F8DATA0_FD10_Pos) /*!< 0x00000400 */
# define CAN_F8DATA0_FD10 CAN_F8DATA0_FD10_Msk /*!< Filter bit 10 */
# define CAN_F8DATA0_FD11_Pos (11U)
# define CAN_F8DATA0_FD11_Msk (0x1U << CAN_F8DATA0_FD11_Pos) /*!< 0x00000800 */
# define CAN_F8DATA0_FD11 CAN_F8DATA0_FD11_Msk /*!< Filter bit 11 */
# define CAN_F8DATA0_FD12_Pos (12U)
# define CAN_F8DATA0_FD12_Msk (0x1U << CAN_F8DATA0_FD12_Pos) /*!< 0x00001000 */
# define CAN_F8DATA0_FD12 CAN_F8DATA0_FD12_Msk /*!< Filter bit 12 */
# define CAN_F8DATA0_FD13_Pos (13U)
# define CAN_F8DATA0_FD13_Msk (0x1U << CAN_F8DATA0_FD13_Pos) /*!< 0x00002000 */
# define CAN_F8DATA0_FD13 CAN_F8DATA0_FD13_Msk /*!< Filter bit 13 */
# define CAN_F8DATA0_FD14_Pos (14U)
# define CAN_F8DATA0_FD14_Msk (0x1U << CAN_F8DATA0_FD14_Pos) /*!< 0x00004000 */
# define CAN_F8DATA0_FD14 CAN_F8DATA0_FD14_Msk /*!< Filter bit 14 */
# define CAN_F8DATA0_FD15_Pos (15U)
# define CAN_F8DATA0_FD15_Msk (0x1U << CAN_F8DATA0_FD15_Pos) /*!< 0x00008000 */
# define CAN_F8DATA0_FD15 CAN_F8DATA0_FD15_Msk /*!< Filter bit 15 */
# define CAN_F8DATA0_FD16_Pos (16U)
# define CAN_F8DATA0_FD16_Msk (0x1U << CAN_F8DATA0_FD16_Pos) /*!< 0x00010000 */
# define CAN_F8DATA0_FD16 CAN_F8DATA0_FD16_Msk /*!< Filter bit 16 */
# define CAN_F8DATA0_FD17_Pos (17U)
# define CAN_F8DATA0_FD17_Msk (0x1U << CAN_F8DATA0_FD17_Pos) /*!< 0x00020000 */
# define CAN_F8DATA0_FD17 CAN_F8DATA0_FD17_Msk /*!< Filter bit 17 */
# define CAN_F8DATA0_FD18_Pos (18U)
# define CAN_F8DATA0_FD18_Msk (0x1U << CAN_F8DATA0_FD18_Pos) /*!< 0x00040000 */
# define CAN_F8DATA0_FD18 CAN_F8DATA0_FD18_Msk /*!< Filter bit 18 */
# define CAN_F8DATA0_FD19_Pos (19U)
# define CAN_F8DATA0_FD19_Msk (0x1U << CAN_F8DATA0_FD19_Pos) /*!< 0x00080000 */
# define CAN_F8DATA0_FD19 CAN_F8DATA0_FD19_Msk /*!< Filter bit 19 */
# define CAN_F8DATA0_FD20_Pos (20U)
# define CAN_F8DATA0_FD20_Msk (0x1U << CAN_F8DATA0_FD20_Pos) /*!< 0x00100000 */
# define CAN_F8DATA0_FD20 CAN_F8DATA0_FD20_Msk /*!< Filter bit 20 */
# define CAN_F8DATA0_FD21_Pos (21U)
# define CAN_F8DATA0_FD21_Msk (0x1U << CAN_F8DATA0_FD21_Pos) /*!< 0x00200000 */
# define CAN_F8DATA0_FD21 CAN_F8DATA0_FD21_Msk /*!< Filter bit 21 */
# define CAN_F8DATA0_FD22_Pos (22U)
# define CAN_F8DATA0_FD22_Msk (0x1U << CAN_F8DATA0_FD22_Pos) /*!< 0x00400000 */
# define CAN_F8DATA0_FD22 CAN_F8DATA0_FD22_Msk /*!< Filter bit 22 */
# define CAN_F8DATA0_FD23_Pos (23U)
# define CAN_F8DATA0_FD23_Msk (0x1U << CAN_F8DATA0_FD23_Pos) /*!< 0x00800000 */
# define CAN_F8DATA0_FD23 CAN_F8DATA0_FD23_Msk /*!< Filter bit 23 */
# define CAN_F8DATA0_FD24_Pos (24U)
# define CAN_F8DATA0_FD24_Msk (0x1U << CAN_F8DATA0_FD24_Pos) /*!< 0x01000000 */
# define CAN_F8DATA0_FD24 CAN_F8DATA0_FD24_Msk /*!< Filter bit 24 */
# define CAN_F8DATA0_FD25_Pos (25U)
# define CAN_F8DATA0_FD25_Msk (0x1U << CAN_F8DATA0_FD25_Pos) /*!< 0x02000000 */
# define CAN_F8DATA0_FD25 CAN_F8DATA0_FD25_Msk /*!< Filter bit 25 */
# define CAN_F8DATA0_FD26_Pos (26U)
# define CAN_F8DATA0_FD26_Msk (0x1U << CAN_F8DATA0_FD26_Pos) /*!< 0x04000000 */
# define CAN_F8DATA0_FD26 CAN_F8DATA0_FD26_Msk /*!< Filter bit 26 */
# define CAN_F8DATA0_FD27_Pos (27U)
# define CAN_F8DATA0_FD27_Msk (0x1U << CAN_F8DATA0_FD27_Pos) /*!< 0x08000000 */
# define CAN_F8DATA0_FD27 CAN_F8DATA0_FD27_Msk /*!< Filter bit 27 */
# define CAN_F8DATA0_FD28_Pos (28U)
# define CAN_F8DATA0_FD28_Msk (0x1U << CAN_F8DATA0_FD28_Pos) /*!< 0x10000000 */
# define CAN_F8DATA0_FD28 CAN_F8DATA0_FD28_Msk /*!< Filter bit 28 */
# define CAN_F8DATA0_FD29_Pos (29U)
# define CAN_F8DATA0_FD29_Msk (0x1U << CAN_F8DATA0_FD29_Pos) /*!< 0x20000000 */
# define CAN_F8DATA0_FD29 CAN_F8DATA0_FD29_Msk /*!< Filter bit 29 */
# define CAN_F8DATA0_FD30_Pos (30U)
# define CAN_F8DATA0_FD30_Msk (0x1U << CAN_F8DATA0_FD30_Pos) /*!< 0x40000000 */
# define CAN_F8DATA0_FD30 CAN_F8DATA0_FD30_Msk /*!< Filter bit 30 */
# define CAN_F8DATA0_FD31_Pos (31U)
# define CAN_F8DATA0_FD31_Msk (0x1U << CAN_F8DATA0_FD31_Pos) /*!< 0x80000000 */
# define CAN_F8DATA0_FD31 CAN_F8DATA0_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F9R1 register *******************/
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# define CAN_F9DATA0_FD0_Pos (0U)
# define CAN_F9DATA0_FD0_Msk (0x1U << CAN_F9DATA0_FD0_Pos) /*!< 0x00000001 */
# define CAN_F9DATA0_FD0 CAN_F9DATA0_FD0_Msk /*!< Filter bit 0 */
# define CAN_F9DATA0_FD1_Pos (1U)
# define CAN_F9DATA0_FD1_Msk (0x1U << CAN_F9DATA0_FD1_Pos) /*!< 0x00000002 */
# define CAN_F9DATA0_FD1 CAN_F9DATA0_FD1_Msk /*!< Filter bit 1 */
# define CAN_F9DATA0_FD2_Pos (2U)
# define CAN_F9DATA0_FD2_Msk (0x1U << CAN_F9DATA0_FD2_Pos) /*!< 0x00000004 */
# define CAN_F9DATA0_FD2 CAN_F9DATA0_FD2_Msk /*!< Filter bit 2 */
# define CAN_F9DATA0_FD3_Pos (3U)
# define CAN_F9DATA0_FD3_Msk (0x1U << CAN_F9DATA0_FD3_Pos) /*!< 0x00000008 */
# define CAN_F9DATA0_FD3 CAN_F9DATA0_FD3_Msk /*!< Filter bit 3 */
# define CAN_F9DATA0_FD4_Pos (4U)
# define CAN_F9DATA0_FD4_Msk (0x1U << CAN_F9DATA0_FD4_Pos) /*!< 0x00000010 */
# define CAN_F9DATA0_FD4 CAN_F9DATA0_FD4_Msk /*!< Filter bit 4 */
# define CAN_F9DATA0_FD5_Pos (5U)
# define CAN_F9DATA0_FD5_Msk (0x1U << CAN_F9DATA0_FD5_Pos) /*!< 0x00000020 */
# define CAN_F9DATA0_FD5 CAN_F9DATA0_FD5_Msk /*!< Filter bit 5 */
# define CAN_F9DATA0_FD6_Pos (6U)
# define CAN_F9DATA0_FD6_Msk (0x1U << CAN_F9DATA0_FD6_Pos) /*!< 0x00000040 */
# define CAN_F9DATA0_FD6 CAN_F9DATA0_FD6_Msk /*!< Filter bit 6 */
# define CAN_F9DATA0_FD7_Pos (7U)
# define CAN_F9DATA0_FD7_Msk (0x1U << CAN_F9DATA0_FD7_Pos) /*!< 0x00000080 */
# define CAN_F9DATA0_FD7 CAN_F9DATA0_FD7_Msk /*!< Filter bit 7 */
# define CAN_F9DATA0_FD8_Pos (8U)
# define CAN_F9DATA0_FD8_Msk (0x1U << CAN_F9DATA0_FD8_Pos) /*!< 0x00000100 */
# define CAN_F9DATA0_FD8 CAN_F9DATA0_FD8_Msk /*!< Filter bit 8 */
# define CAN_F9DATA0_FD9_Pos (9U)
# define CAN_F9DATA0_FD9_Msk (0x1U << CAN_F9DATA0_FD9_Pos) /*!< 0x00000200 */
# define CAN_F9DATA0_FD9 CAN_F9DATA0_FD9_Msk /*!< Filter bit 9 */
# define CAN_F9DATA0_FD10_Pos (10U)
# define CAN_F9DATA0_FD10_Msk (0x1U << CAN_F9DATA0_FD10_Pos) /*!< 0x00000400 */
# define CAN_F9DATA0_FD10 CAN_F9DATA0_FD10_Msk /*!< Filter bit 10 */
# define CAN_F9DATA0_FD11_Pos (11U)
# define CAN_F9DATA0_FD11_Msk (0x1U << CAN_F9DATA0_FD11_Pos) /*!< 0x00000800 */
# define CAN_F9DATA0_FD11 CAN_F9DATA0_FD11_Msk /*!< Filter bit 11 */
# define CAN_F9DATA0_FD12_Pos (12U)
# define CAN_F9DATA0_FD12_Msk (0x1U << CAN_F9DATA0_FD12_Pos) /*!< 0x00001000 */
# define CAN_F9DATA0_FD12 CAN_F9DATA0_FD12_Msk /*!< Filter bit 12 */
# define CAN_F9DATA0_FD13_Pos (13U)
# define CAN_F9DATA0_FD13_Msk (0x1U << CAN_F9DATA0_FD13_Pos) /*!< 0x00002000 */
# define CAN_F9DATA0_FD13 CAN_F9DATA0_FD13_Msk /*!< Filter bit 13 */
# define CAN_F9DATA0_FD14_Pos (14U)
# define CAN_F9DATA0_FD14_Msk (0x1U << CAN_F9DATA0_FD14_Pos) /*!< 0x00004000 */
# define CAN_F9DATA0_FD14 CAN_F9DATA0_FD14_Msk /*!< Filter bit 14 */
# define CAN_F9DATA0_FD15_Pos (15U)
# define CAN_F9DATA0_FD15_Msk (0x1U << CAN_F9DATA0_FD15_Pos) /*!< 0x00008000 */
# define CAN_F9DATA0_FD15 CAN_F9DATA0_FD15_Msk /*!< Filter bit 15 */
# define CAN_F9DATA0_FD16_Pos (16U)
# define CAN_F9DATA0_FD16_Msk (0x1U << CAN_F9DATA0_FD16_Pos) /*!< 0x00010000 */
# define CAN_F9DATA0_FD16 CAN_F9DATA0_FD16_Msk /*!< Filter bit 16 */
# define CAN_F9DATA0_FD17_Pos (17U)
# define CAN_F9DATA0_FD17_Msk (0x1U << CAN_F9DATA0_FD17_Pos) /*!< 0x00020000 */
# define CAN_F9DATA0_FD17 CAN_F9DATA0_FD17_Msk /*!< Filter bit 17 */
# define CAN_F9DATA0_FD18_Pos (18U)
# define CAN_F9DATA0_FD18_Msk (0x1U << CAN_F9DATA0_FD18_Pos) /*!< 0x00040000 */
# define CAN_F9DATA0_FD18 CAN_F9DATA0_FD18_Msk /*!< Filter bit 18 */
# define CAN_F9DATA0_FD19_Pos (19U)
# define CAN_F9DATA0_FD19_Msk (0x1U << CAN_F9DATA0_FD19_Pos) /*!< 0x00080000 */
# define CAN_F9DATA0_FD19 CAN_F9DATA0_FD19_Msk /*!< Filter bit 19 */
# define CAN_F9DATA0_FD20_Pos (20U)
# define CAN_F9DATA0_FD20_Msk (0x1U << CAN_F9DATA0_FD20_Pos) /*!< 0x00100000 */
# define CAN_F9DATA0_FD20 CAN_F9DATA0_FD20_Msk /*!< Filter bit 20 */
# define CAN_F9DATA0_FD21_Pos (21U)
# define CAN_F9DATA0_FD21_Msk (0x1U << CAN_F9DATA0_FD21_Pos) /*!< 0x00200000 */
# define CAN_F9DATA0_FD21 CAN_F9DATA0_FD21_Msk /*!< Filter bit 21 */
# define CAN_F9DATA0_FD22_Pos (22U)
# define CAN_F9DATA0_FD22_Msk (0x1U << CAN_F9DATA0_FD22_Pos) /*!< 0x00400000 */
# define CAN_F9DATA0_FD22 CAN_F9DATA0_FD22_Msk /*!< Filter bit 22 */
# define CAN_F9DATA0_FD23_Pos (23U)
# define CAN_F9DATA0_FD23_Msk (0x1U << CAN_F9DATA0_FD23_Pos) /*!< 0x00800000 */
# define CAN_F9DATA0_FD23 CAN_F9DATA0_FD23_Msk /*!< Filter bit 23 */
# define CAN_F9DATA0_FD24_Pos (24U)
# define CAN_F9DATA0_FD24_Msk (0x1U << CAN_F9DATA0_FD24_Pos) /*!< 0x01000000 */
# define CAN_F9DATA0_FD24 CAN_F9DATA0_FD24_Msk /*!< Filter bit 24 */
# define CAN_F9DATA0_FD25_Pos (25U)
# define CAN_F9DATA0_FD25_Msk (0x1U << CAN_F9DATA0_FD25_Pos) /*!< 0x02000000 */
# define CAN_F9DATA0_FD25 CAN_F9DATA0_FD25_Msk /*!< Filter bit 25 */
# define CAN_F9DATA0_FD26_Pos (26U)
# define CAN_F9DATA0_FD26_Msk (0x1U << CAN_F9DATA0_FD26_Pos) /*!< 0x04000000 */
# define CAN_F9DATA0_FD26 CAN_F9DATA0_FD26_Msk /*!< Filter bit 26 */
# define CAN_F9DATA0_FD27_Pos (27U)
# define CAN_F9DATA0_FD27_Msk (0x1U << CAN_F9DATA0_FD27_Pos) /*!< 0x08000000 */
# define CAN_F9DATA0_FD27 CAN_F9DATA0_FD27_Msk /*!< Filter bit 27 */
# define CAN_F9DATA0_FD28_Pos (28U)
# define CAN_F9DATA0_FD28_Msk (0x1U << CAN_F9DATA0_FD28_Pos) /*!< 0x10000000 */
# define CAN_F9DATA0_FD28 CAN_F9DATA0_FD28_Msk /*!< Filter bit 28 */
# define CAN_F9DATA0_FD29_Pos (29U)
# define CAN_F9DATA0_FD29_Msk (0x1U << CAN_F9DATA0_FD29_Pos) /*!< 0x20000000 */
# define CAN_F9DATA0_FD29 CAN_F9DATA0_FD29_Msk /*!< Filter bit 29 */
# define CAN_F9DATA0_FD30_Pos (30U)
# define CAN_F9DATA0_FD30_Msk (0x1U << CAN_F9DATA0_FD30_Pos) /*!< 0x40000000 */
# define CAN_F9DATA0_FD30 CAN_F9DATA0_FD30_Msk /*!< Filter bit 30 */
# define CAN_F9DATA0_FD31_Pos (31U)
# define CAN_F9DATA0_FD31_Msk (0x1U << CAN_F9DATA0_FD31_Pos) /*!< 0x80000000 */
# define CAN_F9DATA0_FD31 CAN_F9DATA0_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F10R1 register ******************/
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# define CAN_F10DATA0_FD0_Pos (0U)
# define CAN_F10DATA0_FD0_Msk (0x1U << CAN_F10DATA0_FD0_Pos) /*!< 0x00000001 */
# define CAN_F10DATA0_FD0 CAN_F10DATA0_FD0_Msk /*!< Filter bit 0 */
# define CAN_F10DATA0_FD1_Pos (1U)
# define CAN_F10DATA0_FD1_Msk (0x1U << CAN_F10DATA0_FD1_Pos) /*!< 0x00000002 */
# define CAN_F10DATA0_FD1 CAN_F10DATA0_FD1_Msk /*!< Filter bit 1 */
# define CAN_F10DATA0_FD2_Pos (2U)
# define CAN_F10DATA0_FD2_Msk (0x1U << CAN_F10DATA0_FD2_Pos) /*!< 0x00000004 */
# define CAN_F10DATA0_FD2 CAN_F10DATA0_FD2_Msk /*!< Filter bit 2 */
# define CAN_F10DATA0_FD3_Pos (3U)
# define CAN_F10DATA0_FD3_Msk (0x1U << CAN_F10DATA0_FD3_Pos) /*!< 0x00000008 */
# define CAN_F10DATA0_FD3 CAN_F10DATA0_FD3_Msk /*!< Filter bit 3 */
# define CAN_F10DATA0_FD4_Pos (4U)
# define CAN_F10DATA0_FD4_Msk (0x1U << CAN_F10DATA0_FD4_Pos) /*!< 0x00000010 */
# define CAN_F10DATA0_FD4 CAN_F10DATA0_FD4_Msk /*!< Filter bit 4 */
# define CAN_F10DATA0_FD5_Pos (5U)
# define CAN_F10DATA0_FD5_Msk (0x1U << CAN_F10DATA0_FD5_Pos) /*!< 0x00000020 */
# define CAN_F10DATA0_FD5 CAN_F10DATA0_FD5_Msk /*!< Filter bit 5 */
# define CAN_F10DATA0_FD6_Pos (6U)
# define CAN_F10DATA0_FD6_Msk (0x1U << CAN_F10DATA0_FD6_Pos) /*!< 0x00000040 */
# define CAN_F10DATA0_FD6 CAN_F10DATA0_FD6_Msk /*!< Filter bit 6 */
# define CAN_F10DATA0_FD7_Pos (7U)
# define CAN_F10DATA0_FD7_Msk (0x1U << CAN_F10DATA0_FD7_Pos) /*!< 0x00000080 */
# define CAN_F10DATA0_FD7 CAN_F10DATA0_FD7_Msk /*!< Filter bit 7 */
# define CAN_F10DATA0_FD8_Pos (8U)
# define CAN_F10DATA0_FD8_Msk (0x1U << CAN_F10DATA0_FD8_Pos) /*!< 0x00000100 */
# define CAN_F10DATA0_FD8 CAN_F10DATA0_FD8_Msk /*!< Filter bit 8 */
# define CAN_F10DATA0_FD9_Pos (9U)
# define CAN_F10DATA0_FD9_Msk (0x1U << CAN_F10DATA0_FD9_Pos) /*!< 0x00000200 */
# define CAN_F10DATA0_FD9 CAN_F10DATA0_FD9_Msk /*!< Filter bit 9 */
# define CAN_F10DATA0_FD10_Pos (10U)
# define CAN_F10DATA0_FD10_Msk (0x1U << CAN_F10DATA0_FD10_Pos) /*!< 0x00000400 */
# define CAN_F10DATA0_FD10 CAN_F10DATA0_FD10_Msk /*!< Filter bit 10 */
# define CAN_F10DATA0_FD11_Pos (11U)
# define CAN_F10DATA0_FD11_Msk (0x1U << CAN_F10DATA0_FD11_Pos) /*!< 0x00000800 */
# define CAN_F10DATA0_FD11 CAN_F10DATA0_FD11_Msk /*!< Filter bit 11 */
# define CAN_F10DATA0_FD12_Pos (12U)
# define CAN_F10DATA0_FD12_Msk (0x1U << CAN_F10DATA0_FD12_Pos) /*!< 0x00001000 */
# define CAN_F10DATA0_FD12 CAN_F10DATA0_FD12_Msk /*!< Filter bit 12 */
# define CAN_F10DATA0_FD13_Pos (13U)
# define CAN_F10DATA0_FD13_Msk (0x1U << CAN_F10DATA0_FD13_Pos) /*!< 0x00002000 */
# define CAN_F10DATA0_FD13 CAN_F10DATA0_FD13_Msk /*!< Filter bit 13 */
# define CAN_F10DATA0_FD14_Pos (14U)
# define CAN_F10DATA0_FD14_Msk (0x1U << CAN_F10DATA0_FD14_Pos) /*!< 0x00004000 */
# define CAN_F10DATA0_FD14 CAN_F10DATA0_FD14_Msk /*!< Filter bit 14 */
# define CAN_F10DATA0_FD15_Pos (15U)
# define CAN_F10DATA0_FD15_Msk (0x1U << CAN_F10DATA0_FD15_Pos) /*!< 0x00008000 */
# define CAN_F10DATA0_FD15 CAN_F10DATA0_FD15_Msk /*!< Filter bit 15 */
# define CAN_F10DATA0_FD16_Pos (16U)
# define CAN_F10DATA0_FD16_Msk (0x1U << CAN_F10DATA0_FD16_Pos) /*!< 0x00010000 */
# define CAN_F10DATA0_FD16 CAN_F10DATA0_FD16_Msk /*!< Filter bit 16 */
# define CAN_F10DATA0_FD17_Pos (17U)
# define CAN_F10DATA0_FD17_Msk (0x1U << CAN_F10DATA0_FD17_Pos) /*!< 0x00020000 */
# define CAN_F10DATA0_FD17 CAN_F10DATA0_FD17_Msk /*!< Filter bit 17 */
# define CAN_F10DATA0_FD18_Pos (18U)
# define CAN_F10DATA0_FD18_Msk (0x1U << CAN_F10DATA0_FD18_Pos) /*!< 0x00040000 */
# define CAN_F10DATA0_FD18 CAN_F10DATA0_FD18_Msk /*!< Filter bit 18 */
# define CAN_F10DATA0_FD19_Pos (19U)
# define CAN_F10DATA0_FD19_Msk (0x1U << CAN_F10DATA0_FD19_Pos) /*!< 0x00080000 */
# define CAN_F10DATA0_FD19 CAN_F10DATA0_FD19_Msk /*!< Filter bit 19 */
# define CAN_F10DATA0_FD20_Pos (20U)
# define CAN_F10DATA0_FD20_Msk (0x1U << CAN_F10DATA0_FD20_Pos) /*!< 0x00100000 */
# define CAN_F10DATA0_FD20 CAN_F10DATA0_FD20_Msk /*!< Filter bit 20 */
# define CAN_F10DATA0_FD21_Pos (21U)
# define CAN_F10DATA0_FD21_Msk (0x1U << CAN_F10DATA0_FD21_Pos) /*!< 0x00200000 */
# define CAN_F10DATA0_FD21 CAN_F10DATA0_FD21_Msk /*!< Filter bit 21 */
# define CAN_F10DATA0_FD22_Pos (22U)
# define CAN_F10DATA0_FD22_Msk (0x1U << CAN_F10DATA0_FD22_Pos) /*!< 0x00400000 */
# define CAN_F10DATA0_FD22 CAN_F10DATA0_FD22_Msk /*!< Filter bit 22 */
# define CAN_F10DATA0_FD23_Pos (23U)
# define CAN_F10DATA0_FD23_Msk (0x1U << CAN_F10DATA0_FD23_Pos) /*!< 0x00800000 */
# define CAN_F10DATA0_FD23 CAN_F10DATA0_FD23_Msk /*!< Filter bit 23 */
# define CAN_F10DATA0_FD24_Pos (24U)
# define CAN_F10DATA0_FD24_Msk (0x1U << CAN_F10DATA0_FD24_Pos) /*!< 0x01000000 */
# define CAN_F10DATA0_FD24 CAN_F10DATA0_FD24_Msk /*!< Filter bit 24 */
# define CAN_F10DATA0_FD25_Pos (25U)
# define CAN_F10DATA0_FD25_Msk (0x1U << CAN_F10DATA0_FD25_Pos) /*!< 0x02000000 */
# define CAN_F10DATA0_FD25 CAN_F10DATA0_FD25_Msk /*!< Filter bit 25 */
# define CAN_F10DATA0_FD26_Pos (26U)
# define CAN_F10DATA0_FD26_Msk (0x1U << CAN_F10DATA0_FD26_Pos) /*!< 0x04000000 */
# define CAN_F10DATA0_FD26 CAN_F10DATA0_FD26_Msk /*!< Filter bit 26 */
# define CAN_F10DATA0_FD27_Pos (27U)
# define CAN_F10DATA0_FD27_Msk (0x1U << CAN_F10DATA0_FD27_Pos) /*!< 0x08000000 */
# define CAN_F10DATA0_FD27 CAN_F10DATA0_FD27_Msk /*!< Filter bit 27 */
# define CAN_F10DATA0_FD28_Pos (28U)
# define CAN_F10DATA0_FD28_Msk (0x1U << CAN_F10DATA0_FD28_Pos) /*!< 0x10000000 */
# define CAN_F10DATA0_FD28 CAN_F10DATA0_FD28_Msk /*!< Filter bit 28 */
# define CAN_F10DATA0_FD29_Pos (29U)
# define CAN_F10DATA0_FD29_Msk (0x1U << CAN_F10DATA0_FD29_Pos) /*!< 0x20000000 */
# define CAN_F10DATA0_FD29 CAN_F10DATA0_FD29_Msk /*!< Filter bit 29 */
# define CAN_F10DATA0_FD30_Pos (30U)
# define CAN_F10DATA0_FD30_Msk (0x1U << CAN_F10DATA0_FD30_Pos) /*!< 0x40000000 */
# define CAN_F10DATA0_FD30 CAN_F10DATA0_FD30_Msk /*!< Filter bit 30 */
# define CAN_F10DATA0_FD31_Pos (31U)
# define CAN_F10DATA0_FD31_Msk (0x1U << CAN_F10DATA0_FD31_Pos) /*!< 0x80000000 */
# define CAN_F10DATA0_FD31 CAN_F10DATA0_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F11R1 register ******************/
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# define CAN_F11DATA0_FD0_Pos (0U)
# define CAN_F11DATA0_FD0_Msk (0x1U << CAN_F11DATA0_FD0_Pos) /*!< 0x00000001 */
# define CAN_F11DATA0_FD0 CAN_F11DATA0_FD0_Msk /*!< Filter bit 0 */
# define CAN_F11DATA0_FD1_Pos (1U)
# define CAN_F11DATA0_FD1_Msk (0x1U << CAN_F11DATA0_FD1_Pos) /*!< 0x00000002 */
# define CAN_F11DATA0_FD1 CAN_F11DATA0_FD1_Msk /*!< Filter bit 1 */
# define CAN_F11DATA0_FD2_Pos (2U)
# define CAN_F11DATA0_FD2_Msk (0x1U << CAN_F11DATA0_FD2_Pos) /*!< 0x00000004 */
# define CAN_F11DATA0_FD2 CAN_F11DATA0_FD2_Msk /*!< Filter bit 2 */
# define CAN_F11DATA0_FD3_Pos (3U)
# define CAN_F11DATA0_FD3_Msk (0x1U << CAN_F11DATA0_FD3_Pos) /*!< 0x00000008 */
# define CAN_F11DATA0_FD3 CAN_F11DATA0_FD3_Msk /*!< Filter bit 3 */
# define CAN_F11DATA0_FD4_Pos (4U)
# define CAN_F11DATA0_FD4_Msk (0x1U << CAN_F11DATA0_FD4_Pos) /*!< 0x00000010 */
# define CAN_F11DATA0_FD4 CAN_F11DATA0_FD4_Msk /*!< Filter bit 4 */
# define CAN_F11DATA0_FD5_Pos (5U)
# define CAN_F11DATA0_FD5_Msk (0x1U << CAN_F11DATA0_FD5_Pos) /*!< 0x00000020 */
# define CAN_F11DATA0_FD5 CAN_F11DATA0_FD5_Msk /*!< Filter bit 5 */
# define CAN_F11DATA0_FD6_Pos (6U)
# define CAN_F11DATA0_FD6_Msk (0x1U << CAN_F11DATA0_FD6_Pos) /*!< 0x00000040 */
# define CAN_F11DATA0_FD6 CAN_F11DATA0_FD6_Msk /*!< Filter bit 6 */
# define CAN_F11DATA0_FD7_Pos (7U)
# define CAN_F11DATA0_FD7_Msk (0x1U << CAN_F11DATA0_FD7_Pos) /*!< 0x00000080 */
# define CAN_F11DATA0_FD7 CAN_F11DATA0_FD7_Msk /*!< Filter bit 7 */
# define CAN_F11DATA0_FD8_Pos (8U)
# define CAN_F11DATA0_FD8_Msk (0x1U << CAN_F11DATA0_FD8_Pos) /*!< 0x00000100 */
# define CAN_F11DATA0_FD8 CAN_F11DATA0_FD8_Msk /*!< Filter bit 8 */
# define CAN_F11DATA0_FD9_Pos (9U)
# define CAN_F11DATA0_FD9_Msk (0x1U << CAN_F11DATA0_FD9_Pos) /*!< 0x00000200 */
# define CAN_F11DATA0_FD9 CAN_F11DATA0_FD9_Msk /*!< Filter bit 9 */
# define CAN_F11DATA0_FD10_Pos (10U)
# define CAN_F11DATA0_FD10_Msk (0x1U << CAN_F11DATA0_FD10_Pos) /*!< 0x00000400 */
# define CAN_F11DATA0_FD10 CAN_F11DATA0_FD10_Msk /*!< Filter bit 10 */
# define CAN_F11DATA0_FD11_Pos (11U)
# define CAN_F11DATA0_FD11_Msk (0x1U << CAN_F11DATA0_FD11_Pos) /*!< 0x00000800 */
# define CAN_F11DATA0_FD11 CAN_F11DATA0_FD11_Msk /*!< Filter bit 11 */
# define CAN_F11DATA0_FD12_Pos (12U)
# define CAN_F11DATA0_FD12_Msk (0x1U << CAN_F11DATA0_FD12_Pos) /*!< 0x00001000 */
# define CAN_F11DATA0_FD12 CAN_F11DATA0_FD12_Msk /*!< Filter bit 12 */
# define CAN_F11DATA0_FD13_Pos (13U)
# define CAN_F11DATA0_FD13_Msk (0x1U << CAN_F11DATA0_FD13_Pos) /*!< 0x00002000 */
# define CAN_F11DATA0_FD13 CAN_F11DATA0_FD13_Msk /*!< Filter bit 13 */
# define CAN_F11DATA0_FD14_Pos (14U)
# define CAN_F11DATA0_FD14_Msk (0x1U << CAN_F11DATA0_FD14_Pos) /*!< 0x00004000 */
# define CAN_F11DATA0_FD14 CAN_F11DATA0_FD14_Msk /*!< Filter bit 14 */
# define CAN_F11DATA0_FD15_Pos (15U)
# define CAN_F11DATA0_FD15_Msk (0x1U << CAN_F11DATA0_FD15_Pos) /*!< 0x00008000 */
# define CAN_F11DATA0_FD15 CAN_F11DATA0_FD15_Msk /*!< Filter bit 15 */
# define CAN_F11DATA0_FD16_Pos (16U)
# define CAN_F11DATA0_FD16_Msk (0x1U << CAN_F11DATA0_FD16_Pos) /*!< 0x00010000 */
# define CAN_F11DATA0_FD16 CAN_F11DATA0_FD16_Msk /*!< Filter bit 16 */
# define CAN_F11DATA0_FD17_Pos (17U)
# define CAN_F11DATA0_FD17_Msk (0x1U << CAN_F11DATA0_FD17_Pos) /*!< 0x00020000 */
# define CAN_F11DATA0_FD17 CAN_F11DATA0_FD17_Msk /*!< Filter bit 17 */
# define CAN_F11DATA0_FD18_Pos (18U)
# define CAN_F11DATA0_FD18_Msk (0x1U << CAN_F11DATA0_FD18_Pos) /*!< 0x00040000 */
# define CAN_F11DATA0_FD18 CAN_F11DATA0_FD18_Msk /*!< Filter bit 18 */
# define CAN_F11DATA0_FD19_Pos (19U)
# define CAN_F11DATA0_FD19_Msk (0x1U << CAN_F11DATA0_FD19_Pos) /*!< 0x00080000 */
# define CAN_F11DATA0_FD19 CAN_F11DATA0_FD19_Msk /*!< Filter bit 19 */
# define CAN_F11DATA0_FD20_Pos (20U)
# define CAN_F11DATA0_FD20_Msk (0x1U << CAN_F11DATA0_FD20_Pos) /*!< 0x00100000 */
# define CAN_F11DATA0_FD20 CAN_F11DATA0_FD20_Msk /*!< Filter bit 20 */
# define CAN_F11DATA0_FD21_Pos (21U)
# define CAN_F11DATA0_FD21_Msk (0x1U << CAN_F11DATA0_FD21_Pos) /*!< 0x00200000 */
# define CAN_F11DATA0_FD21 CAN_F11DATA0_FD21_Msk /*!< Filter bit 21 */
# define CAN_F11DATA0_FD22_Pos (22U)
# define CAN_F11DATA0_FD22_Msk (0x1U << CAN_F11DATA0_FD22_Pos) /*!< 0x00400000 */
# define CAN_F11DATA0_FD22 CAN_F11DATA0_FD22_Msk /*!< Filter bit 22 */
# define CAN_F11DATA0_FD23_Pos (23U)
# define CAN_F11DATA0_FD23_Msk (0x1U << CAN_F11DATA0_FD23_Pos) /*!< 0x00800000 */
# define CAN_F11DATA0_FD23 CAN_F11DATA0_FD23_Msk /*!< Filter bit 23 */
# define CAN_F11DATA0_FD24_Pos (24U)
# define CAN_F11DATA0_FD24_Msk (0x1U << CAN_F11DATA0_FD24_Pos) /*!< 0x01000000 */
# define CAN_F11DATA0_FD24 CAN_F11DATA0_FD24_Msk /*!< Filter bit 24 */
# define CAN_F11DATA0_FD25_Pos (25U)
# define CAN_F11DATA0_FD25_Msk (0x1U << CAN_F11DATA0_FD25_Pos) /*!< 0x02000000 */
# define CAN_F11DATA0_FD25 CAN_F11DATA0_FD25_Msk /*!< Filter bit 25 */
# define CAN_F11DATA0_FD26_Pos (26U)
# define CAN_F11DATA0_FD26_Msk (0x1U << CAN_F11DATA0_FD26_Pos) /*!< 0x04000000 */
# define CAN_F11DATA0_FD26 CAN_F11DATA0_FD26_Msk /*!< Filter bit 26 */
# define CAN_F11DATA0_FD27_Pos (27U)
# define CAN_F11DATA0_FD27_Msk (0x1U << CAN_F11DATA0_FD27_Pos) /*!< 0x08000000 */
# define CAN_F11DATA0_FD27 CAN_F11DATA0_FD27_Msk /*!< Filter bit 27 */
# define CAN_F11DATA0_FD28_Pos (28U)
# define CAN_F11DATA0_FD28_Msk (0x1U << CAN_F11DATA0_FD28_Pos) /*!< 0x10000000 */
# define CAN_F11DATA0_FD28 CAN_F11DATA0_FD28_Msk /*!< Filter bit 28 */
# define CAN_F11DATA0_FD29_Pos (29U)
# define CAN_F11DATA0_FD29_Msk (0x1U << CAN_F11DATA0_FD29_Pos) /*!< 0x20000000 */
# define CAN_F11DATA0_FD29 CAN_F11DATA0_FD29_Msk /*!< Filter bit 29 */
# define CAN_F11DATA0_FD30_Pos (30U)
# define CAN_F11DATA0_FD30_Msk (0x1U << CAN_F11DATA0_FD30_Pos) /*!< 0x40000000 */
# define CAN_F11DATA0_FD30 CAN_F11DATA0_FD30_Msk /*!< Filter bit 30 */
# define CAN_F11DATA0_FD31_Pos (31U)
# define CAN_F11DATA0_FD31_Msk (0x1U << CAN_F11DATA0_FD31_Pos) /*!< 0x80000000 */
# define CAN_F11DATA0_FD31 CAN_F11DATA0_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F12R1 register ******************/
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# define CAN_F12DATA0_FD0_Pos (0U)
# define CAN_F12DATA0_FD0_Msk (0x1U << CAN_F12DATA0_FD0_Pos) /*!< 0x00000001 */
# define CAN_F12DATA0_FD0 CAN_F12DATA0_FD0_Msk /*!< Filter bit 0 */
# define CAN_F12DATA0_FD1_Pos (1U)
# define CAN_F12DATA0_FD1_Msk (0x1U << CAN_F12DATA0_FD1_Pos) /*!< 0x00000002 */
# define CAN_F12DATA0_FD1 CAN_F12DATA0_FD1_Msk /*!< Filter bit 1 */
# define CAN_F12DATA0_FD2_Pos (2U)
# define CAN_F12DATA0_FD2_Msk (0x1U << CAN_F12DATA0_FD2_Pos) /*!< 0x00000004 */
# define CAN_F12DATA0_FD2 CAN_F12DATA0_FD2_Msk /*!< Filter bit 2 */
# define CAN_F12DATA0_FD3_Pos (3U)
# define CAN_F12DATA0_FD3_Msk (0x1U << CAN_F12DATA0_FD3_Pos) /*!< 0x00000008 */
# define CAN_F12DATA0_FD3 CAN_F12DATA0_FD3_Msk /*!< Filter bit 3 */
# define CAN_F12DATA0_FD4_Pos (4U)
# define CAN_F12DATA0_FD4_Msk (0x1U << CAN_F12DATA0_FD4_Pos) /*!< 0x00000010 */
# define CAN_F12DATA0_FD4 CAN_F12DATA0_FD4_Msk /*!< Filter bit 4 */
# define CAN_F12DATA0_FD5_Pos (5U)
# define CAN_F12DATA0_FD5_Msk (0x1U << CAN_F12DATA0_FD5_Pos) /*!< 0x00000020 */
# define CAN_F12DATA0_FD5 CAN_F12DATA0_FD5_Msk /*!< Filter bit 5 */
# define CAN_F12DATA0_FD6_Pos (6U)
# define CAN_F12DATA0_FD6_Msk (0x1U << CAN_F12DATA0_FD6_Pos) /*!< 0x00000040 */
# define CAN_F12DATA0_FD6 CAN_F12DATA0_FD6_Msk /*!< Filter bit 6 */
# define CAN_F12DATA0_FD7_Pos (7U)
# define CAN_F12DATA0_FD7_Msk (0x1U << CAN_F12DATA0_FD7_Pos) /*!< 0x00000080 */
# define CAN_F12DATA0_FD7 CAN_F12DATA0_FD7_Msk /*!< Filter bit 7 */
# define CAN_F12DATA0_FD8_Pos (8U)
# define CAN_F12DATA0_FD8_Msk (0x1U << CAN_F12DATA0_FD8_Pos) /*!< 0x00000100 */
# define CAN_F12DATA0_FD8 CAN_F12DATA0_FD8_Msk /*!< Filter bit 8 */
# define CAN_F12DATA0_FD9_Pos (9U)
# define CAN_F12DATA0_FD9_Msk (0x1U << CAN_F12DATA0_FD9_Pos) /*!< 0x00000200 */
# define CAN_F12DATA0_FD9 CAN_F12DATA0_FD9_Msk /*!< Filter bit 9 */
# define CAN_F12DATA0_FD10_Pos (10U)
# define CAN_F12DATA0_FD10_Msk (0x1U << CAN_F12DATA0_FD10_Pos) /*!< 0x00000400 */
# define CAN_F12DATA0_FD10 CAN_F12DATA0_FD10_Msk /*!< Filter bit 10 */
# define CAN_F12DATA0_FD11_Pos (11U)
# define CAN_F12DATA0_FD11_Msk (0x1U << CAN_F12DATA0_FD11_Pos) /*!< 0x00000800 */
# define CAN_F12DATA0_FD11 CAN_F12DATA0_FD11_Msk /*!< Filter bit 11 */
# define CAN_F12DATA0_FD12_Pos (12U)
# define CAN_F12DATA0_FD12_Msk (0x1U << CAN_F12DATA0_FD12_Pos) /*!< 0x00001000 */
# define CAN_F12DATA0_FD12 CAN_F12DATA0_FD12_Msk /*!< Filter bit 12 */
# define CAN_F12DATA0_FD13_Pos (13U)
# define CAN_F12DATA0_FD13_Msk (0x1U << CAN_F12DATA0_FD13_Pos) /*!< 0x00002000 */
# define CAN_F12DATA0_FD13 CAN_F12DATA0_FD13_Msk /*!< Filter bit 13 */
# define CAN_F12DATA0_FD14_Pos (14U)
# define CAN_F12DATA0_FD14_Msk (0x1U << CAN_F12DATA0_FD14_Pos) /*!< 0x00004000 */
# define CAN_F12DATA0_FD14 CAN_F12DATA0_FD14_Msk /*!< Filter bit 14 */
# define CAN_F12DATA0_FD15_Pos (15U)
# define CAN_F12DATA0_FD15_Msk (0x1U << CAN_F12DATA0_FD15_Pos) /*!< 0x00008000 */
# define CAN_F12DATA0_FD15 CAN_F12DATA0_FD15_Msk /*!< Filter bit 15 */
# define CAN_F12DATA0_FD16_Pos (16U)
# define CAN_F12DATA0_FD16_Msk (0x1U << CAN_F12DATA0_FD16_Pos) /*!< 0x00010000 */
# define CAN_F12DATA0_FD16 CAN_F12DATA0_FD16_Msk /*!< Filter bit 16 */
# define CAN_F12DATA0_FD17_Pos (17U)
# define CAN_F12DATA0_FD17_Msk (0x1U << CAN_F12DATA0_FD17_Pos) /*!< 0x00020000 */
# define CAN_F12DATA0_FD17 CAN_F12DATA0_FD17_Msk /*!< Filter bit 17 */
# define CAN_F12DATA0_FD18_Pos (18U)
# define CAN_F12DATA0_FD18_Msk (0x1U << CAN_F12DATA0_FD18_Pos) /*!< 0x00040000 */
# define CAN_F12DATA0_FD18 CAN_F12DATA0_FD18_Msk /*!< Filter bit 18 */
# define CAN_F12DATA0_FD19_Pos (19U)
# define CAN_F12DATA0_FD19_Msk (0x1U << CAN_F12DATA0_FD19_Pos) /*!< 0x00080000 */
# define CAN_F12DATA0_FD19 CAN_F12DATA0_FD19_Msk /*!< Filter bit 19 */
# define CAN_F12DATA0_FD20_Pos (20U)
# define CAN_F12DATA0_FD20_Msk (0x1U << CAN_F12DATA0_FD20_Pos) /*!< 0x00100000 */
# define CAN_F12DATA0_FD20 CAN_F12DATA0_FD20_Msk /*!< Filter bit 20 */
# define CAN_F12DATA0_FD21_Pos (21U)
# define CAN_F12DATA0_FD21_Msk (0x1U << CAN_F12DATA0_FD21_Pos) /*!< 0x00200000 */
# define CAN_F12DATA0_FD21 CAN_F12DATA0_FD21_Msk /*!< Filter bit 21 */
# define CAN_F12DATA0_FD22_Pos (22U)
# define CAN_F12DATA0_FD22_Msk (0x1U << CAN_F12DATA0_FD22_Pos) /*!< 0x00400000 */
# define CAN_F12DATA0_FD22 CAN_F12DATA0_FD22_Msk /*!< Filter bit 22 */
# define CAN_F12DATA0_FD23_Pos (23U)
# define CAN_F12DATA0_FD23_Msk (0x1U << CAN_F12DATA0_FD23_Pos) /*!< 0x00800000 */
# define CAN_F12DATA0_FD23 CAN_F12DATA0_FD23_Msk /*!< Filter bit 23 */
# define CAN_F12DATA0_FD24_Pos (24U)
# define CAN_F12DATA0_FD24_Msk (0x1U << CAN_F12DATA0_FD24_Pos) /*!< 0x01000000 */
# define CAN_F12DATA0_FD24 CAN_F12DATA0_FD24_Msk /*!< Filter bit 24 */
# define CAN_F12DATA0_FD25_Pos (25U)
# define CAN_F12DATA0_FD25_Msk (0x1U << CAN_F12DATA0_FD25_Pos) /*!< 0x02000000 */
# define CAN_F12DATA0_FD25 CAN_F12DATA0_FD25_Msk /*!< Filter bit 25 */
# define CAN_F12DATA0_FD26_Pos (26U)
# define CAN_F12DATA0_FD26_Msk (0x1U << CAN_F12DATA0_FD26_Pos) /*!< 0x04000000 */
# define CAN_F12DATA0_FD26 CAN_F12DATA0_FD26_Msk /*!< Filter bit 26 */
# define CAN_F12DATA0_FD27_Pos (27U)
# define CAN_F12DATA0_FD27_Msk (0x1U << CAN_F12DATA0_FD27_Pos) /*!< 0x08000000 */
# define CAN_F12DATA0_FD27 CAN_F12DATA0_FD27_Msk /*!< Filter bit 27 */
# define CAN_F12DATA0_FD28_Pos (28U)
# define CAN_F12DATA0_FD28_Msk (0x1U << CAN_F12DATA0_FD28_Pos) /*!< 0x10000000 */
# define CAN_F12DATA0_FD28 CAN_F12DATA0_FD28_Msk /*!< Filter bit 28 */
# define CAN_F12DATA0_FD29_Pos (29U)
# define CAN_F12DATA0_FD29_Msk (0x1U << CAN_F12DATA0_FD29_Pos) /*!< 0x20000000 */
# define CAN_F12DATA0_FD29 CAN_F12DATA0_FD29_Msk /*!< Filter bit 29 */
# define CAN_F12DATA0_FD30_Pos (30U)
# define CAN_F12DATA0_FD30_Msk (0x1U << CAN_F12DATA0_FD30_Pos) /*!< 0x40000000 */
# define CAN_F12DATA0_FD30 CAN_F12DATA0_FD30_Msk /*!< Filter bit 30 */
# define CAN_F12DATA0_FD31_Pos (31U)
# define CAN_F12DATA0_FD31_Msk (0x1U << CAN_F12DATA0_FD31_Pos) /*!< 0x80000000 */
# define CAN_F12DATA0_FD31 CAN_F12DATA0_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F13R1 register ******************/
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# define CAN_F13DATA0_FD0_Pos (0U)
# define CAN_F13DATA0_FD0_Msk (0x1U << CAN_F13DATA0_FD0_Pos) /*!< 0x00000001 */
# define CAN_F13DATA0_FD0 CAN_F13DATA0_FD0_Msk /*!< Filter bit 0 */
# define CAN_F13DATA0_FD1_Pos (1U)
# define CAN_F13DATA0_FD1_Msk (0x1U << CAN_F13DATA0_FD1_Pos) /*!< 0x00000002 */
# define CAN_F13DATA0_FD1 CAN_F13DATA0_FD1_Msk /*!< Filter bit 1 */
# define CAN_F13DATA0_FD2_Pos (2U)
# define CAN_F13DATA0_FD2_Msk (0x1U << CAN_F13DATA0_FD2_Pos) /*!< 0x00000004 */
# define CAN_F13DATA0_FD2 CAN_F13DATA0_FD2_Msk /*!< Filter bit 2 */
# define CAN_F13DATA0_FD3_Pos (3U)
# define CAN_F13DATA0_FD3_Msk (0x1U << CAN_F13DATA0_FD3_Pos) /*!< 0x00000008 */
# define CAN_F13DATA0_FD3 CAN_F13DATA0_FD3_Msk /*!< Filter bit 3 */
# define CAN_F13DATA0_FD4_Pos (4U)
# define CAN_F13DATA0_FD4_Msk (0x1U << CAN_F13DATA0_FD4_Pos) /*!< 0x00000010 */
# define CAN_F13DATA0_FD4 CAN_F13DATA0_FD4_Msk /*!< Filter bit 4 */
# define CAN_F13DATA0_FD5_Pos (5U)
# define CAN_F13DATA0_FD5_Msk (0x1U << CAN_F13DATA0_FD5_Pos) /*!< 0x00000020 */
# define CAN_F13DATA0_FD5 CAN_F13DATA0_FD5_Msk /*!< Filter bit 5 */
# define CAN_F13DATA0_FD6_Pos (6U)
# define CAN_F13DATA0_FD6_Msk (0x1U << CAN_F13DATA0_FD6_Pos) /*!< 0x00000040 */
# define CAN_F13DATA0_FD6 CAN_F13DATA0_FD6_Msk /*!< Filter bit 6 */
# define CAN_F13DATA0_FD7_Pos (7U)
# define CAN_F13DATA0_FD7_Msk (0x1U << CAN_F13DATA0_FD7_Pos) /*!< 0x00000080 */
# define CAN_F13DATA0_FD7 CAN_F13DATA0_FD7_Msk /*!< Filter bit 7 */
# define CAN_F13DATA0_FD8_Pos (8U)
# define CAN_F13DATA0_FD8_Msk (0x1U << CAN_F13DATA0_FD8_Pos) /*!< 0x00000100 */
# define CAN_F13DATA0_FD8 CAN_F13DATA0_FD8_Msk /*!< Filter bit 8 */
# define CAN_F13DATA0_FD9_Pos (9U)
# define CAN_F13DATA0_FD9_Msk (0x1U << CAN_F13DATA0_FD9_Pos) /*!< 0x00000200 */
# define CAN_F13DATA0_FD9 CAN_F13DATA0_FD9_Msk /*!< Filter bit 9 */
# define CAN_F13DATA0_FD10_Pos (10U)
# define CAN_F13DATA0_FD10_Msk (0x1U << CAN_F13DATA0_FD10_Pos) /*!< 0x00000400 */
# define CAN_F13DATA0_FD10 CAN_F13DATA0_FD10_Msk /*!< Filter bit 10 */
# define CAN_F13DATA0_FD11_Pos (11U)
# define CAN_F13DATA0_FD11_Msk (0x1U << CAN_F13DATA0_FD11_Pos) /*!< 0x00000800 */
# define CAN_F13DATA0_FD11 CAN_F13DATA0_FD11_Msk /*!< Filter bit 11 */
# define CAN_F13DATA0_FD12_Pos (12U)
# define CAN_F13DATA0_FD12_Msk (0x1U << CAN_F13DATA0_FD12_Pos) /*!< 0x00001000 */
# define CAN_F13DATA0_FD12 CAN_F13DATA0_FD12_Msk /*!< Filter bit 12 */
# define CAN_F13DATA0_FD13_Pos (13U)
# define CAN_F13DATA0_FD13_Msk (0x1U << CAN_F13DATA0_FD13_Pos) /*!< 0x00002000 */
# define CAN_F13DATA0_FD13 CAN_F13DATA0_FD13_Msk /*!< Filter bit 13 */
# define CAN_F13DATA0_FD14_Pos (14U)
# define CAN_F13DATA0_FD14_Msk (0x1U << CAN_F13DATA0_FD14_Pos) /*!< 0x00004000 */
# define CAN_F13DATA0_FD14 CAN_F13DATA0_FD14_Msk /*!< Filter bit 14 */
# define CAN_F13DATA0_FD15_Pos (15U)
# define CAN_F13DATA0_FD15_Msk (0x1U << CAN_F13DATA0_FD15_Pos) /*!< 0x00008000 */
# define CAN_F13DATA0_FD15 CAN_F13DATA0_FD15_Msk /*!< Filter bit 15 */
# define CAN_F13DATA0_FD16_Pos (16U)
# define CAN_F13DATA0_FD16_Msk (0x1U << CAN_F13DATA0_FD16_Pos) /*!< 0x00010000 */
# define CAN_F13DATA0_FD16 CAN_F13DATA0_FD16_Msk /*!< Filter bit 16 */
# define CAN_F13DATA0_FD17_Pos (17U)
# define CAN_F13DATA0_FD17_Msk (0x1U << CAN_F13DATA0_FD17_Pos) /*!< 0x00020000 */
# define CAN_F13DATA0_FD17 CAN_F13DATA0_FD17_Msk /*!< Filter bit 17 */
# define CAN_F13DATA0_FD18_Pos (18U)
# define CAN_F13DATA0_FD18_Msk (0x1U << CAN_F13DATA0_FD18_Pos) /*!< 0x00040000 */
# define CAN_F13DATA0_FD18 CAN_F13DATA0_FD18_Msk /*!< Filter bit 18 */
# define CAN_F13DATA0_FD19_Pos (19U)
# define CAN_F13DATA0_FD19_Msk (0x1U << CAN_F13DATA0_FD19_Pos) /*!< 0x00080000 */
# define CAN_F13DATA0_FD19 CAN_F13DATA0_FD19_Msk /*!< Filter bit 19 */
# define CAN_F13DATA0_FD20_Pos (20U)
# define CAN_F13DATA0_FD20_Msk (0x1U << CAN_F13DATA0_FD20_Pos) /*!< 0x00100000 */
# define CAN_F13DATA0_FD20 CAN_F13DATA0_FD20_Msk /*!< Filter bit 20 */
# define CAN_F13DATA0_FD21_Pos (21U)
# define CAN_F13DATA0_FD21_Msk (0x1U << CAN_F13DATA0_FD21_Pos) /*!< 0x00200000 */
# define CAN_F13DATA0_FD21 CAN_F13DATA0_FD21_Msk /*!< Filter bit 21 */
# define CAN_F13DATA0_FD22_Pos (22U)
# define CAN_F13DATA0_FD22_Msk (0x1U << CAN_F13DATA0_FD22_Pos) /*!< 0x00400000 */
# define CAN_F13DATA0_FD22 CAN_F13DATA0_FD22_Msk /*!< Filter bit 22 */
# define CAN_F13DATA0_FD23_Pos (23U)
# define CAN_F13DATA0_FD23_Msk (0x1U << CAN_F13DATA0_FD23_Pos) /*!< 0x00800000 */
# define CAN_F13DATA0_FD23 CAN_F13DATA0_FD23_Msk /*!< Filter bit 23 */
# define CAN_F13DATA0_FD24_Pos (24U)
# define CAN_F13DATA0_FD24_Msk (0x1U << CAN_F13DATA0_FD24_Pos) /*!< 0x01000000 */
# define CAN_F13DATA0_FD24 CAN_F13DATA0_FD24_Msk /*!< Filter bit 24 */
# define CAN_F13DATA0_FD25_Pos (25U)
# define CAN_F13DATA0_FD25_Msk (0x1U << CAN_F13DATA0_FD25_Pos) /*!< 0x02000000 */
# define CAN_F13DATA0_FD25 CAN_F13DATA0_FD25_Msk /*!< Filter bit 25 */
# define CAN_F13DATA0_FD26_Pos (26U)
# define CAN_F13DATA0_FD26_Msk (0x1U << CAN_F13DATA0_FD26_Pos) /*!< 0x04000000 */
# define CAN_F13DATA0_FD26 CAN_F13DATA0_FD26_Msk /*!< Filter bit 26 */
# define CAN_F13DATA0_FD27_Pos (27U)
# define CAN_F13DATA0_FD27_Msk (0x1U << CAN_F13DATA0_FD27_Pos) /*!< 0x08000000 */
# define CAN_F13DATA0_FD27 CAN_F13DATA0_FD27_Msk /*!< Filter bit 27 */
# define CAN_F13DATA0_FD28_Pos (28U)
# define CAN_F13DATA0_FD28_Msk (0x1U << CAN_F13DATA0_FD28_Pos) /*!< 0x10000000 */
# define CAN_F13DATA0_FD28 CAN_F13DATA0_FD28_Msk /*!< Filter bit 28 */
# define CAN_F13DATA0_FD29_Pos (29U)
# define CAN_F13DATA0_FD29_Msk (0x1U << CAN_F13DATA0_FD29_Pos) /*!< 0x20000000 */
# define CAN_F13DATA0_FD29 CAN_F13DATA0_FD29_Msk /*!< Filter bit 29 */
# define CAN_F13DATA0_FD30_Pos (30U)
# define CAN_F13DATA0_FD30_Msk (0x1U << CAN_F13DATA0_FD30_Pos) /*!< 0x40000000 */
# define CAN_F13DATA0_FD30 CAN_F13DATA0_FD30_Msk /*!< Filter bit 30 */
# define CAN_F13DATA0_FD31_Pos (31U)
# define CAN_F13DATA0_FD31_Msk (0x1U << CAN_F13DATA0_FD31_Pos) /*!< 0x80000000 */
# define CAN_F13DATA0_FD31 CAN_F13DATA0_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F14R1 register ******************/
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# define CAN_F14DATA0_FD0_Pos (0U)
# define CAN_F14DATA0_FD0_Msk (0x1U << CAN_F14DATA0_FD0_Pos) /*!< 0x00000001 */
# define CAN_F14DATA0_FD0 CAN_F14DATA0_FD0_Msk /*!< Filter bit 0 */
# define CAN_F14DATA0_FD1_Pos (1U)
# define CAN_F14DATA0_FD1_Msk (0x1U << CAN_F14DATA0_FD1_Pos) /*!< 0x00000002 */
# define CAN_F14DATA0_FD1 CAN_F14DATA0_FD1_Msk /*!< Filter bit 1 */
# define CAN_F14DATA0_FD2_Pos (2U)
# define CAN_F14DATA0_FD2_Msk (0x1U << CAN_F14DATA0_FD2_Pos) /*!< 0x00000004 */
# define CAN_F14DATA0_FD2 CAN_F14DATA0_FD2_Msk /*!< Filter bit 2 */
# define CAN_F14DATA0_FD3_Pos (3U)
# define CAN_F14DATA0_FD3_Msk (0x1U << CAN_F14DATA0_FD3_Pos) /*!< 0x00000008 */
# define CAN_F14DATA0_FD3 CAN_F14DATA0_FD3_Msk /*!< Filter bit 3 */
# define CAN_F14DATA0_FD4_Pos (4U)
# define CAN_F14DATA0_FD4_Msk (0x1U << CAN_F14DATA0_FD4_Pos) /*!< 0x00000010 */
# define CAN_F14DATA0_FD4 CAN_F14DATA0_FD4_Msk /*!< Filter bit 4 */
# define CAN_F14DATA0_FD5_Pos (5U)
# define CAN_F14DATA0_FD5_Msk (0x1U << CAN_F14DATA0_FD5_Pos) /*!< 0x00000020 */
# define CAN_F14DATA0_FD5 CAN_F14DATA0_FD5_Msk /*!< Filter bit 5 */
# define CAN_F14DATA0_FD6_Pos (6U)
# define CAN_F14DATA0_FD6_Msk (0x1U << CAN_F14DATA0_FD6_Pos) /*!< 0x00000040 */
# define CAN_F14DATA0_FD6 CAN_F14DATA0_FD6_Msk /*!< Filter bit 6 */
# define CAN_F14DATA0_FD7_Pos (7U)
# define CAN_F14DATA0_FD7_Msk (0x1U << CAN_F14DATA0_FD7_Pos) /*!< 0x00000080 */
# define CAN_F14DATA0_FD7 CAN_F14DATA0_FD7_Msk /*!< Filter bit 7 */
# define CAN_F14DATA0_FD8_Pos (8U)
# define CAN_F14DATA0_FD8_Msk (0x1U << CAN_F14DATA0_FD8_Pos) /*!< 0x00000100 */
# define CAN_F14DATA0_FD8 CAN_F14DATA0_FD8_Msk /*!< Filter bit 8 */
# define CAN_F14DATA0_FD9_Pos (9U)
# define CAN_F14DATA0_FD9_Msk (0x1U << CAN_F14DATA0_FD9_Pos) /*!< 0x00000200 */
# define CAN_F14DATA0_FD9 CAN_F14DATA0_FD9_Msk /*!< Filter bit 9 */
# define CAN_F14DATA0_FD10_Pos (10U)
# define CAN_F14DATA0_FD10_Msk (0x1U << CAN_F14DATA0_FD10_Pos) /*!< 0x00000400 */
# define CAN_F14DATA0_FD10 CAN_F14DATA0_FD10_Msk /*!< Filter bit 10 */
# define CAN_F14DATA0_FD11_Pos (11U)
# define CAN_F14DATA0_FD11_Msk (0x1U << CAN_F14DATA0_FD11_Pos) /*!< 0x00000800 */
# define CAN_F14DATA0_FD11 CAN_F14DATA0_FD11_Msk /*!< Filter bit 11 */
# define CAN_F14DATA0_FD12_Pos (12U)
# define CAN_F14DATA0_FD12_Msk (0x1U << CAN_F14DATA0_FD12_Pos) /*!< 0x00001000 */
# define CAN_F14DATA0_FD12 CAN_F14DATA0_FD12_Msk /*!< Filter bit 12 */
# define CAN_F14DATA0_FD13_Pos (13U)
# define CAN_F14DATA0_FD13_Msk (0x1U << CAN_F14DATA0_FD13_Pos) /*!< 0x00002000 */
# define CAN_F14DATA0_FD13 CAN_F14DATA0_FD13_Msk /*!< Filter bit 13 */
# define CAN_F14DATA0_FD14_Pos (14U)
# define CAN_F14DATA0_FD14_Msk (0x1U << CAN_F14DATA0_FD14_Pos) /*!< 0x00004000 */
# define CAN_F14DATA0_FD14 CAN_F14DATA0_FD14_Msk /*!< Filter bit 14 */
# define CAN_F14DATA0_FD15_Pos (15U)
# define CAN_F14DATA0_FD15_Msk (0x1U << CAN_F14DATA0_FD15_Pos) /*!< 0x00008000 */
# define CAN_F14DATA0_FD15 CAN_F14DATA0_FD15_Msk /*!< Filter bit 15 */
# define CAN_F14DATA0_FD16_Pos (16U)
# define CAN_F14DATA0_FD16_Msk (0x1U << CAN_F14DATA0_FD16_Pos) /*!< 0x00010000 */
# define CAN_F14DATA0_FD16 CAN_F14DATA0_FD16_Msk /*!< Filter bit 16 */
# define CAN_F14DATA0_FD17_Pos (17U)
# define CAN_F14DATA0_FD17_Msk (0x1U << CAN_F14DATA0_FD17_Pos) /*!< 0x00020000 */
# define CAN_F14DATA0_FD17 CAN_F14DATA0_FD17_Msk /*!< Filter bit 17 */
# define CAN_F14DATA0_FD18_Pos (18U)
# define CAN_F14DATA0_FD18_Msk (0x1U << CAN_F14DATA0_FD18_Pos) /*!< 0x00040000 */
# define CAN_F14DATA0_FD18 CAN_F14DATA0_FD18_Msk /*!< Filter bit 18 */
# define CAN_F14DATA0_FD19_Pos (19U)
# define CAN_F14DATA0_FD19_Msk (0x1U << CAN_F14DATA0_FD19_Pos) /*!< 0x00080000 */
# define CAN_F14DATA0_FD19 CAN_F14DATA0_FD19_Msk /*!< Filter bit 19 */
# define CAN_F14DATA0_FD20_Pos (20U)
# define CAN_F14DATA0_FD20_Msk (0x1U << CAN_F14DATA0_FD20_Pos) /*!< 0x00100000 */
# define CAN_F14DATA0_FD20 CAN_F14DATA0_FD20_Msk /*!< Filter bit 20 */
# define CAN_F14DATA0_FD21_Pos (21U)
# define CAN_F14DATA0_FD21_Msk (0x1U << CAN_F14DATA0_FD21_Pos) /*!< 0x00200000 */
# define CAN_F14DATA0_FD21 CAN_F14DATA0_FD21_Msk /*!< Filter bit 21 */
# define CAN_F14DATA0_FD22_Pos (22U)
# define CAN_F14DATA0_FD22_Msk (0x1U << CAN_F14DATA0_FD22_Pos) /*!< 0x00400000 */
# define CAN_F14DATA0_FD22 CAN_F14DATA0_FD22_Msk /*!< Filter bit 22 */
# define CAN_F14DATA0_FD23_Pos (23U)
# define CAN_F14DATA0_FD23_Msk (0x1U << CAN_F14DATA0_FD23_Pos) /*!< 0x00800000 */
# define CAN_F14DATA0_FD23 CAN_F14DATA0_FD23_Msk /*!< Filter bit 23 */
# define CAN_F14DATA0_FD24_Pos (24U)
# define CAN_F14DATA0_FD24_Msk (0x1U << CAN_F14DATA0_FD24_Pos) /*!< 0x01000000 */
# define CAN_F14DATA0_FD24 CAN_F14DATA0_FD24_Msk /*!< Filter bit 24 */
# define CAN_F14DATA0_FD25_Pos (25U)
# define CAN_F14DATA0_FD25_Msk (0x1U << CAN_F14DATA0_FD25_Pos) /*!< 0x02000000 */
# define CAN_F14DATA0_FD25 CAN_F14DATA0_FD25_Msk /*!< Filter bit 25 */
# define CAN_F14DATA0_FD26_Pos (26U)
# define CAN_F14DATA0_FD26_Msk (0x1U << CAN_F14DATA0_FD26_Pos) /*!< 0x04000000 */
# define CAN_F14DATA0_FD26 CAN_F14DATA0_FD26_Msk /*!< Filter bit 26 */
# define CAN_F14DATA0_FD27_Pos (27U)
# define CAN_F14DATA0_FD27_Msk (0x1U << CAN_F14DATA0_FD27_Pos) /*!< 0x08000000 */
# define CAN_F14DATA0_FD27 CAN_F14DATA0_FD27_Msk /*!< Filter bit 27 */
# define CAN_F14DATA0_FD28_Pos (28U)
# define CAN_F14DATA0_FD28_Msk (0x1U << CAN_F14DATA0_FD28_Pos) /*!< 0x10000000 */
# define CAN_F14DATA0_FD28 CAN_F14DATA0_FD28_Msk /*!< Filter bit 28 */
# define CAN_F14DATA0_FD29_Pos (29U)
# define CAN_F14DATA0_FD29_Msk (0x1U << CAN_F14DATA0_FD29_Pos) /*!< 0x20000000 */
# define CAN_F14DATA0_FD29 CAN_F14DATA0_FD29_Msk /*!< Filter bit 29 */
# define CAN_F14DATA0_FD30_Pos (30U)
# define CAN_F14DATA0_FD30_Msk (0x1U << CAN_F14DATA0_FD30_Pos) /*!< 0x40000000 */
# define CAN_F14DATA0_FD30 CAN_F14DATA0_FD30_Msk /*!< Filter bit 30 */
# define CAN_F14DATA0_FD31_Pos (31U)
# define CAN_F14DATA0_FD31_Msk (0x1U << CAN_F14DATA0_FD31_Pos) /*!< 0x80000000 */
# define CAN_F14DATA0_FD31 CAN_F14DATA0_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F15R1 register ******************/
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# define CAN_F15DATA0_FD0_Pos (0U)
# define CAN_F15DATA0_FD0_Msk (0x1U << CAN_F15DATA0_FD0_Pos) /*!< 0x00000001 */
# define CAN_F15DATA0_FD0 CAN_F15DATA0_FD0_Msk /*!< Filter bit 0 */
# define CAN_F15DATA0_FD1_Pos (1U)
# define CAN_F15DATA0_FD1_Msk (0x1U << CAN_F15DATA0_FD1_Pos) /*!< 0x00000002 */
# define CAN_F15DATA0_FD1 CAN_F15DATA0_FD1_Msk /*!< Filter bit 1 */
# define CAN_F15DATA0_FD2_Pos (2U)
# define CAN_F15DATA0_FD2_Msk (0x1U << CAN_F15DATA0_FD2_Pos) /*!< 0x00000004 */
# define CAN_F15DATA0_FD2 CAN_F15DATA0_FD2_Msk /*!< Filter bit 2 */
# define CAN_F15DATA0_FD3_Pos (3U)
# define CAN_F15DATA0_FD3_Msk (0x1U << CAN_F15DATA0_FD3_Pos) /*!< 0x00000008 */
# define CAN_F15DATA0_FD3 CAN_F15DATA0_FD3_Msk /*!< Filter bit 3 */
# define CAN_F15DATA0_FD4_Pos (4U)
# define CAN_F15DATA0_FD4_Msk (0x1U << CAN_F15DATA0_FD4_Pos) /*!< 0x00000010 */
# define CAN_F15DATA0_FD4 CAN_F15DATA0_FD4_Msk /*!< Filter bit 4 */
# define CAN_F15DATA0_FD5_Pos (5U)
# define CAN_F15DATA0_FD5_Msk (0x1U << CAN_F15DATA0_FD5_Pos) /*!< 0x00000020 */
# define CAN_F15DATA0_FD5 CAN_F15DATA0_FD5_Msk /*!< Filter bit 5 */
# define CAN_F15DATA0_FD6_Pos (6U)
# define CAN_F15DATA0_FD6_Msk (0x1U << CAN_F15DATA0_FD6_Pos) /*!< 0x00000040 */
# define CAN_F15DATA0_FD6 CAN_F15DATA0_FD6_Msk /*!< Filter bit 6 */
# define CAN_F15DATA0_FD7_Pos (7U)
# define CAN_F15DATA0_FD7_Msk (0x1U << CAN_F15DATA0_FD7_Pos) /*!< 0x00000080 */
# define CAN_F15DATA0_FD7 CAN_F15DATA0_FD7_Msk /*!< Filter bit 7 */
# define CAN_F15DATA0_FD8_Pos (8U)
# define CAN_F15DATA0_FD8_Msk (0x1U << CAN_F15DATA0_FD8_Pos) /*!< 0x00000100 */
# define CAN_F15DATA0_FD8 CAN_F15DATA0_FD8_Msk /*!< Filter bit 8 */
# define CAN_F15DATA0_FD9_Pos (9U)
# define CAN_F15DATA0_FD9_Msk (0x1U << CAN_F15DATA0_FD9_Pos) /*!< 0x00000200 */
# define CAN_F15DATA0_FD9 CAN_F15DATA0_FD9_Msk /*!< Filter bit 9 */
# define CAN_F15DATA0_FD10_Pos (10U)
# define CAN_F15DATA0_FD10_Msk (0x1U << CAN_F15DATA0_FD10_Pos) /*!< 0x00000400 */
# define CAN_F15DATA0_FD10 CAN_F15DATA0_FD10_Msk /*!< Filter bit 10 */
# define CAN_F15DATA0_FD11_Pos (11U)
# define CAN_F15DATA0_FD11_Msk (0x1U << CAN_F15DATA0_FD11_Pos) /*!< 0x00000800 */
# define CAN_F15DATA0_FD11 CAN_F15DATA0_FD11_Msk /*!< Filter bit 11 */
# define CAN_F15DATA0_FD12_Pos (12U)
# define CAN_F15DATA0_FD12_Msk (0x1U << CAN_F15DATA0_FD12_Pos) /*!< 0x00001000 */
# define CAN_F15DATA0_FD12 CAN_F15DATA0_FD12_Msk /*!< Filter bit 12 */
# define CAN_F15DATA0_FD13_Pos (13U)
# define CAN_F15DATA0_FD13_Msk (0x1U << CAN_F15DATA0_FD13_Pos) /*!< 0x00002000 */
# define CAN_F15DATA0_FD13 CAN_F15DATA0_FD13_Msk /*!< Filter bit 13 */
# define CAN_F15DATA0_FD14_Pos (14U)
# define CAN_F15DATA0_FD14_Msk (0x1U << CAN_F15DATA0_FD14_Pos) /*!< 0x00004000 */
# define CAN_F15DATA0_FD14 CAN_F15DATA0_FD14_Msk /*!< Filter bit 14 */
# define CAN_F15DATA0_FD15_Pos (15U)
# define CAN_F15DATA0_FD15_Msk (0x1U << CAN_F15DATA0_FD15_Pos) /*!< 0x00008000 */
# define CAN_F15DATA0_FD15 CAN_F15DATA0_FD15_Msk /*!< Filter bit 15 */
# define CAN_F15DATA0_FD16_Pos (16U)
# define CAN_F15DATA0_FD16_Msk (0x1U << CAN_F15DATA0_FD16_Pos) /*!< 0x00010000 */
# define CAN_F15DATA0_FD16 CAN_F15DATA0_FD16_Msk /*!< Filter bit 16 */
# define CAN_F15DATA0_FD17_Pos (17U)
# define CAN_F15DATA0_FD17_Msk (0x1U << CAN_F15DATA0_FD17_Pos) /*!< 0x00020000 */
# define CAN_F15DATA0_FD17 CAN_F15DATA0_FD17_Msk /*!< Filter bit 17 */
# define CAN_F15DATA0_FD18_Pos (18U)
# define CAN_F15DATA0_FD18_Msk (0x1U << CAN_F15DATA0_FD18_Pos) /*!< 0x00040000 */
# define CAN_F15DATA0_FD18 CAN_F15DATA0_FD18_Msk /*!< Filter bit 18 */
# define CAN_F15DATA0_FD19_Pos (19U)
# define CAN_F15DATA0_FD19_Msk (0x1U << CAN_F15DATA0_FD19_Pos) /*!< 0x00080000 */
# define CAN_F15DATA0_FD19 CAN_F15DATA0_FD19_Msk /*!< Filter bit 19 */
# define CAN_F15DATA0_FD20_Pos (20U)
# define CAN_F15DATA0_FD20_Msk (0x1U << CAN_F15DATA0_FD20_Pos) /*!< 0x00100000 */
# define CAN_F15DATA0_FD20 CAN_F15DATA0_FD20_Msk /*!< Filter bit 20 */
# define CAN_F15DATA0_FD21_Pos (21U)
# define CAN_F15DATA0_FD21_Msk (0x1U << CAN_F15DATA0_FD21_Pos) /*!< 0x00200000 */
# define CAN_F15DATA0_FD21 CAN_F15DATA0_FD21_Msk /*!< Filter bit 21 */
# define CAN_F15DATA0_FD22_Pos (22U)
# define CAN_F15DATA0_FD22_Msk (0x1U << CAN_F15DATA0_FD22_Pos) /*!< 0x00400000 */
# define CAN_F15DATA0_FD22 CAN_F15DATA0_FD22_Msk /*!< Filter bit 22 */
# define CAN_F15DATA0_FD23_Pos (23U)
# define CAN_F15DATA0_FD23_Msk (0x1U << CAN_F15DATA0_FD23_Pos) /*!< 0x00800000 */
# define CAN_F15DATA0_FD23 CAN_F15DATA0_FD23_Msk /*!< Filter bit 23 */
# define CAN_F15DATA0_FD24_Pos (24U)
# define CAN_F15DATA0_FD24_Msk (0x1U << CAN_F15DATA0_FD24_Pos) /*!< 0x01000000 */
# define CAN_F15DATA0_FD24 CAN_F15DATA0_FD24_Msk /*!< Filter bit 24 */
# define CAN_F15DATA0_FD25_Pos (25U)
# define CAN_F15DATA0_FD25_Msk (0x1U << CAN_F15DATA0_FD25_Pos) /*!< 0x02000000 */
# define CAN_F15DATA0_FD25 CAN_F15DATA0_FD25_Msk /*!< Filter bit 25 */
# define CAN_F15DATA0_FD26_Pos (26U)
# define CAN_F15DATA0_FD26_Msk (0x1U << CAN_F15DATA0_FD26_Pos) /*!< 0x04000000 */
# define CAN_F15DATA0_FD26 CAN_F15DATA0_FD26_Msk /*!< Filter bit 26 */
# define CAN_F15DATA0_FD27_Pos (27U)
# define CAN_F15DATA0_FD27_Msk (0x1U << CAN_F15DATA0_FD27_Pos) /*!< 0x08000000 */
# define CAN_F15DATA0_FD27 CAN_F15DATA0_FD27_Msk /*!< Filter bit 27 */
# define CAN_F15DATA0_FD28_Pos (28U)
# define CAN_F15DATA0_FD28_Msk (0x1U << CAN_F15DATA0_FD28_Pos) /*!< 0x10000000 */
# define CAN_F15DATA0_FD28 CAN_F15DATA0_FD28_Msk /*!< Filter bit 28 */
# define CAN_F15DATA0_FD29_Pos (29U)
# define CAN_F15DATA0_FD29_Msk (0x1U << CAN_F15DATA0_FD29_Pos) /*!< 0x20000000 */
# define CAN_F15DATA0_FD29 CAN_F15DATA0_FD29_Msk /*!< Filter bit 29 */
# define CAN_F15DATA0_FD30_Pos (30U)
# define CAN_F15DATA0_FD30_Msk (0x1U << CAN_F15DATA0_FD30_Pos) /*!< 0x40000000 */
# define CAN_F15DATA0_FD30 CAN_F15DATA0_FD30_Msk /*!< Filter bit 30 */
# define CAN_F15DATA0_FD31_Pos (31U)
# define CAN_F15DATA0_FD31_Msk (0x1U << CAN_F15DATA0_FD31_Pos) /*!< 0x80000000 */
# define CAN_F15DATA0_FD31 CAN_F15DATA0_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F16R1 register ******************/
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# define CAN_F16DATA0_FD0_Pos (0U)
# define CAN_F16DATA0_FD0_Msk (0x1U << CAN_F16DATA0_FD0_Pos) /*!< 0x00000001 */
# define CAN_F16DATA0_FD0 CAN_F16DATA0_FD0_Msk /*!< Filter bit 0 */
# define CAN_F16DATA0_FD1_Pos (1U)
# define CAN_F16DATA0_FD1_Msk (0x1U << CAN_F16DATA0_FD1_Pos) /*!< 0x00000002 */
# define CAN_F16DATA0_FD1 CAN_F16DATA0_FD1_Msk /*!< Filter bit 1 */
# define CAN_F16DATA0_FD2_Pos (2U)
# define CAN_F16DATA0_FD2_Msk (0x1U << CAN_F16DATA0_FD2_Pos) /*!< 0x00000004 */
# define CAN_F16DATA0_FD2 CAN_F16DATA0_FD2_Msk /*!< Filter bit 2 */
# define CAN_F16DATA0_FD3_Pos (3U)
# define CAN_F16DATA0_FD3_Msk (0x1U << CAN_F16DATA0_FD3_Pos) /*!< 0x00000008 */
# define CAN_F16DATA0_FD3 CAN_F16DATA0_FD3_Msk /*!< Filter bit 3 */
# define CAN_F16DATA0_FD4_Pos (4U)
# define CAN_F16DATA0_FD4_Msk (0x1U << CAN_F16DATA0_FD4_Pos) /*!< 0x00000010 */
# define CAN_F16DATA0_FD4 CAN_F16DATA0_FD4_Msk /*!< Filter bit 4 */
# define CAN_F16DATA0_FD5_Pos (5U)
# define CAN_F16DATA0_FD5_Msk (0x1U << CAN_F16DATA0_FD5_Pos) /*!< 0x00000020 */
# define CAN_F16DATA0_FD5 CAN_F16DATA0_FD5_Msk /*!< Filter bit 5 */
# define CAN_F16DATA0_FD6_Pos (6U)
# define CAN_F16DATA0_FD6_Msk (0x1U << CAN_F16DATA0_FD6_Pos) /*!< 0x00000040 */
# define CAN_F16DATA0_FD6 CAN_F16DATA0_FD6_Msk /*!< Filter bit 6 */
# define CAN_F16DATA0_FD7_Pos (7U)
# define CAN_F16DATA0_FD7_Msk (0x1U << CAN_F16DATA0_FD7_Pos) /*!< 0x00000080 */
# define CAN_F16DATA0_FD7 CAN_F16DATA0_FD7_Msk /*!< Filter bit 7 */
# define CAN_F16DATA0_FD8_Pos (8U)
# define CAN_F16DATA0_FD8_Msk (0x1U << CAN_F16DATA0_FD8_Pos) /*!< 0x00000100 */
# define CAN_F16DATA0_FD8 CAN_F16DATA0_FD8_Msk /*!< Filter bit 8 */
# define CAN_F16DATA0_FD9_Pos (9U)
# define CAN_F16DATA0_FD9_Msk (0x1U << CAN_F16DATA0_FD9_Pos) /*!< 0x00000200 */
# define CAN_F16DATA0_FD9 CAN_F16DATA0_FD9_Msk /*!< Filter bit 9 */
# define CAN_F16DATA0_FD10_Pos (10U)
# define CAN_F16DATA0_FD10_Msk (0x1U << CAN_F16DATA0_FD10_Pos) /*!< 0x00000400 */
# define CAN_F16DATA0_FD10 CAN_F16DATA0_FD10_Msk /*!< Filter bit 10 */
# define CAN_F16DATA0_FD11_Pos (11U)
# define CAN_F16DATA0_FD11_Msk (0x1U << CAN_F16DATA0_FD11_Pos) /*!< 0x00000800 */
# define CAN_F16DATA0_FD11 CAN_F16DATA0_FD11_Msk /*!< Filter bit 11 */
# define CAN_F16DATA0_FD12_Pos (12U)
# define CAN_F16DATA0_FD12_Msk (0x1U << CAN_F16DATA0_FD12_Pos) /*!< 0x00001000 */
# define CAN_F16DATA0_FD12 CAN_F16DATA0_FD12_Msk /*!< Filter bit 12 */
# define CAN_F16DATA0_FD13_Pos (13U)
# define CAN_F16DATA0_FD13_Msk (0x1U << CAN_F16DATA0_FD13_Pos) /*!< 0x00002000 */
# define CAN_F16DATA0_FD13 CAN_F16DATA0_FD13_Msk /*!< Filter bit 13 */
# define CAN_F16DATA0_FD14_Pos (14U)
# define CAN_F16DATA0_FD14_Msk (0x1U << CAN_F16DATA0_FD14_Pos) /*!< 0x00004000 */
# define CAN_F16DATA0_FD14 CAN_F16DATA0_FD14_Msk /*!< Filter bit 14 */
# define CAN_F16DATA0_FD15_Pos (15U)
# define CAN_F16DATA0_FD15_Msk (0x1U << CAN_F16DATA0_FD15_Pos) /*!< 0x00008000 */
# define CAN_F16DATA0_FD15 CAN_F16DATA0_FD15_Msk /*!< Filter bit 15 */
# define CAN_F16DATA0_FD16_Pos (16U)
# define CAN_F16DATA0_FD16_Msk (0x1U << CAN_F16DATA0_FD16_Pos) /*!< 0x00010000 */
# define CAN_F16DATA0_FD16 CAN_F16DATA0_FD16_Msk /*!< Filter bit 16 */
# define CAN_F16DATA0_FD17_Pos (17U)
# define CAN_F16DATA0_FD17_Msk (0x1U << CAN_F16DATA0_FD17_Pos) /*!< 0x00020000 */
# define CAN_F16DATA0_FD17 CAN_F16DATA0_FD17_Msk /*!< Filter bit 17 */
# define CAN_F16DATA0_FD18_Pos (18U)
# define CAN_F16DATA0_FD18_Msk (0x1U << CAN_F16DATA0_FD18_Pos) /*!< 0x00040000 */
# define CAN_F16DATA0_FD18 CAN_F16DATA0_FD18_Msk /*!< Filter bit 18 */
# define CAN_F16DATA0_FD19_Pos (19U)
# define CAN_F16DATA0_FD19_Msk (0x1U << CAN_F16DATA0_FD19_Pos) /*!< 0x00080000 */
# define CAN_F16DATA0_FD19 CAN_F16DATA0_FD19_Msk /*!< Filter bit 19 */
# define CAN_F16DATA0_FD20_Pos (20U)
# define CAN_F16DATA0_FD20_Msk (0x1U << CAN_F16DATA0_FD20_Pos) /*!< 0x00100000 */
# define CAN_F16DATA0_FD20 CAN_F16DATA0_FD20_Msk /*!< Filter bit 20 */
# define CAN_F16DATA0_FD21_Pos (21U)
# define CAN_F16DATA0_FD21_Msk (0x1U << CAN_F16DATA0_FD21_Pos) /*!< 0x00200000 */
# define CAN_F16DATA0_FD21 CAN_F16DATA0_FD21_Msk /*!< Filter bit 21 */
# define CAN_F16DATA0_FD22_Pos (22U)
# define CAN_F16DATA0_FD22_Msk (0x1U << CAN_F16DATA0_FD22_Pos) /*!< 0x00400000 */
# define CAN_F16DATA0_FD22 CAN_F16DATA0_FD22_Msk /*!< Filter bit 22 */
# define CAN_F16DATA0_FD23_Pos (23U)
# define CAN_F16DATA0_FD23_Msk (0x1U << CAN_F16DATA0_FD23_Pos) /*!< 0x00800000 */
# define CAN_F16DATA0_FD23 CAN_F16DATA0_FD23_Msk /*!< Filter bit 23 */
# define CAN_F16DATA0_FD24_Pos (24U)
# define CAN_F16DATA0_FD24_Msk (0x1U << CAN_F16DATA0_FD24_Pos) /*!< 0x01000000 */
# define CAN_F16DATA0_FD24 CAN_F16DATA0_FD24_Msk /*!< Filter bit 24 */
# define CAN_F16DATA0_FD25_Pos (25U)
# define CAN_F16DATA0_FD25_Msk (0x1U << CAN_F16DATA0_FD25_Pos) /*!< 0x02000000 */
# define CAN_F16DATA0_FD25 CAN_F16DATA0_FD25_Msk /*!< Filter bit 25 */
# define CAN_F16DATA0_FD26_Pos (26U)
# define CAN_F16DATA0_FD26_Msk (0x1U << CAN_F16DATA0_FD26_Pos) /*!< 0x04000000 */
# define CAN_F16DATA0_FD26 CAN_F16DATA0_FD26_Msk /*!< Filter bit 26 */
# define CAN_F16DATA0_FD27_Pos (27U)
# define CAN_F16DATA0_FD27_Msk (0x1U << CAN_F16DATA0_FD27_Pos) /*!< 0x08000000 */
# define CAN_F16DATA0_FD27 CAN_F16DATA0_FD27_Msk /*!< Filter bit 27 */
# define CAN_F16DATA0_FD28_Pos (28U)
# define CAN_F16DATA0_FD28_Msk (0x1U << CAN_F16DATA0_FD28_Pos) /*!< 0x10000000 */
# define CAN_F16DATA0_FD28 CAN_F16DATA0_FD28_Msk /*!< Filter bit 28 */
# define CAN_F16DATA0_FD29_Pos (29U)
# define CAN_F16DATA0_FD29_Msk (0x1U << CAN_F16DATA0_FD29_Pos) /*!< 0x20000000 */
# define CAN_F16DATA0_FD29 CAN_F16DATA0_FD29_Msk /*!< Filter bit 29 */
# define CAN_F16DATA0_FD30_Pos (30U)
# define CAN_F16DATA0_FD30_Msk (0x1U << CAN_F16DATA0_FD30_Pos) /*!< 0x40000000 */
# define CAN_F16DATA0_FD30 CAN_F16DATA0_FD30_Msk /*!< Filter bit 30 */
# define CAN_F16DATA0_FD31_Pos (31U)
# define CAN_F16DATA0_FD31_Msk (0x1U << CAN_F16DATA0_FD31_Pos) /*!< 0x80000000 */
# define CAN_F16DATA0_FD31 CAN_F16DATA0_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F17R1 register ******************/
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# define CAN_F17DATA0_FD0_Pos (0U)
# define CAN_F17DATA0_FD0_Msk (0x1U << CAN_F17DATA0_FD0_Pos) /*!< 0x00000001 */
# define CAN_F17DATA0_FD0 CAN_F17DATA0_FD0_Msk /*!< Filter bit 0 */
# define CAN_F17DATA0_FD1_Pos (1U)
# define CAN_F17DATA0_FD1_Msk (0x1U << CAN_F17DATA0_FD1_Pos) /*!< 0x00000002 */
# define CAN_F17DATA0_FD1 CAN_F17DATA0_FD1_Msk /*!< Filter bit 1 */
# define CAN_F17DATA0_FD2_Pos (2U)
# define CAN_F17DATA0_FD2_Msk (0x1U << CAN_F17DATA0_FD2_Pos) /*!< 0x00000004 */
# define CAN_F17DATA0_FD2 CAN_F17DATA0_FD2_Msk /*!< Filter bit 2 */
# define CAN_F17DATA0_FD3_Pos (3U)
# define CAN_F17DATA0_FD3_Msk (0x1U << CAN_F17DATA0_FD3_Pos) /*!< 0x00000008 */
# define CAN_F17DATA0_FD3 CAN_F17DATA0_FD3_Msk /*!< Filter bit 3 */
# define CAN_F17DATA0_FD4_Pos (4U)
# define CAN_F17DATA0_FD4_Msk (0x1U << CAN_F17DATA0_FD4_Pos) /*!< 0x00000010 */
# define CAN_F17DATA0_FD4 CAN_F17DATA0_FD4_Msk /*!< Filter bit 4 */
# define CAN_F17DATA0_FD5_Pos (5U)
# define CAN_F17DATA0_FD5_Msk (0x1U << CAN_F17DATA0_FD5_Pos) /*!< 0x00000020 */
# define CAN_F17DATA0_FD5 CAN_F17DATA0_FD5_Msk /*!< Filter bit 5 */
# define CAN_F17DATA0_FD6_Pos (6U)
# define CAN_F17DATA0_FD6_Msk (0x1U << CAN_F17DATA0_FD6_Pos) /*!< 0x00000040 */
# define CAN_F17DATA0_FD6 CAN_F17DATA0_FD6_Msk /*!< Filter bit 6 */
# define CAN_F17DATA0_FD7_Pos (7U)
# define CAN_F17DATA0_FD7_Msk (0x1U << CAN_F17DATA0_FD7_Pos) /*!< 0x00000080 */
# define CAN_F17DATA0_FD7 CAN_F17DATA0_FD7_Msk /*!< Filter bit 7 */
# define CAN_F17DATA0_FD8_Pos (8U)
# define CAN_F17DATA0_FD8_Msk (0x1U << CAN_F17DATA0_FD8_Pos) /*!< 0x00000100 */
# define CAN_F17DATA0_FD8 CAN_F17DATA0_FD8_Msk /*!< Filter bit 8 */
# define CAN_F17DATA0_FD9_Pos (9U)
# define CAN_F17DATA0_FD9_Msk (0x1U << CAN_F17DATA0_FD9_Pos) /*!< 0x00000200 */
# define CAN_F17DATA0_FD9 CAN_F17DATA0_FD9_Msk /*!< Filter bit 9 */
# define CAN_F17DATA0_FD10_Pos (10U)
# define CAN_F17DATA0_FD10_Msk (0x1U << CAN_F17DATA0_FD10_Pos) /*!< 0x00000400 */
# define CAN_F17DATA0_FD10 CAN_F17DATA0_FD10_Msk /*!< Filter bit 10 */
# define CAN_F17DATA0_FD11_Pos (11U)
# define CAN_F17DATA0_FD11_Msk (0x1U << CAN_F17DATA0_FD11_Pos) /*!< 0x00000800 */
# define CAN_F17DATA0_FD11 CAN_F17DATA0_FD11_Msk /*!< Filter bit 11 */
# define CAN_F17DATA0_FD12_Pos (12U)
# define CAN_F17DATA0_FD12_Msk (0x1U << CAN_F17DATA0_FD12_Pos) /*!< 0x00001000 */
# define CAN_F17DATA0_FD12 CAN_F17DATA0_FD12_Msk /*!< Filter bit 12 */
# define CAN_F17DATA0_FD13_Pos (13U)
# define CAN_F17DATA0_FD13_Msk (0x1U << CAN_F17DATA0_FD13_Pos) /*!< 0x00002000 */
# define CAN_F17DATA0_FD13 CAN_F17DATA0_FD13_Msk /*!< Filter bit 13 */
# define CAN_F17DATA0_FD14_Pos (14U)
# define CAN_F17DATA0_FD14_Msk (0x1U << CAN_F17DATA0_FD14_Pos) /*!< 0x00004000 */
# define CAN_F17DATA0_FD14 CAN_F17DATA0_FD14_Msk /*!< Filter bit 14 */
# define CAN_F17DATA0_FD15_Pos (15U)
# define CAN_F17DATA0_FD15_Msk (0x1U << CAN_F17DATA0_FD15_Pos) /*!< 0x00008000 */
# define CAN_F17DATA0_FD15 CAN_F17DATA0_FD15_Msk /*!< Filter bit 15 */
# define CAN_F17DATA0_FD16_Pos (16U)
# define CAN_F17DATA0_FD16_Msk (0x1U << CAN_F17DATA0_FD16_Pos) /*!< 0x00010000 */
# define CAN_F17DATA0_FD16 CAN_F17DATA0_FD16_Msk /*!< Filter bit 16 */
# define CAN_F17DATA0_FD17_Pos (17U)
# define CAN_F17DATA0_FD17_Msk (0x1U << CAN_F17DATA0_FD17_Pos) /*!< 0x00020000 */
# define CAN_F17DATA0_FD17 CAN_F17DATA0_FD17_Msk /*!< Filter bit 17 */
# define CAN_F17DATA0_FD18_Pos (18U)
# define CAN_F17DATA0_FD18_Msk (0x1U << CAN_F17DATA0_FD18_Pos) /*!< 0x00040000 */
# define CAN_F17DATA0_FD18 CAN_F17DATA0_FD18_Msk /*!< Filter bit 18 */
# define CAN_F17DATA0_FD19_Pos (19U)
# define CAN_F17DATA0_FD19_Msk (0x1U << CAN_F17DATA0_FD19_Pos) /*!< 0x00080000 */
# define CAN_F17DATA0_FD19 CAN_F17DATA0_FD19_Msk /*!< Filter bit 19 */
# define CAN_F17DATA0_FD20_Pos (20U)
# define CAN_F17DATA0_FD20_Msk (0x1U << CAN_F17DATA0_FD20_Pos) /*!< 0x00100000 */
# define CAN_F17DATA0_FD20 CAN_F17DATA0_FD20_Msk /*!< Filter bit 20 */
# define CAN_F17DATA0_FD21_Pos (21U)
# define CAN_F17DATA0_FD21_Msk (0x1U << CAN_F17DATA0_FD21_Pos) /*!< 0x00200000 */
# define CAN_F17DATA0_FD21 CAN_F17DATA0_FD21_Msk /*!< Filter bit 21 */
# define CAN_F17DATA0_FD22_Pos (22U)
# define CAN_F17DATA0_FD22_Msk (0x1U << CAN_F17DATA0_FD22_Pos) /*!< 0x00400000 */
# define CAN_F17DATA0_FD22 CAN_F17DATA0_FD22_Msk /*!< Filter bit 22 */
# define CAN_F17DATA0_FD23_Pos (23U)
# define CAN_F17DATA0_FD23_Msk (0x1U << CAN_F17DATA0_FD23_Pos) /*!< 0x00800000 */
# define CAN_F17DATA0_FD23 CAN_F17DATA0_FD23_Msk /*!< Filter bit 23 */
# define CAN_F17DATA0_FD24_Pos (24U)
# define CAN_F17DATA0_FD24_Msk (0x1U << CAN_F17DATA0_FD24_Pos) /*!< 0x01000000 */
# define CAN_F17DATA0_FD24 CAN_F17DATA0_FD24_Msk /*!< Filter bit 24 */
# define CAN_F17DATA0_FD25_Pos (25U)
# define CAN_F17DATA0_FD25_Msk (0x1U << CAN_F17DATA0_FD25_Pos) /*!< 0x02000000 */
# define CAN_F17DATA0_FD25 CAN_F17DATA0_FD25_Msk /*!< Filter bit 25 */
# define CAN_F17DATA0_FD26_Pos (26U)
# define CAN_F17DATA0_FD26_Msk (0x1U << CAN_F17DATA0_FD26_Pos) /*!< 0x04000000 */
# define CAN_F17DATA0_FD26 CAN_F17DATA0_FD26_Msk /*!< Filter bit 26 */
# define CAN_F17DATA0_FD27_Pos (27U)
# define CAN_F17DATA0_FD27_Msk (0x1U << CAN_F17DATA0_FD27_Pos) /*!< 0x08000000 */
# define CAN_F17DATA0_FD27 CAN_F17DATA0_FD27_Msk /*!< Filter bit 27 */
# define CAN_F17DATA0_FD28_Pos (28U)
# define CAN_F17DATA0_FD28_Msk (0x1U << CAN_F17DATA0_FD28_Pos) /*!< 0x10000000 */
# define CAN_F17DATA0_FD28 CAN_F17DATA0_FD28_Msk /*!< Filter bit 28 */
# define CAN_F17DATA0_FD29_Pos (29U)
# define CAN_F17DATA0_FD29_Msk (0x1U << CAN_F17DATA0_FD29_Pos) /*!< 0x20000000 */
# define CAN_F17DATA0_FD29 CAN_F17DATA0_FD29_Msk /*!< Filter bit 29 */
# define CAN_F17DATA0_FD30_Pos (30U)
# define CAN_F17DATA0_FD30_Msk (0x1U << CAN_F17DATA0_FD30_Pos) /*!< 0x40000000 */
# define CAN_F17DATA0_FD30 CAN_F17DATA0_FD30_Msk /*!< Filter bit 30 */
# define CAN_F17DATA0_FD31_Pos (31U)
# define CAN_F17DATA0_FD31_Msk (0x1U << CAN_F17DATA0_FD31_Pos) /*!< 0x80000000 */
# define CAN_F17DATA0_FD31 CAN_F17DATA0_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F18R1 register ******************/
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# define CAN_F18DATA0_FD0_Pos (0U)
# define CAN_F18DATA0_FD0_Msk (0x1U << CAN_F18DATA0_FD0_Pos) /*!< 0x00000001 */
# define CAN_F18DATA0_FD0 CAN_F18DATA0_FD0_Msk /*!< Filter bit 0 */
# define CAN_F18DATA0_FD1_Pos (1U)
# define CAN_F18DATA0_FD1_Msk (0x1U << CAN_F18DATA0_FD1_Pos) /*!< 0x00000002 */
# define CAN_F18DATA0_FD1 CAN_F18DATA0_FD1_Msk /*!< Filter bit 1 */
# define CAN_F18DATA0_FD2_Pos (2U)
# define CAN_F18DATA0_FD2_Msk (0x1U << CAN_F18DATA0_FD2_Pos) /*!< 0x00000004 */
# define CAN_F18DATA0_FD2 CAN_F18DATA0_FD2_Msk /*!< Filter bit 2 */
# define CAN_F18DATA0_FD3_Pos (3U)
# define CAN_F18DATA0_FD3_Msk (0x1U << CAN_F18DATA0_FD3_Pos) /*!< 0x00000008 */
# define CAN_F18DATA0_FD3 CAN_F18DATA0_FD3_Msk /*!< Filter bit 3 */
# define CAN_F18DATA0_FD4_Pos (4U)
# define CAN_F18DATA0_FD4_Msk (0x1U << CAN_F18DATA0_FD4_Pos) /*!< 0x00000010 */
# define CAN_F18DATA0_FD4 CAN_F18DATA0_FD4_Msk /*!< Filter bit 4 */
# define CAN_F18DATA0_FD5_Pos (5U)
# define CAN_F18DATA0_FD5_Msk (0x1U << CAN_F18DATA0_FD5_Pos) /*!< 0x00000020 */
# define CAN_F18DATA0_FD5 CAN_F18DATA0_FD5_Msk /*!< Filter bit 5 */
# define CAN_F18DATA0_FD6_Pos (6U)
# define CAN_F18DATA0_FD6_Msk (0x1U << CAN_F18DATA0_FD6_Pos) /*!< 0x00000040 */
# define CAN_F18DATA0_FD6 CAN_F18DATA0_FD6_Msk /*!< Filter bit 6 */
# define CAN_F18DATA0_FD7_Pos (7U)
# define CAN_F18DATA0_FD7_Msk (0x1U << CAN_F18DATA0_FD7_Pos) /*!< 0x00000080 */
# define CAN_F18DATA0_FD7 CAN_F18DATA0_FD7_Msk /*!< Filter bit 7 */
# define CAN_F18DATA0_FD8_Pos (8U)
# define CAN_F18DATA0_FD8_Msk (0x1U << CAN_F18DATA0_FD8_Pos) /*!< 0x00000100 */
# define CAN_F18DATA0_FD8 CAN_F18DATA0_FD8_Msk /*!< Filter bit 8 */
# define CAN_F18DATA0_FD9_Pos (9U)
# define CAN_F18DATA0_FD9_Msk (0x1U << CAN_F18DATA0_FD9_Pos) /*!< 0x00000200 */
# define CAN_F18DATA0_FD9 CAN_F18DATA0_FD9_Msk /*!< Filter bit 9 */
# define CAN_F18DATA0_FD10_Pos (10U)
# define CAN_F18DATA0_FD10_Msk (0x1U << CAN_F18DATA0_FD10_Pos) /*!< 0x00000400 */
# define CAN_F18DATA0_FD10 CAN_F18DATA0_FD10_Msk /*!< Filter bit 10 */
# define CAN_F18DATA0_FD11_Pos (11U)
# define CAN_F18DATA0_FD11_Msk (0x1U << CAN_F18DATA0_FD11_Pos) /*!< 0x00000800 */
# define CAN_F18DATA0_FD11 CAN_F18DATA0_FD11_Msk /*!< Filter bit 11 */
# define CAN_F18DATA0_FD12_Pos (12U)
# define CAN_F18DATA0_FD12_Msk (0x1U << CAN_F18DATA0_FD12_Pos) /*!< 0x00001000 */
# define CAN_F18DATA0_FD12 CAN_F18DATA0_FD12_Msk /*!< Filter bit 12 */
# define CAN_F18DATA0_FD13_Pos (13U)
# define CAN_F18DATA0_FD13_Msk (0x1U << CAN_F18DATA0_FD13_Pos) /*!< 0x00002000 */
# define CAN_F18DATA0_FD13 CAN_F18DATA0_FD13_Msk /*!< Filter bit 13 */
# define CAN_F18DATA0_FD14_Pos (14U)
# define CAN_F18DATA0_FD14_Msk (0x1U << CAN_F18DATA0_FD14_Pos) /*!< 0x00004000 */
# define CAN_F18DATA0_FD14 CAN_F18DATA0_FD14_Msk /*!< Filter bit 14 */
# define CAN_F18DATA0_FD15_Pos (15U)
# define CAN_F18DATA0_FD15_Msk (0x1U << CAN_F18DATA0_FD15_Pos) /*!< 0x00008000 */
# define CAN_F18DATA0_FD15 CAN_F18DATA0_FD15_Msk /*!< Filter bit 15 */
# define CAN_F18DATA0_FD16_Pos (16U)
# define CAN_F18DATA0_FD16_Msk (0x1U << CAN_F18DATA0_FD16_Pos) /*!< 0x00010000 */
# define CAN_F18DATA0_FD16 CAN_F18DATA0_FD16_Msk /*!< Filter bit 16 */
# define CAN_F18DATA0_FD17_Pos (17U)
# define CAN_F18DATA0_FD17_Msk (0x1U << CAN_F18DATA0_FD17_Pos) /*!< 0x00020000 */
# define CAN_F18DATA0_FD17 CAN_F18DATA0_FD17_Msk /*!< Filter bit 17 */
# define CAN_F18DATA0_FD18_Pos (18U)
# define CAN_F18DATA0_FD18_Msk (0x1U << CAN_F18DATA0_FD18_Pos) /*!< 0x00040000 */
# define CAN_F18DATA0_FD18 CAN_F18DATA0_FD18_Msk /*!< Filter bit 18 */
# define CAN_F18DATA0_FD19_Pos (19U)
# define CAN_F18DATA0_FD19_Msk (0x1U << CAN_F18DATA0_FD19_Pos) /*!< 0x00080000 */
# define CAN_F18DATA0_FD19 CAN_F18DATA0_FD19_Msk /*!< Filter bit 19 */
# define CAN_F18DATA0_FD20_Pos (20U)
# define CAN_F18DATA0_FD20_Msk (0x1U << CAN_F18DATA0_FD20_Pos) /*!< 0x00100000 */
# define CAN_F18DATA0_FD20 CAN_F18DATA0_FD20_Msk /*!< Filter bit 20 */
# define CAN_F18DATA0_FD21_Pos (21U)
# define CAN_F18DATA0_FD21_Msk (0x1U << CAN_F18DATA0_FD21_Pos) /*!< 0x00200000 */
# define CAN_F18DATA0_FD21 CAN_F18DATA0_FD21_Msk /*!< Filter bit 21 */
# define CAN_F18DATA0_FD22_Pos (22U)
# define CAN_F18DATA0_FD22_Msk (0x1U << CAN_F18DATA0_FD22_Pos) /*!< 0x00400000 */
# define CAN_F18DATA0_FD22 CAN_F18DATA0_FD22_Msk /*!< Filter bit 22 */
# define CAN_F18DATA0_FD23_Pos (23U)
# define CAN_F18DATA0_FD23_Msk (0x1U << CAN_F18DATA0_FD23_Pos) /*!< 0x00800000 */
# define CAN_F18DATA0_FD23 CAN_F18DATA0_FD23_Msk /*!< Filter bit 23 */
# define CAN_F18DATA0_FD24_Pos (24U)
# define CAN_F18DATA0_FD24_Msk (0x1U << CAN_F18DATA0_FD24_Pos) /*!< 0x01000000 */
# define CAN_F18DATA0_FD24 CAN_F18DATA0_FD24_Msk /*!< Filter bit 24 */
# define CAN_F18DATA0_FD25_Pos (25U)
# define CAN_F18DATA0_FD25_Msk (0x1U << CAN_F18DATA0_FD25_Pos) /*!< 0x02000000 */
# define CAN_F18DATA0_FD25 CAN_F18DATA0_FD25_Msk /*!< Filter bit 25 */
# define CAN_F18DATA0_FD26_Pos (26U)
# define CAN_F18DATA0_FD26_Msk (0x1U << CAN_F18DATA0_FD26_Pos) /*!< 0x04000000 */
# define CAN_F18DATA0_FD26 CAN_F18DATA0_FD26_Msk /*!< Filter bit 26 */
# define CAN_F18DATA0_FD27_Pos (27U)
# define CAN_F18DATA0_FD27_Msk (0x1U << CAN_F18DATA0_FD27_Pos) /*!< 0x08000000 */
# define CAN_F18DATA0_FD27 CAN_F18DATA0_FD27_Msk /*!< Filter bit 27 */
# define CAN_F18DATA0_FD28_Pos (28U)
# define CAN_F18DATA0_FD28_Msk (0x1U << CAN_F18DATA0_FD28_Pos) /*!< 0x10000000 */
# define CAN_F18DATA0_FD28 CAN_F18DATA0_FD28_Msk /*!< Filter bit 28 */
# define CAN_F18DATA0_FD29_Pos (29U)
# define CAN_F18DATA0_FD29_Msk (0x1U << CAN_F18DATA0_FD29_Pos) /*!< 0x20000000 */
# define CAN_F18DATA0_FD29 CAN_F18DATA0_FD29_Msk /*!< Filter bit 29 */
# define CAN_F18DATA0_FD30_Pos (30U)
# define CAN_F18DATA0_FD30_Msk (0x1U << CAN_F18DATA0_FD30_Pos) /*!< 0x40000000 */
# define CAN_F18DATA0_FD30 CAN_F18DATA0_FD30_Msk /*!< Filter bit 30 */
# define CAN_F18DATA0_FD31_Pos (31U)
# define CAN_F18DATA0_FD31_Msk (0x1U << CAN_F18DATA0_FD31_Pos) /*!< 0x80000000 */
# define CAN_F18DATA0_FD31 CAN_F18DATA0_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F19R1 register ******************/
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# define CAN_F19DATA0_FD0_Pos (0U)
# define CAN_F19DATA0_FD0_Msk (0x1U << CAN_F19DATA0_FD0_Pos) /*!< 0x00000001 */
# define CAN_F19DATA0_FD0 CAN_F19DATA0_FD0_Msk /*!< Filter bit 0 */
# define CAN_F19DATA0_FD1_Pos (1U)
# define CAN_F19DATA0_FD1_Msk (0x1U << CAN_F19DATA0_FD1_Pos) /*!< 0x00000002 */
# define CAN_F19DATA0_FD1 CAN_F19DATA0_FD1_Msk /*!< Filter bit 1 */
# define CAN_F19DATA0_FD2_Pos (2U)
# define CAN_F19DATA0_FD2_Msk (0x1U << CAN_F19DATA0_FD2_Pos) /*!< 0x00000004 */
# define CAN_F19DATA0_FD2 CAN_F19DATA0_FD2_Msk /*!< Filter bit 2 */
# define CAN_F19DATA0_FD3_Pos (3U)
# define CAN_F19DATA0_FD3_Msk (0x1U << CAN_F19DATA0_FD3_Pos) /*!< 0x00000008 */
# define CAN_F19DATA0_FD3 CAN_F19DATA0_FD3_Msk /*!< Filter bit 3 */
# define CAN_F19DATA0_FD4_Pos (4U)
# define CAN_F19DATA0_FD4_Msk (0x1U << CAN_F19DATA0_FD4_Pos) /*!< 0x00000010 */
# define CAN_F19DATA0_FD4 CAN_F19DATA0_FD4_Msk /*!< Filter bit 4 */
# define CAN_F19DATA0_FD5_Pos (5U)
# define CAN_F19DATA0_FD5_Msk (0x1U << CAN_F19DATA0_FD5_Pos) /*!< 0x00000020 */
# define CAN_F19DATA0_FD5 CAN_F19DATA0_FD5_Msk /*!< Filter bit 5 */
# define CAN_F19DATA0_FD6_Pos (6U)
# define CAN_F19DATA0_FD6_Msk (0x1U << CAN_F19DATA0_FD6_Pos) /*!< 0x00000040 */
# define CAN_F19DATA0_FD6 CAN_F19DATA0_FD6_Msk /*!< Filter bit 6 */
# define CAN_F19DATA0_FD7_Pos (7U)
# define CAN_F19DATA0_FD7_Msk (0x1U << CAN_F19DATA0_FD7_Pos) /*!< 0x00000080 */
# define CAN_F19DATA0_FD7 CAN_F19DATA0_FD7_Msk /*!< Filter bit 7 */
# define CAN_F19DATA0_FD8_Pos (8U)
# define CAN_F19DATA0_FD8_Msk (0x1U << CAN_F19DATA0_FD8_Pos) /*!< 0x00000100 */
# define CAN_F19DATA0_FD8 CAN_F19DATA0_FD8_Msk /*!< Filter bit 8 */
# define CAN_F19DATA0_FD9_Pos (9U)
# define CAN_F19DATA0_FD9_Msk (0x1U << CAN_F19DATA0_FD9_Pos) /*!< 0x00000200 */
# define CAN_F19DATA0_FD9 CAN_F19DATA0_FD9_Msk /*!< Filter bit 9 */
# define CAN_F19DATA0_FD10_Pos (10U)
# define CAN_F19DATA0_FD10_Msk (0x1U << CAN_F19DATA0_FD10_Pos) /*!< 0x00000400 */
# define CAN_F19DATA0_FD10 CAN_F19DATA0_FD10_Msk /*!< Filter bit 10 */
# define CAN_F19DATA0_FD11_Pos (11U)
# define CAN_F19DATA0_FD11_Msk (0x1U << CAN_F19DATA0_FD11_Pos) /*!< 0x00000800 */
# define CAN_F19DATA0_FD11 CAN_F19DATA0_FD11_Msk /*!< Filter bit 11 */
# define CAN_F19DATA0_FD12_Pos (12U)
# define CAN_F19DATA0_FD12_Msk (0x1U << CAN_F19DATA0_FD12_Pos) /*!< 0x00001000 */
# define CAN_F19DATA0_FD12 CAN_F19DATA0_FD12_Msk /*!< Filter bit 12 */
# define CAN_F19DATA0_FD13_Pos (13U)
# define CAN_F19DATA0_FD13_Msk (0x1U << CAN_F19DATA0_FD13_Pos) /*!< 0x00002000 */
# define CAN_F19DATA0_FD13 CAN_F19DATA0_FD13_Msk /*!< Filter bit 13 */
# define CAN_F19DATA0_FD14_Pos (14U)
# define CAN_F19DATA0_FD14_Msk (0x1U << CAN_F19DATA0_FD14_Pos) /*!< 0x00004000 */
# define CAN_F19DATA0_FD14 CAN_F19DATA0_FD14_Msk /*!< Filter bit 14 */
# define CAN_F19DATA0_FD15_Pos (15U)
# define CAN_F19DATA0_FD15_Msk (0x1U << CAN_F19DATA0_FD15_Pos) /*!< 0x00008000 */
# define CAN_F19DATA0_FD15 CAN_F19DATA0_FD15_Msk /*!< Filter bit 15 */
# define CAN_F19DATA0_FD16_Pos (16U)
# define CAN_F19DATA0_FD16_Msk (0x1U << CAN_F19DATA0_FD16_Pos) /*!< 0x00010000 */
# define CAN_F19DATA0_FD16 CAN_F19DATA0_FD16_Msk /*!< Filter bit 16 */
# define CAN_F19DATA0_FD17_Pos (17U)
# define CAN_F19DATA0_FD17_Msk (0x1U << CAN_F19DATA0_FD17_Pos) /*!< 0x00020000 */
# define CAN_F19DATA0_FD17 CAN_F19DATA0_FD17_Msk /*!< Filter bit 17 */
# define CAN_F19DATA0_FD18_Pos (18U)
# define CAN_F19DATA0_FD18_Msk (0x1U << CAN_F19DATA0_FD18_Pos) /*!< 0x00040000 */
# define CAN_F19DATA0_FD18 CAN_F19DATA0_FD18_Msk /*!< Filter bit 18 */
# define CAN_F19DATA0_FD19_Pos (19U)
# define CAN_F19DATA0_FD19_Msk (0x1U << CAN_F19DATA0_FD19_Pos) /*!< 0x00080000 */
# define CAN_F19DATA0_FD19 CAN_F19DATA0_FD19_Msk /*!< Filter bit 19 */
# define CAN_F19DATA0_FD20_Pos (20U)
# define CAN_F19DATA0_FD20_Msk (0x1U << CAN_F19DATA0_FD20_Pos) /*!< 0x00100000 */
# define CAN_F19DATA0_FD20 CAN_F19DATA0_FD20_Msk /*!< Filter bit 20 */
# define CAN_F19DATA0_FD21_Pos (21U)
# define CAN_F19DATA0_FD21_Msk (0x1U << CAN_F19DATA0_FD21_Pos) /*!< 0x00200000 */
# define CAN_F19DATA0_FD21 CAN_F19DATA0_FD21_Msk /*!< Filter bit 21 */
# define CAN_F19DATA0_FD22_Pos (22U)
# define CAN_F19DATA0_FD22_Msk (0x1U << CAN_F19DATA0_FD22_Pos) /*!< 0x00400000 */
# define CAN_F19DATA0_FD22 CAN_F19DATA0_FD22_Msk /*!< Filter bit 22 */
# define CAN_F19DATA0_FD23_Pos (23U)
# define CAN_F19DATA0_FD23_Msk (0x1U << CAN_F19DATA0_FD23_Pos) /*!< 0x00800000 */
# define CAN_F19DATA0_FD23 CAN_F19DATA0_FD23_Msk /*!< Filter bit 23 */
# define CAN_F19DATA0_FD24_Pos (24U)
# define CAN_F19DATA0_FD24_Msk (0x1U << CAN_F19DATA0_FD24_Pos) /*!< 0x01000000 */
# define CAN_F19DATA0_FD24 CAN_F19DATA0_FD24_Msk /*!< Filter bit 24 */
# define CAN_F19DATA0_FD25_Pos (25U)
# define CAN_F19DATA0_FD25_Msk (0x1U << CAN_F19DATA0_FD25_Pos) /*!< 0x02000000 */
# define CAN_F19DATA0_FD25 CAN_F19DATA0_FD25_Msk /*!< Filter bit 25 */
# define CAN_F19DATA0_FD26_Pos (26U)
# define CAN_F19DATA0_FD26_Msk (0x1U << CAN_F19DATA0_FD26_Pos) /*!< 0x04000000 */
# define CAN_F19DATA0_FD26 CAN_F19DATA0_FD26_Msk /*!< Filter bit 26 */
# define CAN_F19DATA0_FD27_Pos (27U)
# define CAN_F19DATA0_FD27_Msk (0x1U << CAN_F19DATA0_FD27_Pos) /*!< 0x08000000 */
# define CAN_F19DATA0_FD27 CAN_F19DATA0_FD27_Msk /*!< Filter bit 27 */
# define CAN_F19DATA0_FD28_Pos (28U)
# define CAN_F19DATA0_FD28_Msk (0x1U << CAN_F19DATA0_FD28_Pos) /*!< 0x10000000 */
# define CAN_F19DATA0_FD28 CAN_F19DATA0_FD28_Msk /*!< Filter bit 28 */
# define CAN_F19DATA0_FD29_Pos (29U)
# define CAN_F19DATA0_FD29_Msk (0x1U << CAN_F19DATA0_FD29_Pos) /*!< 0x20000000 */
# define CAN_F19DATA0_FD29 CAN_F19DATA0_FD29_Msk /*!< Filter bit 29 */
# define CAN_F19DATA0_FD30_Pos (30U)
# define CAN_F19DATA0_FD30_Msk (0x1U << CAN_F19DATA0_FD30_Pos) /*!< 0x40000000 */
# define CAN_F19DATA0_FD30 CAN_F19DATA0_FD30_Msk /*!< Filter bit 30 */
# define CAN_F19DATA0_FD31_Pos (31U)
# define CAN_F19DATA0_FD31_Msk (0x1U << CAN_F19DATA0_FD31_Pos) /*!< 0x80000000 */
# define CAN_F19DATA0_FD31 CAN_F19DATA0_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F20R1 register ******************/
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# define CAN_F20DATA0_FD0_Pos (0U)
# define CAN_F20DATA0_FD0_Msk (0x1U << CAN_F20DATA0_FD0_Pos) /*!< 0x00000001 */
# define CAN_F20DATA0_FD0 CAN_F20DATA0_FD0_Msk /*!< Filter bit 0 */
# define CAN_F20DATA0_FD1_Pos (1U)
# define CAN_F20DATA0_FD1_Msk (0x1U << CAN_F20DATA0_FD1_Pos) /*!< 0x00000002 */
# define CAN_F20DATA0_FD1 CAN_F20DATA0_FD1_Msk /*!< Filter bit 1 */
# define CAN_F20DATA0_FD2_Pos (2U)
# define CAN_F20DATA0_FD2_Msk (0x1U << CAN_F20DATA0_FD2_Pos) /*!< 0x00000004 */
# define CAN_F20DATA0_FD2 CAN_F20DATA0_FD2_Msk /*!< Filter bit 2 */
# define CAN_F20DATA0_FD3_Pos (3U)
# define CAN_F20DATA0_FD3_Msk (0x1U << CAN_F20DATA0_FD3_Pos) /*!< 0x00000008 */
# define CAN_F20DATA0_FD3 CAN_F20DATA0_FD3_Msk /*!< Filter bit 3 */
# define CAN_F20DATA0_FD4_Pos (4U)
# define CAN_F20DATA0_FD4_Msk (0x1U << CAN_F20DATA0_FD4_Pos) /*!< 0x00000010 */
# define CAN_F20DATA0_FD4 CAN_F20DATA0_FD4_Msk /*!< Filter bit 4 */
# define CAN_F20DATA0_FD5_Pos (5U)
# define CAN_F20DATA0_FD5_Msk (0x1U << CAN_F20DATA0_FD5_Pos) /*!< 0x00000020 */
# define CAN_F20DATA0_FD5 CAN_F20DATA0_FD5_Msk /*!< Filter bit 5 */
# define CAN_F20DATA0_FD6_Pos (6U)
# define CAN_F20DATA0_FD6_Msk (0x1U << CAN_F20DATA0_FD6_Pos) /*!< 0x00000040 */
# define CAN_F20DATA0_FD6 CAN_F20DATA0_FD6_Msk /*!< Filter bit 6 */
# define CAN_F20DATA0_FD7_Pos (7U)
# define CAN_F20DATA0_FD7_Msk (0x1U << CAN_F20DATA0_FD7_Pos) /*!< 0x00000080 */
# define CAN_F20DATA0_FD7 CAN_F20DATA0_FD7_Msk /*!< Filter bit 7 */
# define CAN_F20DATA0_FD8_Pos (8U)
# define CAN_F20DATA0_FD8_Msk (0x1U << CAN_F20DATA0_FD8_Pos) /*!< 0x00000100 */
# define CAN_F20DATA0_FD8 CAN_F20DATA0_FD8_Msk /*!< Filter bit 8 */
# define CAN_F20DATA0_FD9_Pos (9U)
# define CAN_F20DATA0_FD9_Msk (0x1U << CAN_F20DATA0_FD9_Pos) /*!< 0x00000200 */
# define CAN_F20DATA0_FD9 CAN_F20DATA0_FD9_Msk /*!< Filter bit 9 */
# define CAN_F20DATA0_FD10_Pos (10U)
# define CAN_F20DATA0_FD10_Msk (0x1U << CAN_F20DATA0_FD10_Pos) /*!< 0x00000400 */
# define CAN_F20DATA0_FD10 CAN_F20DATA0_FD10_Msk /*!< Filter bit 10 */
# define CAN_F20DATA0_FD11_Pos (11U)
# define CAN_F20DATA0_FD11_Msk (0x1U << CAN_F20DATA0_FD11_Pos) /*!< 0x00000800 */
# define CAN_F20DATA0_FD11 CAN_F20DATA0_FD11_Msk /*!< Filter bit 11 */
# define CAN_F20DATA0_FD12_Pos (12U)
# define CAN_F20DATA0_FD12_Msk (0x1U << CAN_F20DATA0_FD12_Pos) /*!< 0x00001000 */
# define CAN_F20DATA0_FD12 CAN_F20DATA0_FD12_Msk /*!< Filter bit 12 */
# define CAN_F20DATA0_FD13_Pos (13U)
# define CAN_F20DATA0_FD13_Msk (0x1U << CAN_F20DATA0_FD13_Pos) /*!< 0x00002000 */
# define CAN_F20DATA0_FD13 CAN_F20DATA0_FD13_Msk /*!< Filter bit 13 */
# define CAN_F20DATA0_FD14_Pos (14U)
# define CAN_F20DATA0_FD14_Msk (0x1U << CAN_F20DATA0_FD14_Pos) /*!< 0x00004000 */
# define CAN_F20DATA0_FD14 CAN_F20DATA0_FD14_Msk /*!< Filter bit 14 */
# define CAN_F20DATA0_FD15_Pos (15U)
# define CAN_F20DATA0_FD15_Msk (0x1U << CAN_F20DATA0_FD15_Pos) /*!< 0x00008000 */
# define CAN_F20DATA0_FD15 CAN_F20DATA0_FD15_Msk /*!< Filter bit 15 */
# define CAN_F20DATA0_FD16_Pos (16U)
# define CAN_F20DATA0_FD16_Msk (0x1U << CAN_F20DATA0_FD16_Pos) /*!< 0x00010000 */
# define CAN_F20DATA0_FD16 CAN_F20DATA0_FD16_Msk /*!< Filter bit 16 */
# define CAN_F20DATA0_FD17_Pos (17U)
# define CAN_F20DATA0_FD17_Msk (0x1U << CAN_F20DATA0_FD17_Pos) /*!< 0x00020000 */
# define CAN_F20DATA0_FD17 CAN_F20DATA0_FD17_Msk /*!< Filter bit 17 */
# define CAN_F20DATA0_FD18_Pos (18U)
# define CAN_F20DATA0_FD18_Msk (0x1U << CAN_F20DATA0_FD18_Pos) /*!< 0x00040000 */
# define CAN_F20DATA0_FD18 CAN_F20DATA0_FD18_Msk /*!< Filter bit 18 */
# define CAN_F20DATA0_FD19_Pos (19U)
# define CAN_F20DATA0_FD19_Msk (0x1U << CAN_F20DATA0_FD19_Pos) /*!< 0x00080000 */
# define CAN_F20DATA0_FD19 CAN_F20DATA0_FD19_Msk /*!< Filter bit 19 */
# define CAN_F20DATA0_FD20_Pos (20U)
# define CAN_F20DATA0_FD20_Msk (0x1U << CAN_F20DATA0_FD20_Pos) /*!< 0x00100000 */
# define CAN_F20DATA0_FD20 CAN_F20DATA0_FD20_Msk /*!< Filter bit 20 */
# define CAN_F20DATA0_FD21_Pos (21U)
# define CAN_F20DATA0_FD21_Msk (0x1U << CAN_F20DATA0_FD21_Pos) /*!< 0x00200000 */
# define CAN_F20DATA0_FD21 CAN_F20DATA0_FD21_Msk /*!< Filter bit 21 */
# define CAN_F20DATA0_FD22_Pos (22U)
# define CAN_F20DATA0_FD22_Msk (0x1U << CAN_F20DATA0_FD22_Pos) /*!< 0x00400000 */
# define CAN_F20DATA0_FD22 CAN_F20DATA0_FD22_Msk /*!< Filter bit 22 */
# define CAN_F20DATA0_FD23_Pos (23U)
# define CAN_F20DATA0_FD23_Msk (0x1U << CAN_F20DATA0_FD23_Pos) /*!< 0x00800000 */
# define CAN_F20DATA0_FD23 CAN_F20DATA0_FD23_Msk /*!< Filter bit 23 */
# define CAN_F20DATA0_FD24_Pos (24U)
# define CAN_F20DATA0_FD24_Msk (0x1U << CAN_F20DATA0_FD24_Pos) /*!< 0x01000000 */
# define CAN_F20DATA0_FD24 CAN_F20DATA0_FD24_Msk /*!< Filter bit 24 */
# define CAN_F20DATA0_FD25_Pos (25U)
# define CAN_F20DATA0_FD25_Msk (0x1U << CAN_F20DATA0_FD25_Pos) /*!< 0x02000000 */
# define CAN_F20DATA0_FD25 CAN_F20DATA0_FD25_Msk /*!< Filter bit 25 */
# define CAN_F20DATA0_FD26_Pos (26U)
# define CAN_F20DATA0_FD26_Msk (0x1U << CAN_F20DATA0_FD26_Pos) /*!< 0x04000000 */
# define CAN_F20DATA0_FD26 CAN_F20DATA0_FD26_Msk /*!< Filter bit 26 */
# define CAN_F20DATA0_FD27_Pos (27U)
# define CAN_F20DATA0_FD27_Msk (0x1U << CAN_F20DATA0_FD27_Pos) /*!< 0x08000000 */
# define CAN_F20DATA0_FD27 CAN_F20DATA0_FD27_Msk /*!< Filter bit 27 */
# define CAN_F20DATA0_FD28_Pos (28U)
# define CAN_F20DATA0_FD28_Msk (0x1U << CAN_F20DATA0_FD28_Pos) /*!< 0x10000000 */
# define CAN_F20DATA0_FD28 CAN_F20DATA0_FD28_Msk /*!< Filter bit 28 */
# define CAN_F20DATA0_FD29_Pos (29U)
# define CAN_F20DATA0_FD29_Msk (0x1U << CAN_F20DATA0_FD29_Pos) /*!< 0x20000000 */
# define CAN_F20DATA0_FD29 CAN_F20DATA0_FD29_Msk /*!< Filter bit 29 */
# define CAN_F20DATA0_FD30_Pos (30U)
# define CAN_F20DATA0_FD30_Msk (0x1U << CAN_F20DATA0_FD30_Pos) /*!< 0x40000000 */
# define CAN_F20DATA0_FD30 CAN_F20DATA0_FD30_Msk /*!< Filter bit 30 */
# define CAN_F20DATA0_FD31_Pos (31U)
# define CAN_F20DATA0_FD31_Msk (0x1U << CAN_F20DATA0_FD31_Pos) /*!< 0x80000000 */
# define CAN_F20DATA0_FD31 CAN_F20DATA0_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F21R1 register ******************/
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# define CAN_F21DATA0_FD0_Pos (0U)
# define CAN_F21DATA0_FD0_Msk (0x1U << CAN_F21DATA0_FD0_Pos) /*!< 0x00000001 */
# define CAN_F21DATA0_FD0 CAN_F21DATA0_FD0_Msk /*!< Filter bit 0 */
# define CAN_F21DATA0_FD1_Pos (1U)
# define CAN_F21DATA0_FD1_Msk (0x1U << CAN_F21DATA0_FD1_Pos) /*!< 0x00000002 */
# define CAN_F21DATA0_FD1 CAN_F21DATA0_FD1_Msk /*!< Filter bit 1 */
# define CAN_F21DATA0_FD2_Pos (2U)
# define CAN_F21DATA0_FD2_Msk (0x1U << CAN_F21DATA0_FD2_Pos) /*!< 0x00000004 */
# define CAN_F21DATA0_FD2 CAN_F21DATA0_FD2_Msk /*!< Filter bit 2 */
# define CAN_F21DATA0_FD3_Pos (3U)
# define CAN_F21DATA0_FD3_Msk (0x1U << CAN_F21DATA0_FD3_Pos) /*!< 0x00000008 */
# define CAN_F21DATA0_FD3 CAN_F21DATA0_FD3_Msk /*!< Filter bit 3 */
# define CAN_F21DATA0_FD4_Pos (4U)
# define CAN_F21DATA0_FD4_Msk (0x1U << CAN_F21DATA0_FD4_Pos) /*!< 0x00000010 */
# define CAN_F21DATA0_FD4 CAN_F21DATA0_FD4_Msk /*!< Filter bit 4 */
# define CAN_F21DATA0_FD5_Pos (5U)
# define CAN_F21DATA0_FD5_Msk (0x1U << CAN_F21DATA0_FD5_Pos) /*!< 0x00000020 */
# define CAN_F21DATA0_FD5 CAN_F21DATA0_FD5_Msk /*!< Filter bit 5 */
# define CAN_F21DATA0_FD6_Pos (6U)
# define CAN_F21DATA0_FD6_Msk (0x1U << CAN_F21DATA0_FD6_Pos) /*!< 0x00000040 */
# define CAN_F21DATA0_FD6 CAN_F21DATA0_FD6_Msk /*!< Filter bit 6 */
# define CAN_F21DATA0_FD7_Pos (7U)
# define CAN_F21DATA0_FD7_Msk (0x1U << CAN_F21DATA0_FD7_Pos) /*!< 0x00000080 */
# define CAN_F21DATA0_FD7 CAN_F21DATA0_FD7_Msk /*!< Filter bit 7 */
# define CAN_F21DATA0_FD8_Pos (8U)
# define CAN_F21DATA0_FD8_Msk (0x1U << CAN_F21DATA0_FD8_Pos) /*!< 0x00000100 */
# define CAN_F21DATA0_FD8 CAN_F21DATA0_FD8_Msk /*!< Filter bit 8 */
# define CAN_F21DATA0_FD9_Pos (9U)
# define CAN_F21DATA0_FD9_Msk (0x1U << CAN_F21DATA0_FD9_Pos) /*!< 0x00000200 */
# define CAN_F21DATA0_FD9 CAN_F21DATA0_FD9_Msk /*!< Filter bit 9 */
# define CAN_F21DATA0_FD10_Pos (10U)
# define CAN_F21DATA0_FD10_Msk (0x1U << CAN_F21DATA0_FD10_Pos) /*!< 0x00000400 */
# define CAN_F21DATA0_FD10 CAN_F21DATA0_FD10_Msk /*!< Filter bit 10 */
# define CAN_F21DATA0_FD11_Pos (11U)
# define CAN_F21DATA0_FD11_Msk (0x1U << CAN_F21DATA0_FD11_Pos) /*!< 0x00000800 */
# define CAN_F21DATA0_FD11 CAN_F21DATA0_FD11_Msk /*!< Filter bit 11 */
# define CAN_F21DATA0_FD12_Pos (12U)
# define CAN_F21DATA0_FD12_Msk (0x1U << CAN_F21DATA0_FD12_Pos) /*!< 0x00001000 */
# define CAN_F21DATA0_FD12 CAN_F21DATA0_FD12_Msk /*!< Filter bit 12 */
# define CAN_F21DATA0_FD13_Pos (13U)
# define CAN_F21DATA0_FD13_Msk (0x1U << CAN_F21DATA0_FD13_Pos) /*!< 0x00002000 */
# define CAN_F21DATA0_FD13 CAN_F21DATA0_FD13_Msk /*!< Filter bit 13 */
# define CAN_F21DATA0_FD14_Pos (14U)
# define CAN_F21DATA0_FD14_Msk (0x1U << CAN_F21DATA0_FD14_Pos) /*!< 0x00004000 */
# define CAN_F21DATA0_FD14 CAN_F21DATA0_FD14_Msk /*!< Filter bit 14 */
# define CAN_F21DATA0_FD15_Pos (15U)
# define CAN_F21DATA0_FD15_Msk (0x1U << CAN_F21DATA0_FD15_Pos) /*!< 0x00008000 */
# define CAN_F21DATA0_FD15 CAN_F21DATA0_FD15_Msk /*!< Filter bit 15 */
# define CAN_F21DATA0_FD16_Pos (16U)
# define CAN_F21DATA0_FD16_Msk (0x1U << CAN_F21DATA0_FD16_Pos) /*!< 0x00010000 */
# define CAN_F21DATA0_FD16 CAN_F21DATA0_FD16_Msk /*!< Filter bit 16 */
# define CAN_F21DATA0_FD17_Pos (17U)
# define CAN_F21DATA0_FD17_Msk (0x1U << CAN_F21DATA0_FD17_Pos) /*!< 0x00020000 */
# define CAN_F21DATA0_FD17 CAN_F21DATA0_FD17_Msk /*!< Filter bit 17 */
# define CAN_F21DATA0_FD18_Pos (18U)
# define CAN_F21DATA0_FD18_Msk (0x1U << CAN_F21DATA0_FD18_Pos) /*!< 0x00040000 */
# define CAN_F21DATA0_FD18 CAN_F21DATA0_FD18_Msk /*!< Filter bit 18 */
# define CAN_F21DATA0_FD19_Pos (19U)
# define CAN_F21DATA0_FD19_Msk (0x1U << CAN_F21DATA0_FD19_Pos) /*!< 0x00080000 */
# define CAN_F21DATA0_FD19 CAN_F21DATA0_FD19_Msk /*!< Filter bit 19 */
# define CAN_F21DATA0_FD20_Pos (20U)
# define CAN_F21DATA0_FD20_Msk (0x1U << CAN_F21DATA0_FD20_Pos) /*!< 0x00100000 */
# define CAN_F21DATA0_FD20 CAN_F21DATA0_FD20_Msk /*!< Filter bit 20 */
# define CAN_F21DATA0_FD21_Pos (21U)
# define CAN_F21DATA0_FD21_Msk (0x1U << CAN_F21DATA0_FD21_Pos) /*!< 0x00200000 */
# define CAN_F21DATA0_FD21 CAN_F21DATA0_FD21_Msk /*!< Filter bit 21 */
# define CAN_F21DATA0_FD22_Pos (22U)
# define CAN_F21DATA0_FD22_Msk (0x1U << CAN_F21DATA0_FD22_Pos) /*!< 0x00400000 */
# define CAN_F21DATA0_FD22 CAN_F21DATA0_FD22_Msk /*!< Filter bit 22 */
# define CAN_F21DATA0_FD23_Pos (23U)
# define CAN_F21DATA0_FD23_Msk (0x1U << CAN_F21DATA0_FD23_Pos) /*!< 0x00800000 */
# define CAN_F21DATA0_FD23 CAN_F21DATA0_FD23_Msk /*!< Filter bit 23 */
# define CAN_F21DATA0_FD24_Pos (24U)
# define CAN_F21DATA0_FD24_Msk (0x1U << CAN_F21DATA0_FD24_Pos) /*!< 0x01000000 */
# define CAN_F21DATA0_FD24 CAN_F21DATA0_FD24_Msk /*!< Filter bit 24 */
# define CAN_F21DATA0_FD25_Pos (25U)
# define CAN_F21DATA0_FD25_Msk (0x1U << CAN_F21DATA0_FD25_Pos) /*!< 0x02000000 */
# define CAN_F21DATA0_FD25 CAN_F21DATA0_FD25_Msk /*!< Filter bit 25 */
# define CAN_F21DATA0_FD26_Pos (26U)
# define CAN_F21DATA0_FD26_Msk (0x1U << CAN_F21DATA0_FD26_Pos) /*!< 0x04000000 */
# define CAN_F21DATA0_FD26 CAN_F21DATA0_FD26_Msk /*!< Filter bit 26 */
# define CAN_F21DATA0_FD27_Pos (27U)
# define CAN_F21DATA0_FD27_Msk (0x1U << CAN_F21DATA0_FD27_Pos) /*!< 0x08000000 */
# define CAN_F21DATA0_FD27 CAN_F21DATA0_FD27_Msk /*!< Filter bit 27 */
# define CAN_F21DATA0_FD28_Pos (28U)
# define CAN_F21DATA0_FD28_Msk (0x1U << CAN_F21DATA0_FD28_Pos) /*!< 0x10000000 */
# define CAN_F21DATA0_FD28 CAN_F21DATA0_FD28_Msk /*!< Filter bit 28 */
# define CAN_F21DATA0_FD29_Pos (29U)
# define CAN_F21DATA0_FD29_Msk (0x1U << CAN_F21DATA0_FD29_Pos) /*!< 0x20000000 */
# define CAN_F21DATA0_FD29 CAN_F21DATA0_FD29_Msk /*!< Filter bit 29 */
# define CAN_F21DATA0_FD30_Pos (30U)
# define CAN_F21DATA0_FD30_Msk (0x1U << CAN_F21DATA0_FD30_Pos) /*!< 0x40000000 */
# define CAN_F21DATA0_FD30 CAN_F21DATA0_FD30_Msk /*!< Filter bit 30 */
# define CAN_F21DATA0_FD31_Pos (31U)
# define CAN_F21DATA0_FD31_Msk (0x1U << CAN_F21DATA0_FD31_Pos) /*!< 0x80000000 */
# define CAN_F21DATA0_FD31 CAN_F21DATA0_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F22R1 register ******************/
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# define CAN_F22DATA0_FD0_Pos (0U)
# define CAN_F22DATA0_FD0_Msk (0x1U << CAN_F22DATA0_FD0_Pos) /*!< 0x00000001 */
# define CAN_F22DATA0_FD0 CAN_F22DATA0_FD0_Msk /*!< Filter bit 0 */
# define CAN_F22DATA0_FD1_Pos (1U)
# define CAN_F22DATA0_FD1_Msk (0x1U << CAN_F22DATA0_FD1_Pos) /*!< 0x00000002 */
# define CAN_F22DATA0_FD1 CAN_F22DATA0_FD1_Msk /*!< Filter bit 1 */
# define CAN_F22DATA0_FD2_Pos (2U)
# define CAN_F22DATA0_FD2_Msk (0x1U << CAN_F22DATA0_FD2_Pos) /*!< 0x00000004 */
# define CAN_F22DATA0_FD2 CAN_F22DATA0_FD2_Msk /*!< Filter bit 2 */
# define CAN_F22DATA0_FD3_Pos (3U)
# define CAN_F22DATA0_FD3_Msk (0x1U << CAN_F22DATA0_FD3_Pos) /*!< 0x00000008 */
# define CAN_F22DATA0_FD3 CAN_F22DATA0_FD3_Msk /*!< Filter bit 3 */
# define CAN_F22DATA0_FD4_Pos (4U)
# define CAN_F22DATA0_FD4_Msk (0x1U << CAN_F22DATA0_FD4_Pos) /*!< 0x00000010 */
# define CAN_F22DATA0_FD4 CAN_F22DATA0_FD4_Msk /*!< Filter bit 4 */
# define CAN_F22DATA0_FD5_Pos (5U)
# define CAN_F22DATA0_FD5_Msk (0x1U << CAN_F22DATA0_FD5_Pos) /*!< 0x00000020 */
# define CAN_F22DATA0_FD5 CAN_F22DATA0_FD5_Msk /*!< Filter bit 5 */
# define CAN_F22DATA0_FD6_Pos (6U)
# define CAN_F22DATA0_FD6_Msk (0x1U << CAN_F22DATA0_FD6_Pos) /*!< 0x00000040 */
# define CAN_F22DATA0_FD6 CAN_F22DATA0_FD6_Msk /*!< Filter bit 6 */
# define CAN_F22DATA0_FD7_Pos (7U)
# define CAN_F22DATA0_FD7_Msk (0x1U << CAN_F22DATA0_FD7_Pos) /*!< 0x00000080 */
# define CAN_F22DATA0_FD7 CAN_F22DATA0_FD7_Msk /*!< Filter bit 7 */
# define CAN_F22DATA0_FD8_Pos (8U)
# define CAN_F22DATA0_FD8_Msk (0x1U << CAN_F22DATA0_FD8_Pos) /*!< 0x00000100 */
# define CAN_F22DATA0_FD8 CAN_F22DATA0_FD8_Msk /*!< Filter bit 8 */
# define CAN_F22DATA0_FD9_Pos (9U)
# define CAN_F22DATA0_FD9_Msk (0x1U << CAN_F22DATA0_FD9_Pos) /*!< 0x00000200 */
# define CAN_F22DATA0_FD9 CAN_F22DATA0_FD9_Msk /*!< Filter bit 9 */
# define CAN_F22DATA0_FD10_Pos (10U)
# define CAN_F22DATA0_FD10_Msk (0x1U << CAN_F22DATA0_FD10_Pos) /*!< 0x00000400 */
# define CAN_F22DATA0_FD10 CAN_F22DATA0_FD10_Msk /*!< Filter bit 10 */
# define CAN_F22DATA0_FD11_Pos (11U)
# define CAN_F22DATA0_FD11_Msk (0x1U << CAN_F22DATA0_FD11_Pos) /*!< 0x00000800 */
# define CAN_F22DATA0_FD11 CAN_F22DATA0_FD11_Msk /*!< Filter bit 11 */
# define CAN_F22DATA0_FD12_Pos (12U)
# define CAN_F22DATA0_FD12_Msk (0x1U << CAN_F22DATA0_FD12_Pos) /*!< 0x00001000 */
# define CAN_F22DATA0_FD12 CAN_F22DATA0_FD12_Msk /*!< Filter bit 12 */
# define CAN_F22DATA0_FD13_Pos (13U)
# define CAN_F22DATA0_FD13_Msk (0x1U << CAN_F22DATA0_FD13_Pos) /*!< 0x00002000 */
# define CAN_F22DATA0_FD13 CAN_F22DATA0_FD13_Msk /*!< Filter bit 13 */
# define CAN_F22DATA0_FD14_Pos (14U)
# define CAN_F22DATA0_FD14_Msk (0x1U << CAN_F22DATA0_FD14_Pos) /*!< 0x00004000 */
# define CAN_F22DATA0_FD14 CAN_F22DATA0_FD14_Msk /*!< Filter bit 14 */
# define CAN_F22DATA0_FD15_Pos (15U)
# define CAN_F22DATA0_FD15_Msk (0x1U << CAN_F22DATA0_FD15_Pos) /*!< 0x00008000 */
# define CAN_F22DATA0_FD15 CAN_F22DATA0_FD15_Msk /*!< Filter bit 15 */
# define CAN_F22DATA0_FD16_Pos (16U)
# define CAN_F22DATA0_FD16_Msk (0x1U << CAN_F22DATA0_FD16_Pos) /*!< 0x00010000 */
# define CAN_F22DATA0_FD16 CAN_F22DATA0_FD16_Msk /*!< Filter bit 16 */
# define CAN_F22DATA0_FD17_Pos (17U)
# define CAN_F22DATA0_FD17_Msk (0x1U << CAN_F22DATA0_FD17_Pos) /*!< 0x00020000 */
# define CAN_F22DATA0_FD17 CAN_F22DATA0_FD17_Msk /*!< Filter bit 17 */
# define CAN_F22DATA0_FD18_Pos (18U)
# define CAN_F22DATA0_FD18_Msk (0x1U << CAN_F22DATA0_FD18_Pos) /*!< 0x00040000 */
# define CAN_F22DATA0_FD18 CAN_F22DATA0_FD18_Msk /*!< Filter bit 18 */
# define CAN_F22DATA0_FD19_Pos (19U)
# define CAN_F22DATA0_FD19_Msk (0x1U << CAN_F22DATA0_FD19_Pos) /*!< 0x00080000 */
# define CAN_F22DATA0_FD19 CAN_F22DATA0_FD19_Msk /*!< Filter bit 19 */
# define CAN_F22DATA0_FD20_Pos (20U)
# define CAN_F22DATA0_FD20_Msk (0x1U << CAN_F22DATA0_FD20_Pos) /*!< 0x00100000 */
# define CAN_F22DATA0_FD20 CAN_F22DATA0_FD20_Msk /*!< Filter bit 20 */
# define CAN_F22DATA0_FD21_Pos (21U)
# define CAN_F22DATA0_FD21_Msk (0x1U << CAN_F22DATA0_FD21_Pos) /*!< 0x00200000 */
# define CAN_F22DATA0_FD21 CAN_F22DATA0_FD21_Msk /*!< Filter bit 21 */
# define CAN_F22DATA0_FD22_Pos (22U)
# define CAN_F22DATA0_FD22_Msk (0x1U << CAN_F22DATA0_FD22_Pos) /*!< 0x00400000 */
# define CAN_F22DATA0_FD22 CAN_F22DATA0_FD22_Msk /*!< Filter bit 22 */
# define CAN_F22DATA0_FD23_Pos (23U)
# define CAN_F22DATA0_FD23_Msk (0x1U << CAN_F22DATA0_FD23_Pos) /*!< 0x00800000 */
# define CAN_F22DATA0_FD23 CAN_F22DATA0_FD23_Msk /*!< Filter bit 23 */
# define CAN_F22DATA0_FD24_Pos (24U)
# define CAN_F22DATA0_FD24_Msk (0x1U << CAN_F22DATA0_FD24_Pos) /*!< 0x01000000 */
# define CAN_F22DATA0_FD24 CAN_F22DATA0_FD24_Msk /*!< Filter bit 24 */
# define CAN_F22DATA0_FD25_Pos (25U)
# define CAN_F22DATA0_FD25_Msk (0x1U << CAN_F22DATA0_FD25_Pos) /*!< 0x02000000 */
# define CAN_F22DATA0_FD25 CAN_F22DATA0_FD25_Msk /*!< Filter bit 25 */
# define CAN_F22DATA0_FD26_Pos (26U)
# define CAN_F22DATA0_FD26_Msk (0x1U << CAN_F22DATA0_FD26_Pos) /*!< 0x04000000 */
# define CAN_F22DATA0_FD26 CAN_F22DATA0_FD26_Msk /*!< Filter bit 26 */
# define CAN_F22DATA0_FD27_Pos (27U)
# define CAN_F22DATA0_FD27_Msk (0x1U << CAN_F22DATA0_FD27_Pos) /*!< 0x08000000 */
# define CAN_F22DATA0_FD27 CAN_F22DATA0_FD27_Msk /*!< Filter bit 27 */
# define CAN_F22DATA0_FD28_Pos (28U)
# define CAN_F22DATA0_FD28_Msk (0x1U << CAN_F22DATA0_FD28_Pos) /*!< 0x10000000 */
# define CAN_F22DATA0_FD28 CAN_F22DATA0_FD28_Msk /*!< Filter bit 28 */
# define CAN_F22DATA0_FD29_Pos (29U)
# define CAN_F22DATA0_FD29_Msk (0x1U << CAN_F22DATA0_FD29_Pos) /*!< 0x20000000 */
# define CAN_F22DATA0_FD29 CAN_F22DATA0_FD29_Msk /*!< Filter bit 29 */
# define CAN_F22DATA0_FD30_Pos (30U)
# define CAN_F22DATA0_FD30_Msk (0x1U << CAN_F22DATA0_FD30_Pos) /*!< 0x40000000 */
# define CAN_F22DATA0_FD30 CAN_F22DATA0_FD30_Msk /*!< Filter bit 30 */
# define CAN_F22DATA0_FD31_Pos (31U)
# define CAN_F22DATA0_FD31_Msk (0x1U << CAN_F22DATA0_FD31_Pos) /*!< 0x80000000 */
# define CAN_F22DATA0_FD31 CAN_F22DATA0_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F23R1 register ******************/
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# define CAN_F23DATA0_FD0_Pos (0U)
# define CAN_F23DATA0_FD0_Msk (0x1U << CAN_F23DATA0_FD0_Pos) /*!< 0x00000001 */
# define CAN_F23DATA0_FD0 CAN_F23DATA0_FD0_Msk /*!< Filter bit 0 */
# define CAN_F23DATA0_FD1_Pos (1U)
# define CAN_F23DATA0_FD1_Msk (0x1U << CAN_F23DATA0_FD1_Pos) /*!< 0x00000002 */
# define CAN_F23DATA0_FD1 CAN_F23DATA0_FD1_Msk /*!< Filter bit 1 */
# define CAN_F23DATA0_FD2_Pos (2U)
# define CAN_F23DATA0_FD2_Msk (0x1U << CAN_F23DATA0_FD2_Pos) /*!< 0x00000004 */
# define CAN_F23DATA0_FD2 CAN_F23DATA0_FD2_Msk /*!< Filter bit 2 */
# define CAN_F23DATA0_FD3_Pos (3U)
# define CAN_F23DATA0_FD3_Msk (0x1U << CAN_F23DATA0_FD3_Pos) /*!< 0x00000008 */
# define CAN_F23DATA0_FD3 CAN_F23DATA0_FD3_Msk /*!< Filter bit 3 */
# define CAN_F23DATA0_FD4_Pos (4U)
# define CAN_F23DATA0_FD4_Msk (0x1U << CAN_F23DATA0_FD4_Pos) /*!< 0x00000010 */
# define CAN_F23DATA0_FD4 CAN_F23DATA0_FD4_Msk /*!< Filter bit 4 */
# define CAN_F23DATA0_FD5_Pos (5U)
# define CAN_F23DATA0_FD5_Msk (0x1U << CAN_F23DATA0_FD5_Pos) /*!< 0x00000020 */
# define CAN_F23DATA0_FD5 CAN_F23DATA0_FD5_Msk /*!< Filter bit 5 */
# define CAN_F23DATA0_FD6_Pos (6U)
# define CAN_F23DATA0_FD6_Msk (0x1U << CAN_F23DATA0_FD6_Pos) /*!< 0x00000040 */
# define CAN_F23DATA0_FD6 CAN_F23DATA0_FD6_Msk /*!< Filter bit 6 */
# define CAN_F23DATA0_FD7_Pos (7U)
# define CAN_F23DATA0_FD7_Msk (0x1U << CAN_F23DATA0_FD7_Pos) /*!< 0x00000080 */
# define CAN_F23DATA0_FD7 CAN_F23DATA0_FD7_Msk /*!< Filter bit 7 */
# define CAN_F23DATA0_FD8_Pos (8U)
# define CAN_F23DATA0_FD8_Msk (0x1U << CAN_F23DATA0_FD8_Pos) /*!< 0x00000100 */
# define CAN_F23DATA0_FD8 CAN_F23DATA0_FD8_Msk /*!< Filter bit 8 */
# define CAN_F23DATA0_FD9_Pos (9U)
# define CAN_F23DATA0_FD9_Msk (0x1U << CAN_F23DATA0_FD9_Pos) /*!< 0x00000200 */
# define CAN_F23DATA0_FD9 CAN_F23DATA0_FD9_Msk /*!< Filter bit 9 */
# define CAN_F23DATA0_FD10_Pos (10U)
# define CAN_F23DATA0_FD10_Msk (0x1U << CAN_F23DATA0_FD10_Pos) /*!< 0x00000400 */
# define CAN_F23DATA0_FD10 CAN_F23DATA0_FD10_Msk /*!< Filter bit 10 */
# define CAN_F23DATA0_FD11_Pos (11U)
# define CAN_F23DATA0_FD11_Msk (0x1U << CAN_F23DATA0_FD11_Pos) /*!< 0x00000800 */
# define CAN_F23DATA0_FD11 CAN_F23DATA0_FD11_Msk /*!< Filter bit 11 */
# define CAN_F23DATA0_FD12_Pos (12U)
# define CAN_F23DATA0_FD12_Msk (0x1U << CAN_F23DATA0_FD12_Pos) /*!< 0x00001000 */
# define CAN_F23DATA0_FD12 CAN_F23DATA0_FD12_Msk /*!< Filter bit 12 */
# define CAN_F23DATA0_FD13_Pos (13U)
# define CAN_F23DATA0_FD13_Msk (0x1U << CAN_F23DATA0_FD13_Pos) /*!< 0x00002000 */
# define CAN_F23DATA0_FD13 CAN_F23DATA0_FD13_Msk /*!< Filter bit 13 */
# define CAN_F23DATA0_FD14_Pos (14U)
# define CAN_F23DATA0_FD14_Msk (0x1U << CAN_F23DATA0_FD14_Pos) /*!< 0x00004000 */
# define CAN_F23DATA0_FD14 CAN_F23DATA0_FD14_Msk /*!< Filter bit 14 */
# define CAN_F23DATA0_FD15_Pos (15U)
# define CAN_F23DATA0_FD15_Msk (0x1U << CAN_F23DATA0_FD15_Pos) /*!< 0x00008000 */
# define CAN_F23DATA0_FD15 CAN_F23DATA0_FD15_Msk /*!< Filter bit 15 */
# define CAN_F23DATA0_FD16_Pos (16U)
# define CAN_F23DATA0_FD16_Msk (0x1U << CAN_F23DATA0_FD16_Pos) /*!< 0x00010000 */
# define CAN_F23DATA0_FD16 CAN_F23DATA0_FD16_Msk /*!< Filter bit 16 */
# define CAN_F23DATA0_FD17_Pos (17U)
# define CAN_F23DATA0_FD17_Msk (0x1U << CAN_F23DATA0_FD17_Pos) /*!< 0x00020000 */
# define CAN_F23DATA0_FD17 CAN_F23DATA0_FD17_Msk /*!< Filter bit 17 */
# define CAN_F23DATA0_FD18_Pos (18U)
# define CAN_F23DATA0_FD18_Msk (0x1U << CAN_F23DATA0_FD18_Pos) /*!< 0x00040000 */
# define CAN_F23DATA0_FD18 CAN_F23DATA0_FD18_Msk /*!< Filter bit 18 */
# define CAN_F23DATA0_FD19_Pos (19U)
# define CAN_F23DATA0_FD19_Msk (0x1U << CAN_F23DATA0_FD19_Pos) /*!< 0x00080000 */
# define CAN_F23DATA0_FD19 CAN_F23DATA0_FD19_Msk /*!< Filter bit 19 */
# define CAN_F23DATA0_FD20_Pos (20U)
# define CAN_F23DATA0_FD20_Msk (0x1U << CAN_F23DATA0_FD20_Pos) /*!< 0x00100000 */
# define CAN_F23DATA0_FD20 CAN_F23DATA0_FD20_Msk /*!< Filter bit 20 */
# define CAN_F23DATA0_FD21_Pos (21U)
# define CAN_F23DATA0_FD21_Msk (0x1U << CAN_F23DATA0_FD21_Pos) /*!< 0x00200000 */
# define CAN_F23DATA0_FD21 CAN_F23DATA0_FD21_Msk /*!< Filter bit 21 */
# define CAN_F23DATA0_FD22_Pos (22U)
# define CAN_F23DATA0_FD22_Msk (0x1U << CAN_F23DATA0_FD22_Pos) /*!< 0x00400000 */
# define CAN_F23DATA0_FD22 CAN_F23DATA0_FD22_Msk /*!< Filter bit 22 */
# define CAN_F23DATA0_FD23_Pos (23U)
# define CAN_F23DATA0_FD23_Msk (0x1U << CAN_F23DATA0_FD23_Pos) /*!< 0x00800000 */
# define CAN_F23DATA0_FD23 CAN_F23DATA0_FD23_Msk /*!< Filter bit 23 */
# define CAN_F23DATA0_FD24_Pos (24U)
# define CAN_F23DATA0_FD24_Msk (0x1U << CAN_F23DATA0_FD24_Pos) /*!< 0x01000000 */
# define CAN_F23DATA0_FD24 CAN_F23DATA0_FD24_Msk /*!< Filter bit 24 */
# define CAN_F23DATA0_FD25_Pos (25U)
# define CAN_F23DATA0_FD25_Msk (0x1U << CAN_F23DATA0_FD25_Pos) /*!< 0x02000000 */
# define CAN_F23DATA0_FD25 CAN_F23DATA0_FD25_Msk /*!< Filter bit 25 */
# define CAN_F23DATA0_FD26_Pos (26U)
# define CAN_F23DATA0_FD26_Msk (0x1U << CAN_F23DATA0_FD26_Pos) /*!< 0x04000000 */
# define CAN_F23DATA0_FD26 CAN_F23DATA0_FD26_Msk /*!< Filter bit 26 */
# define CAN_F23DATA0_FD27_Pos (27U)
# define CAN_F23DATA0_FD27_Msk (0x1U << CAN_F23DATA0_FD27_Pos) /*!< 0x08000000 */
# define CAN_F23DATA0_FD27 CAN_F23DATA0_FD27_Msk /*!< Filter bit 27 */
# define CAN_F23DATA0_FD28_Pos (28U)
# define CAN_F23DATA0_FD28_Msk (0x1U << CAN_F23DATA0_FD28_Pos) /*!< 0x10000000 */
# define CAN_F23DATA0_FD28 CAN_F23DATA0_FD28_Msk /*!< Filter bit 28 */
# define CAN_F23DATA0_FD29_Pos (29U)
# define CAN_F23DATA0_FD29_Msk (0x1U << CAN_F23DATA0_FD29_Pos) /*!< 0x20000000 */
# define CAN_F23DATA0_FD29 CAN_F23DATA0_FD29_Msk /*!< Filter bit 29 */
# define CAN_F23DATA0_FD30_Pos (30U)
# define CAN_F23DATA0_FD30_Msk (0x1U << CAN_F23DATA0_FD30_Pos) /*!< 0x40000000 */
# define CAN_F23DATA0_FD30 CAN_F23DATA0_FD30_Msk /*!< Filter bit 30 */
# define CAN_F23DATA0_FD31_Pos (31U)
# define CAN_F23DATA0_FD31_Msk (0x1U << CAN_F23DATA0_FD31_Pos) /*!< 0x80000000 */
# define CAN_F23DATA0_FD31 CAN_F23DATA0_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F24R1 register ******************/
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# define CAN_F24DATA0_FD0_Pos (0U)
# define CAN_F24DATA0_FD0_Msk (0x1U << CAN_F24DATA0_FD0_Pos) /*!< 0x00000001 */
# define CAN_F24DATA0_FD0 CAN_F24DATA0_FD0_Msk /*!< Filter bit 0 */
# define CAN_F24DATA0_FD1_Pos (1U)
# define CAN_F24DATA0_FD1_Msk (0x1U << CAN_F24DATA0_FD1_Pos) /*!< 0x00000002 */
# define CAN_F24DATA0_FD1 CAN_F24DATA0_FD1_Msk /*!< Filter bit 1 */
# define CAN_F24DATA0_FD2_Pos (2U)
# define CAN_F24DATA0_FD2_Msk (0x1U << CAN_F24DATA0_FD2_Pos) /*!< 0x00000004 */
# define CAN_F24DATA0_FD2 CAN_F24DATA0_FD2_Msk /*!< Filter bit 2 */
# define CAN_F24DATA0_FD3_Pos (3U)
# define CAN_F24DATA0_FD3_Msk (0x1U << CAN_F24DATA0_FD3_Pos) /*!< 0x00000008 */
# define CAN_F24DATA0_FD3 CAN_F24DATA0_FD3_Msk /*!< Filter bit 3 */
# define CAN_F24DATA0_FD4_Pos (4U)
# define CAN_F24DATA0_FD4_Msk (0x1U << CAN_F24DATA0_FD4_Pos) /*!< 0x00000010 */
# define CAN_F24DATA0_FD4 CAN_F24DATA0_FD4_Msk /*!< Filter bit 4 */
# define CAN_F24DATA0_FD5_Pos (5U)
# define CAN_F24DATA0_FD5_Msk (0x1U << CAN_F24DATA0_FD5_Pos) /*!< 0x00000020 */
# define CAN_F24DATA0_FD5 CAN_F24DATA0_FD5_Msk /*!< Filter bit 5 */
# define CAN_F24DATA0_FD6_Pos (6U)
# define CAN_F24DATA0_FD6_Msk (0x1U << CAN_F24DATA0_FD6_Pos) /*!< 0x00000040 */
# define CAN_F24DATA0_FD6 CAN_F24DATA0_FD6_Msk /*!< Filter bit 6 */
# define CAN_F24DATA0_FD7_Pos (7U)
# define CAN_F24DATA0_FD7_Msk (0x1U << CAN_F24DATA0_FD7_Pos) /*!< 0x00000080 */
# define CAN_F24DATA0_FD7 CAN_F24DATA0_FD7_Msk /*!< Filter bit 7 */
# define CAN_F24DATA0_FD8_Pos (8U)
# define CAN_F24DATA0_FD8_Msk (0x1U << CAN_F24DATA0_FD8_Pos) /*!< 0x00000100 */
# define CAN_F24DATA0_FD8 CAN_F24DATA0_FD8_Msk /*!< Filter bit 8 */
# define CAN_F24DATA0_FD9_Pos (9U)
# define CAN_F24DATA0_FD9_Msk (0x1U << CAN_F24DATA0_FD9_Pos) /*!< 0x00000200 */
# define CAN_F24DATA0_FD9 CAN_F24DATA0_FD9_Msk /*!< Filter bit 9 */
# define CAN_F24DATA0_FD10_Pos (10U)
# define CAN_F24DATA0_FD10_Msk (0x1U << CAN_F24DATA0_FD10_Pos) /*!< 0x00000400 */
# define CAN_F24DATA0_FD10 CAN_F24DATA0_FD10_Msk /*!< Filter bit 10 */
# define CAN_F24DATA0_FD11_Pos (11U)
# define CAN_F24DATA0_FD11_Msk (0x1U << CAN_F24DATA0_FD11_Pos) /*!< 0x00000800 */
# define CAN_F24DATA0_FD11 CAN_F24DATA0_FD11_Msk /*!< Filter bit 11 */
# define CAN_F24DATA0_FD12_Pos (12U)
# define CAN_F24DATA0_FD12_Msk (0x1U << CAN_F24DATA0_FD12_Pos) /*!< 0x00001000 */
# define CAN_F24DATA0_FD12 CAN_F24DATA0_FD12_Msk /*!< Filter bit 12 */
# define CAN_F24DATA0_FD13_Pos (13U)
# define CAN_F24DATA0_FD13_Msk (0x1U << CAN_F24DATA0_FD13_Pos) /*!< 0x00002000 */
# define CAN_F24DATA0_FD13 CAN_F24DATA0_FD13_Msk /*!< Filter bit 13 */
# define CAN_F24DATA0_FD14_Pos (14U)
# define CAN_F24DATA0_FD14_Msk (0x1U << CAN_F24DATA0_FD14_Pos) /*!< 0x00004000 */
# define CAN_F24DATA0_FD14 CAN_F24DATA0_FD14_Msk /*!< Filter bit 14 */
# define CAN_F24DATA0_FD15_Pos (15U)
# define CAN_F24DATA0_FD15_Msk (0x1U << CAN_F24DATA0_FD15_Pos) /*!< 0x00008000 */
# define CAN_F24DATA0_FD15 CAN_F24DATA0_FD15_Msk /*!< Filter bit 15 */
# define CAN_F24DATA0_FD16_Pos (16U)
# define CAN_F24DATA0_FD16_Msk (0x1U << CAN_F24DATA0_FD16_Pos) /*!< 0x00010000 */
# define CAN_F24DATA0_FD16 CAN_F24DATA0_FD16_Msk /*!< Filter bit 16 */
# define CAN_F24DATA0_FD17_Pos (17U)
# define CAN_F24DATA0_FD17_Msk (0x1U << CAN_F24DATA0_FD17_Pos) /*!< 0x00020000 */
# define CAN_F24DATA0_FD17 CAN_F24DATA0_FD17_Msk /*!< Filter bit 17 */
# define CAN_F24DATA0_FD18_Pos (18U)
# define CAN_F24DATA0_FD18_Msk (0x1U << CAN_F24DATA0_FD18_Pos) /*!< 0x00040000 */
# define CAN_F24DATA0_FD18 CAN_F24DATA0_FD18_Msk /*!< Filter bit 18 */
# define CAN_F24DATA0_FD19_Pos (19U)
# define CAN_F24DATA0_FD19_Msk (0x1U << CAN_F24DATA0_FD19_Pos) /*!< 0x00080000 */
# define CAN_F24DATA0_FD19 CAN_F24DATA0_FD19_Msk /*!< Filter bit 19 */
# define CAN_F24DATA0_FD20_Pos (20U)
# define CAN_F24DATA0_FD20_Msk (0x1U << CAN_F24DATA0_FD20_Pos) /*!< 0x00100000 */
# define CAN_F24DATA0_FD20 CAN_F24DATA0_FD20_Msk /*!< Filter bit 20 */
# define CAN_F24DATA0_FD21_Pos (21U)
# define CAN_F24DATA0_FD21_Msk (0x1U << CAN_F24DATA0_FD21_Pos) /*!< 0x00200000 */
# define CAN_F24DATA0_FD21 CAN_F24DATA0_FD21_Msk /*!< Filter bit 21 */
# define CAN_F24DATA0_FD22_Pos (22U)
# define CAN_F24DATA0_FD22_Msk (0x1U << CAN_F24DATA0_FD22_Pos) /*!< 0x00400000 */
# define CAN_F24DATA0_FD22 CAN_F24DATA0_FD22_Msk /*!< Filter bit 22 */
# define CAN_F24DATA0_FD23_Pos (23U)
# define CAN_F24DATA0_FD23_Msk (0x1U << CAN_F24DATA0_FD23_Pos) /*!< 0x00800000 */
# define CAN_F24DATA0_FD23 CAN_F24DATA0_FD23_Msk /*!< Filter bit 23 */
# define CAN_F24DATA0_FD24_Pos (24U)
# define CAN_F24DATA0_FD24_Msk (0x1U << CAN_F24DATA0_FD24_Pos) /*!< 0x01000000 */
# define CAN_F24DATA0_FD24 CAN_F24DATA0_FD24_Msk /*!< Filter bit 24 */
# define CAN_F24DATA0_FD25_Pos (25U)
# define CAN_F24DATA0_FD25_Msk (0x1U << CAN_F24DATA0_FD25_Pos) /*!< 0x02000000 */
# define CAN_F24DATA0_FD25 CAN_F24DATA0_FD25_Msk /*!< Filter bit 25 */
# define CAN_F24DATA0_FD26_Pos (26U)
# define CAN_F24DATA0_FD26_Msk (0x1U << CAN_F24DATA0_FD26_Pos) /*!< 0x04000000 */
# define CAN_F24DATA0_FD26 CAN_F24DATA0_FD26_Msk /*!< Filter bit 26 */
# define CAN_F24DATA0_FD27_Pos (27U)
# define CAN_F24DATA0_FD27_Msk (0x1U << CAN_F24DATA0_FD27_Pos) /*!< 0x08000000 */
# define CAN_F24DATA0_FD27 CAN_F24DATA0_FD27_Msk /*!< Filter bit 27 */
# define CAN_F24DATA0_FD28_Pos (28U)
# define CAN_F24DATA0_FD28_Msk (0x1U << CAN_F24DATA0_FD28_Pos) /*!< 0x10000000 */
# define CAN_F24DATA0_FD28 CAN_F24DATA0_FD28_Msk /*!< Filter bit 28 */
# define CAN_F24DATA0_FD29_Pos (29U)
# define CAN_F24DATA0_FD29_Msk (0x1U << CAN_F24DATA0_FD29_Pos) /*!< 0x20000000 */
# define CAN_F24DATA0_FD29 CAN_F24DATA0_FD29_Msk /*!< Filter bit 29 */
# define CAN_F24DATA0_FD30_Pos (30U)
# define CAN_F24DATA0_FD30_Msk (0x1U << CAN_F24DATA0_FD30_Pos) /*!< 0x40000000 */
# define CAN_F24DATA0_FD30 CAN_F24DATA0_FD30_Msk /*!< Filter bit 30 */
# define CAN_F24DATA0_FD31_Pos (31U)
# define CAN_F24DATA0_FD31_Msk (0x1U << CAN_F24DATA0_FD31_Pos) /*!< 0x80000000 */
# define CAN_F24DATA0_FD31 CAN_F24DATA0_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F25R1 register ******************/
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# define CAN_F25DATA0_FD0_Pos (0U)
# define CAN_F25DATA0_FD0_Msk (0x1U << CAN_F25DATA0_FD0_Pos) /*!< 0x00000001 */
# define CAN_F25DATA0_FD0 CAN_F25DATA0_FD0_Msk /*!< Filter bit 0 */
# define CAN_F25DATA0_FD1_Pos (1U)
# define CAN_F25DATA0_FD1_Msk (0x1U << CAN_F25DATA0_FD1_Pos) /*!< 0x00000002 */
# define CAN_F25DATA0_FD1 CAN_F25DATA0_FD1_Msk /*!< Filter bit 1 */
# define CAN_F25DATA0_FD2_Pos (2U)
# define CAN_F25DATA0_FD2_Msk (0x1U << CAN_F25DATA0_FD2_Pos) /*!< 0x00000004 */
# define CAN_F25DATA0_FD2 CAN_F25DATA0_FD2_Msk /*!< Filter bit 2 */
# define CAN_F25DATA0_FD3_Pos (3U)
# define CAN_F25DATA0_FD3_Msk (0x1U << CAN_F25DATA0_FD3_Pos) /*!< 0x00000008 */
# define CAN_F25DATA0_FD3 CAN_F25DATA0_FD3_Msk /*!< Filter bit 3 */
# define CAN_F25DATA0_FD4_Pos (4U)
# define CAN_F25DATA0_FD4_Msk (0x1U << CAN_F25DATA0_FD4_Pos) /*!< 0x00000010 */
# define CAN_F25DATA0_FD4 CAN_F25DATA0_FD4_Msk /*!< Filter bit 4 */
# define CAN_F25DATA0_FD5_Pos (5U)
# define CAN_F25DATA0_FD5_Msk (0x1U << CAN_F25DATA0_FD5_Pos) /*!< 0x00000020 */
# define CAN_F25DATA0_FD5 CAN_F25DATA0_FD5_Msk /*!< Filter bit 5 */
# define CAN_F25DATA0_FD6_Pos (6U)
# define CAN_F25DATA0_FD6_Msk (0x1U << CAN_F25DATA0_FD6_Pos) /*!< 0x00000040 */
# define CAN_F25DATA0_FD6 CAN_F25DATA0_FD6_Msk /*!< Filter bit 6 */
# define CAN_F25DATA0_FD7_Pos (7U)
# define CAN_F25DATA0_FD7_Msk (0x1U << CAN_F25DATA0_FD7_Pos) /*!< 0x00000080 */
# define CAN_F25DATA0_FD7 CAN_F25DATA0_FD7_Msk /*!< Filter bit 7 */
# define CAN_F25DATA0_FD8_Pos (8U)
# define CAN_F25DATA0_FD8_Msk (0x1U << CAN_F25DATA0_FD8_Pos) /*!< 0x00000100 */
# define CAN_F25DATA0_FD8 CAN_F25DATA0_FD8_Msk /*!< Filter bit 8 */
# define CAN_F25DATA0_FD9_Pos (9U)
# define CAN_F25DATA0_FD9_Msk (0x1U << CAN_F25DATA0_FD9_Pos) /*!< 0x00000200 */
# define CAN_F25DATA0_FD9 CAN_F25DATA0_FD9_Msk /*!< Filter bit 9 */
# define CAN_F25DATA0_FD10_Pos (10U)
# define CAN_F25DATA0_FD10_Msk (0x1U << CAN_F25DATA0_FD10_Pos) /*!< 0x00000400 */
# define CAN_F25DATA0_FD10 CAN_F25DATA0_FD10_Msk /*!< Filter bit 10 */
# define CAN_F25DATA0_FD11_Pos (11U)
# define CAN_F25DATA0_FD11_Msk (0x1U << CAN_F25DATA0_FD11_Pos) /*!< 0x00000800 */
# define CAN_F25DATA0_FD11 CAN_F25DATA0_FD11_Msk /*!< Filter bit 11 */
# define CAN_F25DATA0_FD12_Pos (12U)
# define CAN_F25DATA0_FD12_Msk (0x1U << CAN_F25DATA0_FD12_Pos) /*!< 0x00001000 */
# define CAN_F25DATA0_FD12 CAN_F25DATA0_FD12_Msk /*!< Filter bit 12 */
# define CAN_F25DATA0_FD13_Pos (13U)
# define CAN_F25DATA0_FD13_Msk (0x1U << CAN_F25DATA0_FD13_Pos) /*!< 0x00002000 */
# define CAN_F25DATA0_FD13 CAN_F25DATA0_FD13_Msk /*!< Filter bit 13 */
# define CAN_F25DATA0_FD14_Pos (14U)
# define CAN_F25DATA0_FD14_Msk (0x1U << CAN_F25DATA0_FD14_Pos) /*!< 0x00004000 */
# define CAN_F25DATA0_FD14 CAN_F25DATA0_FD14_Msk /*!< Filter bit 14 */
# define CAN_F25DATA0_FD15_Pos (15U)
# define CAN_F25DATA0_FD15_Msk (0x1U << CAN_F25DATA0_FD15_Pos) /*!< 0x00008000 */
# define CAN_F25DATA0_FD15 CAN_F25DATA0_FD15_Msk /*!< Filter bit 15 */
# define CAN_F25DATA0_FD16_Pos (16U)
# define CAN_F25DATA0_FD16_Msk (0x1U << CAN_F25DATA0_FD16_Pos) /*!< 0x00010000 */
# define CAN_F25DATA0_FD16 CAN_F25DATA0_FD16_Msk /*!< Filter bit 16 */
# define CAN_F25DATA0_FD17_Pos (17U)
# define CAN_F25DATA0_FD17_Msk (0x1U << CAN_F25DATA0_FD17_Pos) /*!< 0x00020000 */
# define CAN_F25DATA0_FD17 CAN_F25DATA0_FD17_Msk /*!< Filter bit 17 */
# define CAN_F25DATA0_FD18_Pos (18U)
# define CAN_F25DATA0_FD18_Msk (0x1U << CAN_F25DATA0_FD18_Pos) /*!< 0x00040000 */
# define CAN_F25DATA0_FD18 CAN_F25DATA0_FD18_Msk /*!< Filter bit 18 */
# define CAN_F25DATA0_FD19_Pos (19U)
# define CAN_F25DATA0_FD19_Msk (0x1U << CAN_F25DATA0_FD19_Pos) /*!< 0x00080000 */
# define CAN_F25DATA0_FD19 CAN_F25DATA0_FD19_Msk /*!< Filter bit 19 */
# define CAN_F25DATA0_FD20_Pos (20U)
# define CAN_F25DATA0_FD20_Msk (0x1U << CAN_F25DATA0_FD20_Pos) /*!< 0x00100000 */
# define CAN_F25DATA0_FD20 CAN_F25DATA0_FD20_Msk /*!< Filter bit 20 */
# define CAN_F25DATA0_FD21_Pos (21U)
# define CAN_F25DATA0_FD21_Msk (0x1U << CAN_F25DATA0_FD21_Pos) /*!< 0x00200000 */
# define CAN_F25DATA0_FD21 CAN_F25DATA0_FD21_Msk /*!< Filter bit 21 */
# define CAN_F25DATA0_FD22_Pos (22U)
# define CAN_F25DATA0_FD22_Msk (0x1U << CAN_F25DATA0_FD22_Pos) /*!< 0x00400000 */
# define CAN_F25DATA0_FD22 CAN_F25DATA0_FD22_Msk /*!< Filter bit 22 */
# define CAN_F25DATA0_FD23_Pos (23U)
# define CAN_F25DATA0_FD23_Msk (0x1U << CAN_F25DATA0_FD23_Pos) /*!< 0x00800000 */
# define CAN_F25DATA0_FD23 CAN_F25DATA0_FD23_Msk /*!< Filter bit 23 */
# define CAN_F25DATA0_FD24_Pos (24U)
# define CAN_F25DATA0_FD24_Msk (0x1U << CAN_F25DATA0_FD24_Pos) /*!< 0x01000000 */
# define CAN_F25DATA0_FD24 CAN_F25DATA0_FD24_Msk /*!< Filter bit 24 */
# define CAN_F25DATA0_FD25_Pos (25U)
# define CAN_F25DATA0_FD25_Msk (0x1U << CAN_F25DATA0_FD25_Pos) /*!< 0x02000000 */
# define CAN_F25DATA0_FD25 CAN_F25DATA0_FD25_Msk /*!< Filter bit 25 */
# define CAN_F25DATA0_FD26_Pos (26U)
# define CAN_F25DATA0_FD26_Msk (0x1U << CAN_F25DATA0_FD26_Pos) /*!< 0x04000000 */
# define CAN_F25DATA0_FD26 CAN_F25DATA0_FD26_Msk /*!< Filter bit 26 */
# define CAN_F25DATA0_FD27_Pos (27U)
# define CAN_F25DATA0_FD27_Msk (0x1U << CAN_F25DATA0_FD27_Pos) /*!< 0x08000000 */
# define CAN_F25DATA0_FD27 CAN_F25DATA0_FD27_Msk /*!< Filter bit 27 */
# define CAN_F25DATA0_FD28_Pos (28U)
# define CAN_F25DATA0_FD28_Msk (0x1U << CAN_F25DATA0_FD28_Pos) /*!< 0x10000000 */
# define CAN_F25DATA0_FD28 CAN_F25DATA0_FD28_Msk /*!< Filter bit 28 */
# define CAN_F25DATA0_FD29_Pos (29U)
# define CAN_F25DATA0_FD29_Msk (0x1U << CAN_F25DATA0_FD29_Pos) /*!< 0x20000000 */
# define CAN_F25DATA0_FD29 CAN_F25DATA0_FD29_Msk /*!< Filter bit 29 */
# define CAN_F25DATA0_FD30_Pos (30U)
# define CAN_F25DATA0_FD30_Msk (0x1U << CAN_F25DATA0_FD30_Pos) /*!< 0x40000000 */
# define CAN_F25DATA0_FD30 CAN_F25DATA0_FD30_Msk /*!< Filter bit 30 */
# define CAN_F25DATA0_FD31_Pos (31U)
# define CAN_F25DATA0_FD31_Msk (0x1U << CAN_F25DATA0_FD31_Pos) /*!< 0x80000000 */
# define CAN_F25DATA0_FD31 CAN_F25DATA0_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F26R1 register ******************/
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# define CAN_F26DATA0_FD0_Pos (0U)
# define CAN_F26DATA0_FD0_Msk (0x1U << CAN_F26DATA0_FD0_Pos) /*!< 0x00000001 */
# define CAN_F26DATA0_FD0 CAN_F26DATA0_FD0_Msk /*!< Filter bit 0 */
# define CAN_F26DATA0_FD1_Pos (1U)
# define CAN_F26DATA0_FD1_Msk (0x1U << CAN_F26DATA0_FD1_Pos) /*!< 0x00000002 */
# define CAN_F26DATA0_FD1 CAN_F26DATA0_FD1_Msk /*!< Filter bit 1 */
# define CAN_F26DATA0_FD2_Pos (2U)
# define CAN_F26DATA0_FD2_Msk (0x1U << CAN_F26DATA0_FD2_Pos) /*!< 0x00000004 */
# define CAN_F26DATA0_FD2 CAN_F26DATA0_FD2_Msk /*!< Filter bit 2 */
# define CAN_F26DATA0_FD3_Pos (3U)
# define CAN_F26DATA0_FD3_Msk (0x1U << CAN_F26DATA0_FD3_Pos) /*!< 0x00000008 */
# define CAN_F26DATA0_FD3 CAN_F26DATA0_FD3_Msk /*!< Filter bit 3 */
# define CAN_F26DATA0_FD4_Pos (4U)
# define CAN_F26DATA0_FD4_Msk (0x1U << CAN_F26DATA0_FD4_Pos) /*!< 0x00000010 */
# define CAN_F26DATA0_FD4 CAN_F26DATA0_FD4_Msk /*!< Filter bit 4 */
# define CAN_F26DATA0_FD5_Pos (5U)
# define CAN_F26DATA0_FD5_Msk (0x1U << CAN_F26DATA0_FD5_Pos) /*!< 0x00000020 */
# define CAN_F26DATA0_FD5 CAN_F26DATA0_FD5_Msk /*!< Filter bit 5 */
# define CAN_F26DATA0_FD6_Pos (6U)
# define CAN_F26DATA0_FD6_Msk (0x1U << CAN_F26DATA0_FD6_Pos) /*!< 0x00000040 */
# define CAN_F26DATA0_FD6 CAN_F26DATA0_FD6_Msk /*!< Filter bit 6 */
# define CAN_F26DATA0_FD7_Pos (7U)
# define CAN_F26DATA0_FD7_Msk (0x1U << CAN_F26DATA0_FD7_Pos) /*!< 0x00000080 */
# define CAN_F26DATA0_FD7 CAN_F26DATA0_FD7_Msk /*!< Filter bit 7 */
# define CAN_F26DATA0_FD8_Pos (8U)
# define CAN_F26DATA0_FD8_Msk (0x1U << CAN_F26DATA0_FD8_Pos) /*!< 0x00000100 */
# define CAN_F26DATA0_FD8 CAN_F26DATA0_FD8_Msk /*!< Filter bit 8 */
# define CAN_F26DATA0_FD9_Pos (9U)
# define CAN_F26DATA0_FD9_Msk (0x1U << CAN_F26DATA0_FD9_Pos) /*!< 0x00000200 */
# define CAN_F26DATA0_FD9 CAN_F26DATA0_FD9_Msk /*!< Filter bit 9 */
# define CAN_F26DATA0_FD10_Pos (10U)
# define CAN_F26DATA0_FD10_Msk (0x1U << CAN_F26DATA0_FD10_Pos) /*!< 0x00000400 */
# define CAN_F26DATA0_FD10 CAN_F26DATA0_FD10_Msk /*!< Filter bit 10 */
# define CAN_F26DATA0_FD11_Pos (11U)
# define CAN_F26DATA0_FD11_Msk (0x1U << CAN_F26DATA0_FD11_Pos) /*!< 0x00000800 */
# define CAN_F26DATA0_FD11 CAN_F26DATA0_FD11_Msk /*!< Filter bit 11 */
# define CAN_F26DATA0_FD12_Pos (12U)
# define CAN_F26DATA0_FD12_Msk (0x1U << CAN_F26DATA0_FD12_Pos) /*!< 0x00001000 */
# define CAN_F26DATA0_FD12 CAN_F26DATA0_FD12_Msk /*!< Filter bit 12 */
# define CAN_F26DATA0_FD13_Pos (13U)
# define CAN_F26DATA0_FD13_Msk (0x1U << CAN_F26DATA0_FD13_Pos) /*!< 0x00002000 */
# define CAN_F26DATA0_FD13 CAN_F26DATA0_FD13_Msk /*!< Filter bit 13 */
# define CAN_F26DATA0_FD14_Pos (14U)
# define CAN_F26DATA0_FD14_Msk (0x1U << CAN_F26DATA0_FD14_Pos) /*!< 0x00004000 */
# define CAN_F26DATA0_FD14 CAN_F26DATA0_FD14_Msk /*!< Filter bit 14 */
# define CAN_F26DATA0_FD15_Pos (15U)
# define CAN_F26DATA0_FD15_Msk (0x1U << CAN_F26DATA0_FD15_Pos) /*!< 0x00008000 */
# define CAN_F26DATA0_FD15 CAN_F26DATA0_FD15_Msk /*!< Filter bit 15 */
# define CAN_F26DATA0_FD16_Pos (16U)
# define CAN_F26DATA0_FD16_Msk (0x1U << CAN_F26DATA0_FD16_Pos) /*!< 0x00010000 */
# define CAN_F26DATA0_FD16 CAN_F26DATA0_FD16_Msk /*!< Filter bit 16 */
# define CAN_F26DATA0_FD17_Pos (17U)
# define CAN_F26DATA0_FD17_Msk (0x1U << CAN_F26DATA0_FD17_Pos) /*!< 0x00020000 */
# define CAN_F26DATA0_FD17 CAN_F26DATA0_FD17_Msk /*!< Filter bit 17 */
# define CAN_F26DATA0_FD18_Pos (18U)
# define CAN_F26DATA0_FD18_Msk (0x1U << CAN_F26DATA0_FD18_Pos) /*!< 0x00040000 */
# define CAN_F26DATA0_FD18 CAN_F26DATA0_FD18_Msk /*!< Filter bit 18 */
# define CAN_F26DATA0_FD19_Pos (19U)
# define CAN_F26DATA0_FD19_Msk (0x1U << CAN_F26DATA0_FD19_Pos) /*!< 0x00080000 */
# define CAN_F26DATA0_FD19 CAN_F26DATA0_FD19_Msk /*!< Filter bit 19 */
# define CAN_F26DATA0_FD20_Pos (20U)
# define CAN_F26DATA0_FD20_Msk (0x1U << CAN_F26DATA0_FD20_Pos) /*!< 0x00100000 */
# define CAN_F26DATA0_FD20 CAN_F26DATA0_FD20_Msk /*!< Filter bit 20 */
# define CAN_F26DATA0_FD21_Pos (21U)
# define CAN_F26DATA0_FD21_Msk (0x1U << CAN_F26DATA0_FD21_Pos) /*!< 0x00200000 */
# define CAN_F26DATA0_FD21 CAN_F26DATA0_FD21_Msk /*!< Filter bit 21 */
# define CAN_F26DATA0_FD22_Pos (22U)
# define CAN_F26DATA0_FD22_Msk (0x1U << CAN_F26DATA0_FD22_Pos) /*!< 0x00400000 */
# define CAN_F26DATA0_FD22 CAN_F26DATA0_FD22_Msk /*!< Filter bit 22 */
# define CAN_F26DATA0_FD23_Pos (23U)
# define CAN_F26DATA0_FD23_Msk (0x1U << CAN_F26DATA0_FD23_Pos) /*!< 0x00800000 */
# define CAN_F26DATA0_FD23 CAN_F26DATA0_FD23_Msk /*!< Filter bit 23 */
# define CAN_F26DATA0_FD24_Pos (24U)
# define CAN_F26DATA0_FD24_Msk (0x1U << CAN_F26DATA0_FD24_Pos) /*!< 0x01000000 */
# define CAN_F26DATA0_FD24 CAN_F26DATA0_FD24_Msk /*!< Filter bit 24 */
# define CAN_F26DATA0_FD25_Pos (25U)
# define CAN_F26DATA0_FD25_Msk (0x1U << CAN_F26DATA0_FD25_Pos) /*!< 0x02000000 */
# define CAN_F26DATA0_FD25 CAN_F26DATA0_FD25_Msk /*!< Filter bit 25 */
# define CAN_F26DATA0_FD26_Pos (26U)
# define CAN_F26DATA0_FD26_Msk (0x1U << CAN_F26DATA0_FD26_Pos) /*!< 0x04000000 */
# define CAN_F26DATA0_FD26 CAN_F26DATA0_FD26_Msk /*!< Filter bit 26 */
# define CAN_F26DATA0_FD27_Pos (27U)
# define CAN_F26DATA0_FD27_Msk (0x1U << CAN_F26DATA0_FD27_Pos) /*!< 0x08000000 */
# define CAN_F26DATA0_FD27 CAN_F26DATA0_FD27_Msk /*!< Filter bit 27 */
# define CAN_F26DATA0_FD28_Pos (28U)
# define CAN_F26DATA0_FD28_Msk (0x1U << CAN_F26DATA0_FD28_Pos) /*!< 0x10000000 */
# define CAN_F26DATA0_FD28 CAN_F26DATA0_FD28_Msk /*!< Filter bit 28 */
# define CAN_F26DATA0_FD29_Pos (29U)
# define CAN_F26DATA0_FD29_Msk (0x1U << CAN_F26DATA0_FD29_Pos) /*!< 0x20000000 */
# define CAN_F26DATA0_FD29 CAN_F26DATA0_FD29_Msk /*!< Filter bit 29 */
# define CAN_F26DATA0_FD30_Pos (30U)
# define CAN_F26DATA0_FD30_Msk (0x1U << CAN_F26DATA0_FD30_Pos) /*!< 0x40000000 */
# define CAN_F26DATA0_FD30 CAN_F26DATA0_FD30_Msk /*!< Filter bit 30 */
# define CAN_F26DATA0_FD31_Pos (31U)
# define CAN_F26DATA0_FD31_Msk (0x1U << CAN_F26DATA0_FD31_Pos) /*!< 0x80000000 */
# define CAN_F26DATA0_FD31 CAN_F26DATA0_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F27R1 register ******************/
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# define CAN_F27DATA0_FD0_Pos (0U)
# define CAN_F27DATA0_FD0_Msk (0x1U << CAN_F27DATA0_FD0_Pos) /*!< 0x00000001 */
# define CAN_F27DATA0_FD0 CAN_F27DATA0_FD0_Msk /*!< Filter bit 0 */
# define CAN_F27DATA0_FD1_Pos (1U)
# define CAN_F27DATA0_FD1_Msk (0x1U << CAN_F27DATA0_FD1_Pos) /*!< 0x00000002 */
# define CAN_F27DATA0_FD1 CAN_F27DATA0_FD1_Msk /*!< Filter bit 1 */
# define CAN_F27DATA0_FD2_Pos (2U)
# define CAN_F27DATA0_FD2_Msk (0x1U << CAN_F27DATA0_FD2_Pos) /*!< 0x00000004 */
# define CAN_F27DATA0_FD2 CAN_F27DATA0_FD2_Msk /*!< Filter bit 2 */
# define CAN_F27DATA0_FD3_Pos (3U)
# define CAN_F27DATA0_FD3_Msk (0x1U << CAN_F27DATA0_FD3_Pos) /*!< 0x00000008 */
# define CAN_F27DATA0_FD3 CAN_F27DATA0_FD3_Msk /*!< Filter bit 3 */
# define CAN_F27DATA0_FD4_Pos (4U)
# define CAN_F27DATA0_FD4_Msk (0x1U << CAN_F27DATA0_FD4_Pos) /*!< 0x00000010 */
# define CAN_F27DATA0_FD4 CAN_F27DATA0_FD4_Msk /*!< Filter bit 4 */
# define CAN_F27DATA0_FD5_Pos (5U)
# define CAN_F27DATA0_FD5_Msk (0x1U << CAN_F27DATA0_FD5_Pos) /*!< 0x00000020 */
# define CAN_F27DATA0_FD5 CAN_F27DATA0_FD5_Msk /*!< Filter bit 5 */
# define CAN_F27DATA0_FD6_Pos (6U)
# define CAN_F27DATA0_FD6_Msk (0x1U << CAN_F27DATA0_FD6_Pos) /*!< 0x00000040 */
# define CAN_F27DATA0_FD6 CAN_F27DATA0_FD6_Msk /*!< Filter bit 6 */
# define CAN_F27DATA0_FD7_Pos (7U)
# define CAN_F27DATA0_FD7_Msk (0x1U << CAN_F27DATA0_FD7_Pos) /*!< 0x00000080 */
# define CAN_F27DATA0_FD7 CAN_F27DATA0_FD7_Msk /*!< Filter bit 7 */
# define CAN_F27DATA0_FD8_Pos (8U)
# define CAN_F27DATA0_FD8_Msk (0x1U << CAN_F27DATA0_FD8_Pos) /*!< 0x00000100 */
# define CAN_F27DATA0_FD8 CAN_F27DATA0_FD8_Msk /*!< Filter bit 8 */
# define CAN_F27DATA0_FD9_Pos (9U)
# define CAN_F27DATA0_FD9_Msk (0x1U << CAN_F27DATA0_FD9_Pos) /*!< 0x00000200 */
# define CAN_F27DATA0_FD9 CAN_F27DATA0_FD9_Msk /*!< Filter bit 9 */
# define CAN_F27DATA0_FD10_Pos (10U)
# define CAN_F27DATA0_FD10_Msk (0x1U << CAN_F27DATA0_FD10_Pos) /*!< 0x00000400 */
# define CAN_F27DATA0_FD10 CAN_F27DATA0_FD10_Msk /*!< Filter bit 10 */
# define CAN_F27DATA0_FD11_Pos (11U)
# define CAN_F27DATA0_FD11_Msk (0x1U << CAN_F27DATA0_FD11_Pos) /*!< 0x00000800 */
# define CAN_F27DATA0_FD11 CAN_F27DATA0_FD11_Msk /*!< Filter bit 11 */
# define CAN_F27DATA0_FD12_Pos (12U)
# define CAN_F27DATA0_FD12_Msk (0x1U << CAN_F27DATA0_FD12_Pos) /*!< 0x00001000 */
# define CAN_F27DATA0_FD12 CAN_F27DATA0_FD12_Msk /*!< Filter bit 12 */
# define CAN_F27DATA0_FD13_Pos (13U)
# define CAN_F27DATA0_FD13_Msk (0x1U << CAN_F27DATA0_FD13_Pos) /*!< 0x00002000 */
# define CAN_F27DATA0_FD13 CAN_F27DATA0_FD13_Msk /*!< Filter bit 13 */
# define CAN_F27DATA0_FD14_Pos (14U)
# define CAN_F27DATA0_FD14_Msk (0x1U << CAN_F27DATA0_FD14_Pos) /*!< 0x00004000 */
# define CAN_F27DATA0_FD14 CAN_F27DATA0_FD14_Msk /*!< Filter bit 14 */
# define CAN_F27DATA0_FD15_Pos (15U)
# define CAN_F27DATA0_FD15_Msk (0x1U << CAN_F27DATA0_FD15_Pos) /*!< 0x00008000 */
# define CAN_F27DATA0_FD15 CAN_F27DATA0_FD15_Msk /*!< Filter bit 15 */
# define CAN_F27DATA0_FD16_Pos (16U)
# define CAN_F27DATA0_FD16_Msk (0x1U << CAN_F27DATA0_FD16_Pos) /*!< 0x00010000 */
# define CAN_F27DATA0_FD16 CAN_F27DATA0_FD16_Msk /*!< Filter bit 16 */
# define CAN_F27DATA0_FD17_Pos (17U)
# define CAN_F27DATA0_FD17_Msk (0x1U << CAN_F27DATA0_FD17_Pos) /*!< 0x00020000 */
# define CAN_F27DATA0_FD17 CAN_F27DATA0_FD17_Msk /*!< Filter bit 17 */
# define CAN_F27DATA0_FD18_Pos (18U)
# define CAN_F27DATA0_FD18_Msk (0x1U << CAN_F27DATA0_FD18_Pos) /*!< 0x00040000 */
# define CAN_F27DATA0_FD18 CAN_F27DATA0_FD18_Msk /*!< Filter bit 18 */
# define CAN_F27DATA0_FD19_Pos (19U)
# define CAN_F27DATA0_FD19_Msk (0x1U << CAN_F27DATA0_FD19_Pos) /*!< 0x00080000 */
# define CAN_F27DATA0_FD19 CAN_F27DATA0_FD19_Msk /*!< Filter bit 19 */
# define CAN_F27DATA0_FD20_Pos (20U)
# define CAN_F27DATA0_FD20_Msk (0x1U << CAN_F27DATA0_FD20_Pos) /*!< 0x00100000 */
# define CAN_F27DATA0_FD20 CAN_F27DATA0_FD20_Msk /*!< Filter bit 20 */
# define CAN_F27DATA0_FD21_Pos (21U)
# define CAN_F27DATA0_FD21_Msk (0x1U << CAN_F27DATA0_FD21_Pos) /*!< 0x00200000 */
# define CAN_F27DATA0_FD21 CAN_F27DATA0_FD21_Msk /*!< Filter bit 21 */
# define CAN_F27DATA0_FD22_Pos (22U)
# define CAN_F27DATA0_FD22_Msk (0x1U << CAN_F27DATA0_FD22_Pos) /*!< 0x00400000 */
# define CAN_F27DATA0_FD22 CAN_F27DATA0_FD22_Msk /*!< Filter bit 22 */
# define CAN_F27DATA0_FD23_Pos (23U)
# define CAN_F27DATA0_FD23_Msk (0x1U << CAN_F27DATA0_FD23_Pos) /*!< 0x00800000 */
# define CAN_F27DATA0_FD23 CAN_F27DATA0_FD23_Msk /*!< Filter bit 23 */
# define CAN_F27DATA0_FD24_Pos (24U)
# define CAN_F27DATA0_FD24_Msk (0x1U << CAN_F27DATA0_FD24_Pos) /*!< 0x01000000 */
# define CAN_F27DATA0_FD24 CAN_F27DATA0_FD24_Msk /*!< Filter bit 24 */
# define CAN_F27DATA0_FD25_Pos (25U)
# define CAN_F27DATA0_FD25_Msk (0x1U << CAN_F27DATA0_FD25_Pos) /*!< 0x02000000 */
# define CAN_F27DATA0_FD25 CAN_F27DATA0_FD25_Msk /*!< Filter bit 25 */
# define CAN_F27DATA0_FD26_Pos (26U)
# define CAN_F27DATA0_FD26_Msk (0x1U << CAN_F27DATA0_FD26_Pos) /*!< 0x04000000 */
# define CAN_F27DATA0_FD26 CAN_F27DATA0_FD26_Msk /*!< Filter bit 26 */
# define CAN_F27DATA0_FD27_Pos (27U)
# define CAN_F27DATA0_FD27_Msk (0x1U << CAN_F27DATA0_FD27_Pos) /*!< 0x08000000 */
# define CAN_F27DATA0_FD27 CAN_F27DATA0_FD27_Msk /*!< Filter bit 27 */
# define CAN_F27DATA0_FD28_Pos (28U)
# define CAN_F27DATA0_FD28_Msk (0x1U << CAN_F27DATA0_FD28_Pos) /*!< 0x10000000 */
# define CAN_F27DATA0_FD28 CAN_F27DATA0_FD28_Msk /*!< Filter bit 28 */
# define CAN_F27DATA0_FD29_Pos (29U)
# define CAN_F27DATA0_FD29_Msk (0x1U << CAN_F27DATA0_FD29_Pos) /*!< 0x20000000 */
# define CAN_F27DATA0_FD29 CAN_F27DATA0_FD29_Msk /*!< Filter bit 29 */
# define CAN_F27DATA0_FD30_Pos (30U)
# define CAN_F27DATA0_FD30_Msk (0x1U << CAN_F27DATA0_FD30_Pos) /*!< 0x40000000 */
# define CAN_F27DATA0_FD30 CAN_F27DATA0_FD30_Msk /*!< Filter bit 30 */
# define CAN_F27DATA0_FD31_Pos (31U)
# define CAN_F27DATA0_FD31_Msk (0x1U << CAN_F27DATA0_FD31_Pos) /*!< 0x80000000 */
# define CAN_F27DATA0_FD31 CAN_F27DATA0_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F0R2 register *******************/
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# define CAN_F0DATA1_FD0_Pos (0U)
# define CAN_F0DATA1_FD0_Msk (0x1U << CAN_F0DATA1_FD0_Pos) /*!< 0x00000001 */
# define CAN_F0DATA1_FD0 CAN_F0DATA1_FD0_Msk /*!< Filter bit 0 */
# define CAN_F0DATA1_FD1_Pos (1U)
# define CAN_F0DATA1_FD1_Msk (0x1U << CAN_F0DATA1_FD1_Pos) /*!< 0x00000002 */
# define CAN_F0DATA1_FD1 CAN_F0DATA1_FD1_Msk /*!< Filter bit 1 */
# define CAN_F0DATA1_FD2_Pos (2U)
# define CAN_F0DATA1_FD2_Msk (0x1U << CAN_F0DATA1_FD2_Pos) /*!< 0x00000004 */
# define CAN_F0DATA1_FD2 CAN_F0DATA1_FD2_Msk /*!< Filter bit 2 */
# define CAN_F0DATA1_FD3_Pos (3U)
# define CAN_F0DATA1_FD3_Msk (0x1U << CAN_F0DATA1_FD3_Pos) /*!< 0x00000008 */
# define CAN_F0DATA1_FD3 CAN_F0DATA1_FD3_Msk /*!< Filter bit 3 */
# define CAN_F0DATA1_FD4_Pos (4U)
# define CAN_F0DATA1_FD4_Msk (0x1U << CAN_F0DATA1_FD4_Pos) /*!< 0x00000010 */
# define CAN_F0DATA1_FD4 CAN_F0DATA1_FD4_Msk /*!< Filter bit 4 */
# define CAN_F0DATA1_FD5_Pos (5U)
# define CAN_F0DATA1_FD5_Msk (0x1U << CAN_F0DATA1_FD5_Pos) /*!< 0x00000020 */
# define CAN_F0DATA1_FD5 CAN_F0DATA1_FD5_Msk /*!< Filter bit 5 */
# define CAN_F0DATA1_FD6_Pos (6U)
# define CAN_F0DATA1_FD6_Msk (0x1U << CAN_F0DATA1_FD6_Pos) /*!< 0x00000040 */
# define CAN_F0DATA1_FD6 CAN_F0DATA1_FD6_Msk /*!< Filter bit 6 */
# define CAN_F0DATA1_FD7_Pos (7U)
# define CAN_F0DATA1_FD7_Msk (0x1U << CAN_F0DATA1_FD7_Pos) /*!< 0x00000080 */
# define CAN_F0DATA1_FD7 CAN_F0DATA1_FD7_Msk /*!< Filter bit 7 */
# define CAN_F0DATA1_FD8_Pos (8U)
# define CAN_F0DATA1_FD8_Msk (0x1U << CAN_F0DATA1_FD8_Pos) /*!< 0x00000100 */
# define CAN_F0DATA1_FD8 CAN_F0DATA1_FD8_Msk /*!< Filter bit 8 */
# define CAN_F0DATA1_FD9_Pos (9U)
# define CAN_F0DATA1_FD9_Msk (0x1U << CAN_F0DATA1_FD9_Pos) /*!< 0x00000200 */
# define CAN_F0DATA1_FD9 CAN_F0DATA1_FD9_Msk /*!< Filter bit 9 */
# define CAN_F0DATA1_FD10_Pos (10U)
# define CAN_F0DATA1_FD10_Msk (0x1U << CAN_F0DATA1_FD10_Pos) /*!< 0x00000400 */
# define CAN_F0DATA1_FD10 CAN_F0DATA1_FD10_Msk /*!< Filter bit 10 */
# define CAN_F0DATA1_FD11_Pos (11U)
# define CAN_F0DATA1_FD11_Msk (0x1U << CAN_F0DATA1_FD11_Pos) /*!< 0x00000800 */
# define CAN_F0DATA1_FD11 CAN_F0DATA1_FD11_Msk /*!< Filter bit 11 */
# define CAN_F0DATA1_FD12_Pos (12U)
# define CAN_F0DATA1_FD12_Msk (0x1U << CAN_F0DATA1_FD12_Pos) /*!< 0x00001000 */
# define CAN_F0DATA1_FD12 CAN_F0DATA1_FD12_Msk /*!< Filter bit 12 */
# define CAN_F0DATA1_FD13_Pos (13U)
# define CAN_F0DATA1_FD13_Msk (0x1U << CAN_F0DATA1_FD13_Pos) /*!< 0x00002000 */
# define CAN_F0DATA1_FD13 CAN_F0DATA1_FD13_Msk /*!< Filter bit 13 */
# define CAN_F0DATA1_FD14_Pos (14U)
# define CAN_F0DATA1_FD14_Msk (0x1U << CAN_F0DATA1_FD14_Pos) /*!< 0x00004000 */
# define CAN_F0DATA1_FD14 CAN_F0DATA1_FD14_Msk /*!< Filter bit 14 */
# define CAN_F0DATA1_FD15_Pos (15U)
# define CAN_F0DATA1_FD15_Msk (0x1U << CAN_F0DATA1_FD15_Pos) /*!< 0x00008000 */
# define CAN_F0DATA1_FD15 CAN_F0DATA1_FD15_Msk /*!< Filter bit 15 */
# define CAN_F0DATA1_FD16_Pos (16U)
# define CAN_F0DATA1_FD16_Msk (0x1U << CAN_F0DATA1_FD16_Pos) /*!< 0x00010000 */
# define CAN_F0DATA1_FD16 CAN_F0DATA1_FD16_Msk /*!< Filter bit 16 */
# define CAN_F0DATA1_FD17_Pos (17U)
# define CAN_F0DATA1_FD17_Msk (0x1U << CAN_F0DATA1_FD17_Pos) /*!< 0x00020000 */
# define CAN_F0DATA1_FD17 CAN_F0DATA1_FD17_Msk /*!< Filter bit 17 */
# define CAN_F0DATA1_FD18_Pos (18U)
# define CAN_F0DATA1_FD18_Msk (0x1U << CAN_F0DATA1_FD18_Pos) /*!< 0x00040000 */
# define CAN_F0DATA1_FD18 CAN_F0DATA1_FD18_Msk /*!< Filter bit 18 */
# define CAN_F0DATA1_FD19_Pos (19U)
# define CAN_F0DATA1_FD19_Msk (0x1U << CAN_F0DATA1_FD19_Pos) /*!< 0x00080000 */
# define CAN_F0DATA1_FD19 CAN_F0DATA1_FD19_Msk /*!< Filter bit 19 */
# define CAN_F0DATA1_FD20_Pos (20U)
# define CAN_F0DATA1_FD20_Msk (0x1U << CAN_F0DATA1_FD20_Pos) /*!< 0x00100000 */
# define CAN_F0DATA1_FD20 CAN_F0DATA1_FD20_Msk /*!< Filter bit 20 */
# define CAN_F0DATA1_FD21_Pos (21U)
# define CAN_F0DATA1_FD21_Msk (0x1U << CAN_F0DATA1_FD21_Pos) /*!< 0x00200000 */
# define CAN_F0DATA1_FD21 CAN_F0DATA1_FD21_Msk /*!< Filter bit 21 */
# define CAN_F0DATA1_FD22_Pos (22U)
# define CAN_F0DATA1_FD22_Msk (0x1U << CAN_F0DATA1_FD22_Pos) /*!< 0x00400000 */
# define CAN_F0DATA1_FD22 CAN_F0DATA1_FD22_Msk /*!< Filter bit 22 */
# define CAN_F0DATA1_FD23_Pos (23U)
# define CAN_F0DATA1_FD23_Msk (0x1U << CAN_F0DATA1_FD23_Pos) /*!< 0x00800000 */
# define CAN_F0DATA1_FD23 CAN_F0DATA1_FD23_Msk /*!< Filter bit 23 */
# define CAN_F0DATA1_FD24_Pos (24U)
# define CAN_F0DATA1_FD24_Msk (0x1U << CAN_F0DATA1_FD24_Pos) /*!< 0x01000000 */
# define CAN_F0DATA1_FD24 CAN_F0DATA1_FD24_Msk /*!< Filter bit 24 */
# define CAN_F0DATA1_FD25_Pos (25U)
# define CAN_F0DATA1_FD25_Msk (0x1U << CAN_F0DATA1_FD25_Pos) /*!< 0x02000000 */
# define CAN_F0DATA1_FD25 CAN_F0DATA1_FD25_Msk /*!< Filter bit 25 */
# define CAN_F0DATA1_FD26_Pos (26U)
# define CAN_F0DATA1_FD26_Msk (0x1U << CAN_F0DATA1_FD26_Pos) /*!< 0x04000000 */
# define CAN_F0DATA1_FD26 CAN_F0DATA1_FD26_Msk /*!< Filter bit 26 */
# define CAN_F0DATA1_FD27_Pos (27U)
# define CAN_F0DATA1_FD27_Msk (0x1U << CAN_F0DATA1_FD27_Pos) /*!< 0x08000000 */
# define CAN_F0DATA1_FD27 CAN_F0DATA1_FD27_Msk /*!< Filter bit 27 */
# define CAN_F0DATA1_FD28_Pos (28U)
# define CAN_F0DATA1_FD28_Msk (0x1U << CAN_F0DATA1_FD28_Pos) /*!< 0x10000000 */
# define CAN_F0DATA1_FD28 CAN_F0DATA1_FD28_Msk /*!< Filter bit 28 */
# define CAN_F0DATA1_FD29_Pos (29U)
# define CAN_F0DATA1_FD29_Msk (0x1U << CAN_F0DATA1_FD29_Pos) /*!< 0x20000000 */
# define CAN_F0DATA1_FD29 CAN_F0DATA1_FD29_Msk /*!< Filter bit 29 */
# define CAN_F0DATA1_FD30_Pos (30U)
# define CAN_F0DATA1_FD30_Msk (0x1U << CAN_F0DATA1_FD30_Pos) /*!< 0x40000000 */
# define CAN_F0DATA1_FD30 CAN_F0DATA1_FD30_Msk /*!< Filter bit 30 */
# define CAN_F0DATA1_FD31_Pos (31U)
# define CAN_F0DATA1_FD31_Msk (0x1U << CAN_F0DATA1_FD31_Pos) /*!< 0x80000000 */
# define CAN_F0DATA1_FD31 CAN_F0DATA1_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F1R2 register *******************/
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# define CAN_F1DATA1_FD0_Pos (0U)
# define CAN_F1DATA1_FD0_Msk (0x1U << CAN_F1DATA1_FD0_Pos) /*!< 0x00000001 */
# define CAN_F1DATA1_FD0 CAN_F1DATA1_FD0_Msk /*!< Filter bit 0 */
# define CAN_F1DATA1_FD1_Pos (1U)
# define CAN_F1DATA1_FD1_Msk (0x1U << CAN_F1DATA1_FD1_Pos) /*!< 0x00000002 */
# define CAN_F1DATA1_FD1 CAN_F1DATA1_FD1_Msk /*!< Filter bit 1 */
# define CAN_F1DATA1_FD2_Pos (2U)
# define CAN_F1DATA1_FD2_Msk (0x1U << CAN_F1DATA1_FD2_Pos) /*!< 0x00000004 */
# define CAN_F1DATA1_FD2 CAN_F1DATA1_FD2_Msk /*!< Filter bit 2 */
# define CAN_F1DATA1_FD3_Pos (3U)
# define CAN_F1DATA1_FD3_Msk (0x1U << CAN_F1DATA1_FD3_Pos) /*!< 0x00000008 */
# define CAN_F1DATA1_FD3 CAN_F1DATA1_FD3_Msk /*!< Filter bit 3 */
# define CAN_F1DATA1_FD4_Pos (4U)
# define CAN_F1DATA1_FD4_Msk (0x1U << CAN_F1DATA1_FD4_Pos) /*!< 0x00000010 */
# define CAN_F1DATA1_FD4 CAN_F1DATA1_FD4_Msk /*!< Filter bit 4 */
# define CAN_F1DATA1_FD5_Pos (5U)
# define CAN_F1DATA1_FD5_Msk (0x1U << CAN_F1DATA1_FD5_Pos) /*!< 0x00000020 */
# define CAN_F1DATA1_FD5 CAN_F1DATA1_FD5_Msk /*!< Filter bit 5 */
# define CAN_F1DATA1_FD6_Pos (6U)
# define CAN_F1DATA1_FD6_Msk (0x1U << CAN_F1DATA1_FD6_Pos) /*!< 0x00000040 */
# define CAN_F1DATA1_FD6 CAN_F1DATA1_FD6_Msk /*!< Filter bit 6 */
# define CAN_F1DATA1_FD7_Pos (7U)
# define CAN_F1DATA1_FD7_Msk (0x1U << CAN_F1DATA1_FD7_Pos) /*!< 0x00000080 */
# define CAN_F1DATA1_FD7 CAN_F1DATA1_FD7_Msk /*!< Filter bit 7 */
# define CAN_F1DATA1_FD8_Pos (8U)
# define CAN_F1DATA1_FD8_Msk (0x1U << CAN_F1DATA1_FD8_Pos) /*!< 0x00000100 */
# define CAN_F1DATA1_FD8 CAN_F1DATA1_FD8_Msk /*!< Filter bit 8 */
# define CAN_F1DATA1_FD9_Pos (9U)
# define CAN_F1DATA1_FD9_Msk (0x1U << CAN_F1DATA1_FD9_Pos) /*!< 0x00000200 */
# define CAN_F1DATA1_FD9 CAN_F1DATA1_FD9_Msk /*!< Filter bit 9 */
# define CAN_F1DATA1_FD10_Pos (10U)
# define CAN_F1DATA1_FD10_Msk (0x1U << CAN_F1DATA1_FD10_Pos) /*!< 0x00000400 */
# define CAN_F1DATA1_FD10 CAN_F1DATA1_FD10_Msk /*!< Filter bit 10 */
# define CAN_F1DATA1_FD11_Pos (11U)
# define CAN_F1DATA1_FD11_Msk (0x1U << CAN_F1DATA1_FD11_Pos) /*!< 0x00000800 */
# define CAN_F1DATA1_FD11 CAN_F1DATA1_FD11_Msk /*!< Filter bit 11 */
# define CAN_F1DATA1_FD12_Pos (12U)
# define CAN_F1DATA1_FD12_Msk (0x1U << CAN_F1DATA1_FD12_Pos) /*!< 0x00001000 */
# define CAN_F1DATA1_FD12 CAN_F1DATA1_FD12_Msk /*!< Filter bit 12 */
# define CAN_F1DATA1_FD13_Pos (13U)
# define CAN_F1DATA1_FD13_Msk (0x1U << CAN_F1DATA1_FD13_Pos) /*!< 0x00002000 */
# define CAN_F1DATA1_FD13 CAN_F1DATA1_FD13_Msk /*!< Filter bit 13 */
# define CAN_F1DATA1_FD14_Pos (14U)
# define CAN_F1DATA1_FD14_Msk (0x1U << CAN_F1DATA1_FD14_Pos) /*!< 0x00004000 */
# define CAN_F1DATA1_FD14 CAN_F1DATA1_FD14_Msk /*!< Filter bit 14 */
# define CAN_F1DATA1_FD15_Pos (15U)
# define CAN_F1DATA1_FD15_Msk (0x1U << CAN_F1DATA1_FD15_Pos) /*!< 0x00008000 */
# define CAN_F1DATA1_FD15 CAN_F1DATA1_FD15_Msk /*!< Filter bit 15 */
# define CAN_F1DATA1_FD16_Pos (16U)
# define CAN_F1DATA1_FD16_Msk (0x1U << CAN_F1DATA1_FD16_Pos) /*!< 0x00010000 */
# define CAN_F1DATA1_FD16 CAN_F1DATA1_FD16_Msk /*!< Filter bit 16 */
# define CAN_F1DATA1_FD17_Pos (17U)
# define CAN_F1DATA1_FD17_Msk (0x1U << CAN_F1DATA1_FD17_Pos) /*!< 0x00020000 */
# define CAN_F1DATA1_FD17 CAN_F1DATA1_FD17_Msk /*!< Filter bit 17 */
# define CAN_F1DATA1_FD18_Pos (18U)
# define CAN_F1DATA1_FD18_Msk (0x1U << CAN_F1DATA1_FD18_Pos) /*!< 0x00040000 */
# define CAN_F1DATA1_FD18 CAN_F1DATA1_FD18_Msk /*!< Filter bit 18 */
# define CAN_F1DATA1_FD19_Pos (19U)
# define CAN_F1DATA1_FD19_Msk (0x1U << CAN_F1DATA1_FD19_Pos) /*!< 0x00080000 */
# define CAN_F1DATA1_FD19 CAN_F1DATA1_FD19_Msk /*!< Filter bit 19 */
# define CAN_F1DATA1_FD20_Pos (20U)
# define CAN_F1DATA1_FD20_Msk (0x1U << CAN_F1DATA1_FD20_Pos) /*!< 0x00100000 */
# define CAN_F1DATA1_FD20 CAN_F1DATA1_FD20_Msk /*!< Filter bit 20 */
# define CAN_F1DATA1_FD21_Pos (21U)
# define CAN_F1DATA1_FD21_Msk (0x1U << CAN_F1DATA1_FD21_Pos) /*!< 0x00200000 */
# define CAN_F1DATA1_FD21 CAN_F1DATA1_FD21_Msk /*!< Filter bit 21 */
# define CAN_F1DATA1_FD22_Pos (22U)
# define CAN_F1DATA1_FD22_Msk (0x1U << CAN_F1DATA1_FD22_Pos) /*!< 0x00400000 */
# define CAN_F1DATA1_FD22 CAN_F1DATA1_FD22_Msk /*!< Filter bit 22 */
# define CAN_F1DATA1_FD23_Pos (23U)
# define CAN_F1DATA1_FD23_Msk (0x1U << CAN_F1DATA1_FD23_Pos) /*!< 0x00800000 */
# define CAN_F1DATA1_FD23 CAN_F1DATA1_FD23_Msk /*!< Filter bit 23 */
# define CAN_F1DATA1_FD24_Pos (24U)
# define CAN_F1DATA1_FD24_Msk (0x1U << CAN_F1DATA1_FD24_Pos) /*!< 0x01000000 */
# define CAN_F1DATA1_FD24 CAN_F1DATA1_FD24_Msk /*!< Filter bit 24 */
# define CAN_F1DATA1_FD25_Pos (25U)
# define CAN_F1DATA1_FD25_Msk (0x1U << CAN_F1DATA1_FD25_Pos) /*!< 0x02000000 */
# define CAN_F1DATA1_FD25 CAN_F1DATA1_FD25_Msk /*!< Filter bit 25 */
# define CAN_F1DATA1_FD26_Pos (26U)
# define CAN_F1DATA1_FD26_Msk (0x1U << CAN_F1DATA1_FD26_Pos) /*!< 0x04000000 */
# define CAN_F1DATA1_FD26 CAN_F1DATA1_FD26_Msk /*!< Filter bit 26 */
# define CAN_F1DATA1_FD27_Pos (27U)
# define CAN_F1DATA1_FD27_Msk (0x1U << CAN_F1DATA1_FD27_Pos) /*!< 0x08000000 */
# define CAN_F1DATA1_FD27 CAN_F1DATA1_FD27_Msk /*!< Filter bit 27 */
# define CAN_F1DATA1_FD28_Pos (28U)
# define CAN_F1DATA1_FD28_Msk (0x1U << CAN_F1DATA1_FD28_Pos) /*!< 0x10000000 */
# define CAN_F1DATA1_FD28 CAN_F1DATA1_FD28_Msk /*!< Filter bit 28 */
# define CAN_F1DATA1_FD29_Pos (29U)
# define CAN_F1DATA1_FD29_Msk (0x1U << CAN_F1DATA1_FD29_Pos) /*!< 0x20000000 */
# define CAN_F1DATA1_FD29 CAN_F1DATA1_FD29_Msk /*!< Filter bit 29 */
# define CAN_F1DATA1_FD30_Pos (30U)
# define CAN_F1DATA1_FD30_Msk (0x1U << CAN_F1DATA1_FD30_Pos) /*!< 0x40000000 */
# define CAN_F1DATA1_FD30 CAN_F1DATA1_FD30_Msk /*!< Filter bit 30 */
# define CAN_F1DATA1_FD31_Pos (31U)
# define CAN_F1DATA1_FD31_Msk (0x1U << CAN_F1DATA1_FD31_Pos) /*!< 0x80000000 */
# define CAN_F1DATA1_FD31 CAN_F1DATA1_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F2R2 register *******************/
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# define CAN_F2DATA1_FD0_Pos (0U)
# define CAN_F2DATA1_FD0_Msk (0x1U << CAN_F2DATA1_FD0_Pos) /*!< 0x00000001 */
# define CAN_F2DATA1_FD0 CAN_F2DATA1_FD0_Msk /*!< Filter bit 0 */
# define CAN_F2DATA1_FD1_Pos (1U)
# define CAN_F2DATA1_FD1_Msk (0x1U << CAN_F2DATA1_FD1_Pos) /*!< 0x00000002 */
# define CAN_F2DATA1_FD1 CAN_F2DATA1_FD1_Msk /*!< Filter bit 1 */
# define CAN_F2DATA1_FD2_Pos (2U)
# define CAN_F2DATA1_FD2_Msk (0x1U << CAN_F2DATA1_FD2_Pos) /*!< 0x00000004 */
# define CAN_F2DATA1_FD2 CAN_F2DATA1_FD2_Msk /*!< Filter bit 2 */
# define CAN_F2DATA1_FD3_Pos (3U)
# define CAN_F2DATA1_FD3_Msk (0x1U << CAN_F2DATA1_FD3_Pos) /*!< 0x00000008 */
# define CAN_F2DATA1_FD3 CAN_F2DATA1_FD3_Msk /*!< Filter bit 3 */
# define CAN_F2DATA1_FD4_Pos (4U)
# define CAN_F2DATA1_FD4_Msk (0x1U << CAN_F2DATA1_FD4_Pos) /*!< 0x00000010 */
# define CAN_F2DATA1_FD4 CAN_F2DATA1_FD4_Msk /*!< Filter bit 4 */
# define CAN_F2DATA1_FD5_Pos (5U)
# define CAN_F2DATA1_FD5_Msk (0x1U << CAN_F2DATA1_FD5_Pos) /*!< 0x00000020 */
# define CAN_F2DATA1_FD5 CAN_F2DATA1_FD5_Msk /*!< Filter bit 5 */
# define CAN_F2DATA1_FD6_Pos (6U)
# define CAN_F2DATA1_FD6_Msk (0x1U << CAN_F2DATA1_FD6_Pos) /*!< 0x00000040 */
# define CAN_F2DATA1_FD6 CAN_F2DATA1_FD6_Msk /*!< Filter bit 6 */
# define CAN_F2DATA1_FD7_Pos (7U)
# define CAN_F2DATA1_FD7_Msk (0x1U << CAN_F2DATA1_FD7_Pos) /*!< 0x00000080 */
# define CAN_F2DATA1_FD7 CAN_F2DATA1_FD7_Msk /*!< Filter bit 7 */
# define CAN_F2DATA1_FD8_Pos (8U)
# define CAN_F2DATA1_FD8_Msk (0x1U << CAN_F2DATA1_FD8_Pos) /*!< 0x00000100 */
# define CAN_F2DATA1_FD8 CAN_F2DATA1_FD8_Msk /*!< Filter bit 8 */
# define CAN_F2DATA1_FD9_Pos (9U)
# define CAN_F2DATA1_FD9_Msk (0x1U << CAN_F2DATA1_FD9_Pos) /*!< 0x00000200 */
# define CAN_F2DATA1_FD9 CAN_F2DATA1_FD9_Msk /*!< Filter bit 9 */
# define CAN_F2DATA1_FD10_Pos (10U)
# define CAN_F2DATA1_FD10_Msk (0x1U << CAN_F2DATA1_FD10_Pos) /*!< 0x00000400 */
# define CAN_F2DATA1_FD10 CAN_F2DATA1_FD10_Msk /*!< Filter bit 10 */
# define CAN_F2DATA1_FD11_Pos (11U)
# define CAN_F2DATA1_FD11_Msk (0x1U << CAN_F2DATA1_FD11_Pos) /*!< 0x00000800 */
# define CAN_F2DATA1_FD11 CAN_F2DATA1_FD11_Msk /*!< Filter bit 11 */
# define CAN_F2DATA1_FD12_Pos (12U)
# define CAN_F2DATA1_FD12_Msk (0x1U << CAN_F2DATA1_FD12_Pos) /*!< 0x00001000 */
# define CAN_F2DATA1_FD12 CAN_F2DATA1_FD12_Msk /*!< Filter bit 12 */
# define CAN_F2DATA1_FD13_Pos (13U)
# define CAN_F2DATA1_FD13_Msk (0x1U << CAN_F2DATA1_FD13_Pos) /*!< 0x00002000 */
# define CAN_F2DATA1_FD13 CAN_F2DATA1_FD13_Msk /*!< Filter bit 13 */
# define CAN_F2DATA1_FD14_Pos (14U)
# define CAN_F2DATA1_FD14_Msk (0x1U << CAN_F2DATA1_FD14_Pos) /*!< 0x00004000 */
# define CAN_F2DATA1_FD14 CAN_F2DATA1_FD14_Msk /*!< Filter bit 14 */
# define CAN_F2DATA1_FD15_Pos (15U)
# define CAN_F2DATA1_FD15_Msk (0x1U << CAN_F2DATA1_FD15_Pos) /*!< 0x00008000 */
# define CAN_F2DATA1_FD15 CAN_F2DATA1_FD15_Msk /*!< Filter bit 15 */
# define CAN_F2DATA1_FD16_Pos (16U)
# define CAN_F2DATA1_FD16_Msk (0x1U << CAN_F2DATA1_FD16_Pos) /*!< 0x00010000 */
# define CAN_F2DATA1_FD16 CAN_F2DATA1_FD16_Msk /*!< Filter bit 16 */
# define CAN_F2DATA1_FD17_Pos (17U)
# define CAN_F2DATA1_FD17_Msk (0x1U << CAN_F2DATA1_FD17_Pos) /*!< 0x00020000 */
# define CAN_F2DATA1_FD17 CAN_F2DATA1_FD17_Msk /*!< Filter bit 17 */
# define CAN_F2DATA1_FD18_Pos (18U)
# define CAN_F2DATA1_FD18_Msk (0x1U << CAN_F2DATA1_FD18_Pos) /*!< 0x00040000 */
# define CAN_F2DATA1_FD18 CAN_F2DATA1_FD18_Msk /*!< Filter bit 18 */
# define CAN_F2DATA1_FD19_Pos (19U)
# define CAN_F2DATA1_FD19_Msk (0x1U << CAN_F2DATA1_FD19_Pos) /*!< 0x00080000 */
# define CAN_F2DATA1_FD19 CAN_F2DATA1_FD19_Msk /*!< Filter bit 19 */
# define CAN_F2DATA1_FD20_Pos (20U)
# define CAN_F2DATA1_FD20_Msk (0x1U << CAN_F2DATA1_FD20_Pos) /*!< 0x00100000 */
# define CAN_F2DATA1_FD20 CAN_F2DATA1_FD20_Msk /*!< Filter bit 20 */
# define CAN_F2DATA1_FD21_Pos (21U)
# define CAN_F2DATA1_FD21_Msk (0x1U << CAN_F2DATA1_FD21_Pos) /*!< 0x00200000 */
# define CAN_F2DATA1_FD21 CAN_F2DATA1_FD21_Msk /*!< Filter bit 21 */
# define CAN_F2DATA1_FD22_Pos (22U)
# define CAN_F2DATA1_FD22_Msk (0x1U << CAN_F2DATA1_FD22_Pos) /*!< 0x00400000 */
# define CAN_F2DATA1_FD22 CAN_F2DATA1_FD22_Msk /*!< Filter bit 22 */
# define CAN_F2DATA1_FD23_Pos (23U)
# define CAN_F2DATA1_FD23_Msk (0x1U << CAN_F2DATA1_FD23_Pos) /*!< 0x00800000 */
# define CAN_F2DATA1_FD23 CAN_F2DATA1_FD23_Msk /*!< Filter bit 23 */
# define CAN_F2DATA1_FD24_Pos (24U)
# define CAN_F2DATA1_FD24_Msk (0x1U << CAN_F2DATA1_FD24_Pos) /*!< 0x01000000 */
# define CAN_F2DATA1_FD24 CAN_F2DATA1_FD24_Msk /*!< Filter bit 24 */
# define CAN_F2DATA1_FD25_Pos (25U)
# define CAN_F2DATA1_FD25_Msk (0x1U << CAN_F2DATA1_FD25_Pos) /*!< 0x02000000 */
# define CAN_F2DATA1_FD25 CAN_F2DATA1_FD25_Msk /*!< Filter bit 25 */
# define CAN_F2DATA1_FD26_Pos (26U)
# define CAN_F2DATA1_FD26_Msk (0x1U << CAN_F2DATA1_FD26_Pos) /*!< 0x04000000 */
# define CAN_F2DATA1_FD26 CAN_F2DATA1_FD26_Msk /*!< Filter bit 26 */
# define CAN_F2DATA1_FD27_Pos (27U)
# define CAN_F2DATA1_FD27_Msk (0x1U << CAN_F2DATA1_FD27_Pos) /*!< 0x08000000 */
# define CAN_F2DATA1_FD27 CAN_F2DATA1_FD27_Msk /*!< Filter bit 27 */
# define CAN_F2DATA1_FD28_Pos (28U)
# define CAN_F2DATA1_FD28_Msk (0x1U << CAN_F2DATA1_FD28_Pos) /*!< 0x10000000 */
# define CAN_F2DATA1_FD28 CAN_F2DATA1_FD28_Msk /*!< Filter bit 28 */
# define CAN_F2DATA1_FD29_Pos (29U)
# define CAN_F2DATA1_FD29_Msk (0x1U << CAN_F2DATA1_FD29_Pos) /*!< 0x20000000 */
# define CAN_F2DATA1_FD29 CAN_F2DATA1_FD29_Msk /*!< Filter bit 29 */
# define CAN_F2DATA1_FD30_Pos (30U)
# define CAN_F2DATA1_FD30_Msk (0x1U << CAN_F2DATA1_FD30_Pos) /*!< 0x40000000 */
# define CAN_F2DATA1_FD30 CAN_F2DATA1_FD30_Msk /*!< Filter bit 30 */
# define CAN_F2DATA1_FD31_Pos (31U)
# define CAN_F2DATA1_FD31_Msk (0x1U << CAN_F2DATA1_FD31_Pos) /*!< 0x80000000 */
# define CAN_F2DATA1_FD31 CAN_F2DATA1_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F3R2 register *******************/
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# define CAN_F3DATA1_FD0_Pos (0U)
# define CAN_F3DATA1_FD0_Msk (0x1U << CAN_F3DATA1_FD0_Pos) /*!< 0x00000001 */
# define CAN_F3DATA1_FD0 CAN_F3DATA1_FD0_Msk /*!< Filter bit 0 */
# define CAN_F3DATA1_FD1_Pos (1U)
# define CAN_F3DATA1_FD1_Msk (0x1U << CAN_F3DATA1_FD1_Pos) /*!< 0x00000002 */
# define CAN_F3DATA1_FD1 CAN_F3DATA1_FD1_Msk /*!< Filter bit 1 */
# define CAN_F3DATA1_FD2_Pos (2U)
# define CAN_F3DATA1_FD2_Msk (0x1U << CAN_F3DATA1_FD2_Pos) /*!< 0x00000004 */
# define CAN_F3DATA1_FD2 CAN_F3DATA1_FD2_Msk /*!< Filter bit 2 */
# define CAN_F3DATA1_FD3_Pos (3U)
# define CAN_F3DATA1_FD3_Msk (0x1U << CAN_F3DATA1_FD3_Pos) /*!< 0x00000008 */
# define CAN_F3DATA1_FD3 CAN_F3DATA1_FD3_Msk /*!< Filter bit 3 */
# define CAN_F3DATA1_FD4_Pos (4U)
# define CAN_F3DATA1_FD4_Msk (0x1U << CAN_F3DATA1_FD4_Pos) /*!< 0x00000010 */
# define CAN_F3DATA1_FD4 CAN_F3DATA1_FD4_Msk /*!< Filter bit 4 */
# define CAN_F3DATA1_FD5_Pos (5U)
# define CAN_F3DATA1_FD5_Msk (0x1U << CAN_F3DATA1_FD5_Pos) /*!< 0x00000020 */
# define CAN_F3DATA1_FD5 CAN_F3DATA1_FD5_Msk /*!< Filter bit 5 */
# define CAN_F3DATA1_FD6_Pos (6U)
# define CAN_F3DATA1_FD6_Msk (0x1U << CAN_F3DATA1_FD6_Pos) /*!< 0x00000040 */
# define CAN_F3DATA1_FD6 CAN_F3DATA1_FD6_Msk /*!< Filter bit 6 */
# define CAN_F3DATA1_FD7_Pos (7U)
# define CAN_F3DATA1_FD7_Msk (0x1U << CAN_F3DATA1_FD7_Pos) /*!< 0x00000080 */
# define CAN_F3DATA1_FD7 CAN_F3DATA1_FD7_Msk /*!< Filter bit 7 */
# define CAN_F3DATA1_FD8_Pos (8U)
# define CAN_F3DATA1_FD8_Msk (0x1U << CAN_F3DATA1_FD8_Pos) /*!< 0x00000100 */
# define CAN_F3DATA1_FD8 CAN_F3DATA1_FD8_Msk /*!< Filter bit 8 */
# define CAN_F3DATA1_FD9_Pos (9U)
# define CAN_F3DATA1_FD9_Msk (0x1U << CAN_F3DATA1_FD9_Pos) /*!< 0x00000200 */
# define CAN_F3DATA1_FD9 CAN_F3DATA1_FD9_Msk /*!< Filter bit 9 */
# define CAN_F3DATA1_FD10_Pos (10U)
# define CAN_F3DATA1_FD10_Msk (0x1U << CAN_F3DATA1_FD10_Pos) /*!< 0x00000400 */
# define CAN_F3DATA1_FD10 CAN_F3DATA1_FD10_Msk /*!< Filter bit 10 */
# define CAN_F3DATA1_FD11_Pos (11U)
# define CAN_F3DATA1_FD11_Msk (0x1U << CAN_F3DATA1_FD11_Pos) /*!< 0x00000800 */
# define CAN_F3DATA1_FD11 CAN_F3DATA1_FD11_Msk /*!< Filter bit 11 */
# define CAN_F3DATA1_FD12_Pos (12U)
# define CAN_F3DATA1_FD12_Msk (0x1U << CAN_F3DATA1_FD12_Pos) /*!< 0x00001000 */
# define CAN_F3DATA1_FD12 CAN_F3DATA1_FD12_Msk /*!< Filter bit 12 */
# define CAN_F3DATA1_FD13_Pos (13U)
# define CAN_F3DATA1_FD13_Msk (0x1U << CAN_F3DATA1_FD13_Pos) /*!< 0x00002000 */
# define CAN_F3DATA1_FD13 CAN_F3DATA1_FD13_Msk /*!< Filter bit 13 */
# define CAN_F3DATA1_FD14_Pos (14U)
# define CAN_F3DATA1_FD14_Msk (0x1U << CAN_F3DATA1_FD14_Pos) /*!< 0x00004000 */
# define CAN_F3DATA1_FD14 CAN_F3DATA1_FD14_Msk /*!< Filter bit 14 */
# define CAN_F3DATA1_FD15_Pos (15U)
# define CAN_F3DATA1_FD15_Msk (0x1U << CAN_F3DATA1_FD15_Pos) /*!< 0x00008000 */
# define CAN_F3DATA1_FD15 CAN_F3DATA1_FD15_Msk /*!< Filter bit 15 */
# define CAN_F3DATA1_FD16_Pos (16U)
# define CAN_F3DATA1_FD16_Msk (0x1U << CAN_F3DATA1_FD16_Pos) /*!< 0x00010000 */
# define CAN_F3DATA1_FD16 CAN_F3DATA1_FD16_Msk /*!< Filter bit 16 */
# define CAN_F3DATA1_FD17_Pos (17U)
# define CAN_F3DATA1_FD17_Msk (0x1U << CAN_F3DATA1_FD17_Pos) /*!< 0x00020000 */
# define CAN_F3DATA1_FD17 CAN_F3DATA1_FD17_Msk /*!< Filter bit 17 */
# define CAN_F3DATA1_FD18_Pos (18U)
# define CAN_F3DATA1_FD18_Msk (0x1U << CAN_F3DATA1_FD18_Pos) /*!< 0x00040000 */
# define CAN_F3DATA1_FD18 CAN_F3DATA1_FD18_Msk /*!< Filter bit 18 */
# define CAN_F3DATA1_FD19_Pos (19U)
# define CAN_F3DATA1_FD19_Msk (0x1U << CAN_F3DATA1_FD19_Pos) /*!< 0x00080000 */
# define CAN_F3DATA1_FD19 CAN_F3DATA1_FD19_Msk /*!< Filter bit 19 */
# define CAN_F3DATA1_FD20_Pos (20U)
# define CAN_F3DATA1_FD20_Msk (0x1U << CAN_F3DATA1_FD20_Pos) /*!< 0x00100000 */
# define CAN_F3DATA1_FD20 CAN_F3DATA1_FD20_Msk /*!< Filter bit 20 */
# define CAN_F3DATA1_FD21_Pos (21U)
# define CAN_F3DATA1_FD21_Msk (0x1U << CAN_F3DATA1_FD21_Pos) /*!< 0x00200000 */
# define CAN_F3DATA1_FD21 CAN_F3DATA1_FD21_Msk /*!< Filter bit 21 */
# define CAN_F3DATA1_FD22_Pos (22U)
# define CAN_F3DATA1_FD22_Msk (0x1U << CAN_F3DATA1_FD22_Pos) /*!< 0x00400000 */
# define CAN_F3DATA1_FD22 CAN_F3DATA1_FD22_Msk /*!< Filter bit 22 */
# define CAN_F3DATA1_FD23_Pos (23U)
# define CAN_F3DATA1_FD23_Msk (0x1U << CAN_F3DATA1_FD23_Pos) /*!< 0x00800000 */
# define CAN_F3DATA1_FD23 CAN_F3DATA1_FD23_Msk /*!< Filter bit 23 */
# define CAN_F3DATA1_FD24_Pos (24U)
# define CAN_F3DATA1_FD24_Msk (0x1U << CAN_F3DATA1_FD24_Pos) /*!< 0x01000000 */
# define CAN_F3DATA1_FD24 CAN_F3DATA1_FD24_Msk /*!< Filter bit 24 */
# define CAN_F3DATA1_FD25_Pos (25U)
# define CAN_F3DATA1_FD25_Msk (0x1U << CAN_F3DATA1_FD25_Pos) /*!< 0x02000000 */
# define CAN_F3DATA1_FD25 CAN_F3DATA1_FD25_Msk /*!< Filter bit 25 */
# define CAN_F3DATA1_FD26_Pos (26U)
# define CAN_F3DATA1_FD26_Msk (0x1U << CAN_F3DATA1_FD26_Pos) /*!< 0x04000000 */
# define CAN_F3DATA1_FD26 CAN_F3DATA1_FD26_Msk /*!< Filter bit 26 */
# define CAN_F3DATA1_FD27_Pos (27U)
# define CAN_F3DATA1_FD27_Msk (0x1U << CAN_F3DATA1_FD27_Pos) /*!< 0x08000000 */
# define CAN_F3DATA1_FD27 CAN_F3DATA1_FD27_Msk /*!< Filter bit 27 */
# define CAN_F3DATA1_FD28_Pos (28U)
# define CAN_F3DATA1_FD28_Msk (0x1U << CAN_F3DATA1_FD28_Pos) /*!< 0x10000000 */
# define CAN_F3DATA1_FD28 CAN_F3DATA1_FD28_Msk /*!< Filter bit 28 */
# define CAN_F3DATA1_FD29_Pos (29U)
# define CAN_F3DATA1_FD29_Msk (0x1U << CAN_F3DATA1_FD29_Pos) /*!< 0x20000000 */
# define CAN_F3DATA1_FD29 CAN_F3DATA1_FD29_Msk /*!< Filter bit 29 */
# define CAN_F3DATA1_FD30_Pos (30U)
# define CAN_F3DATA1_FD30_Msk (0x1U << CAN_F3DATA1_FD30_Pos) /*!< 0x40000000 */
# define CAN_F3DATA1_FD30 CAN_F3DATA1_FD30_Msk /*!< Filter bit 30 */
# define CAN_F3DATA1_FD31_Pos (31U)
# define CAN_F3DATA1_FD31_Msk (0x1U << CAN_F3DATA1_FD31_Pos) /*!< 0x80000000 */
# define CAN_F3DATA1_FD31 CAN_F3DATA1_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F4R2 register *******************/
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# define CAN_F4DATA1_FD0_Pos (0U)
# define CAN_F4DATA1_FD0_Msk (0x1U << CAN_F4DATA1_FD0_Pos) /*!< 0x00000001 */
# define CAN_F4DATA1_FD0 CAN_F4DATA1_FD0_Msk /*!< Filter bit 0 */
# define CAN_F4DATA1_FD1_Pos (1U)
# define CAN_F4DATA1_FD1_Msk (0x1U << CAN_F4DATA1_FD1_Pos) /*!< 0x00000002 */
# define CAN_F4DATA1_FD1 CAN_F4DATA1_FD1_Msk /*!< Filter bit 1 */
# define CAN_F4DATA1_FD2_Pos (2U)
# define CAN_F4DATA1_FD2_Msk (0x1U << CAN_F4DATA1_FD2_Pos) /*!< 0x00000004 */
# define CAN_F4DATA1_FD2 CAN_F4DATA1_FD2_Msk /*!< Filter bit 2 */
# define CAN_F4DATA1_FD3_Pos (3U)
# define CAN_F4DATA1_FD3_Msk (0x1U << CAN_F4DATA1_FD3_Pos) /*!< 0x00000008 */
# define CAN_F4DATA1_FD3 CAN_F4DATA1_FD3_Msk /*!< Filter bit 3 */
# define CAN_F4DATA1_FD4_Pos (4U)
# define CAN_F4DATA1_FD4_Msk (0x1U << CAN_F4DATA1_FD4_Pos) /*!< 0x00000010 */
# define CAN_F4DATA1_FD4 CAN_F4DATA1_FD4_Msk /*!< Filter bit 4 */
# define CAN_F4DATA1_FD5_Pos (5U)
# define CAN_F4DATA1_FD5_Msk (0x1U << CAN_F4DATA1_FD5_Pos) /*!< 0x00000020 */
# define CAN_F4DATA1_FD5 CAN_F4DATA1_FD5_Msk /*!< Filter bit 5 */
# define CAN_F4DATA1_FD6_Pos (6U)
# define CAN_F4DATA1_FD6_Msk (0x1U << CAN_F4DATA1_FD6_Pos) /*!< 0x00000040 */
# define CAN_F4DATA1_FD6 CAN_F4DATA1_FD6_Msk /*!< Filter bit 6 */
# define CAN_F4DATA1_FD7_Pos (7U)
# define CAN_F4DATA1_FD7_Msk (0x1U << CAN_F4DATA1_FD7_Pos) /*!< 0x00000080 */
# define CAN_F4DATA1_FD7 CAN_F4DATA1_FD7_Msk /*!< Filter bit 7 */
# define CAN_F4DATA1_FD8_Pos (8U)
# define CAN_F4DATA1_FD8_Msk (0x1U << CAN_F4DATA1_FD8_Pos) /*!< 0x00000100 */
# define CAN_F4DATA1_FD8 CAN_F4DATA1_FD8_Msk /*!< Filter bit 8 */
# define CAN_F4DATA1_FD9_Pos (9U)
# define CAN_F4DATA1_FD9_Msk (0x1U << CAN_F4DATA1_FD9_Pos) /*!< 0x00000200 */
# define CAN_F4DATA1_FD9 CAN_F4DATA1_FD9_Msk /*!< Filter bit 9 */
# define CAN_F4DATA1_FD10_Pos (10U)
# define CAN_F4DATA1_FD10_Msk (0x1U << CAN_F4DATA1_FD10_Pos) /*!< 0x00000400 */
# define CAN_F4DATA1_FD10 CAN_F4DATA1_FD10_Msk /*!< Filter bit 10 */
# define CAN_F4DATA1_FD11_Pos (11U)
# define CAN_F4DATA1_FD11_Msk (0x1U << CAN_F4DATA1_FD11_Pos) /*!< 0x00000800 */
# define CAN_F4DATA1_FD11 CAN_F4DATA1_FD11_Msk /*!< Filter bit 11 */
# define CAN_F4DATA1_FD12_Pos (12U)
# define CAN_F4DATA1_FD12_Msk (0x1U << CAN_F4DATA1_FD12_Pos) /*!< 0x00001000 */
# define CAN_F4DATA1_FD12 CAN_F4DATA1_FD12_Msk /*!< Filter bit 12 */
# define CAN_F4DATA1_FD13_Pos (13U)
# define CAN_F4DATA1_FD13_Msk (0x1U << CAN_F4DATA1_FD13_Pos) /*!< 0x00002000 */
# define CAN_F4DATA1_FD13 CAN_F4DATA1_FD13_Msk /*!< Filter bit 13 */
# define CAN_F4DATA1_FD14_Pos (14U)
# define CAN_F4DATA1_FD14_Msk (0x1U << CAN_F4DATA1_FD14_Pos) /*!< 0x00004000 */
# define CAN_F4DATA1_FD14 CAN_F4DATA1_FD14_Msk /*!< Filter bit 14 */
# define CAN_F4DATA1_FD15_Pos (15U)
# define CAN_F4DATA1_FD15_Msk (0x1U << CAN_F4DATA1_FD15_Pos) /*!< 0x00008000 */
# define CAN_F4DATA1_FD15 CAN_F4DATA1_FD15_Msk /*!< Filter bit 15 */
# define CAN_F4DATA1_FD16_Pos (16U)
# define CAN_F4DATA1_FD16_Msk (0x1U << CAN_F4DATA1_FD16_Pos) /*!< 0x00010000 */
# define CAN_F4DATA1_FD16 CAN_F4DATA1_FD16_Msk /*!< Filter bit 16 */
# define CAN_F4DATA1_FD17_Pos (17U)
# define CAN_F4DATA1_FD17_Msk (0x1U << CAN_F4DATA1_FD17_Pos) /*!< 0x00020000 */
# define CAN_F4DATA1_FD17 CAN_F4DATA1_FD17_Msk /*!< Filter bit 17 */
# define CAN_F4DATA1_FD18_Pos (18U)
# define CAN_F4DATA1_FD18_Msk (0x1U << CAN_F4DATA1_FD18_Pos) /*!< 0x00040000 */
# define CAN_F4DATA1_FD18 CAN_F4DATA1_FD18_Msk /*!< Filter bit 18 */
# define CAN_F4DATA1_FD19_Pos (19U)
# define CAN_F4DATA1_FD19_Msk (0x1U << CAN_F4DATA1_FD19_Pos) /*!< 0x00080000 */
# define CAN_F4DATA1_FD19 CAN_F4DATA1_FD19_Msk /*!< Filter bit 19 */
# define CAN_F4DATA1_FD20_Pos (20U)
# define CAN_F4DATA1_FD20_Msk (0x1U << CAN_F4DATA1_FD20_Pos) /*!< 0x00100000 */
# define CAN_F4DATA1_FD20 CAN_F4DATA1_FD20_Msk /*!< Filter bit 20 */
# define CAN_F4DATA1_FD21_Pos (21U)
# define CAN_F4DATA1_FD21_Msk (0x1U << CAN_F4DATA1_FD21_Pos) /*!< 0x00200000 */
# define CAN_F4DATA1_FD21 CAN_F4DATA1_FD21_Msk /*!< Filter bit 21 */
# define CAN_F4DATA1_FD22_Pos (22U)
# define CAN_F4DATA1_FD22_Msk (0x1U << CAN_F4DATA1_FD22_Pos) /*!< 0x00400000 */
# define CAN_F4DATA1_FD22 CAN_F4DATA1_FD22_Msk /*!< Filter bit 22 */
# define CAN_F4DATA1_FD23_Pos (23U)
# define CAN_F4DATA1_FD23_Msk (0x1U << CAN_F4DATA1_FD23_Pos) /*!< 0x00800000 */
# define CAN_F4DATA1_FD23 CAN_F4DATA1_FD23_Msk /*!< Filter bit 23 */
# define CAN_F4DATA1_FD24_Pos (24U)
# define CAN_F4DATA1_FD24_Msk (0x1U << CAN_F4DATA1_FD24_Pos) /*!< 0x01000000 */
# define CAN_F4DATA1_FD24 CAN_F4DATA1_FD24_Msk /*!< Filter bit 24 */
# define CAN_F4DATA1_FD25_Pos (25U)
# define CAN_F4DATA1_FD25_Msk (0x1U << CAN_F4DATA1_FD25_Pos) /*!< 0x02000000 */
# define CAN_F4DATA1_FD25 CAN_F4DATA1_FD25_Msk /*!< Filter bit 25 */
# define CAN_F4DATA1_FD26_Pos (26U)
# define CAN_F4DATA1_FD26_Msk (0x1U << CAN_F4DATA1_FD26_Pos) /*!< 0x04000000 */
# define CAN_F4DATA1_FD26 CAN_F4DATA1_FD26_Msk /*!< Filter bit 26 */
# define CAN_F4DATA1_FD27_Pos (27U)
# define CAN_F4DATA1_FD27_Msk (0x1U << CAN_F4DATA1_FD27_Pos) /*!< 0x08000000 */
# define CAN_F4DATA1_FD27 CAN_F4DATA1_FD27_Msk /*!< Filter bit 27 */
# define CAN_F4DATA1_FD28_Pos (28U)
# define CAN_F4DATA1_FD28_Msk (0x1U << CAN_F4DATA1_FD28_Pos) /*!< 0x10000000 */
# define CAN_F4DATA1_FD28 CAN_F4DATA1_FD28_Msk /*!< Filter bit 28 */
# define CAN_F4DATA1_FD29_Pos (29U)
# define CAN_F4DATA1_FD29_Msk (0x1U << CAN_F4DATA1_FD29_Pos) /*!< 0x20000000 */
# define CAN_F4DATA1_FD29 CAN_F4DATA1_FD29_Msk /*!< Filter bit 29 */
# define CAN_F4DATA1_FD30_Pos (30U)
# define CAN_F4DATA1_FD30_Msk (0x1U << CAN_F4DATA1_FD30_Pos) /*!< 0x40000000 */
# define CAN_F4DATA1_FD30 CAN_F4DATA1_FD30_Msk /*!< Filter bit 30 */
# define CAN_F4DATA1_FD31_Pos (31U)
# define CAN_F4DATA1_FD31_Msk (0x1U << CAN_F4DATA1_FD31_Pos) /*!< 0x80000000 */
# define CAN_F4DATA1_FD31 CAN_F4DATA1_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F5R2 register *******************/
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# define CAN_F5DATA1_FD0_Pos (0U)
# define CAN_F5DATA1_FD0_Msk (0x1U << CAN_F5DATA1_FD0_Pos) /*!< 0x00000001 */
# define CAN_F5DATA1_FD0 CAN_F5DATA1_FD0_Msk /*!< Filter bit 0 */
# define CAN_F5DATA1_FD1_Pos (1U)
# define CAN_F5DATA1_FD1_Msk (0x1U << CAN_F5DATA1_FD1_Pos) /*!< 0x00000002 */
# define CAN_F5DATA1_FD1 CAN_F5DATA1_FD1_Msk /*!< Filter bit 1 */
# define CAN_F5DATA1_FD2_Pos (2U)
# define CAN_F5DATA1_FD2_Msk (0x1U << CAN_F5DATA1_FD2_Pos) /*!< 0x00000004 */
# define CAN_F5DATA1_FD2 CAN_F5DATA1_FD2_Msk /*!< Filter bit 2 */
# define CAN_F5DATA1_FD3_Pos (3U)
# define CAN_F5DATA1_FD3_Msk (0x1U << CAN_F5DATA1_FD3_Pos) /*!< 0x00000008 */
# define CAN_F5DATA1_FD3 CAN_F5DATA1_FD3_Msk /*!< Filter bit 3 */
# define CAN_F5DATA1_FD4_Pos (4U)
# define CAN_F5DATA1_FD4_Msk (0x1U << CAN_F5DATA1_FD4_Pos) /*!< 0x00000010 */
# define CAN_F5DATA1_FD4 CAN_F5DATA1_FD4_Msk /*!< Filter bit 4 */
# define CAN_F5DATA1_FD5_Pos (5U)
# define CAN_F5DATA1_FD5_Msk (0x1U << CAN_F5DATA1_FD5_Pos) /*!< 0x00000020 */
# define CAN_F5DATA1_FD5 CAN_F5DATA1_FD5_Msk /*!< Filter bit 5 */
# define CAN_F5DATA1_FD6_Pos (6U)
# define CAN_F5DATA1_FD6_Msk (0x1U << CAN_F5DATA1_FD6_Pos) /*!< 0x00000040 */
# define CAN_F5DATA1_FD6 CAN_F5DATA1_FD6_Msk /*!< Filter bit 6 */
# define CAN_F5DATA1_FD7_Pos (7U)
# define CAN_F5DATA1_FD7_Msk (0x1U << CAN_F5DATA1_FD7_Pos) /*!< 0x00000080 */
# define CAN_F5DATA1_FD7 CAN_F5DATA1_FD7_Msk /*!< Filter bit 7 */
# define CAN_F5DATA1_FD8_Pos (8U)
# define CAN_F5DATA1_FD8_Msk (0x1U << CAN_F5DATA1_FD8_Pos) /*!< 0x00000100 */
# define CAN_F5DATA1_FD8 CAN_F5DATA1_FD8_Msk /*!< Filter bit 8 */
# define CAN_F5DATA1_FD9_Pos (9U)
# define CAN_F5DATA1_FD9_Msk (0x1U << CAN_F5DATA1_FD9_Pos) /*!< 0x00000200 */
# define CAN_F5DATA1_FD9 CAN_F5DATA1_FD9_Msk /*!< Filter bit 9 */
# define CAN_F5DATA1_FD10_Pos (10U)
# define CAN_F5DATA1_FD10_Msk (0x1U << CAN_F5DATA1_FD10_Pos) /*!< 0x00000400 */
# define CAN_F5DATA1_FD10 CAN_F5DATA1_FD10_Msk /*!< Filter bit 10 */
# define CAN_F5DATA1_FD11_Pos (11U)
# define CAN_F5DATA1_FD11_Msk (0x1U << CAN_F5DATA1_FD11_Pos) /*!< 0x00000800 */
# define CAN_F5DATA1_FD11 CAN_F5DATA1_FD11_Msk /*!< Filter bit 11 */
# define CAN_F5DATA1_FD12_Pos (12U)
# define CAN_F5DATA1_FD12_Msk (0x1U << CAN_F5DATA1_FD12_Pos) /*!< 0x00001000 */
# define CAN_F5DATA1_FD12 CAN_F5DATA1_FD12_Msk /*!< Filter bit 12 */
# define CAN_F5DATA1_FD13_Pos (13U)
# define CAN_F5DATA1_FD13_Msk (0x1U << CAN_F5DATA1_FD13_Pos) /*!< 0x00002000 */
# define CAN_F5DATA1_FD13 CAN_F5DATA1_FD13_Msk /*!< Filter bit 13 */
# define CAN_F5DATA1_FD14_Pos (14U)
# define CAN_F5DATA1_FD14_Msk (0x1U << CAN_F5DATA1_FD14_Pos) /*!< 0x00004000 */
# define CAN_F5DATA1_FD14 CAN_F5DATA1_FD14_Msk /*!< Filter bit 14 */
# define CAN_F5DATA1_FD15_Pos (15U)
# define CAN_F5DATA1_FD15_Msk (0x1U << CAN_F5DATA1_FD15_Pos) /*!< 0x00008000 */
# define CAN_F5DATA1_FD15 CAN_F5DATA1_FD15_Msk /*!< Filter bit 15 */
# define CAN_F5DATA1_FD16_Pos (16U)
# define CAN_F5DATA1_FD16_Msk (0x1U << CAN_F5DATA1_FD16_Pos) /*!< 0x00010000 */
# define CAN_F5DATA1_FD16 CAN_F5DATA1_FD16_Msk /*!< Filter bit 16 */
# define CAN_F5DATA1_FD17_Pos (17U)
# define CAN_F5DATA1_FD17_Msk (0x1U << CAN_F5DATA1_FD17_Pos) /*!< 0x00020000 */
# define CAN_F5DATA1_FD17 CAN_F5DATA1_FD17_Msk /*!< Filter bit 17 */
# define CAN_F5DATA1_FD18_Pos (18U)
# define CAN_F5DATA1_FD18_Msk (0x1U << CAN_F5DATA1_FD18_Pos) /*!< 0x00040000 */
# define CAN_F5DATA1_FD18 CAN_F5DATA1_FD18_Msk /*!< Filter bit 18 */
# define CAN_F5DATA1_FD19_Pos (19U)
# define CAN_F5DATA1_FD19_Msk (0x1U << CAN_F5DATA1_FD19_Pos) /*!< 0x00080000 */
# define CAN_F5DATA1_FD19 CAN_F5DATA1_FD19_Msk /*!< Filter bit 19 */
# define CAN_F5DATA1_FD20_Pos (20U)
# define CAN_F5DATA1_FD20_Msk (0x1U << CAN_F5DATA1_FD20_Pos) /*!< 0x00100000 */
# define CAN_F5DATA1_FD20 CAN_F5DATA1_FD20_Msk /*!< Filter bit 20 */
# define CAN_F5DATA1_FD21_Pos (21U)
# define CAN_F5DATA1_FD21_Msk (0x1U << CAN_F5DATA1_FD21_Pos) /*!< 0x00200000 */
# define CAN_F5DATA1_FD21 CAN_F5DATA1_FD21_Msk /*!< Filter bit 21 */
# define CAN_F5DATA1_FD22_Pos (22U)
# define CAN_F5DATA1_FD22_Msk (0x1U << CAN_F5DATA1_FD22_Pos) /*!< 0x00400000 */
# define CAN_F5DATA1_FD22 CAN_F5DATA1_FD22_Msk /*!< Filter bit 22 */
# define CAN_F5DATA1_FD23_Pos (23U)
# define CAN_F5DATA1_FD23_Msk (0x1U << CAN_F5DATA1_FD23_Pos) /*!< 0x00800000 */
# define CAN_F5DATA1_FD23 CAN_F5DATA1_FD23_Msk /*!< Filter bit 23 */
# define CAN_F5DATA1_FD24_Pos (24U)
# define CAN_F5DATA1_FD24_Msk (0x1U << CAN_F5DATA1_FD24_Pos) /*!< 0x01000000 */
# define CAN_F5DATA1_FD24 CAN_F5DATA1_FD24_Msk /*!< Filter bit 24 */
# define CAN_F5DATA1_FD25_Pos (25U)
# define CAN_F5DATA1_FD25_Msk (0x1U << CAN_F5DATA1_FD25_Pos) /*!< 0x02000000 */
# define CAN_F5DATA1_FD25 CAN_F5DATA1_FD25_Msk /*!< Filter bit 25 */
# define CAN_F5DATA1_FD26_Pos (26U)
# define CAN_F5DATA1_FD26_Msk (0x1U << CAN_F5DATA1_FD26_Pos) /*!< 0x04000000 */
# define CAN_F5DATA1_FD26 CAN_F5DATA1_FD26_Msk /*!< Filter bit 26 */
# define CAN_F5DATA1_FD27_Pos (27U)
# define CAN_F5DATA1_FD27_Msk (0x1U << CAN_F5DATA1_FD27_Pos) /*!< 0x08000000 */
# define CAN_F5DATA1_FD27 CAN_F5DATA1_FD27_Msk /*!< Filter bit 27 */
# define CAN_F5DATA1_FD28_Pos (28U)
# define CAN_F5DATA1_FD28_Msk (0x1U << CAN_F5DATA1_FD28_Pos) /*!< 0x10000000 */
# define CAN_F5DATA1_FD28 CAN_F5DATA1_FD28_Msk /*!< Filter bit 28 */
# define CAN_F5DATA1_FD29_Pos (29U)
# define CAN_F5DATA1_FD29_Msk (0x1U << CAN_F5DATA1_FD29_Pos) /*!< 0x20000000 */
# define CAN_F5DATA1_FD29 CAN_F5DATA1_FD29_Msk /*!< Filter bit 29 */
# define CAN_F5DATA1_FD30_Pos (30U)
# define CAN_F5DATA1_FD30_Msk (0x1U << CAN_F5DATA1_FD30_Pos) /*!< 0x40000000 */
# define CAN_F5DATA1_FD30 CAN_F5DATA1_FD30_Msk /*!< Filter bit 30 */
# define CAN_F5DATA1_FD31_Pos (31U)
# define CAN_F5DATA1_FD31_Msk (0x1U << CAN_F5DATA1_FD31_Pos) /*!< 0x80000000 */
# define CAN_F5DATA1_FD31 CAN_F5DATA1_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F6R2 register *******************/
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# define CAN_F6DATA1_FD0_Pos (0U)
# define CAN_F6DATA1_FD0_Msk (0x1U << CAN_F6DATA1_FD0_Pos) /*!< 0x00000001 */
# define CAN_F6DATA1_FD0 CAN_F6DATA1_FD0_Msk /*!< Filter bit 0 */
# define CAN_F6DATA1_FD1_Pos (1U)
# define CAN_F6DATA1_FD1_Msk (0x1U << CAN_F6DATA1_FD1_Pos) /*!< 0x00000002 */
# define CAN_F6DATA1_FD1 CAN_F6DATA1_FD1_Msk /*!< Filter bit 1 */
# define CAN_F6DATA1_FD2_Pos (2U)
# define CAN_F6DATA1_FD2_Msk (0x1U << CAN_F6DATA1_FD2_Pos) /*!< 0x00000004 */
# define CAN_F6DATA1_FD2 CAN_F6DATA1_FD2_Msk /*!< Filter bit 2 */
# define CAN_F6DATA1_FD3_Pos (3U)
# define CAN_F6DATA1_FD3_Msk (0x1U << CAN_F6DATA1_FD3_Pos) /*!< 0x00000008 */
# define CAN_F6DATA1_FD3 CAN_F6DATA1_FD3_Msk /*!< Filter bit 3 */
# define CAN_F6DATA1_FD4_Pos (4U)
# define CAN_F6DATA1_FD4_Msk (0x1U << CAN_F6DATA1_FD4_Pos) /*!< 0x00000010 */
# define CAN_F6DATA1_FD4 CAN_F6DATA1_FD4_Msk /*!< Filter bit 4 */
# define CAN_F6DATA1_FD5_Pos (5U)
# define CAN_F6DATA1_FD5_Msk (0x1U << CAN_F6DATA1_FD5_Pos) /*!< 0x00000020 */
# define CAN_F6DATA1_FD5 CAN_F6DATA1_FD5_Msk /*!< Filter bit 5 */
# define CAN_F6DATA1_FD6_Pos (6U)
# define CAN_F6DATA1_FD6_Msk (0x1U << CAN_F6DATA1_FD6_Pos) /*!< 0x00000040 */
# define CAN_F6DATA1_FD6 CAN_F6DATA1_FD6_Msk /*!< Filter bit 6 */
# define CAN_F6DATA1_FD7_Pos (7U)
# define CAN_F6DATA1_FD7_Msk (0x1U << CAN_F6DATA1_FD7_Pos) /*!< 0x00000080 */
# define CAN_F6DATA1_FD7 CAN_F6DATA1_FD7_Msk /*!< Filter bit 7 */
# define CAN_F6DATA1_FD8_Pos (8U)
# define CAN_F6DATA1_FD8_Msk (0x1U << CAN_F6DATA1_FD8_Pos) /*!< 0x00000100 */
# define CAN_F6DATA1_FD8 CAN_F6DATA1_FD8_Msk /*!< Filter bit 8 */
# define CAN_F6DATA1_FD9_Pos (9U)
# define CAN_F6DATA1_FD9_Msk (0x1U << CAN_F6DATA1_FD9_Pos) /*!< 0x00000200 */
# define CAN_F6DATA1_FD9 CAN_F6DATA1_FD9_Msk /*!< Filter bit 9 */
# define CAN_F6DATA1_FD10_Pos (10U)
# define CAN_F6DATA1_FD10_Msk (0x1U << CAN_F6DATA1_FD10_Pos) /*!< 0x00000400 */
# define CAN_F6DATA1_FD10 CAN_F6DATA1_FD10_Msk /*!< Filter bit 10 */
# define CAN_F6DATA1_FD11_Pos (11U)
# define CAN_F6DATA1_FD11_Msk (0x1U << CAN_F6DATA1_FD11_Pos) /*!< 0x00000800 */
# define CAN_F6DATA1_FD11 CAN_F6DATA1_FD11_Msk /*!< Filter bit 11 */
# define CAN_F6DATA1_FD12_Pos (12U)
# define CAN_F6DATA1_FD12_Msk (0x1U << CAN_F6DATA1_FD12_Pos) /*!< 0x00001000 */
# define CAN_F6DATA1_FD12 CAN_F6DATA1_FD12_Msk /*!< Filter bit 12 */
# define CAN_F6DATA1_FD13_Pos (13U)
# define CAN_F6DATA1_FD13_Msk (0x1U << CAN_F6DATA1_FD13_Pos) /*!< 0x00002000 */
# define CAN_F6DATA1_FD13 CAN_F6DATA1_FD13_Msk /*!< Filter bit 13 */
# define CAN_F6DATA1_FD14_Pos (14U)
# define CAN_F6DATA1_FD14_Msk (0x1U << CAN_F6DATA1_FD14_Pos) /*!< 0x00004000 */
# define CAN_F6DATA1_FD14 CAN_F6DATA1_FD14_Msk /*!< Filter bit 14 */
# define CAN_F6DATA1_FD15_Pos (15U)
# define CAN_F6DATA1_FD15_Msk (0x1U << CAN_F6DATA1_FD15_Pos) /*!< 0x00008000 */
# define CAN_F6DATA1_FD15 CAN_F6DATA1_FD15_Msk /*!< Filter bit 15 */
# define CAN_F6DATA1_FD16_Pos (16U)
# define CAN_F6DATA1_FD16_Msk (0x1U << CAN_F6DATA1_FD16_Pos) /*!< 0x00010000 */
# define CAN_F6DATA1_FD16 CAN_F6DATA1_FD16_Msk /*!< Filter bit 16 */
# define CAN_F6DATA1_FD17_Pos (17U)
# define CAN_F6DATA1_FD17_Msk (0x1U << CAN_F6DATA1_FD17_Pos) /*!< 0x00020000 */
# define CAN_F6DATA1_FD17 CAN_F6DATA1_FD17_Msk /*!< Filter bit 17 */
# define CAN_F6DATA1_FD18_Pos (18U)
# define CAN_F6DATA1_FD18_Msk (0x1U << CAN_F6DATA1_FD18_Pos) /*!< 0x00040000 */
# define CAN_F6DATA1_FD18 CAN_F6DATA1_FD18_Msk /*!< Filter bit 18 */
# define CAN_F6DATA1_FD19_Pos (19U)
# define CAN_F6DATA1_FD19_Msk (0x1U << CAN_F6DATA1_FD19_Pos) /*!< 0x00080000 */
# define CAN_F6DATA1_FD19 CAN_F6DATA1_FD19_Msk /*!< Filter bit 19 */
# define CAN_F6DATA1_FD20_Pos (20U)
# define CAN_F6DATA1_FD20_Msk (0x1U << CAN_F6DATA1_FD20_Pos) /*!< 0x00100000 */
# define CAN_F6DATA1_FD20 CAN_F6DATA1_FD20_Msk /*!< Filter bit 20 */
# define CAN_F6DATA1_FD21_Pos (21U)
# define CAN_F6DATA1_FD21_Msk (0x1U << CAN_F6DATA1_FD21_Pos) /*!< 0x00200000 */
# define CAN_F6DATA1_FD21 CAN_F6DATA1_FD21_Msk /*!< Filter bit 21 */
# define CAN_F6DATA1_FD22_Pos (22U)
# define CAN_F6DATA1_FD22_Msk (0x1U << CAN_F6DATA1_FD22_Pos) /*!< 0x00400000 */
# define CAN_F6DATA1_FD22 CAN_F6DATA1_FD22_Msk /*!< Filter bit 22 */
# define CAN_F6DATA1_FD23_Pos (23U)
# define CAN_F6DATA1_FD23_Msk (0x1U << CAN_F6DATA1_FD23_Pos) /*!< 0x00800000 */
# define CAN_F6DATA1_FD23 CAN_F6DATA1_FD23_Msk /*!< Filter bit 23 */
# define CAN_F6DATA1_FD24_Pos (24U)
# define CAN_F6DATA1_FD24_Msk (0x1U << CAN_F6DATA1_FD24_Pos) /*!< 0x01000000 */
# define CAN_F6DATA1_FD24 CAN_F6DATA1_FD24_Msk /*!< Filter bit 24 */
# define CAN_F6DATA1_FD25_Pos (25U)
# define CAN_F6DATA1_FD25_Msk (0x1U << CAN_F6DATA1_FD25_Pos) /*!< 0x02000000 */
# define CAN_F6DATA1_FD25 CAN_F6DATA1_FD25_Msk /*!< Filter bit 25 */
# define CAN_F6DATA1_FD26_Pos (26U)
# define CAN_F6DATA1_FD26_Msk (0x1U << CAN_F6DATA1_FD26_Pos) /*!< 0x04000000 */
# define CAN_F6DATA1_FD26 CAN_F6DATA1_FD26_Msk /*!< Filter bit 26 */
# define CAN_F6DATA1_FD27_Pos (27U)
# define CAN_F6DATA1_FD27_Msk (0x1U << CAN_F6DATA1_FD27_Pos) /*!< 0x08000000 */
# define CAN_F6DATA1_FD27 CAN_F6DATA1_FD27_Msk /*!< Filter bit 27 */
# define CAN_F6DATA1_FD28_Pos (28U)
# define CAN_F6DATA1_FD28_Msk (0x1U << CAN_F6DATA1_FD28_Pos) /*!< 0x10000000 */
# define CAN_F6DATA1_FD28 CAN_F6DATA1_FD28_Msk /*!< Filter bit 28 */
# define CAN_F6DATA1_FD29_Pos (29U)
# define CAN_F6DATA1_FD29_Msk (0x1U << CAN_F6DATA1_FD29_Pos) /*!< 0x20000000 */
# define CAN_F6DATA1_FD29 CAN_F6DATA1_FD29_Msk /*!< Filter bit 29 */
# define CAN_F6DATA1_FD30_Pos (30U)
# define CAN_F6DATA1_FD30_Msk (0x1U << CAN_F6DATA1_FD30_Pos) /*!< 0x40000000 */
# define CAN_F6DATA1_FD30 CAN_F6DATA1_FD30_Msk /*!< Filter bit 30 */
# define CAN_F6DATA1_FD31_Pos (31U)
# define CAN_F6DATA1_FD31_Msk (0x1U << CAN_F6DATA1_FD31_Pos) /*!< 0x80000000 */
# define CAN_F6DATA1_FD31 CAN_F6DATA1_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F7R2 register *******************/
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# define CAN_F7DATA1_FD0_Pos (0U)
# define CAN_F7DATA1_FD0_Msk (0x1U << CAN_F7DATA1_FD0_Pos) /*!< 0x00000001 */
# define CAN_F7DATA1_FD0 CAN_F7DATA1_FD0_Msk /*!< Filter bit 0 */
# define CAN_F7DATA1_FD1_Pos (1U)
# define CAN_F7DATA1_FD1_Msk (0x1U << CAN_F7DATA1_FD1_Pos) /*!< 0x00000002 */
# define CAN_F7DATA1_FD1 CAN_F7DATA1_FD1_Msk /*!< Filter bit 1 */
# define CAN_F7DATA1_FD2_Pos (2U)
# define CAN_F7DATA1_FD2_Msk (0x1U << CAN_F7DATA1_FD2_Pos) /*!< 0x00000004 */
# define CAN_F7DATA1_FD2 CAN_F7DATA1_FD2_Msk /*!< Filter bit 2 */
# define CAN_F7DATA1_FD3_Pos (3U)
# define CAN_F7DATA1_FD3_Msk (0x1U << CAN_F7DATA1_FD3_Pos) /*!< 0x00000008 */
# define CAN_F7DATA1_FD3 CAN_F7DATA1_FD3_Msk /*!< Filter bit 3 */
# define CAN_F7DATA1_FD4_Pos (4U)
# define CAN_F7DATA1_FD4_Msk (0x1U << CAN_F7DATA1_FD4_Pos) /*!< 0x00000010 */
# define CAN_F7DATA1_FD4 CAN_F7DATA1_FD4_Msk /*!< Filter bit 4 */
# define CAN_F7DATA1_FD5_Pos (5U)
# define CAN_F7DATA1_FD5_Msk (0x1U << CAN_F7DATA1_FD5_Pos) /*!< 0x00000020 */
# define CAN_F7DATA1_FD5 CAN_F7DATA1_FD5_Msk /*!< Filter bit 5 */
# define CAN_F7DATA1_FD6_Pos (6U)
# define CAN_F7DATA1_FD6_Msk (0x1U << CAN_F7DATA1_FD6_Pos) /*!< 0x00000040 */
# define CAN_F7DATA1_FD6 CAN_F7DATA1_FD6_Msk /*!< Filter bit 6 */
# define CAN_F7DATA1_FD7_Pos (7U)
# define CAN_F7DATA1_FD7_Msk (0x1U << CAN_F7DATA1_FD7_Pos) /*!< 0x00000080 */
# define CAN_F7DATA1_FD7 CAN_F7DATA1_FD7_Msk /*!< Filter bit 7 */
# define CAN_F7DATA1_FD8_Pos (8U)
# define CAN_F7DATA1_FD8_Msk (0x1U << CAN_F7DATA1_FD8_Pos) /*!< 0x00000100 */
# define CAN_F7DATA1_FD8 CAN_F7DATA1_FD8_Msk /*!< Filter bit 8 */
# define CAN_F7DATA1_FD9_Pos (9U)
# define CAN_F7DATA1_FD9_Msk (0x1U << CAN_F7DATA1_FD9_Pos) /*!< 0x00000200 */
# define CAN_F7DATA1_FD9 CAN_F7DATA1_FD9_Msk /*!< Filter bit 9 */
# define CAN_F7DATA1_FD10_Pos (10U)
# define CAN_F7DATA1_FD10_Msk (0x1U << CAN_F7DATA1_FD10_Pos) /*!< 0x00000400 */
# define CAN_F7DATA1_FD10 CAN_F7DATA1_FD10_Msk /*!< Filter bit 10 */
# define CAN_F7DATA1_FD11_Pos (11U)
# define CAN_F7DATA1_FD11_Msk (0x1U << CAN_F7DATA1_FD11_Pos) /*!< 0x00000800 */
# define CAN_F7DATA1_FD11 CAN_F7DATA1_FD11_Msk /*!< Filter bit 11 */
# define CAN_F7DATA1_FD12_Pos (12U)
# define CAN_F7DATA1_FD12_Msk (0x1U << CAN_F7DATA1_FD12_Pos) /*!< 0x00001000 */
# define CAN_F7DATA1_FD12 CAN_F7DATA1_FD12_Msk /*!< Filter bit 12 */
# define CAN_F7DATA1_FD13_Pos (13U)
# define CAN_F7DATA1_FD13_Msk (0x1U << CAN_F7DATA1_FD13_Pos) /*!< 0x00002000 */
# define CAN_F7DATA1_FD13 CAN_F7DATA1_FD13_Msk /*!< Filter bit 13 */
# define CAN_F7DATA1_FD14_Pos (14U)
# define CAN_F7DATA1_FD14_Msk (0x1U << CAN_F7DATA1_FD14_Pos) /*!< 0x00004000 */
# define CAN_F7DATA1_FD14 CAN_F7DATA1_FD14_Msk /*!< Filter bit 14 */
# define CAN_F7DATA1_FD15_Pos (15U)
# define CAN_F7DATA1_FD15_Msk (0x1U << CAN_F7DATA1_FD15_Pos) /*!< 0x00008000 */
# define CAN_F7DATA1_FD15 CAN_F7DATA1_FD15_Msk /*!< Filter bit 15 */
# define CAN_F7DATA1_FD16_Pos (16U)
# define CAN_F7DATA1_FD16_Msk (0x1U << CAN_F7DATA1_FD16_Pos) /*!< 0x00010000 */
# define CAN_F7DATA1_FD16 CAN_F7DATA1_FD16_Msk /*!< Filter bit 16 */
# define CAN_F7DATA1_FD17_Pos (17U)
# define CAN_F7DATA1_FD17_Msk (0x1U << CAN_F7DATA1_FD17_Pos) /*!< 0x00020000 */
# define CAN_F7DATA1_FD17 CAN_F7DATA1_FD17_Msk /*!< Filter bit 17 */
# define CAN_F7DATA1_FD18_Pos (18U)
# define CAN_F7DATA1_FD18_Msk (0x1U << CAN_F7DATA1_FD18_Pos) /*!< 0x00040000 */
# define CAN_F7DATA1_FD18 CAN_F7DATA1_FD18_Msk /*!< Filter bit 18 */
# define CAN_F7DATA1_FD19_Pos (19U)
# define CAN_F7DATA1_FD19_Msk (0x1U << CAN_F7DATA1_FD19_Pos) /*!< 0x00080000 */
# define CAN_F7DATA1_FD19 CAN_F7DATA1_FD19_Msk /*!< Filter bit 19 */
# define CAN_F7DATA1_FD20_Pos (20U)
# define CAN_F7DATA1_FD20_Msk (0x1U << CAN_F7DATA1_FD20_Pos) /*!< 0x00100000 */
# define CAN_F7DATA1_FD20 CAN_F7DATA1_FD20_Msk /*!< Filter bit 20 */
# define CAN_F7DATA1_FD21_Pos (21U)
# define CAN_F7DATA1_FD21_Msk (0x1U << CAN_F7DATA1_FD21_Pos) /*!< 0x00200000 */
# define CAN_F7DATA1_FD21 CAN_F7DATA1_FD21_Msk /*!< Filter bit 21 */
# define CAN_F7DATA1_FD22_Pos (22U)
# define CAN_F7DATA1_FD22_Msk (0x1U << CAN_F7DATA1_FD22_Pos) /*!< 0x00400000 */
# define CAN_F7DATA1_FD22 CAN_F7DATA1_FD22_Msk /*!< Filter bit 22 */
# define CAN_F7DATA1_FD23_Pos (23U)
# define CAN_F7DATA1_FD23_Msk (0x1U << CAN_F7DATA1_FD23_Pos) /*!< 0x00800000 */
# define CAN_F7DATA1_FD23 CAN_F7DATA1_FD23_Msk /*!< Filter bit 23 */
# define CAN_F7DATA1_FD24_Pos (24U)
# define CAN_F7DATA1_FD24_Msk (0x1U << CAN_F7DATA1_FD24_Pos) /*!< 0x01000000 */
# define CAN_F7DATA1_FD24 CAN_F7DATA1_FD24_Msk /*!< Filter bit 24 */
# define CAN_F7DATA1_FD25_Pos (25U)
# define CAN_F7DATA1_FD25_Msk (0x1U << CAN_F7DATA1_FD25_Pos) /*!< 0x02000000 */
# define CAN_F7DATA1_FD25 CAN_F7DATA1_FD25_Msk /*!< Filter bit 25 */
# define CAN_F7DATA1_FD26_Pos (26U)
# define CAN_F7DATA1_FD26_Msk (0x1U << CAN_F7DATA1_FD26_Pos) /*!< 0x04000000 */
# define CAN_F7DATA1_FD26 CAN_F7DATA1_FD26_Msk /*!< Filter bit 26 */
# define CAN_F7DATA1_FD27_Pos (27U)
# define CAN_F7DATA1_FD27_Msk (0x1U << CAN_F7DATA1_FD27_Pos) /*!< 0x08000000 */
# define CAN_F7DATA1_FD27 CAN_F7DATA1_FD27_Msk /*!< Filter bit 27 */
# define CAN_F7DATA1_FD28_Pos (28U)
# define CAN_F7DATA1_FD28_Msk (0x1U << CAN_F7DATA1_FD28_Pos) /*!< 0x10000000 */
# define CAN_F7DATA1_FD28 CAN_F7DATA1_FD28_Msk /*!< Filter bit 28 */
# define CAN_F7DATA1_FD29_Pos (29U)
# define CAN_F7DATA1_FD29_Msk (0x1U << CAN_F7DATA1_FD29_Pos) /*!< 0x20000000 */
# define CAN_F7DATA1_FD29 CAN_F7DATA1_FD29_Msk /*!< Filter bit 29 */
# define CAN_F7DATA1_FD30_Pos (30U)
# define CAN_F7DATA1_FD30_Msk (0x1U << CAN_F7DATA1_FD30_Pos) /*!< 0x40000000 */
# define CAN_F7DATA1_FD30 CAN_F7DATA1_FD30_Msk /*!< Filter bit 30 */
# define CAN_F7DATA1_FD31_Pos (31U)
# define CAN_F7DATA1_FD31_Msk (0x1U << CAN_F7DATA1_FD31_Pos) /*!< 0x80000000 */
# define CAN_F7DATA1_FD31 CAN_F7DATA1_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F8R2 register *******************/
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# define CAN_F8DATA1_FD0_Pos (0U)
# define CAN_F8DATA1_FD0_Msk (0x1U << CAN_F8DATA1_FD0_Pos) /*!< 0x00000001 */
# define CAN_F8DATA1_FD0 CAN_F8DATA1_FD0_Msk /*!< Filter bit 0 */
# define CAN_F8DATA1_FD1_Pos (1U)
# define CAN_F8DATA1_FD1_Msk (0x1U << CAN_F8DATA1_FD1_Pos) /*!< 0x00000002 */
# define CAN_F8DATA1_FD1 CAN_F8DATA1_FD1_Msk /*!< Filter bit 1 */
# define CAN_F8DATA1_FD2_Pos (2U)
# define CAN_F8DATA1_FD2_Msk (0x1U << CAN_F8DATA1_FD2_Pos) /*!< 0x00000004 */
# define CAN_F8DATA1_FD2 CAN_F8DATA1_FD2_Msk /*!< Filter bit 2 */
# define CAN_F8DATA1_FD3_Pos (3U)
# define CAN_F8DATA1_FD3_Msk (0x1U << CAN_F8DATA1_FD3_Pos) /*!< 0x00000008 */
# define CAN_F8DATA1_FD3 CAN_F8DATA1_FD3_Msk /*!< Filter bit 3 */
# define CAN_F8DATA1_FD4_Pos (4U)
# define CAN_F8DATA1_FD4_Msk (0x1U << CAN_F8DATA1_FD4_Pos) /*!< 0x00000010 */
# define CAN_F8DATA1_FD4 CAN_F8DATA1_FD4_Msk /*!< Filter bit 4 */
# define CAN_F8DATA1_FD5_Pos (5U)
# define CAN_F8DATA1_FD5_Msk (0x1U << CAN_F8DATA1_FD5_Pos) /*!< 0x00000020 */
# define CAN_F8DATA1_FD5 CAN_F8DATA1_FD5_Msk /*!< Filter bit 5 */
# define CAN_F8DATA1_FD6_Pos (6U)
# define CAN_F8DATA1_FD6_Msk (0x1U << CAN_F8DATA1_FD6_Pos) /*!< 0x00000040 */
# define CAN_F8DATA1_FD6 CAN_F8DATA1_FD6_Msk /*!< Filter bit 6 */
# define CAN_F8DATA1_FD7_Pos (7U)
# define CAN_F8DATA1_FD7_Msk (0x1U << CAN_F8DATA1_FD7_Pos) /*!< 0x00000080 */
# define CAN_F8DATA1_FD7 CAN_F8DATA1_FD7_Msk /*!< Filter bit 7 */
# define CAN_F8DATA1_FD8_Pos (8U)
# define CAN_F8DATA1_FD8_Msk (0x1U << CAN_F8DATA1_FD8_Pos) /*!< 0x00000100 */
# define CAN_F8DATA1_FD8 CAN_F8DATA1_FD8_Msk /*!< Filter bit 8 */
# define CAN_F8DATA1_FD9_Pos (9U)
# define CAN_F8DATA1_FD9_Msk (0x1U << CAN_F8DATA1_FD9_Pos) /*!< 0x00000200 */
# define CAN_F8DATA1_FD9 CAN_F8DATA1_FD9_Msk /*!< Filter bit 9 */
# define CAN_F8DATA1_FD10_Pos (10U)
# define CAN_F8DATA1_FD10_Msk (0x1U << CAN_F8DATA1_FD10_Pos) /*!< 0x00000400 */
# define CAN_F8DATA1_FD10 CAN_F8DATA1_FD10_Msk /*!< Filter bit 10 */
# define CAN_F8DATA1_FD11_Pos (11U)
# define CAN_F8DATA1_FD11_Msk (0x1U << CAN_F8DATA1_FD11_Pos) /*!< 0x00000800 */
# define CAN_F8DATA1_FD11 CAN_F8DATA1_FD11_Msk /*!< Filter bit 11 */
# define CAN_F8DATA1_FD12_Pos (12U)
# define CAN_F8DATA1_FD12_Msk (0x1U << CAN_F8DATA1_FD12_Pos) /*!< 0x00001000 */
# define CAN_F8DATA1_FD12 CAN_F8DATA1_FD12_Msk /*!< Filter bit 12 */
# define CAN_F8DATA1_FD13_Pos (13U)
# define CAN_F8DATA1_FD13_Msk (0x1U << CAN_F8DATA1_FD13_Pos) /*!< 0x00002000 */
# define CAN_F8DATA1_FD13 CAN_F8DATA1_FD13_Msk /*!< Filter bit 13 */
# define CAN_F8DATA1_FD14_Pos (14U)
# define CAN_F8DATA1_FD14_Msk (0x1U << CAN_F8DATA1_FD14_Pos) /*!< 0x00004000 */
# define CAN_F8DATA1_FD14 CAN_F8DATA1_FD14_Msk /*!< Filter bit 14 */
# define CAN_F8DATA1_FD15_Pos (15U)
# define CAN_F8DATA1_FD15_Msk (0x1U << CAN_F8DATA1_FD15_Pos) /*!< 0x00008000 */
# define CAN_F8DATA1_FD15 CAN_F8DATA1_FD15_Msk /*!< Filter bit 15 */
# define CAN_F8DATA1_FD16_Pos (16U)
# define CAN_F8DATA1_FD16_Msk (0x1U << CAN_F8DATA1_FD16_Pos) /*!< 0x00010000 */
# define CAN_F8DATA1_FD16 CAN_F8DATA1_FD16_Msk /*!< Filter bit 16 */
# define CAN_F8DATA1_FD17_Pos (17U)
# define CAN_F8DATA1_FD17_Msk (0x1U << CAN_F8DATA1_FD17_Pos) /*!< 0x00020000 */
# define CAN_F8DATA1_FD17 CAN_F8DATA1_FD17_Msk /*!< Filter bit 17 */
# define CAN_F8DATA1_FD18_Pos (18U)
# define CAN_F8DATA1_FD18_Msk (0x1U << CAN_F8DATA1_FD18_Pos) /*!< 0x00040000 */
# define CAN_F8DATA1_FD18 CAN_F8DATA1_FD18_Msk /*!< Filter bit 18 */
# define CAN_F8DATA1_FD19_Pos (19U)
# define CAN_F8DATA1_FD19_Msk (0x1U << CAN_F8DATA1_FD19_Pos) /*!< 0x00080000 */
# define CAN_F8DATA1_FD19 CAN_F8DATA1_FD19_Msk /*!< Filter bit 19 */
# define CAN_F8DATA1_FD20_Pos (20U)
# define CAN_F8DATA1_FD20_Msk (0x1U << CAN_F8DATA1_FD20_Pos) /*!< 0x00100000 */
# define CAN_F8DATA1_FD20 CAN_F8DATA1_FD20_Msk /*!< Filter bit 20 */
# define CAN_F8DATA1_FD21_Pos (21U)
# define CAN_F8DATA1_FD21_Msk (0x1U << CAN_F8DATA1_FD21_Pos) /*!< 0x00200000 */
# define CAN_F8DATA1_FD21 CAN_F8DATA1_FD21_Msk /*!< Filter bit 21 */
# define CAN_F8DATA1_FD22_Pos (22U)
# define CAN_F8DATA1_FD22_Msk (0x1U << CAN_F8DATA1_FD22_Pos) /*!< 0x00400000 */
# define CAN_F8DATA1_FD22 CAN_F8DATA1_FD22_Msk /*!< Filter bit 22 */
# define CAN_F8DATA1_FD23_Pos (23U)
# define CAN_F8DATA1_FD23_Msk (0x1U << CAN_F8DATA1_FD23_Pos) /*!< 0x00800000 */
# define CAN_F8DATA1_FD23 CAN_F8DATA1_FD23_Msk /*!< Filter bit 23 */
# define CAN_F8DATA1_FD24_Pos (24U)
# define CAN_F8DATA1_FD24_Msk (0x1U << CAN_F8DATA1_FD24_Pos) /*!< 0x01000000 */
# define CAN_F8DATA1_FD24 CAN_F8DATA1_FD24_Msk /*!< Filter bit 24 */
# define CAN_F8DATA1_FD25_Pos (25U)
# define CAN_F8DATA1_FD25_Msk (0x1U << CAN_F8DATA1_FD25_Pos) /*!< 0x02000000 */
# define CAN_F8DATA1_FD25 CAN_F8DATA1_FD25_Msk /*!< Filter bit 25 */
# define CAN_F8DATA1_FD26_Pos (26U)
# define CAN_F8DATA1_FD26_Msk (0x1U << CAN_F8DATA1_FD26_Pos) /*!< 0x04000000 */
# define CAN_F8DATA1_FD26 CAN_F8DATA1_FD26_Msk /*!< Filter bit 26 */
# define CAN_F8DATA1_FD27_Pos (27U)
# define CAN_F8DATA1_FD27_Msk (0x1U << CAN_F8DATA1_FD27_Pos) /*!< 0x08000000 */
# define CAN_F8DATA1_FD27 CAN_F8DATA1_FD27_Msk /*!< Filter bit 27 */
# define CAN_F8DATA1_FD28_Pos (28U)
# define CAN_F8DATA1_FD28_Msk (0x1U << CAN_F8DATA1_FD28_Pos) /*!< 0x10000000 */
# define CAN_F8DATA1_FD28 CAN_F8DATA1_FD28_Msk /*!< Filter bit 28 */
# define CAN_F8DATA1_FD29_Pos (29U)
# define CAN_F8DATA1_FD29_Msk (0x1U << CAN_F8DATA1_FD29_Pos) /*!< 0x20000000 */
# define CAN_F8DATA1_FD29 CAN_F8DATA1_FD29_Msk /*!< Filter bit 29 */
# define CAN_F8DATA1_FD30_Pos (30U)
# define CAN_F8DATA1_FD30_Msk (0x1U << CAN_F8DATA1_FD30_Pos) /*!< 0x40000000 */
# define CAN_F8DATA1_FD30 CAN_F8DATA1_FD30_Msk /*!< Filter bit 30 */
# define CAN_F8DATA1_FD31_Pos (31U)
# define CAN_F8DATA1_FD31_Msk (0x1U << CAN_F8DATA1_FD31_Pos) /*!< 0x80000000 */
# define CAN_F8DATA1_FD31 CAN_F8DATA1_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F9R2 register *******************/
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# define CAN_F9DATA1_FD0_Pos (0U)
# define CAN_F9DATA1_FD0_Msk (0x1U << CAN_F9DATA1_FD0_Pos) /*!< 0x00000001 */
# define CAN_F9DATA1_FD0 CAN_F9DATA1_FD0_Msk /*!< Filter bit 0 */
# define CAN_F9DATA1_FD1_Pos (1U)
# define CAN_F9DATA1_FD1_Msk (0x1U << CAN_F9DATA1_FD1_Pos) /*!< 0x00000002 */
# define CAN_F9DATA1_FD1 CAN_F9DATA1_FD1_Msk /*!< Filter bit 1 */
# define CAN_F9DATA1_FD2_Pos (2U)
# define CAN_F9DATA1_FD2_Msk (0x1U << CAN_F9DATA1_FD2_Pos) /*!< 0x00000004 */
# define CAN_F9DATA1_FD2 CAN_F9DATA1_FD2_Msk /*!< Filter bit 2 */
# define CAN_F9DATA1_FD3_Pos (3U)
# define CAN_F9DATA1_FD3_Msk (0x1U << CAN_F9DATA1_FD3_Pos) /*!< 0x00000008 */
# define CAN_F9DATA1_FD3 CAN_F9DATA1_FD3_Msk /*!< Filter bit 3 */
# define CAN_F9DATA1_FD4_Pos (4U)
# define CAN_F9DATA1_FD4_Msk (0x1U << CAN_F9DATA1_FD4_Pos) /*!< 0x00000010 */
# define CAN_F9DATA1_FD4 CAN_F9DATA1_FD4_Msk /*!< Filter bit 4 */
# define CAN_F9DATA1_FD5_Pos (5U)
# define CAN_F9DATA1_FD5_Msk (0x1U << CAN_F9DATA1_FD5_Pos) /*!< 0x00000020 */
# define CAN_F9DATA1_FD5 CAN_F9DATA1_FD5_Msk /*!< Filter bit 5 */
# define CAN_F9DATA1_FD6_Pos (6U)
# define CAN_F9DATA1_FD6_Msk (0x1U << CAN_F9DATA1_FD6_Pos) /*!< 0x00000040 */
# define CAN_F9DATA1_FD6 CAN_F9DATA1_FD6_Msk /*!< Filter bit 6 */
# define CAN_F9DATA1_FD7_Pos (7U)
# define CAN_F9DATA1_FD7_Msk (0x1U << CAN_F9DATA1_FD7_Pos) /*!< 0x00000080 */
# define CAN_F9DATA1_FD7 CAN_F9DATA1_FD7_Msk /*!< Filter bit 7 */
# define CAN_F9DATA1_FD8_Pos (8U)
# define CAN_F9DATA1_FD8_Msk (0x1U << CAN_F9DATA1_FD8_Pos) /*!< 0x00000100 */
# define CAN_F9DATA1_FD8 CAN_F9DATA1_FD8_Msk /*!< Filter bit 8 */
# define CAN_F9DATA1_FD9_Pos (9U)
# define CAN_F9DATA1_FD9_Msk (0x1U << CAN_F9DATA1_FD9_Pos) /*!< 0x00000200 */
# define CAN_F9DATA1_FD9 CAN_F9DATA1_FD9_Msk /*!< Filter bit 9 */
# define CAN_F9DATA1_FD10_Pos (10U)
# define CAN_F9DATA1_FD10_Msk (0x1U << CAN_F9DATA1_FD10_Pos) /*!< 0x00000400 */
# define CAN_F9DATA1_FD10 CAN_F9DATA1_FD10_Msk /*!< Filter bit 10 */
# define CAN_F9DATA1_FD11_Pos (11U)
# define CAN_F9DATA1_FD11_Msk (0x1U << CAN_F9DATA1_FD11_Pos) /*!< 0x00000800 */
# define CAN_F9DATA1_FD11 CAN_F9DATA1_FD11_Msk /*!< Filter bit 11 */
# define CAN_F9DATA1_FD12_Pos (12U)
# define CAN_F9DATA1_FD12_Msk (0x1U << CAN_F9DATA1_FD12_Pos) /*!< 0x00001000 */
# define CAN_F9DATA1_FD12 CAN_F9DATA1_FD12_Msk /*!< Filter bit 12 */
# define CAN_F9DATA1_FD13_Pos (13U)
# define CAN_F9DATA1_FD13_Msk (0x1U << CAN_F9DATA1_FD13_Pos) /*!< 0x00002000 */
# define CAN_F9DATA1_FD13 CAN_F9DATA1_FD13_Msk /*!< Filter bit 13 */
# define CAN_F9DATA1_FD14_Pos (14U)
# define CAN_F9DATA1_FD14_Msk (0x1U << CAN_F9DATA1_FD14_Pos) /*!< 0x00004000 */
# define CAN_F9DATA1_FD14 CAN_F9DATA1_FD14_Msk /*!< Filter bit 14 */
# define CAN_F9DATA1_FD15_Pos (15U)
# define CAN_F9DATA1_FD15_Msk (0x1U << CAN_F9DATA1_FD15_Pos) /*!< 0x00008000 */
# define CAN_F9DATA1_FD15 CAN_F9DATA1_FD15_Msk /*!< Filter bit 15 */
# define CAN_F9DATA1_FD16_Pos (16U)
# define CAN_F9DATA1_FD16_Msk (0x1U << CAN_F9DATA1_FD16_Pos) /*!< 0x00010000 */
# define CAN_F9DATA1_FD16 CAN_F9DATA1_FD16_Msk /*!< Filter bit 16 */
# define CAN_F9DATA1_FD17_Pos (17U)
# define CAN_F9DATA1_FD17_Msk (0x1U << CAN_F9DATA1_FD17_Pos) /*!< 0x00020000 */
# define CAN_F9DATA1_FD17 CAN_F9DATA1_FD17_Msk /*!< Filter bit 17 */
# define CAN_F9DATA1_FD18_Pos (18U)
# define CAN_F9DATA1_FD18_Msk (0x1U << CAN_F9DATA1_FD18_Pos) /*!< 0x00040000 */
# define CAN_F9DATA1_FD18 CAN_F9DATA1_FD18_Msk /*!< Filter bit 18 */
# define CAN_F9DATA1_FD19_Pos (19U)
# define CAN_F9DATA1_FD19_Msk (0x1U << CAN_F9DATA1_FD19_Pos) /*!< 0x00080000 */
# define CAN_F9DATA1_FD19 CAN_F9DATA1_FD19_Msk /*!< Filter bit 19 */
# define CAN_F9DATA1_FD20_Pos (20U)
# define CAN_F9DATA1_FD20_Msk (0x1U << CAN_F9DATA1_FD20_Pos) /*!< 0x00100000 */
# define CAN_F9DATA1_FD20 CAN_F9DATA1_FD20_Msk /*!< Filter bit 20 */
# define CAN_F9DATA1_FD21_Pos (21U)
# define CAN_F9DATA1_FD21_Msk (0x1U << CAN_F9DATA1_FD21_Pos) /*!< 0x00200000 */
# define CAN_F9DATA1_FD21 CAN_F9DATA1_FD21_Msk /*!< Filter bit 21 */
# define CAN_F9DATA1_FD22_Pos (22U)
# define CAN_F9DATA1_FD22_Msk (0x1U << CAN_F9DATA1_FD22_Pos) /*!< 0x00400000 */
# define CAN_F9DATA1_FD22 CAN_F9DATA1_FD22_Msk /*!< Filter bit 22 */
# define CAN_F9DATA1_FD23_Pos (23U)
# define CAN_F9DATA1_FD23_Msk (0x1U << CAN_F9DATA1_FD23_Pos) /*!< 0x00800000 */
# define CAN_F9DATA1_FD23 CAN_F9DATA1_FD23_Msk /*!< Filter bit 23 */
# define CAN_F9DATA1_FD24_Pos (24U)
# define CAN_F9DATA1_FD24_Msk (0x1U << CAN_F9DATA1_FD24_Pos) /*!< 0x01000000 */
# define CAN_F9DATA1_FD24 CAN_F9DATA1_FD24_Msk /*!< Filter bit 24 */
# define CAN_F9DATA1_FD25_Pos (25U)
# define CAN_F9DATA1_FD25_Msk (0x1U << CAN_F9DATA1_FD25_Pos) /*!< 0x02000000 */
# define CAN_F9DATA1_FD25 CAN_F9DATA1_FD25_Msk /*!< Filter bit 25 */
# define CAN_F9DATA1_FD26_Pos (26U)
# define CAN_F9DATA1_FD26_Msk (0x1U << CAN_F9DATA1_FD26_Pos) /*!< 0x04000000 */
# define CAN_F9DATA1_FD26 CAN_F9DATA1_FD26_Msk /*!< Filter bit 26 */
# define CAN_F9DATA1_FD27_Pos (27U)
# define CAN_F9DATA1_FD27_Msk (0x1U << CAN_F9DATA1_FD27_Pos) /*!< 0x08000000 */
# define CAN_F9DATA1_FD27 CAN_F9DATA1_FD27_Msk /*!< Filter bit 27 */
# define CAN_F9DATA1_FD28_Pos (28U)
# define CAN_F9DATA1_FD28_Msk (0x1U << CAN_F9DATA1_FD28_Pos) /*!< 0x10000000 */
# define CAN_F9DATA1_FD28 CAN_F9DATA1_FD28_Msk /*!< Filter bit 28 */
# define CAN_F9DATA1_FD29_Pos (29U)
# define CAN_F9DATA1_FD29_Msk (0x1U << CAN_F9DATA1_FD29_Pos) /*!< 0x20000000 */
# define CAN_F9DATA1_FD29 CAN_F9DATA1_FD29_Msk /*!< Filter bit 29 */
# define CAN_F9DATA1_FD30_Pos (30U)
# define CAN_F9DATA1_FD30_Msk (0x1U << CAN_F9DATA1_FD30_Pos) /*!< 0x40000000 */
# define CAN_F9DATA1_FD30 CAN_F9DATA1_FD30_Msk /*!< Filter bit 30 */
# define CAN_F9DATA1_FD31_Pos (31U)
# define CAN_F9DATA1_FD31_Msk (0x1U << CAN_F9DATA1_FD31_Pos) /*!< 0x80000000 */
# define CAN_F9DATA1_FD31 CAN_F9DATA1_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F10R2 register ******************/
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# define CAN_F10DATA1_FD0_Pos (0U)
# define CAN_F10DATA1_FD0_Msk (0x1U << CAN_F10DATA1_FD0_Pos) /*!< 0x00000001 */
# define CAN_F10DATA1_FD0 CAN_F10DATA1_FD0_Msk /*!< Filter bit 0 */
# define CAN_F10DATA1_FD1_Pos (1U)
# define CAN_F10DATA1_FD1_Msk (0x1U << CAN_F10DATA1_FD1_Pos) /*!< 0x00000002 */
# define CAN_F10DATA1_FD1 CAN_F10DATA1_FD1_Msk /*!< Filter bit 1 */
# define CAN_F10DATA1_FD2_Pos (2U)
# define CAN_F10DATA1_FD2_Msk (0x1U << CAN_F10DATA1_FD2_Pos) /*!< 0x00000004 */
# define CAN_F10DATA1_FD2 CAN_F10DATA1_FD2_Msk /*!< Filter bit 2 */
# define CAN_F10DATA1_FD3_Pos (3U)
# define CAN_F10DATA1_FD3_Msk (0x1U << CAN_F10DATA1_FD3_Pos) /*!< 0x00000008 */
# define CAN_F10DATA1_FD3 CAN_F10DATA1_FD3_Msk /*!< Filter bit 3 */
# define CAN_F10DATA1_FD4_Pos (4U)
# define CAN_F10DATA1_FD4_Msk (0x1U << CAN_F10DATA1_FD4_Pos) /*!< 0x00000010 */
# define CAN_F10DATA1_FD4 CAN_F10DATA1_FD4_Msk /*!< Filter bit 4 */
# define CAN_F10DATA1_FD5_Pos (5U)
# define CAN_F10DATA1_FD5_Msk (0x1U << CAN_F10DATA1_FD5_Pos) /*!< 0x00000020 */
# define CAN_F10DATA1_FD5 CAN_F10DATA1_FD5_Msk /*!< Filter bit 5 */
# define CAN_F10DATA1_FD6_Pos (6U)
# define CAN_F10DATA1_FD6_Msk (0x1U << CAN_F10DATA1_FD6_Pos) /*!< 0x00000040 */
# define CAN_F10DATA1_FD6 CAN_F10DATA1_FD6_Msk /*!< Filter bit 6 */
# define CAN_F10DATA1_FD7_Pos (7U)
# define CAN_F10DATA1_FD7_Msk (0x1U << CAN_F10DATA1_FD7_Pos) /*!< 0x00000080 */
# define CAN_F10DATA1_FD7 CAN_F10DATA1_FD7_Msk /*!< Filter bit 7 */
# define CAN_F10DATA1_FD8_Pos (8U)
# define CAN_F10DATA1_FD8_Msk (0x1U << CAN_F10DATA1_FD8_Pos) /*!< 0x00000100 */
# define CAN_F10DATA1_FD8 CAN_F10DATA1_FD8_Msk /*!< Filter bit 8 */
# define CAN_F10DATA1_FD9_Pos (9U)
# define CAN_F10DATA1_FD9_Msk (0x1U << CAN_F10DATA1_FD9_Pos) /*!< 0x00000200 */
# define CAN_F10DATA1_FD9 CAN_F10DATA1_FD9_Msk /*!< Filter bit 9 */
# define CAN_F10DATA1_FD10_Pos (10U)
# define CAN_F10DATA1_FD10_Msk (0x1U << CAN_F10DATA1_FD10_Pos) /*!< 0x00000400 */
# define CAN_F10DATA1_FD10 CAN_F10DATA1_FD10_Msk /*!< Filter bit 10 */
# define CAN_F10DATA1_FD11_Pos (11U)
# define CAN_F10DATA1_FD11_Msk (0x1U << CAN_F10DATA1_FD11_Pos) /*!< 0x00000800 */
# define CAN_F10DATA1_FD11 CAN_F10DATA1_FD11_Msk /*!< Filter bit 11 */
# define CAN_F10DATA1_FD12_Pos (12U)
# define CAN_F10DATA1_FD12_Msk (0x1U << CAN_F10DATA1_FD12_Pos) /*!< 0x00001000 */
# define CAN_F10DATA1_FD12 CAN_F10DATA1_FD12_Msk /*!< Filter bit 12 */
# define CAN_F10DATA1_FD13_Pos (13U)
# define CAN_F10DATA1_FD13_Msk (0x1U << CAN_F10DATA1_FD13_Pos) /*!< 0x00002000 */
# define CAN_F10DATA1_FD13 CAN_F10DATA1_FD13_Msk /*!< Filter bit 13 */
# define CAN_F10DATA1_FD14_Pos (14U)
# define CAN_F10DATA1_FD14_Msk (0x1U << CAN_F10DATA1_FD14_Pos) /*!< 0x00004000 */
# define CAN_F10DATA1_FD14 CAN_F10DATA1_FD14_Msk /*!< Filter bit 14 */
# define CAN_F10DATA1_FD15_Pos (15U)
# define CAN_F10DATA1_FD15_Msk (0x1U << CAN_F10DATA1_FD15_Pos) /*!< 0x00008000 */
# define CAN_F10DATA1_FD15 CAN_F10DATA1_FD15_Msk /*!< Filter bit 15 */
# define CAN_F10DATA1_FD16_Pos (16U)
# define CAN_F10DATA1_FD16_Msk (0x1U << CAN_F10DATA1_FD16_Pos) /*!< 0x00010000 */
# define CAN_F10DATA1_FD16 CAN_F10DATA1_FD16_Msk /*!< Filter bit 16 */
# define CAN_F10DATA1_FD17_Pos (17U)
# define CAN_F10DATA1_FD17_Msk (0x1U << CAN_F10DATA1_FD17_Pos) /*!< 0x00020000 */
# define CAN_F10DATA1_FD17 CAN_F10DATA1_FD17_Msk /*!< Filter bit 17 */
# define CAN_F10DATA1_FD18_Pos (18U)
# define CAN_F10DATA1_FD18_Msk (0x1U << CAN_F10DATA1_FD18_Pos) /*!< 0x00040000 */
# define CAN_F10DATA1_FD18 CAN_F10DATA1_FD18_Msk /*!< Filter bit 18 */
# define CAN_F10DATA1_FD19_Pos (19U)
# define CAN_F10DATA1_FD19_Msk (0x1U << CAN_F10DATA1_FD19_Pos) /*!< 0x00080000 */
# define CAN_F10DATA1_FD19 CAN_F10DATA1_FD19_Msk /*!< Filter bit 19 */
# define CAN_F10DATA1_FD20_Pos (20U)
# define CAN_F10DATA1_FD20_Msk (0x1U << CAN_F10DATA1_FD20_Pos) /*!< 0x00100000 */
# define CAN_F10DATA1_FD20 CAN_F10DATA1_FD20_Msk /*!< Filter bit 20 */
# define CAN_F10DATA1_FD21_Pos (21U)
# define CAN_F10DATA1_FD21_Msk (0x1U << CAN_F10DATA1_FD21_Pos) /*!< 0x00200000 */
# define CAN_F10DATA1_FD21 CAN_F10DATA1_FD21_Msk /*!< Filter bit 21 */
# define CAN_F10DATA1_FD22_Pos (22U)
# define CAN_F10DATA1_FD22_Msk (0x1U << CAN_F10DATA1_FD22_Pos) /*!< 0x00400000 */
# define CAN_F10DATA1_FD22 CAN_F10DATA1_FD22_Msk /*!< Filter bit 22 */
# define CAN_F10DATA1_FD23_Pos (23U)
# define CAN_F10DATA1_FD23_Msk (0x1U << CAN_F10DATA1_FD23_Pos) /*!< 0x00800000 */
# define CAN_F10DATA1_FD23 CAN_F10DATA1_FD23_Msk /*!< Filter bit 23 */
# define CAN_F10DATA1_FD24_Pos (24U)
# define CAN_F10DATA1_FD24_Msk (0x1U << CAN_F10DATA1_FD24_Pos) /*!< 0x01000000 */
# define CAN_F10DATA1_FD24 CAN_F10DATA1_FD24_Msk /*!< Filter bit 24 */
# define CAN_F10DATA1_FD25_Pos (25U)
# define CAN_F10DATA1_FD25_Msk (0x1U << CAN_F10DATA1_FD25_Pos) /*!< 0x02000000 */
# define CAN_F10DATA1_FD25 CAN_F10DATA1_FD25_Msk /*!< Filter bit 25 */
# define CAN_F10DATA1_FD26_Pos (26U)
# define CAN_F10DATA1_FD26_Msk (0x1U << CAN_F10DATA1_FD26_Pos) /*!< 0x04000000 */
# define CAN_F10DATA1_FD26 CAN_F10DATA1_FD26_Msk /*!< Filter bit 26 */
# define CAN_F10DATA1_FD27_Pos (27U)
# define CAN_F10DATA1_FD27_Msk (0x1U << CAN_F10DATA1_FD27_Pos) /*!< 0x08000000 */
# define CAN_F10DATA1_FD27 CAN_F10DATA1_FD27_Msk /*!< Filter bit 27 */
# define CAN_F10DATA1_FD28_Pos (28U)
# define CAN_F10DATA1_FD28_Msk (0x1U << CAN_F10DATA1_FD28_Pos) /*!< 0x10000000 */
# define CAN_F10DATA1_FD28 CAN_F10DATA1_FD28_Msk /*!< Filter bit 28 */
# define CAN_F10DATA1_FD29_Pos (29U)
# define CAN_F10DATA1_FD29_Msk (0x1U << CAN_F10DATA1_FD29_Pos) /*!< 0x20000000 */
# define CAN_F10DATA1_FD29 CAN_F10DATA1_FD29_Msk /*!< Filter bit 29 */
# define CAN_F10DATA1_FD30_Pos (30U)
# define CAN_F10DATA1_FD30_Msk (0x1U << CAN_F10DATA1_FD30_Pos) /*!< 0x40000000 */
# define CAN_F10DATA1_FD30 CAN_F10DATA1_FD30_Msk /*!< Filter bit 30 */
# define CAN_F10DATA1_FD31_Pos (31U)
# define CAN_F10DATA1_FD31_Msk (0x1U << CAN_F10DATA1_FD31_Pos) /*!< 0x80000000 */
# define CAN_F10DATA1_FD31 CAN_F10DATA1_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F11R2 register ******************/
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# define CAN_F11DATA1_FD0_Pos (0U)
# define CAN_F11DATA1_FD0_Msk (0x1U << CAN_F11DATA1_FD0_Pos) /*!< 0x00000001 */
# define CAN_F11DATA1_FD0 CAN_F11DATA1_FD0_Msk /*!< Filter bit 0 */
# define CAN_F11DATA1_FD1_Pos (1U)
# define CAN_F11DATA1_FD1_Msk (0x1U << CAN_F11DATA1_FD1_Pos) /*!< 0x00000002 */
# define CAN_F11DATA1_FD1 CAN_F11DATA1_FD1_Msk /*!< Filter bit 1 */
# define CAN_F11DATA1_FD2_Pos (2U)
# define CAN_F11DATA1_FD2_Msk (0x1U << CAN_F11DATA1_FD2_Pos) /*!< 0x00000004 */
# define CAN_F11DATA1_FD2 CAN_F11DATA1_FD2_Msk /*!< Filter bit 2 */
# define CAN_F11DATA1_FD3_Pos (3U)
# define CAN_F11DATA1_FD3_Msk (0x1U << CAN_F11DATA1_FD3_Pos) /*!< 0x00000008 */
# define CAN_F11DATA1_FD3 CAN_F11DATA1_FD3_Msk /*!< Filter bit 3 */
# define CAN_F11DATA1_FD4_Pos (4U)
# define CAN_F11DATA1_FD4_Msk (0x1U << CAN_F11DATA1_FD4_Pos) /*!< 0x00000010 */
# define CAN_F11DATA1_FD4 CAN_F11DATA1_FD4_Msk /*!< Filter bit 4 */
# define CAN_F11DATA1_FD5_Pos (5U)
# define CAN_F11DATA1_FD5_Msk (0x1U << CAN_F11DATA1_FD5_Pos) /*!< 0x00000020 */
# define CAN_F11DATA1_FD5 CAN_F11DATA1_FD5_Msk /*!< Filter bit 5 */
# define CAN_F11DATA1_FD6_Pos (6U)
# define CAN_F11DATA1_FD6_Msk (0x1U << CAN_F11DATA1_FD6_Pos) /*!< 0x00000040 */
# define CAN_F11DATA1_FD6 CAN_F11DATA1_FD6_Msk /*!< Filter bit 6 */
# define CAN_F11DATA1_FD7_Pos (7U)
# define CAN_F11DATA1_FD7_Msk (0x1U << CAN_F11DATA1_FD7_Pos) /*!< 0x00000080 */
# define CAN_F11DATA1_FD7 CAN_F11DATA1_FD7_Msk /*!< Filter bit 7 */
# define CAN_F11DATA1_FD8_Pos (8U)
# define CAN_F11DATA1_FD8_Msk (0x1U << CAN_F11DATA1_FD8_Pos) /*!< 0x00000100 */
# define CAN_F11DATA1_FD8 CAN_F11DATA1_FD8_Msk /*!< Filter bit 8 */
# define CAN_F11DATA1_FD9_Pos (9U)
# define CAN_F11DATA1_FD9_Msk (0x1U << CAN_F11DATA1_FD9_Pos) /*!< 0x00000200 */
# define CAN_F11DATA1_FD9 CAN_F11DATA1_FD9_Msk /*!< Filter bit 9 */
# define CAN_F11DATA1_FD10_Pos (10U)
# define CAN_F11DATA1_FD10_Msk (0x1U << CAN_F11DATA1_FD10_Pos) /*!< 0x00000400 */
# define CAN_F11DATA1_FD10 CAN_F11DATA1_FD10_Msk /*!< Filter bit 10 */
# define CAN_F11DATA1_FD11_Pos (11U)
# define CAN_F11DATA1_FD11_Msk (0x1U << CAN_F11DATA1_FD11_Pos) /*!< 0x00000800 */
# define CAN_F11DATA1_FD11 CAN_F11DATA1_FD11_Msk /*!< Filter bit 11 */
# define CAN_F11DATA1_FD12_Pos (12U)
# define CAN_F11DATA1_FD12_Msk (0x1U << CAN_F11DATA1_FD12_Pos) /*!< 0x00001000 */
# define CAN_F11DATA1_FD12 CAN_F11DATA1_FD12_Msk /*!< Filter bit 12 */
# define CAN_F11DATA1_FD13_Pos (13U)
# define CAN_F11DATA1_FD13_Msk (0x1U << CAN_F11DATA1_FD13_Pos) /*!< 0x00002000 */
# define CAN_F11DATA1_FD13 CAN_F11DATA1_FD13_Msk /*!< Filter bit 13 */
# define CAN_F11DATA1_FD14_Pos (14U)
# define CAN_F11DATA1_FD14_Msk (0x1U << CAN_F11DATA1_FD14_Pos) /*!< 0x00004000 */
# define CAN_F11DATA1_FD14 CAN_F11DATA1_FD14_Msk /*!< Filter bit 14 */
# define CAN_F11DATA1_FD15_Pos (15U)
# define CAN_F11DATA1_FD15_Msk (0x1U << CAN_F11DATA1_FD15_Pos) /*!< 0x00008000 */
# define CAN_F11DATA1_FD15 CAN_F11DATA1_FD15_Msk /*!< Filter bit 15 */
# define CAN_F11DATA1_FD16_Pos (16U)
# define CAN_F11DATA1_FD16_Msk (0x1U << CAN_F11DATA1_FD16_Pos) /*!< 0x00010000 */
# define CAN_F11DATA1_FD16 CAN_F11DATA1_FD16_Msk /*!< Filter bit 16 */
# define CAN_F11DATA1_FD17_Pos (17U)
# define CAN_F11DATA1_FD17_Msk (0x1U << CAN_F11DATA1_FD17_Pos) /*!< 0x00020000 */
# define CAN_F11DATA1_FD17 CAN_F11DATA1_FD17_Msk /*!< Filter bit 17 */
# define CAN_F11DATA1_FD18_Pos (18U)
# define CAN_F11DATA1_FD18_Msk (0x1U << CAN_F11DATA1_FD18_Pos) /*!< 0x00040000 */
# define CAN_F11DATA1_FD18 CAN_F11DATA1_FD18_Msk /*!< Filter bit 18 */
# define CAN_F11DATA1_FD19_Pos (19U)
# define CAN_F11DATA1_FD19_Msk (0x1U << CAN_F11DATA1_FD19_Pos) /*!< 0x00080000 */
# define CAN_F11DATA1_FD19 CAN_F11DATA1_FD19_Msk /*!< Filter bit 19 */
# define CAN_F11DATA1_FD20_Pos (20U)
# define CAN_F11DATA1_FD20_Msk (0x1U << CAN_F11DATA1_FD20_Pos) /*!< 0x00100000 */
# define CAN_F11DATA1_FD20 CAN_F11DATA1_FD20_Msk /*!< Filter bit 20 */
# define CAN_F11DATA1_FD21_Pos (21U)
# define CAN_F11DATA1_FD21_Msk (0x1U << CAN_F11DATA1_FD21_Pos) /*!< 0x00200000 */
# define CAN_F11DATA1_FD21 CAN_F11DATA1_FD21_Msk /*!< Filter bit 21 */
# define CAN_F11DATA1_FD22_Pos (22U)
# define CAN_F11DATA1_FD22_Msk (0x1U << CAN_F11DATA1_FD22_Pos) /*!< 0x00400000 */
# define CAN_F11DATA1_FD22 CAN_F11DATA1_FD22_Msk /*!< Filter bit 22 */
# define CAN_F11DATA1_FD23_Pos (23U)
# define CAN_F11DATA1_FD23_Msk (0x1U << CAN_F11DATA1_FD23_Pos) /*!< 0x00800000 */
# define CAN_F11DATA1_FD23 CAN_F11DATA1_FD23_Msk /*!< Filter bit 23 */
# define CAN_F11DATA1_FD24_Pos (24U)
# define CAN_F11DATA1_FD24_Msk (0x1U << CAN_F11DATA1_FD24_Pos) /*!< 0x01000000 */
# define CAN_F11DATA1_FD24 CAN_F11DATA1_FD24_Msk /*!< Filter bit 24 */
# define CAN_F11DATA1_FD25_Pos (25U)
# define CAN_F11DATA1_FD25_Msk (0x1U << CAN_F11DATA1_FD25_Pos) /*!< 0x02000000 */
# define CAN_F11DATA1_FD25 CAN_F11DATA1_FD25_Msk /*!< Filter bit 25 */
# define CAN_F11DATA1_FD26_Pos (26U)
# define CAN_F11DATA1_FD26_Msk (0x1U << CAN_F11DATA1_FD26_Pos) /*!< 0x04000000 */
# define CAN_F11DATA1_FD26 CAN_F11DATA1_FD26_Msk /*!< Filter bit 26 */
# define CAN_F11DATA1_FD27_Pos (27U)
# define CAN_F11DATA1_FD27_Msk (0x1U << CAN_F11DATA1_FD27_Pos) /*!< 0x08000000 */
# define CAN_F11DATA1_FD27 CAN_F11DATA1_FD27_Msk /*!< Filter bit 27 */
# define CAN_F11DATA1_FD28_Pos (28U)
# define CAN_F11DATA1_FD28_Msk (0x1U << CAN_F11DATA1_FD28_Pos) /*!< 0x10000000 */
# define CAN_F11DATA1_FD28 CAN_F11DATA1_FD28_Msk /*!< Filter bit 28 */
# define CAN_F11DATA1_FD29_Pos (29U)
# define CAN_F11DATA1_FD29_Msk (0x1U << CAN_F11DATA1_FD29_Pos) /*!< 0x20000000 */
# define CAN_F11DATA1_FD29 CAN_F11DATA1_FD29_Msk /*!< Filter bit 29 */
# define CAN_F11DATA1_FD30_Pos (30U)
# define CAN_F11DATA1_FD30_Msk (0x1U << CAN_F11DATA1_FD30_Pos) /*!< 0x40000000 */
# define CAN_F11DATA1_FD30 CAN_F11DATA1_FD30_Msk /*!< Filter bit 30 */
# define CAN_F11DATA1_FD31_Pos (31U)
# define CAN_F11DATA1_FD31_Msk (0x1U << CAN_F11DATA1_FD31_Pos) /*!< 0x80000000 */
# define CAN_F11DATA1_FD31 CAN_F11DATA1_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F12R2 register ******************/
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# define CAN_F12DATA1_FD0_Pos (0U)
# define CAN_F12DATA1_FD0_Msk (0x1U << CAN_F12DATA1_FD0_Pos) /*!< 0x00000001 */
# define CAN_F12DATA1_FD0 CAN_F12DATA1_FD0_Msk /*!< Filter bit 0 */
# define CAN_F12DATA1_FD1_Pos (1U)
# define CAN_F12DATA1_FD1_Msk (0x1U << CAN_F12DATA1_FD1_Pos) /*!< 0x00000002 */
# define CAN_F12DATA1_FD1 CAN_F12DATA1_FD1_Msk /*!< Filter bit 1 */
# define CAN_F12DATA1_FD2_Pos (2U)
# define CAN_F12DATA1_FD2_Msk (0x1U << CAN_F12DATA1_FD2_Pos) /*!< 0x00000004 */
# define CAN_F12DATA1_FD2 CAN_F12DATA1_FD2_Msk /*!< Filter bit 2 */
# define CAN_F12DATA1_FD3_Pos (3U)
# define CAN_F12DATA1_FD3_Msk (0x1U << CAN_F12DATA1_FD3_Pos) /*!< 0x00000008 */
# define CAN_F12DATA1_FD3 CAN_F12DATA1_FD3_Msk /*!< Filter bit 3 */
# define CAN_F12DATA1_FD4_Pos (4U)
# define CAN_F12DATA1_FD4_Msk (0x1U << CAN_F12DATA1_FD4_Pos) /*!< 0x00000010 */
# define CAN_F12DATA1_FD4 CAN_F12DATA1_FD4_Msk /*!< Filter bit 4 */
# define CAN_F12DATA1_FD5_Pos (5U)
# define CAN_F12DATA1_FD5_Msk (0x1U << CAN_F12DATA1_FD5_Pos) /*!< 0x00000020 */
# define CAN_F12DATA1_FD5 CAN_F12DATA1_FD5_Msk /*!< Filter bit 5 */
# define CAN_F12DATA1_FD6_Pos (6U)
# define CAN_F12DATA1_FD6_Msk (0x1U << CAN_F12DATA1_FD6_Pos) /*!< 0x00000040 */
# define CAN_F12DATA1_FD6 CAN_F12DATA1_FD6_Msk /*!< Filter bit 6 */
# define CAN_F12DATA1_FD7_Pos (7U)
# define CAN_F12DATA1_FD7_Msk (0x1U << CAN_F12DATA1_FD7_Pos) /*!< 0x00000080 */
# define CAN_F12DATA1_FD7 CAN_F12DATA1_FD7_Msk /*!< Filter bit 7 */
# define CAN_F12DATA1_FD8_Pos (8U)
# define CAN_F12DATA1_FD8_Msk (0x1U << CAN_F12DATA1_FD8_Pos) /*!< 0x00000100 */
# define CAN_F12DATA1_FD8 CAN_F12DATA1_FD8_Msk /*!< Filter bit 8 */
# define CAN_F12DATA1_FD9_Pos (9U)
# define CAN_F12DATA1_FD9_Msk (0x1U << CAN_F12DATA1_FD9_Pos) /*!< 0x00000200 */
# define CAN_F12DATA1_FD9 CAN_F12DATA1_FD9_Msk /*!< Filter bit 9 */
# define CAN_F12DATA1_FD10_Pos (10U)
# define CAN_F12DATA1_FD10_Msk (0x1U << CAN_F12DATA1_FD10_Pos) /*!< 0x00000400 */
# define CAN_F12DATA1_FD10 CAN_F12DATA1_FD10_Msk /*!< Filter bit 10 */
# define CAN_F12DATA1_FD11_Pos (11U)
# define CAN_F12DATA1_FD11_Msk (0x1U << CAN_F12DATA1_FD11_Pos) /*!< 0x00000800 */
# define CAN_F12DATA1_FD11 CAN_F12DATA1_FD11_Msk /*!< Filter bit 11 */
# define CAN_F12DATA1_FD12_Pos (12U)
# define CAN_F12DATA1_FD12_Msk (0x1U << CAN_F12DATA1_FD12_Pos) /*!< 0x00001000 */
# define CAN_F12DATA1_FD12 CAN_F12DATA1_FD12_Msk /*!< Filter bit 12 */
# define CAN_F12DATA1_FD13_Pos (13U)
# define CAN_F12DATA1_FD13_Msk (0x1U << CAN_F12DATA1_FD13_Pos) /*!< 0x00002000 */
# define CAN_F12DATA1_FD13 CAN_F12DATA1_FD13_Msk /*!< Filter bit 13 */
# define CAN_F12DATA1_FD14_Pos (14U)
# define CAN_F12DATA1_FD14_Msk (0x1U << CAN_F12DATA1_FD14_Pos) /*!< 0x00004000 */
# define CAN_F12DATA1_FD14 CAN_F12DATA1_FD14_Msk /*!< Filter bit 14 */
# define CAN_F12DATA1_FD15_Pos (15U)
# define CAN_F12DATA1_FD15_Msk (0x1U << CAN_F12DATA1_FD15_Pos) /*!< 0x00008000 */
# define CAN_F12DATA1_FD15 CAN_F12DATA1_FD15_Msk /*!< Filter bit 15 */
# define CAN_F12DATA1_FD16_Pos (16U)
# define CAN_F12DATA1_FD16_Msk (0x1U << CAN_F12DATA1_FD16_Pos) /*!< 0x00010000 */
# define CAN_F12DATA1_FD16 CAN_F12DATA1_FD16_Msk /*!< Filter bit 16 */
# define CAN_F12DATA1_FD17_Pos (17U)
# define CAN_F12DATA1_FD17_Msk (0x1U << CAN_F12DATA1_FD17_Pos) /*!< 0x00020000 */
# define CAN_F12DATA1_FD17 CAN_F12DATA1_FD17_Msk /*!< Filter bit 17 */
# define CAN_F12DATA1_FD18_Pos (18U)
# define CAN_F12DATA1_FD18_Msk (0x1U << CAN_F12DATA1_FD18_Pos) /*!< 0x00040000 */
# define CAN_F12DATA1_FD18 CAN_F12DATA1_FD18_Msk /*!< Filter bit 18 */
# define CAN_F12DATA1_FD19_Pos (19U)
# define CAN_F12DATA1_FD19_Msk (0x1U << CAN_F12DATA1_FD19_Pos) /*!< 0x00080000 */
# define CAN_F12DATA1_FD19 CAN_F12DATA1_FD19_Msk /*!< Filter bit 19 */
# define CAN_F12DATA1_FD20_Pos (20U)
# define CAN_F12DATA1_FD20_Msk (0x1U << CAN_F12DATA1_FD20_Pos) /*!< 0x00100000 */
# define CAN_F12DATA1_FD20 CAN_F12DATA1_FD20_Msk /*!< Filter bit 20 */
# define CAN_F12DATA1_FD21_Pos (21U)
# define CAN_F12DATA1_FD21_Msk (0x1U << CAN_F12DATA1_FD21_Pos) /*!< 0x00200000 */
# define CAN_F12DATA1_FD21 CAN_F12DATA1_FD21_Msk /*!< Filter bit 21 */
# define CAN_F12DATA1_FD22_Pos (22U)
# define CAN_F12DATA1_FD22_Msk (0x1U << CAN_F12DATA1_FD22_Pos) /*!< 0x00400000 */
# define CAN_F12DATA1_FD22 CAN_F12DATA1_FD22_Msk /*!< Filter bit 22 */
# define CAN_F12DATA1_FD23_Pos (23U)
# define CAN_F12DATA1_FD23_Msk (0x1U << CAN_F12DATA1_FD23_Pos) /*!< 0x00800000 */
# define CAN_F12DATA1_FD23 CAN_F12DATA1_FD23_Msk /*!< Filter bit 23 */
# define CAN_F12DATA1_FD24_Pos (24U)
# define CAN_F12DATA1_FD24_Msk (0x1U << CAN_F12DATA1_FD24_Pos) /*!< 0x01000000 */
# define CAN_F12DATA1_FD24 CAN_F12DATA1_FD24_Msk /*!< Filter bit 24 */
# define CAN_F12DATA1_FD25_Pos (25U)
# define CAN_F12DATA1_FD25_Msk (0x1U << CAN_F12DATA1_FD25_Pos) /*!< 0x02000000 */
# define CAN_F12DATA1_FD25 CAN_F12DATA1_FD25_Msk /*!< Filter bit 25 */
# define CAN_F12DATA1_FD26_Pos (26U)
# define CAN_F12DATA1_FD26_Msk (0x1U << CAN_F12DATA1_FD26_Pos) /*!< 0x04000000 */
# define CAN_F12DATA1_FD26 CAN_F12DATA1_FD26_Msk /*!< Filter bit 26 */
# define CAN_F12DATA1_FD27_Pos (27U)
# define CAN_F12DATA1_FD27_Msk (0x1U << CAN_F12DATA1_FD27_Pos) /*!< 0x08000000 */
# define CAN_F12DATA1_FD27 CAN_F12DATA1_FD27_Msk /*!< Filter bit 27 */
# define CAN_F12DATA1_FD28_Pos (28U)
# define CAN_F12DATA1_FD28_Msk (0x1U << CAN_F12DATA1_FD28_Pos) /*!< 0x10000000 */
# define CAN_F12DATA1_FD28 CAN_F12DATA1_FD28_Msk /*!< Filter bit 28 */
# define CAN_F12DATA1_FD29_Pos (29U)
# define CAN_F12DATA1_FD29_Msk (0x1U << CAN_F12DATA1_FD29_Pos) /*!< 0x20000000 */
# define CAN_F12DATA1_FD29 CAN_F12DATA1_FD29_Msk /*!< Filter bit 29 */
# define CAN_F12DATA1_FD30_Pos (30U)
# define CAN_F12DATA1_FD30_Msk (0x1U << CAN_F12DATA1_FD30_Pos) /*!< 0x40000000 */
# define CAN_F12DATA1_FD30 CAN_F12DATA1_FD30_Msk /*!< Filter bit 30 */
# define CAN_F12DATA1_FD31_Pos (31U)
# define CAN_F12DATA1_FD31_Msk (0x1U << CAN_F12DATA1_FD31_Pos) /*!< 0x80000000 */
# define CAN_F12DATA1_FD31 CAN_F12DATA1_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F13R2 register ******************/
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# define CAN_F13DATA1_FD0_Pos (0U)
# define CAN_F13DATA1_FD0_Msk (0x1U << CAN_F13DATA1_FD0_Pos) /*!< 0x00000001 */
# define CAN_F13DATA1_FD0 CAN_F13DATA1_FD0_Msk /*!< Filter bit 0 */
# define CAN_F13DATA1_FD1_Pos (1U)
# define CAN_F13DATA1_FD1_Msk (0x1U << CAN_F13DATA1_FD1_Pos) /*!< 0x00000002 */
# define CAN_F13DATA1_FD1 CAN_F13DATA1_FD1_Msk /*!< Filter bit 1 */
# define CAN_F13DATA1_FD2_Pos (2U)
# define CAN_F13DATA1_FD2_Msk (0x1U << CAN_F13DATA1_FD2_Pos) /*!< 0x00000004 */
# define CAN_F13DATA1_FD2 CAN_F13DATA1_FD2_Msk /*!< Filter bit 2 */
# define CAN_F13DATA1_FD3_Pos (3U)
# define CAN_F13DATA1_FD3_Msk (0x1U << CAN_F13DATA1_FD3_Pos) /*!< 0x00000008 */
# define CAN_F13DATA1_FD3 CAN_F13DATA1_FD3_Msk /*!< Filter bit 3 */
# define CAN_F13DATA1_FD4_Pos (4U)
# define CAN_F13DATA1_FD4_Msk (0x1U << CAN_F13DATA1_FD4_Pos) /*!< 0x00000010 */
# define CAN_F13DATA1_FD4 CAN_F13DATA1_FD4_Msk /*!< Filter bit 4 */
# define CAN_F13DATA1_FD5_Pos (5U)
# define CAN_F13DATA1_FD5_Msk (0x1U << CAN_F13DATA1_FD5_Pos) /*!< 0x00000020 */
# define CAN_F13DATA1_FD5 CAN_F13DATA1_FD5_Msk /*!< Filter bit 5 */
# define CAN_F13DATA1_FD6_Pos (6U)
# define CAN_F13DATA1_FD6_Msk (0x1U << CAN_F13DATA1_FD6_Pos) /*!< 0x00000040 */
# define CAN_F13DATA1_FD6 CAN_F13DATA1_FD6_Msk /*!< Filter bit 6 */
# define CAN_F13DATA1_FD7_Pos (7U)
# define CAN_F13DATA1_FD7_Msk (0x1U << CAN_F13DATA1_FD7_Pos) /*!< 0x00000080 */
# define CAN_F13DATA1_FD7 CAN_F13DATA1_FD7_Msk /*!< Filter bit 7 */
# define CAN_F13DATA1_FD8_Pos (8U)
# define CAN_F13DATA1_FD8_Msk (0x1U << CAN_F13DATA1_FD8_Pos) /*!< 0x00000100 */
# define CAN_F13DATA1_FD8 CAN_F13DATA1_FD8_Msk /*!< Filter bit 8 */
# define CAN_F13DATA1_FD9_Pos (9U)
# define CAN_F13DATA1_FD9_Msk (0x1U << CAN_F13DATA1_FD9_Pos) /*!< 0x00000200 */
# define CAN_F13DATA1_FD9 CAN_F13DATA1_FD9_Msk /*!< Filter bit 9 */
# define CAN_F13DATA1_FD10_Pos (10U)
# define CAN_F13DATA1_FD10_Msk (0x1U << CAN_F13DATA1_FD10_Pos) /*!< 0x00000400 */
# define CAN_F13DATA1_FD10 CAN_F13DATA1_FD10_Msk /*!< Filter bit 10 */
# define CAN_F13DATA1_FD11_Pos (11U)
# define CAN_F13DATA1_FD11_Msk (0x1U << CAN_F13DATA1_FD11_Pos) /*!< 0x00000800 */
# define CAN_F13DATA1_FD11 CAN_F13DATA1_FD11_Msk /*!< Filter bit 11 */
# define CAN_F13DATA1_FD12_Pos (12U)
# define CAN_F13DATA1_FD12_Msk (0x1U << CAN_F13DATA1_FD12_Pos) /*!< 0x00001000 */
# define CAN_F13DATA1_FD12 CAN_F13DATA1_FD12_Msk /*!< Filter bit 12 */
# define CAN_F13DATA1_FD13_Pos (13U)
# define CAN_F13DATA1_FD13_Msk (0x1U << CAN_F13DATA1_FD13_Pos) /*!< 0x00002000 */
# define CAN_F13DATA1_FD13 CAN_F13DATA1_FD13_Msk /*!< Filter bit 13 */
# define CAN_F13DATA1_FD14_Pos (14U)
# define CAN_F13DATA1_FD14_Msk (0x1U << CAN_F13DATA1_FD14_Pos) /*!< 0x00004000 */
# define CAN_F13DATA1_FD14 CAN_F13DATA1_FD14_Msk /*!< Filter bit 14 */
# define CAN_F13DATA1_FD15_Pos (15U)
# define CAN_F13DATA1_FD15_Msk (0x1U << CAN_F13DATA1_FD15_Pos) /*!< 0x00008000 */
# define CAN_F13DATA1_FD15 CAN_F13DATA1_FD15_Msk /*!< Filter bit 15 */
# define CAN_F13DATA1_FD16_Pos (16U)
# define CAN_F13DATA1_FD16_Msk (0x1U << CAN_F13DATA1_FD16_Pos) /*!< 0x00010000 */
# define CAN_F13DATA1_FD16 CAN_F13DATA1_FD16_Msk /*!< Filter bit 16 */
# define CAN_F13DATA1_FD17_Pos (17U)
# define CAN_F13DATA1_FD17_Msk (0x1U << CAN_F13DATA1_FD17_Pos) /*!< 0x00020000 */
# define CAN_F13DATA1_FD17 CAN_F13DATA1_FD17_Msk /*!< Filter bit 17 */
# define CAN_F13DATA1_FD18_Pos (18U)
# define CAN_F13DATA1_FD18_Msk (0x1U << CAN_F13DATA1_FD18_Pos) /*!< 0x00040000 */
# define CAN_F13DATA1_FD18 CAN_F13DATA1_FD18_Msk /*!< Filter bit 18 */
# define CAN_F13DATA1_FD19_Pos (19U)
# define CAN_F13DATA1_FD19_Msk (0x1U << CAN_F13DATA1_FD19_Pos) /*!< 0x00080000 */
# define CAN_F13DATA1_FD19 CAN_F13DATA1_FD19_Msk /*!< Filter bit 19 */
# define CAN_F13DATA1_FD20_Pos (20U)
# define CAN_F13DATA1_FD20_Msk (0x1U << CAN_F13DATA1_FD20_Pos) /*!< 0x00100000 */
# define CAN_F13DATA1_FD20 CAN_F13DATA1_FD20_Msk /*!< Filter bit 20 */
# define CAN_F13DATA1_FD21_Pos (21U)
# define CAN_F13DATA1_FD21_Msk (0x1U << CAN_F13DATA1_FD21_Pos) /*!< 0x00200000 */
# define CAN_F13DATA1_FD21 CAN_F13DATA1_FD21_Msk /*!< Filter bit 21 */
# define CAN_F13DATA1_FD22_Pos (22U)
# define CAN_F13DATA1_FD22_Msk (0x1U << CAN_F13DATA1_FD22_Pos) /*!< 0x00400000 */
# define CAN_F13DATA1_FD22 CAN_F13DATA1_FD22_Msk /*!< Filter bit 22 */
# define CAN_F13DATA1_FD23_Pos (23U)
# define CAN_F13DATA1_FD23_Msk (0x1U << CAN_F13DATA1_FD23_Pos) /*!< 0x00800000 */
# define CAN_F13DATA1_FD23 CAN_F13DATA1_FD23_Msk /*!< Filter bit 23 */
# define CAN_F13DATA1_FD24_Pos (24U)
# define CAN_F13DATA1_FD24_Msk (0x1U << CAN_F13DATA1_FD24_Pos) /*!< 0x01000000 */
# define CAN_F13DATA1_FD24 CAN_F13DATA1_FD24_Msk /*!< Filter bit 24 */
# define CAN_F13DATA1_FD25_Pos (25U)
# define CAN_F13DATA1_FD25_Msk (0x1U << CAN_F13DATA1_FD25_Pos) /*!< 0x02000000 */
# define CAN_F13DATA1_FD25 CAN_F13DATA1_FD25_Msk /*!< Filter bit 25 */
# define CAN_F13DATA1_FD26_Pos (26U)
# define CAN_F13DATA1_FD26_Msk (0x1U << CAN_F13DATA1_FD26_Pos) /*!< 0x04000000 */
# define CAN_F13DATA1_FD26 CAN_F13DATA1_FD26_Msk /*!< Filter bit 26 */
# define CAN_F13DATA1_FD27_Pos (27U)
# define CAN_F13DATA1_FD27_Msk (0x1U << CAN_F13DATA1_FD27_Pos) /*!< 0x08000000 */
# define CAN_F13DATA1_FD27 CAN_F13DATA1_FD27_Msk /*!< Filter bit 27 */
# define CAN_F13DATA1_FD28_Pos (28U)
# define CAN_F13DATA1_FD28_Msk (0x1U << CAN_F13DATA1_FD28_Pos) /*!< 0x10000000 */
# define CAN_F13DATA1_FD28 CAN_F13DATA1_FD28_Msk /*!< Filter bit 28 */
# define CAN_F13DATA1_FD29_Pos (29U)
# define CAN_F13DATA1_FD29_Msk (0x1U << CAN_F13DATA1_FD29_Pos) /*!< 0x20000000 */
# define CAN_F13DATA1_FD29 CAN_F13DATA1_FD29_Msk /*!< Filter bit 29 */
# define CAN_F13DATA1_FD30_Pos (30U)
# define CAN_F13DATA1_FD30_Msk (0x1U << CAN_F13DATA1_FD30_Pos) /*!< 0x40000000 */
# define CAN_F13DATA1_FD30 CAN_F13DATA1_FD30_Msk /*!< Filter bit 30 */
# define CAN_F13DATA1_FD31_Pos (31U)
# define CAN_F13DATA1_FD31_Msk (0x1U << CAN_F13DATA1_FD31_Pos) /*!< 0x80000000 */
# define CAN_F13DATA1_FD31 CAN_F13DATA1_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F14R2 register ******************/
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# define CAN_F14DATA1_FD0_Pos (0U)
# define CAN_F14DATA1_FD0_Msk (0x1U << CAN_F14DATA1_FD0_Pos) /*!< 0x00000001 */
# define CAN_F14DATA1_FD0 CAN_F14DATA1_FD0_Msk /*!< Filter bit 0 */
# define CAN_F14DATA1_FD1_Pos (1U)
# define CAN_F14DATA1_FD1_Msk (0x1U << CAN_F14DATA1_FD1_Pos) /*!< 0x00000002 */
# define CAN_F14DATA1_FD1 CAN_F14DATA1_FD1_Msk /*!< Filter bit 1 */
# define CAN_F14DATA1_FD2_Pos (2U)
# define CAN_F14DATA1_FD2_Msk (0x1U << CAN_F14DATA1_FD2_Pos) /*!< 0x00000004 */
# define CAN_F14DATA1_FD2 CAN_F14DATA1_FD2_Msk /*!< Filter bit 2 */
# define CAN_F14DATA1_FD3_Pos (3U)
# define CAN_F14DATA1_FD3_Msk (0x1U << CAN_F14DATA1_FD3_Pos) /*!< 0x00000008 */
# define CAN_F14DATA1_FD3 CAN_F14DATA1_FD3_Msk /*!< Filter bit 3 */
# define CAN_F14DATA1_FD4_Pos (4U)
# define CAN_F14DATA1_FD4_Msk (0x1U << CAN_F14DATA1_FD4_Pos) /*!< 0x00000010 */
# define CAN_F14DATA1_FD4 CAN_F14DATA1_FD4_Msk /*!< Filter bit 4 */
# define CAN_F14DATA1_FD5_Pos (5U)
# define CAN_F14DATA1_FD5_Msk (0x1U << CAN_F14DATA1_FD5_Pos) /*!< 0x00000020 */
# define CAN_F14DATA1_FD5 CAN_F14DATA1_FD5_Msk /*!< Filter bit 5 */
# define CAN_F14DATA1_FD6_Pos (6U)
# define CAN_F14DATA1_FD6_Msk (0x1U << CAN_F14DATA1_FD6_Pos) /*!< 0x00000040 */
# define CAN_F14DATA1_FD6 CAN_F14DATA1_FD6_Msk /*!< Filter bit 6 */
# define CAN_F14DATA1_FD7_Pos (7U)
# define CAN_F14DATA1_FD7_Msk (0x1U << CAN_F14DATA1_FD7_Pos) /*!< 0x00000080 */
# define CAN_F14DATA1_FD7 CAN_F14DATA1_FD7_Msk /*!< Filter bit 7 */
# define CAN_F14DATA1_FD8_Pos (8U)
# define CAN_F14DATA1_FD8_Msk (0x1U << CAN_F14DATA1_FD8_Pos) /*!< 0x00000100 */
# define CAN_F14DATA1_FD8 CAN_F14DATA1_FD8_Msk /*!< Filter bit 8 */
# define CAN_F14DATA1_FD9_Pos (9U)
# define CAN_F14DATA1_FD9_Msk (0x1U << CAN_F14DATA1_FD9_Pos) /*!< 0x00000200 */
# define CAN_F14DATA1_FD9 CAN_F14DATA1_FD9_Msk /*!< Filter bit 9 */
# define CAN_F14DATA1_FD10_Pos (10U)
# define CAN_F14DATA1_FD10_Msk (0x1U << CAN_F14DATA1_FD10_Pos) /*!< 0x00000400 */
# define CAN_F14DATA1_FD10 CAN_F14DATA1_FD10_Msk /*!< Filter bit 10 */
# define CAN_F14DATA1_FD11_Pos (11U)
# define CAN_F14DATA1_FD11_Msk (0x1U << CAN_F14DATA1_FD11_Pos) /*!< 0x00000800 */
# define CAN_F14DATA1_FD11 CAN_F14DATA1_FD11_Msk /*!< Filter bit 11 */
# define CAN_F14DATA1_FD12_Pos (12U)
# define CAN_F14DATA1_FD12_Msk (0x1U << CAN_F14DATA1_FD12_Pos) /*!< 0x00001000 */
# define CAN_F14DATA1_FD12 CAN_F14DATA1_FD12_Msk /*!< Filter bit 12 */
# define CAN_F14DATA1_FD13_Pos (13U)
# define CAN_F14DATA1_FD13_Msk (0x1U << CAN_F14DATA1_FD13_Pos) /*!< 0x00002000 */
# define CAN_F14DATA1_FD13 CAN_F14DATA1_FD13_Msk /*!< Filter bit 13 */
# define CAN_F14DATA1_FD14_Pos (14U)
# define CAN_F14DATA1_FD14_Msk (0x1U << CAN_F14DATA1_FD14_Pos) /*!< 0x00004000 */
# define CAN_F14DATA1_FD14 CAN_F14DATA1_FD14_Msk /*!< Filter bit 14 */
# define CAN_F14DATA1_FD15_Pos (15U)
# define CAN_F14DATA1_FD15_Msk (0x1U << CAN_F14DATA1_FD15_Pos) /*!< 0x00008000 */
# define CAN_F14DATA1_FD15 CAN_F14DATA1_FD15_Msk /*!< Filter bit 15 */
# define CAN_F14DATA1_FD16_Pos (16U)
# define CAN_F14DATA1_FD16_Msk (0x1U << CAN_F14DATA1_FD16_Pos) /*!< 0x00010000 */
# define CAN_F14DATA1_FD16 CAN_F14DATA1_FD16_Msk /*!< Filter bit 16 */
# define CAN_F14DATA1_FD17_Pos (17U)
# define CAN_F14DATA1_FD17_Msk (0x1U << CAN_F14DATA1_FD17_Pos) /*!< 0x00020000 */
# define CAN_F14DATA1_FD17 CAN_F14DATA1_FD17_Msk /*!< Filter bit 17 */
# define CAN_F14DATA1_FD18_Pos (18U)
# define CAN_F14DATA1_FD18_Msk (0x1U << CAN_F14DATA1_FD18_Pos) /*!< 0x00040000 */
# define CAN_F14DATA1_FD18 CAN_F14DATA1_FD18_Msk /*!< Filter bit 18 */
# define CAN_F14DATA1_FD19_Pos (19U)
# define CAN_F14DATA1_FD19_Msk (0x1U << CAN_F14DATA1_FD19_Pos) /*!< 0x00080000 */
# define CAN_F14DATA1_FD19 CAN_F14DATA1_FD19_Msk /*!< Filter bit 19 */
# define CAN_F14DATA1_FD20_Pos (20U)
# define CAN_F14DATA1_FD20_Msk (0x1U << CAN_F14DATA1_FD20_Pos) /*!< 0x00100000 */
# define CAN_F14DATA1_FD20 CAN_F14DATA1_FD20_Msk /*!< Filter bit 20 */
# define CAN_F14DATA1_FD21_Pos (21U)
# define CAN_F14DATA1_FD21_Msk (0x1U << CAN_F14DATA1_FD21_Pos) /*!< 0x00200000 */
# define CAN_F14DATA1_FD21 CAN_F14DATA1_FD21_Msk /*!< Filter bit 21 */
# define CAN_F14DATA1_FD22_Pos (22U)
# define CAN_F14DATA1_FD22_Msk (0x1U << CAN_F14DATA1_FD22_Pos) /*!< 0x00400000 */
# define CAN_F14DATA1_FD22 CAN_F14DATA1_FD22_Msk /*!< Filter bit 22 */
# define CAN_F14DATA1_FD23_Pos (23U)
# define CAN_F14DATA1_FD23_Msk (0x1U << CAN_F14DATA1_FD23_Pos) /*!< 0x00800000 */
# define CAN_F14DATA1_FD23 CAN_F14DATA1_FD23_Msk /*!< Filter bit 23 */
# define CAN_F14DATA1_FD24_Pos (24U)
# define CAN_F14DATA1_FD24_Msk (0x1U << CAN_F14DATA1_FD24_Pos) /*!< 0x01000000 */
# define CAN_F14DATA1_FD24 CAN_F14DATA1_FD24_Msk /*!< Filter bit 24 */
# define CAN_F14DATA1_FD25_Pos (25U)
# define CAN_F14DATA1_FD25_Msk (0x1U << CAN_F14DATA1_FD25_Pos) /*!< 0x02000000 */
# define CAN_F14DATA1_FD25 CAN_F14DATA1_FD25_Msk /*!< Filter bit 25 */
# define CAN_F14DATA1_FD26_Pos (26U)
# define CAN_F14DATA1_FD26_Msk (0x1U << CAN_F14DATA1_FD26_Pos) /*!< 0x04000000 */
# define CAN_F14DATA1_FD26 CAN_F14DATA1_FD26_Msk /*!< Filter bit 26 */
# define CAN_F14DATA1_FD27_Pos (27U)
# define CAN_F14DATA1_FD27_Msk (0x1U << CAN_F14DATA1_FD27_Pos) /*!< 0x08000000 */
# define CAN_F14DATA1_FD27 CAN_F14DATA1_FD27_Msk /*!< Filter bit 27 */
# define CAN_F14DATA1_FD28_Pos (28U)
# define CAN_F14DATA1_FD28_Msk (0x1U << CAN_F14DATA1_FD28_Pos) /*!< 0x10000000 */
# define CAN_F14DATA1_FD28 CAN_F14DATA1_FD28_Msk /*!< Filter bit 28 */
# define CAN_F14DATA1_FD29_Pos (29U)
# define CAN_F14DATA1_FD29_Msk (0x1U << CAN_F14DATA1_FD29_Pos) /*!< 0x20000000 */
# define CAN_F14DATA1_FD29 CAN_F14DATA1_FD29_Msk /*!< Filter bit 29 */
# define CAN_F14DATA1_FD30_Pos (30U)
# define CAN_F14DATA1_FD30_Msk (0x1U << CAN_F14DATA1_FD30_Pos) /*!< 0x40000000 */
# define CAN_F14DATA1_FD30 CAN_F14DATA1_FD30_Msk /*!< Filter bit 30 */
# define CAN_F14DATA1_FD31_Pos (31U)
# define CAN_F14DATA1_FD31_Msk (0x1U << CAN_F14DATA1_FD31_Pos) /*!< 0x80000000 */
# define CAN_F14DATA1_FD31 CAN_F14DATA1_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F15R2 register ******************/
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# define CAN_F15DATA1_FD0_Pos (0U)
# define CAN_F15DATA1_FD0_Msk (0x1U << CAN_F15DATA1_FD0_Pos) /*!< 0x00000001 */
# define CAN_F15DATA1_FD0 CAN_F15DATA1_FD0_Msk /*!< Filter bit 0 */
# define CAN_F15DATA1_FD1_Pos (1U)
# define CAN_F15DATA1_FD1_Msk (0x1U << CAN_F15DATA1_FD1_Pos) /*!< 0x00000002 */
# define CAN_F15DATA1_FD1 CAN_F15DATA1_FD1_Msk /*!< Filter bit 1 */
# define CAN_F15DATA1_FD2_Pos (2U)
# define CAN_F15DATA1_FD2_Msk (0x1U << CAN_F15DATA1_FD2_Pos) /*!< 0x00000004 */
# define CAN_F15DATA1_FD2 CAN_F15DATA1_FD2_Msk /*!< Filter bit 2 */
# define CAN_F15DATA1_FD3_Pos (3U)
# define CAN_F15DATA1_FD3_Msk (0x1U << CAN_F15DATA1_FD3_Pos) /*!< 0x00000008 */
# define CAN_F15DATA1_FD3 CAN_F15DATA1_FD3_Msk /*!< Filter bit 3 */
# define CAN_F15DATA1_FD4_Pos (4U)
# define CAN_F15DATA1_FD4_Msk (0x1U << CAN_F15DATA1_FD4_Pos) /*!< 0x00000010 */
# define CAN_F15DATA1_FD4 CAN_F15DATA1_FD4_Msk /*!< Filter bit 4 */
# define CAN_F15DATA1_FD5_Pos (5U)
# define CAN_F15DATA1_FD5_Msk (0x1U << CAN_F15DATA1_FD5_Pos) /*!< 0x00000020 */
# define CAN_F15DATA1_FD5 CAN_F15DATA1_FD5_Msk /*!< Filter bit 5 */
# define CAN_F15DATA1_FD6_Pos (6U)
# define CAN_F15DATA1_FD6_Msk (0x1U << CAN_F15DATA1_FD6_Pos) /*!< 0x00000040 */
# define CAN_F15DATA1_FD6 CAN_F15DATA1_FD6_Msk /*!< Filter bit 6 */
# define CAN_F15DATA1_FD7_Pos (7U)
# define CAN_F15DATA1_FD7_Msk (0x1U << CAN_F15DATA1_FD7_Pos) /*!< 0x00000080 */
# define CAN_F15DATA1_FD7 CAN_F15DATA1_FD7_Msk /*!< Filter bit 7 */
# define CAN_F15DATA1_FD8_Pos (8U)
# define CAN_F15DATA1_FD8_Msk (0x1U << CAN_F15DATA1_FD8_Pos) /*!< 0x00000100 */
# define CAN_F15DATA1_FD8 CAN_F15DATA1_FD8_Msk /*!< Filter bit 8 */
# define CAN_F15DATA1_FD9_Pos (9U)
# define CAN_F15DATA1_FD9_Msk (0x1U << CAN_F15DATA1_FD9_Pos) /*!< 0x00000200 */
# define CAN_F15DATA1_FD9 CAN_F15DATA1_FD9_Msk /*!< Filter bit 9 */
# define CAN_F15DATA1_FD10_Pos (10U)
# define CAN_F15DATA1_FD10_Msk (0x1U << CAN_F15DATA1_FD10_Pos) /*!< 0x00000400 */
# define CAN_F15DATA1_FD10 CAN_F15DATA1_FD10_Msk /*!< Filter bit 10 */
# define CAN_F15DATA1_FD11_Pos (11U)
# define CAN_F15DATA1_FD11_Msk (0x1U << CAN_F15DATA1_FD11_Pos) /*!< 0x00000800 */
# define CAN_F15DATA1_FD11 CAN_F15DATA1_FD11_Msk /*!< Filter bit 11 */
# define CAN_F15DATA1_FD12_Pos (12U)
# define CAN_F15DATA1_FD12_Msk (0x1U << CAN_F15DATA1_FD12_Pos) /*!< 0x00001000 */
# define CAN_F15DATA1_FD12 CAN_F15DATA1_FD12_Msk /*!< Filter bit 12 */
# define CAN_F15DATA1_FD13_Pos (13U)
# define CAN_F15DATA1_FD13_Msk (0x1U << CAN_F15DATA1_FD13_Pos) /*!< 0x00002000 */
# define CAN_F15DATA1_FD13 CAN_F15DATA1_FD13_Msk /*!< Filter bit 13 */
# define CAN_F15DATA1_FD14_Pos (14U)
# define CAN_F15DATA1_FD14_Msk (0x1U << CAN_F15DATA1_FD14_Pos) /*!< 0x00004000 */
# define CAN_F15DATA1_FD14 CAN_F15DATA1_FD14_Msk /*!< Filter bit 14 */
# define CAN_F15DATA1_FD15_Pos (15U)
# define CAN_F15DATA1_FD15_Msk (0x1U << CAN_F15DATA1_FD15_Pos) /*!< 0x00008000 */
# define CAN_F15DATA1_FD15 CAN_F15DATA1_FD15_Msk /*!< Filter bit 15 */
# define CAN_F15DATA1_FD16_Pos (16U)
# define CAN_F15DATA1_FD16_Msk (0x1U << CAN_F15DATA1_FD16_Pos) /*!< 0x00010000 */
# define CAN_F15DATA1_FD16 CAN_F15DATA1_FD16_Msk /*!< Filter bit 16 */
# define CAN_F15DATA1_FD17_Pos (17U)
# define CAN_F15DATA1_FD17_Msk (0x1U << CAN_F15DATA1_FD17_Pos) /*!< 0x00020000 */
# define CAN_F15DATA1_FD17 CAN_F15DATA1_FD17_Msk /*!< Filter bit 17 */
# define CAN_F15DATA1_FD18_Pos (18U)
# define CAN_F15DATA1_FD18_Msk (0x1U << CAN_F15DATA1_FD18_Pos) /*!< 0x00040000 */
# define CAN_F15DATA1_FD18 CAN_F15DATA1_FD18_Msk /*!< Filter bit 18 */
# define CAN_F15DATA1_FD19_Pos (19U)
# define CAN_F15DATA1_FD19_Msk (0x1U << CAN_F15DATA1_FD19_Pos) /*!< 0x00080000 */
# define CAN_F15DATA1_FD19 CAN_F15DATA1_FD19_Msk /*!< Filter bit 19 */
# define CAN_F15DATA1_FD20_Pos (20U)
# define CAN_F15DATA1_FD20_Msk (0x1U << CAN_F15DATA1_FD20_Pos) /*!< 0x00100000 */
# define CAN_F15DATA1_FD20 CAN_F15DATA1_FD20_Msk /*!< Filter bit 20 */
# define CAN_F15DATA1_FD21_Pos (21U)
# define CAN_F15DATA1_FD21_Msk (0x1U << CAN_F15DATA1_FD21_Pos) /*!< 0x00200000 */
# define CAN_F15DATA1_FD21 CAN_F15DATA1_FD21_Msk /*!< Filter bit 21 */
# define CAN_F15DATA1_FD22_Pos (22U)
# define CAN_F15DATA1_FD22_Msk (0x1U << CAN_F15DATA1_FD22_Pos) /*!< 0x00400000 */
# define CAN_F15DATA1_FD22 CAN_F15DATA1_FD22_Msk /*!< Filter bit 22 */
# define CAN_F15DATA1_FD23_Pos (23U)
# define CAN_F15DATA1_FD23_Msk (0x1U << CAN_F15DATA1_FD23_Pos) /*!< 0x00800000 */
# define CAN_F15DATA1_FD23 CAN_F15DATA1_FD23_Msk /*!< Filter bit 23 */
# define CAN_F15DATA1_FD24_Pos (24U)
# define CAN_F15DATA1_FD24_Msk (0x1U << CAN_F15DATA1_FD24_Pos) /*!< 0x01000000 */
# define CAN_F15DATA1_FD24 CAN_F15DATA1_FD24_Msk /*!< Filter bit 24 */
# define CAN_F15DATA1_FD25_Pos (25U)
# define CAN_F15DATA1_FD25_Msk (0x1U << CAN_F15DATA1_FD25_Pos) /*!< 0x02000000 */
# define CAN_F15DATA1_FD25 CAN_F15DATA1_FD25_Msk /*!< Filter bit 25 */
# define CAN_F15DATA1_FD26_Pos (26U)
# define CAN_F15DATA1_FD26_Msk (0x1U << CAN_F15DATA1_FD26_Pos) /*!< 0x04000000 */
# define CAN_F15DATA1_FD26 CAN_F15DATA1_FD26_Msk /*!< Filter bit 26 */
# define CAN_F15DATA1_FD27_Pos (27U)
# define CAN_F15DATA1_FD27_Msk (0x1U << CAN_F15DATA1_FD27_Pos) /*!< 0x08000000 */
# define CAN_F15DATA1_FD27 CAN_F15DATA1_FD27_Msk /*!< Filter bit 27 */
# define CAN_F15DATA1_FD28_Pos (28U)
# define CAN_F15DATA1_FD28_Msk (0x1U << CAN_F15DATA1_FD28_Pos) /*!< 0x10000000 */
# define CAN_F15DATA1_FD28 CAN_F15DATA1_FD28_Msk /*!< Filter bit 28 */
# define CAN_F15DATA1_FD29_Pos (29U)
# define CAN_F15DATA1_FD29_Msk (0x1U << CAN_F15DATA1_FD29_Pos) /*!< 0x20000000 */
# define CAN_F15DATA1_FD29 CAN_F15DATA1_FD29_Msk /*!< Filter bit 29 */
# define CAN_F15DATA1_FD30_Pos (30U)
# define CAN_F15DATA1_FD30_Msk (0x1U << CAN_F15DATA1_FD30_Pos) /*!< 0x40000000 */
# define CAN_F15DATA1_FD30 CAN_F15DATA1_FD30_Msk /*!< Filter bit 30 */
# define CAN_F15DATA1_FD31_Pos (31U)
# define CAN_F15DATA1_FD31_Msk (0x1U << CAN_F15DATA1_FD31_Pos) /*!< 0x80000000 */
# define CAN_F15DATA1_FD31 CAN_F15DATA1_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F16R2 register ******************/
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# define CAN_F16DATA1_FD0_Pos (0U)
# define CAN_F16DATA1_FD0_Msk (0x1U << CAN_F16DATA1_FD0_Pos) /*!< 0x00000001 */
# define CAN_F16DATA1_FD0 CAN_F16DATA1_FD0_Msk /*!< Filter bit 0 */
# define CAN_F16DATA1_FD1_Pos (1U)
# define CAN_F16DATA1_FD1_Msk (0x1U << CAN_F16DATA1_FD1_Pos) /*!< 0x00000002 */
# define CAN_F16DATA1_FD1 CAN_F16DATA1_FD1_Msk /*!< Filter bit 1 */
# define CAN_F16DATA1_FD2_Pos (2U)
# define CAN_F16DATA1_FD2_Msk (0x1U << CAN_F16DATA1_FD2_Pos) /*!< 0x00000004 */
# define CAN_F16DATA1_FD2 CAN_F16DATA1_FD2_Msk /*!< Filter bit 2 */
# define CAN_F16DATA1_FD3_Pos (3U)
# define CAN_F16DATA1_FD3_Msk (0x1U << CAN_F16DATA1_FD3_Pos) /*!< 0x00000008 */
# define CAN_F16DATA1_FD3 CAN_F16DATA1_FD3_Msk /*!< Filter bit 3 */
# define CAN_F16DATA1_FD4_Pos (4U)
# define CAN_F16DATA1_FD4_Msk (0x1U << CAN_F16DATA1_FD4_Pos) /*!< 0x00000010 */
# define CAN_F16DATA1_FD4 CAN_F16DATA1_FD4_Msk /*!< Filter bit 4 */
# define CAN_F16DATA1_FD5_Pos (5U)
# define CAN_F16DATA1_FD5_Msk (0x1U << CAN_F16DATA1_FD5_Pos) /*!< 0x00000020 */
# define CAN_F16DATA1_FD5 CAN_F16DATA1_FD5_Msk /*!< Filter bit 5 */
# define CAN_F16DATA1_FD6_Pos (6U)
# define CAN_F16DATA1_FD6_Msk (0x1U << CAN_F16DATA1_FD6_Pos) /*!< 0x00000040 */
# define CAN_F16DATA1_FD6 CAN_F16DATA1_FD6_Msk /*!< Filter bit 6 */
# define CAN_F16DATA1_FD7_Pos (7U)
# define CAN_F16DATA1_FD7_Msk (0x1U << CAN_F16DATA1_FD7_Pos) /*!< 0x00000080 */
# define CAN_F16DATA1_FD7 CAN_F16DATA1_FD7_Msk /*!< Filter bit 7 */
# define CAN_F16DATA1_FD8_Pos (8U)
# define CAN_F16DATA1_FD8_Msk (0x1U << CAN_F16DATA1_FD8_Pos) /*!< 0x00000100 */
# define CAN_F16DATA1_FD8 CAN_F16DATA1_FD8_Msk /*!< Filter bit 8 */
# define CAN_F16DATA1_FD9_Pos (9U)
# define CAN_F16DATA1_FD9_Msk (0x1U << CAN_F16DATA1_FD9_Pos) /*!< 0x00000200 */
# define CAN_F16DATA1_FD9 CAN_F16DATA1_FD9_Msk /*!< Filter bit 9 */
# define CAN_F16DATA1_FD10_Pos (10U)
# define CAN_F16DATA1_FD10_Msk (0x1U << CAN_F16DATA1_FD10_Pos) /*!< 0x00000400 */
# define CAN_F16DATA1_FD10 CAN_F16DATA1_FD10_Msk /*!< Filter bit 10 */
# define CAN_F16DATA1_FD11_Pos (11U)
# define CAN_F16DATA1_FD11_Msk (0x1U << CAN_F16DATA1_FD11_Pos) /*!< 0x00000800 */
# define CAN_F16DATA1_FD11 CAN_F16DATA1_FD11_Msk /*!< Filter bit 11 */
# define CAN_F16DATA1_FD12_Pos (12U)
# define CAN_F16DATA1_FD12_Msk (0x1U << CAN_F16DATA1_FD12_Pos) /*!< 0x00001000 */
# define CAN_F16DATA1_FD12 CAN_F16DATA1_FD12_Msk /*!< Filter bit 12 */
# define CAN_F16DATA1_FD13_Pos (13U)
# define CAN_F16DATA1_FD13_Msk (0x1U << CAN_F16DATA1_FD13_Pos) /*!< 0x00002000 */
# define CAN_F16DATA1_FD13 CAN_F16DATA1_FD13_Msk /*!< Filter bit 13 */
# define CAN_F16DATA1_FD14_Pos (14U)
# define CAN_F16DATA1_FD14_Msk (0x1U << CAN_F16DATA1_FD14_Pos) /*!< 0x00004000 */
# define CAN_F16DATA1_FD14 CAN_F16DATA1_FD14_Msk /*!< Filter bit 14 */
# define CAN_F16DATA1_FD15_Pos (15U)
# define CAN_F16DATA1_FD15_Msk (0x1U << CAN_F16DATA1_FD15_Pos) /*!< 0x00008000 */
# define CAN_F16DATA1_FD15 CAN_F16DATA1_FD15_Msk /*!< Filter bit 15 */
# define CAN_F16DATA1_FD16_Pos (16U)
# define CAN_F16DATA1_FD16_Msk (0x1U << CAN_F16DATA1_FD16_Pos) /*!< 0x00010000 */
# define CAN_F16DATA1_FD16 CAN_F16DATA1_FD16_Msk /*!< Filter bit 16 */
# define CAN_F16DATA1_FD17_Pos (17U)
# define CAN_F16DATA1_FD17_Msk (0x1U << CAN_F16DATA1_FD17_Pos) /*!< 0x00020000 */
# define CAN_F16DATA1_FD17 CAN_F16DATA1_FD17_Msk /*!< Filter bit 17 */
# define CAN_F16DATA1_FD18_Pos (18U)
# define CAN_F16DATA1_FD18_Msk (0x1U << CAN_F16DATA1_FD18_Pos) /*!< 0x00040000 */
# define CAN_F16DATA1_FD18 CAN_F16DATA1_FD18_Msk /*!< Filter bit 18 */
# define CAN_F16DATA1_FD19_Pos (19U)
# define CAN_F16DATA1_FD19_Msk (0x1U << CAN_F16DATA1_FD19_Pos) /*!< 0x00080000 */
# define CAN_F16DATA1_FD19 CAN_F16DATA1_FD19_Msk /*!< Filter bit 19 */
# define CAN_F16DATA1_FD20_Pos (20U)
# define CAN_F16DATA1_FD20_Msk (0x1U << CAN_F16DATA1_FD20_Pos) /*!< 0x00100000 */
# define CAN_F16DATA1_FD20 CAN_F16DATA1_FD20_Msk /*!< Filter bit 20 */
# define CAN_F16DATA1_FD21_Pos (21U)
# define CAN_F16DATA1_FD21_Msk (0x1U << CAN_F16DATA1_FD21_Pos) /*!< 0x00200000 */
# define CAN_F16DATA1_FD21 CAN_F16DATA1_FD21_Msk /*!< Filter bit 21 */
# define CAN_F16DATA1_FD22_Pos (22U)
# define CAN_F16DATA1_FD22_Msk (0x1U << CAN_F16DATA1_FD22_Pos) /*!< 0x00400000 */
# define CAN_F16DATA1_FD22 CAN_F16DATA1_FD22_Msk /*!< Filter bit 22 */
# define CAN_F16DATA1_FD23_Pos (23U)
# define CAN_F16DATA1_FD23_Msk (0x1U << CAN_F16DATA1_FD23_Pos) /*!< 0x00800000 */
# define CAN_F16DATA1_FD23 CAN_F16DATA1_FD23_Msk /*!< Filter bit 23 */
# define CAN_F16DATA1_FD24_Pos (24U)
# define CAN_F16DATA1_FD24_Msk (0x1U << CAN_F16DATA1_FD24_Pos) /*!< 0x01000000 */
# define CAN_F16DATA1_FD24 CAN_F16DATA1_FD24_Msk /*!< Filter bit 24 */
# define CAN_F16DATA1_FD25_Pos (25U)
# define CAN_F16DATA1_FD25_Msk (0x1U << CAN_F16DATA1_FD25_Pos) /*!< 0x02000000 */
# define CAN_F16DATA1_FD25 CAN_F16DATA1_FD25_Msk /*!< Filter bit 25 */
# define CAN_F16DATA1_FD26_Pos (26U)
# define CAN_F16DATA1_FD26_Msk (0x1U << CAN_F16DATA1_FD26_Pos) /*!< 0x04000000 */
# define CAN_F16DATA1_FD26 CAN_F16DATA1_FD26_Msk /*!< Filter bit 26 */
# define CAN_F16DATA1_FD27_Pos (27U)
# define CAN_F16DATA1_FD27_Msk (0x1U << CAN_F16DATA1_FD27_Pos) /*!< 0x08000000 */
# define CAN_F16DATA1_FD27 CAN_F16DATA1_FD27_Msk /*!< Filter bit 27 */
# define CAN_F16DATA1_FD28_Pos (28U)
# define CAN_F16DATA1_FD28_Msk (0x1U << CAN_F16DATA1_FD28_Pos) /*!< 0x10000000 */
# define CAN_F16DATA1_FD28 CAN_F16DATA1_FD28_Msk /*!< Filter bit 28 */
# define CAN_F16DATA1_FD29_Pos (29U)
# define CAN_F16DATA1_FD29_Msk (0x1U << CAN_F16DATA1_FD29_Pos) /*!< 0x20000000 */
# define CAN_F16DATA1_FD29 CAN_F16DATA1_FD29_Msk /*!< Filter bit 29 */
# define CAN_F16DATA1_FD30_Pos (30U)
# define CAN_F16DATA1_FD30_Msk (0x1U << CAN_F16DATA1_FD30_Pos) /*!< 0x40000000 */
# define CAN_F16DATA1_FD30 CAN_F16DATA1_FD30_Msk /*!< Filter bit 30 */
# define CAN_F16DATA1_FD31_Pos (31U)
# define CAN_F16DATA1_FD31_Msk (0x1U << CAN_F16DATA1_FD31_Pos) /*!< 0x80000000 */
# define CAN_F16DATA1_FD31 CAN_F16DATA1_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F17R2 register ******************/
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# define CAN_F17DATA1_FD0_Pos (0U)
# define CAN_F17DATA1_FD0_Msk (0x1U << CAN_F17DATA1_FD0_Pos) /*!< 0x00000001 */
# define CAN_F17DATA1_FD0 CAN_F17DATA1_FD0_Msk /*!< Filter bit 0 */
# define CAN_F17DATA1_FD1_Pos (1U)
# define CAN_F17DATA1_FD1_Msk (0x1U << CAN_F17DATA1_FD1_Pos) /*!< 0x00000002 */
# define CAN_F17DATA1_FD1 CAN_F17DATA1_FD1_Msk /*!< Filter bit 1 */
# define CAN_F17DATA1_FD2_Pos (2U)
# define CAN_F17DATA1_FD2_Msk (0x1U << CAN_F17DATA1_FD2_Pos) /*!< 0x00000004 */
# define CAN_F17DATA1_FD2 CAN_F17DATA1_FD2_Msk /*!< Filter bit 2 */
# define CAN_F17DATA1_FD3_Pos (3U)
# define CAN_F17DATA1_FD3_Msk (0x1U << CAN_F17DATA1_FD3_Pos) /*!< 0x00000008 */
# define CAN_F17DATA1_FD3 CAN_F17DATA1_FD3_Msk /*!< Filter bit 3 */
# define CAN_F17DATA1_FD4_Pos (4U)
# define CAN_F17DATA1_FD4_Msk (0x1U << CAN_F17DATA1_FD4_Pos) /*!< 0x00000010 */
# define CAN_F17DATA1_FD4 CAN_F17DATA1_FD4_Msk /*!< Filter bit 4 */
# define CAN_F17DATA1_FD5_Pos (5U)
# define CAN_F17DATA1_FD5_Msk (0x1U << CAN_F17DATA1_FD5_Pos) /*!< 0x00000020 */
# define CAN_F17DATA1_FD5 CAN_F17DATA1_FD5_Msk /*!< Filter bit 5 */
# define CAN_F17DATA1_FD6_Pos (6U)
# define CAN_F17DATA1_FD6_Msk (0x1U << CAN_F17DATA1_FD6_Pos) /*!< 0x00000040 */
# define CAN_F17DATA1_FD6 CAN_F17DATA1_FD6_Msk /*!< Filter bit 6 */
# define CAN_F17DATA1_FD7_Pos (7U)
# define CAN_F17DATA1_FD7_Msk (0x1U << CAN_F17DATA1_FD7_Pos) /*!< 0x00000080 */
# define CAN_F17DATA1_FD7 CAN_F17DATA1_FD7_Msk /*!< Filter bit 7 */
# define CAN_F17DATA1_FD8_Pos (8U)
# define CAN_F17DATA1_FD8_Msk (0x1U << CAN_F17DATA1_FD8_Pos) /*!< 0x00000100 */
# define CAN_F17DATA1_FD8 CAN_F17DATA1_FD8_Msk /*!< Filter bit 8 */
# define CAN_F17DATA1_FD9_Pos (9U)
# define CAN_F17DATA1_FD9_Msk (0x1U << CAN_F17DATA1_FD9_Pos) /*!< 0x00000200 */
# define CAN_F17DATA1_FD9 CAN_F17DATA1_FD9_Msk /*!< Filter bit 9 */
# define CAN_F17DATA1_FD10_Pos (10U)
# define CAN_F17DATA1_FD10_Msk (0x1U << CAN_F17DATA1_FD10_Pos) /*!< 0x00000400 */
# define CAN_F17DATA1_FD10 CAN_F17DATA1_FD10_Msk /*!< Filter bit 10 */
# define CAN_F17DATA1_FD11_Pos (11U)
# define CAN_F17DATA1_FD11_Msk (0x1U << CAN_F17DATA1_FD11_Pos) /*!< 0x00000800 */
# define CAN_F17DATA1_FD11 CAN_F17DATA1_FD11_Msk /*!< Filter bit 11 */
# define CAN_F17DATA1_FD12_Pos (12U)
# define CAN_F17DATA1_FD12_Msk (0x1U << CAN_F17DATA1_FD12_Pos) /*!< 0x00001000 */
# define CAN_F17DATA1_FD12 CAN_F17DATA1_FD12_Msk /*!< Filter bit 12 */
# define CAN_F17DATA1_FD13_Pos (13U)
# define CAN_F17DATA1_FD13_Msk (0x1U << CAN_F17DATA1_FD13_Pos) /*!< 0x00002000 */
# define CAN_F17DATA1_FD13 CAN_F17DATA1_FD13_Msk /*!< Filter bit 13 */
# define CAN_F17DATA1_FD14_Pos (14U)
# define CAN_F17DATA1_FD14_Msk (0x1U << CAN_F17DATA1_FD14_Pos) /*!< 0x00004000 */
# define CAN_F17DATA1_FD14 CAN_F17DATA1_FD14_Msk /*!< Filter bit 14 */
# define CAN_F17DATA1_FD15_Pos (15U)
# define CAN_F17DATA1_FD15_Msk (0x1U << CAN_F17DATA1_FD15_Pos) /*!< 0x00008000 */
# define CAN_F17DATA1_FD15 CAN_F17DATA1_FD15_Msk /*!< Filter bit 15 */
# define CAN_F17DATA1_FD16_Pos (16U)
# define CAN_F17DATA1_FD16_Msk (0x1U << CAN_F17DATA1_FD16_Pos) /*!< 0x00010000 */
# define CAN_F17DATA1_FD16 CAN_F17DATA1_FD16_Msk /*!< Filter bit 16 */
# define CAN_F17DATA1_FD17_Pos (17U)
# define CAN_F17DATA1_FD17_Msk (0x1U << CAN_F17DATA1_FD17_Pos) /*!< 0x00020000 */
# define CAN_F17DATA1_FD17 CAN_F17DATA1_FD17_Msk /*!< Filter bit 17 */
# define CAN_F17DATA1_FD18_Pos (18U)
# define CAN_F17DATA1_FD18_Msk (0x1U << CAN_F17DATA1_FD18_Pos) /*!< 0x00040000 */
# define CAN_F17DATA1_FD18 CAN_F17DATA1_FD18_Msk /*!< Filter bit 18 */
# define CAN_F17DATA1_FD19_Pos (19U)
# define CAN_F17DATA1_FD19_Msk (0x1U << CAN_F17DATA1_FD19_Pos) /*!< 0x00080000 */
# define CAN_F17DATA1_FD19 CAN_F17DATA1_FD19_Msk /*!< Filter bit 19 */
# define CAN_F17DATA1_FD20_Pos (20U)
# define CAN_F17DATA1_FD20_Msk (0x1U << CAN_F17DATA1_FD20_Pos) /*!< 0x00100000 */
# define CAN_F17DATA1_FD20 CAN_F17DATA1_FD20_Msk /*!< Filter bit 20 */
# define CAN_F17DATA1_FD21_Pos (21U)
# define CAN_F17DATA1_FD21_Msk (0x1U << CAN_F17DATA1_FD21_Pos) /*!< 0x00200000 */
# define CAN_F17DATA1_FD21 CAN_F17DATA1_FD21_Msk /*!< Filter bit 21 */
# define CAN_F17DATA1_FD22_Pos (22U)
# define CAN_F17DATA1_FD22_Msk (0x1U << CAN_F17DATA1_FD22_Pos) /*!< 0x00400000 */
# define CAN_F17DATA1_FD22 CAN_F17DATA1_FD22_Msk /*!< Filter bit 22 */
# define CAN_F17DATA1_FD23_Pos (23U)
# define CAN_F17DATA1_FD23_Msk (0x1U << CAN_F17DATA1_FD23_Pos) /*!< 0x00800000 */
# define CAN_F17DATA1_FD23 CAN_F17DATA1_FD23_Msk /*!< Filter bit 23 */
# define CAN_F17DATA1_FD24_Pos (24U)
# define CAN_F17DATA1_FD24_Msk (0x1U << CAN_F17DATA1_FD24_Pos) /*!< 0x01000000 */
# define CAN_F17DATA1_FD24 CAN_F17DATA1_FD24_Msk /*!< Filter bit 24 */
# define CAN_F17DATA1_FD25_Pos (25U)
# define CAN_F17DATA1_FD25_Msk (0x1U << CAN_F17DATA1_FD25_Pos) /*!< 0x02000000 */
# define CAN_F17DATA1_FD25 CAN_F17DATA1_FD25_Msk /*!< Filter bit 25 */
# define CAN_F17DATA1_FD26_Pos (26U)
# define CAN_F17DATA1_FD26_Msk (0x1U << CAN_F17DATA1_FD26_Pos) /*!< 0x04000000 */
# define CAN_F17DATA1_FD26 CAN_F17DATA1_FD26_Msk /*!< Filter bit 26 */
# define CAN_F17DATA1_FD27_Pos (27U)
# define CAN_F17DATA1_FD27_Msk (0x1U << CAN_F17DATA1_FD27_Pos) /*!< 0x08000000 */
# define CAN_F17DATA1_FD27 CAN_F17DATA1_FD27_Msk /*!< Filter bit 27 */
# define CAN_F17DATA1_FD28_Pos (28U)
# define CAN_F17DATA1_FD28_Msk (0x1U << CAN_F17DATA1_FD28_Pos) /*!< 0x10000000 */
# define CAN_F17DATA1_FD28 CAN_F17DATA1_FD28_Msk /*!< Filter bit 28 */
# define CAN_F17DATA1_FD29_Pos (29U)
# define CAN_F17DATA1_FD29_Msk (0x1U << CAN_F17DATA1_FD29_Pos) /*!< 0x20000000 */
# define CAN_F17DATA1_FD29 CAN_F17DATA1_FD29_Msk /*!< Filter bit 29 */
# define CAN_F17DATA1_FD30_Pos (30U)
# define CAN_F17DATA1_FD30_Msk (0x1U << CAN_F17DATA1_FD30_Pos) /*!< 0x40000000 */
# define CAN_F17DATA1_FD30 CAN_F17DATA1_FD30_Msk /*!< Filter bit 30 */
# define CAN_F17DATA1_FD31_Pos (31U)
# define CAN_F17DATA1_FD31_Msk (0x1U << CAN_F17DATA1_FD31_Pos) /*!< 0x80000000 */
# define CAN_F17DATA1_FD31 CAN_F17DATA1_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F18R2 register ******************/
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# define CAN_F18DATA1_FD0_Pos (0U)
# define CAN_F18DATA1_FD0_Msk (0x1U << CAN_F18DATA1_FD0_Pos) /*!< 0x00000001 */
# define CAN_F18DATA1_FD0 CAN_F18DATA1_FD0_Msk /*!< Filter bit 0 */
# define CAN_F18DATA1_FD1_Pos (1U)
# define CAN_F18DATA1_FD1_Msk (0x1U << CAN_F18DATA1_FD1_Pos) /*!< 0x00000002 */
# define CAN_F18DATA1_FD1 CAN_F18DATA1_FD1_Msk /*!< Filter bit 1 */
# define CAN_F18DATA1_FD2_Pos (2U)
# define CAN_F18DATA1_FD2_Msk (0x1U << CAN_F18DATA1_FD2_Pos) /*!< 0x00000004 */
# define CAN_F18DATA1_FD2 CAN_F18DATA1_FD2_Msk /*!< Filter bit 2 */
# define CAN_F18DATA1_FD3_Pos (3U)
# define CAN_F18DATA1_FD3_Msk (0x1U << CAN_F18DATA1_FD3_Pos) /*!< 0x00000008 */
# define CAN_F18DATA1_FD3 CAN_F18DATA1_FD3_Msk /*!< Filter bit 3 */
# define CAN_F18DATA1_FD4_Pos (4U)
# define CAN_F18DATA1_FD4_Msk (0x1U << CAN_F18DATA1_FD4_Pos) /*!< 0x00000010 */
# define CAN_F18DATA1_FD4 CAN_F18DATA1_FD4_Msk /*!< Filter bit 4 */
# define CAN_F18DATA1_FD5_Pos (5U)
# define CAN_F18DATA1_FD5_Msk (0x1U << CAN_F18DATA1_FD5_Pos) /*!< 0x00000020 */
# define CAN_F18DATA1_FD5 CAN_F18DATA1_FD5_Msk /*!< Filter bit 5 */
# define CAN_F18DATA1_FD6_Pos (6U)
# define CAN_F18DATA1_FD6_Msk (0x1U << CAN_F18DATA1_FD6_Pos) /*!< 0x00000040 */
# define CAN_F18DATA1_FD6 CAN_F18DATA1_FD6_Msk /*!< Filter bit 6 */
# define CAN_F18DATA1_FD7_Pos (7U)
# define CAN_F18DATA1_FD7_Msk (0x1U << CAN_F18DATA1_FD7_Pos) /*!< 0x00000080 */
# define CAN_F18DATA1_FD7 CAN_F18DATA1_FD7_Msk /*!< Filter bit 7 */
# define CAN_F18DATA1_FD8_Pos (8U)
# define CAN_F18DATA1_FD8_Msk (0x1U << CAN_F18DATA1_FD8_Pos) /*!< 0x00000100 */
# define CAN_F18DATA1_FD8 CAN_F18DATA1_FD8_Msk /*!< Filter bit 8 */
# define CAN_F18DATA1_FD9_Pos (9U)
# define CAN_F18DATA1_FD9_Msk (0x1U << CAN_F18DATA1_FD9_Pos) /*!< 0x00000200 */
# define CAN_F18DATA1_FD9 CAN_F18DATA1_FD9_Msk /*!< Filter bit 9 */
# define CAN_F18DATA1_FD10_Pos (10U)
# define CAN_F18DATA1_FD10_Msk (0x1U << CAN_F18DATA1_FD10_Pos) /*!< 0x00000400 */
# define CAN_F18DATA1_FD10 CAN_F18DATA1_FD10_Msk /*!< Filter bit 10 */
# define CAN_F18DATA1_FD11_Pos (11U)
# define CAN_F18DATA1_FD11_Msk (0x1U << CAN_F18DATA1_FD11_Pos) /*!< 0x00000800 */
# define CAN_F18DATA1_FD11 CAN_F18DATA1_FD11_Msk /*!< Filter bit 11 */
# define CAN_F18DATA1_FD12_Pos (12U)
# define CAN_F18DATA1_FD12_Msk (0x1U << CAN_F18DATA1_FD12_Pos) /*!< 0x00001000 */
# define CAN_F18DATA1_FD12 CAN_F18DATA1_FD12_Msk /*!< Filter bit 12 */
# define CAN_F18DATA1_FD13_Pos (13U)
# define CAN_F18DATA1_FD13_Msk (0x1U << CAN_F18DATA1_FD13_Pos) /*!< 0x00002000 */
# define CAN_F18DATA1_FD13 CAN_F18DATA1_FD13_Msk /*!< Filter bit 13 */
# define CAN_F18DATA1_FD14_Pos (14U)
# define CAN_F18DATA1_FD14_Msk (0x1U << CAN_F18DATA1_FD14_Pos) /*!< 0x00004000 */
# define CAN_F18DATA1_FD14 CAN_F18DATA1_FD14_Msk /*!< Filter bit 14 */
# define CAN_F18DATA1_FD15_Pos (15U)
# define CAN_F18DATA1_FD15_Msk (0x1U << CAN_F18DATA1_FD15_Pos) /*!< 0x00008000 */
# define CAN_F18DATA1_FD15 CAN_F18DATA1_FD15_Msk /*!< Filter bit 15 */
# define CAN_F18DATA1_FD16_Pos (16U)
# define CAN_F18DATA1_FD16_Msk (0x1U << CAN_F18DATA1_FD16_Pos) /*!< 0x00010000 */
# define CAN_F18DATA1_FD16 CAN_F18DATA1_FD16_Msk /*!< Filter bit 16 */
# define CAN_F18DATA1_FD17_Pos (17U)
# define CAN_F18DATA1_FD17_Msk (0x1U << CAN_F18DATA1_FD17_Pos) /*!< 0x00020000 */
# define CAN_F18DATA1_FD17 CAN_F18DATA1_FD17_Msk /*!< Filter bit 17 */
# define CAN_F18DATA1_FD18_Pos (18U)
# define CAN_F18DATA1_FD18_Msk (0x1U << CAN_F18DATA1_FD18_Pos) /*!< 0x00040000 */
# define CAN_F18DATA1_FD18 CAN_F18DATA1_FD18_Msk /*!< Filter bit 18 */
# define CAN_F18DATA1_FD19_Pos (19U)
# define CAN_F18DATA1_FD19_Msk (0x1U << CAN_F18DATA1_FD19_Pos) /*!< 0x00080000 */
# define CAN_F18DATA1_FD19 CAN_F18DATA1_FD19_Msk /*!< Filter bit 19 */
# define CAN_F18DATA1_FD20_Pos (20U)
# define CAN_F18DATA1_FD20_Msk (0x1U << CAN_F18DATA1_FD20_Pos) /*!< 0x00100000 */
# define CAN_F18DATA1_FD20 CAN_F18DATA1_FD20_Msk /*!< Filter bit 20 */
# define CAN_F18DATA1_FD21_Pos (21U)
# define CAN_F18DATA1_FD21_Msk (0x1U << CAN_F18DATA1_FD21_Pos) /*!< 0x00200000 */
# define CAN_F18DATA1_FD21 CAN_F18DATA1_FD21_Msk /*!< Filter bit 21 */
# define CAN_F18DATA1_FD22_Pos (22U)
# define CAN_F18DATA1_FD22_Msk (0x1U << CAN_F18DATA1_FD22_Pos) /*!< 0x00400000 */
# define CAN_F18DATA1_FD22 CAN_F18DATA1_FD22_Msk /*!< Filter bit 22 */
# define CAN_F18DATA1_FD23_Pos (23U)
# define CAN_F18DATA1_FD23_Msk (0x1U << CAN_F18DATA1_FD23_Pos) /*!< 0x00800000 */
# define CAN_F18DATA1_FD23 CAN_F18DATA1_FD23_Msk /*!< Filter bit 23 */
# define CAN_F18DATA1_FD24_Pos (24U)
# define CAN_F18DATA1_FD24_Msk (0x1U << CAN_F18DATA1_FD24_Pos) /*!< 0x01000000 */
# define CAN_F18DATA1_FD24 CAN_F18DATA1_FD24_Msk /*!< Filter bit 24 */
# define CAN_F18DATA1_FD25_Pos (25U)
# define CAN_F18DATA1_FD25_Msk (0x1U << CAN_F18DATA1_FD25_Pos) /*!< 0x02000000 */
# define CAN_F18DATA1_FD25 CAN_F18DATA1_FD25_Msk /*!< Filter bit 25 */
# define CAN_F18DATA1_FD26_Pos (26U)
# define CAN_F18DATA1_FD26_Msk (0x1U << CAN_F18DATA1_FD26_Pos) /*!< 0x04000000 */
# define CAN_F18DATA1_FD26 CAN_F18DATA1_FD26_Msk /*!< Filter bit 26 */
# define CAN_F18DATA1_FD27_Pos (27U)
# define CAN_F18DATA1_FD27_Msk (0x1U << CAN_F18DATA1_FD27_Pos) /*!< 0x08000000 */
# define CAN_F18DATA1_FD27 CAN_F18DATA1_FD27_Msk /*!< Filter bit 27 */
# define CAN_F18DATA1_FD28_Pos (28U)
# define CAN_F18DATA1_FD28_Msk (0x1U << CAN_F18DATA1_FD28_Pos) /*!< 0x10000000 */
# define CAN_F18DATA1_FD28 CAN_F18DATA1_FD28_Msk /*!< Filter bit 28 */
# define CAN_F18DATA1_FD29_Pos (29U)
# define CAN_F18DATA1_FD29_Msk (0x1U << CAN_F18DATA1_FD29_Pos) /*!< 0x20000000 */
# define CAN_F18DATA1_FD29 CAN_F18DATA1_FD29_Msk /*!< Filter bit 29 */
# define CAN_F18DATA1_FD30_Pos (30U)
# define CAN_F18DATA1_FD30_Msk (0x1U << CAN_F18DATA1_FD30_Pos) /*!< 0x40000000 */
# define CAN_F18DATA1_FD30 CAN_F18DATA1_FD30_Msk /*!< Filter bit 30 */
# define CAN_F18DATA1_FD31_Pos (31U)
# define CAN_F18DATA1_FD31_Msk (0x1U << CAN_F18DATA1_FD31_Pos) /*!< 0x80000000 */
# define CAN_F18DATA1_FD31 CAN_F18DATA1_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F19R2 register ******************/
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# define CAN_F19DATA1_FD0_Pos (0U)
# define CAN_F19DATA1_FD0_Msk (0x1U << CAN_F19DATA1_FD0_Pos) /*!< 0x00000001 */
# define CAN_F19DATA1_FD0 CAN_F19DATA1_FD0_Msk /*!< Filter bit 0 */
# define CAN_F19DATA1_FD1_Pos (1U)
# define CAN_F19DATA1_FD1_Msk (0x1U << CAN_F19DATA1_FD1_Pos) /*!< 0x00000002 */
# define CAN_F19DATA1_FD1 CAN_F19DATA1_FD1_Msk /*!< Filter bit 1 */
# define CAN_F19DATA1_FD2_Pos (2U)
# define CAN_F19DATA1_FD2_Msk (0x1U << CAN_F19DATA1_FD2_Pos) /*!< 0x00000004 */
# define CAN_F19DATA1_FD2 CAN_F19DATA1_FD2_Msk /*!< Filter bit 2 */
# define CAN_F19DATA1_FD3_Pos (3U)
# define CAN_F19DATA1_FD3_Msk (0x1U << CAN_F19DATA1_FD3_Pos) /*!< 0x00000008 */
# define CAN_F19DATA1_FD3 CAN_F19DATA1_FD3_Msk /*!< Filter bit 3 */
# define CAN_F19DATA1_FD4_Pos (4U)
# define CAN_F19DATA1_FD4_Msk (0x1U << CAN_F19DATA1_FD4_Pos) /*!< 0x00000010 */
# define CAN_F19DATA1_FD4 CAN_F19DATA1_FD4_Msk /*!< Filter bit 4 */
# define CAN_F19DATA1_FD5_Pos (5U)
# define CAN_F19DATA1_FD5_Msk (0x1U << CAN_F19DATA1_FD5_Pos) /*!< 0x00000020 */
# define CAN_F19DATA1_FD5 CAN_F19DATA1_FD5_Msk /*!< Filter bit 5 */
# define CAN_F19DATA1_FD6_Pos (6U)
# define CAN_F19DATA1_FD6_Msk (0x1U << CAN_F19DATA1_FD6_Pos) /*!< 0x00000040 */
# define CAN_F19DATA1_FD6 CAN_F19DATA1_FD6_Msk /*!< Filter bit 6 */
# define CAN_F19DATA1_FD7_Pos (7U)
# define CAN_F19DATA1_FD7_Msk (0x1U << CAN_F19DATA1_FD7_Pos) /*!< 0x00000080 */
# define CAN_F19DATA1_FD7 CAN_F19DATA1_FD7_Msk /*!< Filter bit 7 */
# define CAN_F19DATA1_FD8_Pos (8U)
# define CAN_F19DATA1_FD8_Msk (0x1U << CAN_F19DATA1_FD8_Pos) /*!< 0x00000100 */
# define CAN_F19DATA1_FD8 CAN_F19DATA1_FD8_Msk /*!< Filter bit 8 */
# define CAN_F19DATA1_FD9_Pos (9U)
# define CAN_F19DATA1_FD9_Msk (0x1U << CAN_F19DATA1_FD9_Pos) /*!< 0x00000200 */
# define CAN_F19DATA1_FD9 CAN_F19DATA1_FD9_Msk /*!< Filter bit 9 */
# define CAN_F19DATA1_FD10_Pos (10U)
# define CAN_F19DATA1_FD10_Msk (0x1U << CAN_F19DATA1_FD10_Pos) /*!< 0x00000400 */
# define CAN_F19DATA1_FD10 CAN_F19DATA1_FD10_Msk /*!< Filter bit 10 */
# define CAN_F19DATA1_FD11_Pos (11U)
# define CAN_F19DATA1_FD11_Msk (0x1U << CAN_F19DATA1_FD11_Pos) /*!< 0x00000800 */
# define CAN_F19DATA1_FD11 CAN_F19DATA1_FD11_Msk /*!< Filter bit 11 */
# define CAN_F19DATA1_FD12_Pos (12U)
# define CAN_F19DATA1_FD12_Msk (0x1U << CAN_F19DATA1_FD12_Pos) /*!< 0x00001000 */
# define CAN_F19DATA1_FD12 CAN_F19DATA1_FD12_Msk /*!< Filter bit 12 */
# define CAN_F19DATA1_FD13_Pos (13U)
# define CAN_F19DATA1_FD13_Msk (0x1U << CAN_F19DATA1_FD13_Pos) /*!< 0x00002000 */
# define CAN_F19DATA1_FD13 CAN_F19DATA1_FD13_Msk /*!< Filter bit 13 */
# define CAN_F19DATA1_FD14_Pos (14U)
# define CAN_F19DATA1_FD14_Msk (0x1U << CAN_F19DATA1_FD14_Pos) /*!< 0x00004000 */
# define CAN_F19DATA1_FD14 CAN_F19DATA1_FD14_Msk /*!< Filter bit 14 */
# define CAN_F19DATA1_FD15_Pos (15U)
# define CAN_F19DATA1_FD15_Msk (0x1U << CAN_F19DATA1_FD15_Pos) /*!< 0x00008000 */
# define CAN_F19DATA1_FD15 CAN_F19DATA1_FD15_Msk /*!< Filter bit 15 */
# define CAN_F19DATA1_FD16_Pos (16U)
# define CAN_F19DATA1_FD16_Msk (0x1U << CAN_F19DATA1_FD16_Pos) /*!< 0x00010000 */
# define CAN_F19DATA1_FD16 CAN_F19DATA1_FD16_Msk /*!< Filter bit 16 */
# define CAN_F19DATA1_FD17_Pos (17U)
# define CAN_F19DATA1_FD17_Msk (0x1U << CAN_F19DATA1_FD17_Pos) /*!< 0x00020000 */
# define CAN_F19DATA1_FD17 CAN_F19DATA1_FD17_Msk /*!< Filter bit 17 */
# define CAN_F19DATA1_FD18_Pos (18U)
# define CAN_F19DATA1_FD18_Msk (0x1U << CAN_F19DATA1_FD18_Pos) /*!< 0x00040000 */
# define CAN_F19DATA1_FD18 CAN_F19DATA1_FD18_Msk /*!< Filter bit 18 */
# define CAN_F19DATA1_FD19_Pos (19U)
# define CAN_F19DATA1_FD19_Msk (0x1U << CAN_F19DATA1_FD19_Pos) /*!< 0x00080000 */
# define CAN_F19DATA1_FD19 CAN_F19DATA1_FD19_Msk /*!< Filter bit 19 */
# define CAN_F19DATA1_FD20_Pos (20U)
# define CAN_F19DATA1_FD20_Msk (0x1U << CAN_F19DATA1_FD20_Pos) /*!< 0x00100000 */
# define CAN_F19DATA1_FD20 CAN_F19DATA1_FD20_Msk /*!< Filter bit 20 */
# define CAN_F19DATA1_FD21_Pos (21U)
# define CAN_F19DATA1_FD21_Msk (0x1U << CAN_F19DATA1_FD21_Pos) /*!< 0x00200000 */
# define CAN_F19DATA1_FD21 CAN_F19DATA1_FD21_Msk /*!< Filter bit 21 */
# define CAN_F19DATA1_FD22_Pos (22U)
# define CAN_F19DATA1_FD22_Msk (0x1U << CAN_F19DATA1_FD22_Pos) /*!< 0x00400000 */
# define CAN_F19DATA1_FD22 CAN_F19DATA1_FD22_Msk /*!< Filter bit 22 */
# define CAN_F19DATA1_FD23_Pos (23U)
# define CAN_F19DATA1_FD23_Msk (0x1U << CAN_F19DATA1_FD23_Pos) /*!< 0x00800000 */
# define CAN_F19DATA1_FD23 CAN_F19DATA1_FD23_Msk /*!< Filter bit 23 */
# define CAN_F19DATA1_FD24_Pos (24U)
# define CAN_F19DATA1_FD24_Msk (0x1U << CAN_F19DATA1_FD24_Pos) /*!< 0x01000000 */
# define CAN_F19DATA1_FD24 CAN_F19DATA1_FD24_Msk /*!< Filter bit 24 */
# define CAN_F19DATA1_FD25_Pos (25U)
# define CAN_F19DATA1_FD25_Msk (0x1U << CAN_F19DATA1_FD25_Pos) /*!< 0x02000000 */
# define CAN_F19DATA1_FD25 CAN_F19DATA1_FD25_Msk /*!< Filter bit 25 */
# define CAN_F19DATA1_FD26_Pos (26U)
# define CAN_F19DATA1_FD26_Msk (0x1U << CAN_F19DATA1_FD26_Pos) /*!< 0x04000000 */
# define CAN_F19DATA1_FD26 CAN_F19DATA1_FD26_Msk /*!< Filter bit 26 */
# define CAN_F19DATA1_FD27_Pos (27U)
# define CAN_F19DATA1_FD27_Msk (0x1U << CAN_F19DATA1_FD27_Pos) /*!< 0x08000000 */
# define CAN_F19DATA1_FD27 CAN_F19DATA1_FD27_Msk /*!< Filter bit 27 */
# define CAN_F19DATA1_FD28_Pos (28U)
# define CAN_F19DATA1_FD28_Msk (0x1U << CAN_F19DATA1_FD28_Pos) /*!< 0x10000000 */
# define CAN_F19DATA1_FD28 CAN_F19DATA1_FD28_Msk /*!< Filter bit 28 */
# define CAN_F19DATA1_FD29_Pos (29U)
# define CAN_F19DATA1_FD29_Msk (0x1U << CAN_F19DATA1_FD29_Pos) /*!< 0x20000000 */
# define CAN_F19DATA1_FD29 CAN_F19DATA1_FD29_Msk /*!< Filter bit 29 */
# define CAN_F19DATA1_FD30_Pos (30U)
# define CAN_F19DATA1_FD30_Msk (0x1U << CAN_F19DATA1_FD30_Pos) /*!< 0x40000000 */
# define CAN_F19DATA1_FD30 CAN_F19DATA1_FD30_Msk /*!< Filter bit 30 */
# define CAN_F19DATA1_FD31_Pos (31U)
# define CAN_F19DATA1_FD31_Msk (0x1U << CAN_F19DATA1_FD31_Pos) /*!< 0x80000000 */
# define CAN_F19DATA1_FD31 CAN_F19DATA1_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F20R2 register ******************/
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# define CAN_F20DATA1_FD0_Pos (0U)
# define CAN_F20DATA1_FD0_Msk (0x1U << CAN_F20DATA1_FD0_Pos) /*!< 0x00000001 */
# define CAN_F20DATA1_FD0 CAN_F20DATA1_FD0_Msk /*!< Filter bit 0 */
# define CAN_F20DATA1_FD1_Pos (1U)
# define CAN_F20DATA1_FD1_Msk (0x1U << CAN_F20DATA1_FD1_Pos) /*!< 0x00000002 */
# define CAN_F20DATA1_FD1 CAN_F20DATA1_FD1_Msk /*!< Filter bit 1 */
# define CAN_F20DATA1_FD2_Pos (2U)
# define CAN_F20DATA1_FD2_Msk (0x1U << CAN_F20DATA1_FD2_Pos) /*!< 0x00000004 */
# define CAN_F20DATA1_FD2 CAN_F20DATA1_FD2_Msk /*!< Filter bit 2 */
# define CAN_F20DATA1_FD3_Pos (3U)
# define CAN_F20DATA1_FD3_Msk (0x1U << CAN_F20DATA1_FD3_Pos) /*!< 0x00000008 */
# define CAN_F20DATA1_FD3 CAN_F20DATA1_FD3_Msk /*!< Filter bit 3 */
# define CAN_F20DATA1_FD4_Pos (4U)
# define CAN_F20DATA1_FD4_Msk (0x1U << CAN_F20DATA1_FD4_Pos) /*!< 0x00000010 */
# define CAN_F20DATA1_FD4 CAN_F20DATA1_FD4_Msk /*!< Filter bit 4 */
# define CAN_F20DATA1_FD5_Pos (5U)
# define CAN_F20DATA1_FD5_Msk (0x1U << CAN_F20DATA1_FD5_Pos) /*!< 0x00000020 */
# define CAN_F20DATA1_FD5 CAN_F20DATA1_FD5_Msk /*!< Filter bit 5 */
# define CAN_F20DATA1_FD6_Pos (6U)
# define CAN_F20DATA1_FD6_Msk (0x1U << CAN_F20DATA1_FD6_Pos) /*!< 0x00000040 */
# define CAN_F20DATA1_FD6 CAN_F20DATA1_FD6_Msk /*!< Filter bit 6 */
# define CAN_F20DATA1_FD7_Pos (7U)
# define CAN_F20DATA1_FD7_Msk (0x1U << CAN_F20DATA1_FD7_Pos) /*!< 0x00000080 */
# define CAN_F20DATA1_FD7 CAN_F20DATA1_FD7_Msk /*!< Filter bit 7 */
# define CAN_F20DATA1_FD8_Pos (8U)
# define CAN_F20DATA1_FD8_Msk (0x1U << CAN_F20DATA1_FD8_Pos) /*!< 0x00000100 */
# define CAN_F20DATA1_FD8 CAN_F20DATA1_FD8_Msk /*!< Filter bit 8 */
# define CAN_F20DATA1_FD9_Pos (9U)
# define CAN_F20DATA1_FD9_Msk (0x1U << CAN_F20DATA1_FD9_Pos) /*!< 0x00000200 */
# define CAN_F20DATA1_FD9 CAN_F20DATA1_FD9_Msk /*!< Filter bit 9 */
# define CAN_F20DATA1_FD10_Pos (10U)
# define CAN_F20DATA1_FD10_Msk (0x1U << CAN_F20DATA1_FD10_Pos) /*!< 0x00000400 */
# define CAN_F20DATA1_FD10 CAN_F20DATA1_FD10_Msk /*!< Filter bit 10 */
# define CAN_F20DATA1_FD11_Pos (11U)
# define CAN_F20DATA1_FD11_Msk (0x1U << CAN_F20DATA1_FD11_Pos) /*!< 0x00000800 */
# define CAN_F20DATA1_FD11 CAN_F20DATA1_FD11_Msk /*!< Filter bit 11 */
# define CAN_F20DATA1_FD12_Pos (12U)
# define CAN_F20DATA1_FD12_Msk (0x1U << CAN_F20DATA1_FD12_Pos) /*!< 0x00001000 */
# define CAN_F20DATA1_FD12 CAN_F20DATA1_FD12_Msk /*!< Filter bit 12 */
# define CAN_F20DATA1_FD13_Pos (13U)
# define CAN_F20DATA1_FD13_Msk (0x1U << CAN_F20DATA1_FD13_Pos) /*!< 0x00002000 */
# define CAN_F20DATA1_FD13 CAN_F20DATA1_FD13_Msk /*!< Filter bit 13 */
# define CAN_F20DATA1_FD14_Pos (14U)
# define CAN_F20DATA1_FD14_Msk (0x1U << CAN_F20DATA1_FD14_Pos) /*!< 0x00004000 */
# define CAN_F20DATA1_FD14 CAN_F20DATA1_FD14_Msk /*!< Filter bit 14 */
# define CAN_F20DATA1_FD15_Pos (15U)
# define CAN_F20DATA1_FD15_Msk (0x1U << CAN_F20DATA1_FD15_Pos) /*!< 0x00008000 */
# define CAN_F20DATA1_FD15 CAN_F20DATA1_FD15_Msk /*!< Filter bit 15 */
# define CAN_F20DATA1_FD16_Pos (16U)
# define CAN_F20DATA1_FD16_Msk (0x1U << CAN_F20DATA1_FD16_Pos) /*!< 0x00010000 */
# define CAN_F20DATA1_FD16 CAN_F20DATA1_FD16_Msk /*!< Filter bit 16 */
# define CAN_F20DATA1_FD17_Pos (17U)
# define CAN_F20DATA1_FD17_Msk (0x1U << CAN_F20DATA1_FD17_Pos) /*!< 0x00020000 */
# define CAN_F20DATA1_FD17 CAN_F20DATA1_FD17_Msk /*!< Filter bit 17 */
# define CAN_F20DATA1_FD18_Pos (18U)
# define CAN_F20DATA1_FD18_Msk (0x1U << CAN_F20DATA1_FD18_Pos) /*!< 0x00040000 */
# define CAN_F20DATA1_FD18 CAN_F20DATA1_FD18_Msk /*!< Filter bit 18 */
# define CAN_F20DATA1_FD19_Pos (19U)
# define CAN_F20DATA1_FD19_Msk (0x1U << CAN_F20DATA1_FD19_Pos) /*!< 0x00080000 */
# define CAN_F20DATA1_FD19 CAN_F20DATA1_FD19_Msk /*!< Filter bit 19 */
# define CAN_F20DATA1_FD20_Pos (20U)
# define CAN_F20DATA1_FD20_Msk (0x1U << CAN_F20DATA1_FD20_Pos) /*!< 0x00100000 */
# define CAN_F20DATA1_FD20 CAN_F20DATA1_FD20_Msk /*!< Filter bit 20 */
# define CAN_F20DATA1_FD21_Pos (21U)
# define CAN_F20DATA1_FD21_Msk (0x1U << CAN_F20DATA1_FD21_Pos) /*!< 0x00200000 */
# define CAN_F20DATA1_FD21 CAN_F20DATA1_FD21_Msk /*!< Filter bit 21 */
# define CAN_F20DATA1_FD22_Pos (22U)
# define CAN_F20DATA1_FD22_Msk (0x1U << CAN_F20DATA1_FD22_Pos) /*!< 0x00400000 */
# define CAN_F20DATA1_FD22 CAN_F20DATA1_FD22_Msk /*!< Filter bit 22 */
# define CAN_F20DATA1_FD23_Pos (23U)
# define CAN_F20DATA1_FD23_Msk (0x1U << CAN_F20DATA1_FD23_Pos) /*!< 0x00800000 */
# define CAN_F20DATA1_FD23 CAN_F20DATA1_FD23_Msk /*!< Filter bit 23 */
# define CAN_F20DATA1_FD24_Pos (24U)
# define CAN_F20DATA1_FD24_Msk (0x1U << CAN_F20DATA1_FD24_Pos) /*!< 0x01000000 */
# define CAN_F20DATA1_FD24 CAN_F20DATA1_FD24_Msk /*!< Filter bit 24 */
# define CAN_F20DATA1_FD25_Pos (25U)
# define CAN_F20DATA1_FD25_Msk (0x1U << CAN_F20DATA1_FD25_Pos) /*!< 0x02000000 */
# define CAN_F20DATA1_FD25 CAN_F20DATA1_FD25_Msk /*!< Filter bit 25 */
# define CAN_F20DATA1_FD26_Pos (26U)
# define CAN_F20DATA1_FD26_Msk (0x1U << CAN_F20DATA1_FD26_Pos) /*!< 0x04000000 */
# define CAN_F20DATA1_FD26 CAN_F20DATA1_FD26_Msk /*!< Filter bit 26 */
# define CAN_F20DATA1_FD27_Pos (27U)
# define CAN_F20DATA1_FD27_Msk (0x1U << CAN_F20DATA1_FD27_Pos) /*!< 0x08000000 */
# define CAN_F20DATA1_FD27 CAN_F20DATA1_FD27_Msk /*!< Filter bit 27 */
# define CAN_F20DATA1_FD28_Pos (28U)
# define CAN_F20DATA1_FD28_Msk (0x1U << CAN_F20DATA1_FD28_Pos) /*!< 0x10000000 */
# define CAN_F20DATA1_FD28 CAN_F20DATA1_FD28_Msk /*!< Filter bit 28 */
# define CAN_F20DATA1_FD29_Pos (29U)
# define CAN_F20DATA1_FD29_Msk (0x1U << CAN_F20DATA1_FD29_Pos) /*!< 0x20000000 */
# define CAN_F20DATA1_FD29 CAN_F20DATA1_FD29_Msk /*!< Filter bit 29 */
# define CAN_F20DATA1_FD30_Pos (30U)
# define CAN_F20DATA1_FD30_Msk (0x1U << CAN_F20DATA1_FD30_Pos) /*!< 0x40000000 */
# define CAN_F20DATA1_FD30 CAN_F20DATA1_FD30_Msk /*!< Filter bit 30 */
# define CAN_F20DATA1_FD31_Pos (31U)
# define CAN_F20DATA1_FD31_Msk (0x1U << CAN_F20DATA1_FD31_Pos) /*!< 0x80000000 */
# define CAN_F20DATA1_FD31 CAN_F20DATA1_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F21R2 register ******************/
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# define CAN_F21DATA1_FD0_Pos (0U)
# define CAN_F21DATA1_FD0_Msk (0x1U << CAN_F21DATA1_FD0_Pos) /*!< 0x00000001 */
# define CAN_F21DATA1_FD0 CAN_F21DATA1_FD0_Msk /*!< Filter bit 0 */
# define CAN_F21DATA1_FD1_Pos (1U)
# define CAN_F21DATA1_FD1_Msk (0x1U << CAN_F21DATA1_FD1_Pos) /*!< 0x00000002 */
# define CAN_F21DATA1_FD1 CAN_F21DATA1_FD1_Msk /*!< Filter bit 1 */
# define CAN_F21DATA1_FD2_Pos (2U)
# define CAN_F21DATA1_FD2_Msk (0x1U << CAN_F21DATA1_FD2_Pos) /*!< 0x00000004 */
# define CAN_F21DATA1_FD2 CAN_F21DATA1_FD2_Msk /*!< Filter bit 2 */
# define CAN_F21DATA1_FD3_Pos (3U)
# define CAN_F21DATA1_FD3_Msk (0x1U << CAN_F21DATA1_FD3_Pos) /*!< 0x00000008 */
# define CAN_F21DATA1_FD3 CAN_F21DATA1_FD3_Msk /*!< Filter bit 3 */
# define CAN_F21DATA1_FD4_Pos (4U)
# define CAN_F21DATA1_FD4_Msk (0x1U << CAN_F21DATA1_FD4_Pos) /*!< 0x00000010 */
# define CAN_F21DATA1_FD4 CAN_F21DATA1_FD4_Msk /*!< Filter bit 4 */
# define CAN_F21DATA1_FD5_Pos (5U)
# define CAN_F21DATA1_FD5_Msk (0x1U << CAN_F21DATA1_FD5_Pos) /*!< 0x00000020 */
# define CAN_F21DATA1_FD5 CAN_F21DATA1_FD5_Msk /*!< Filter bit 5 */
# define CAN_F21DATA1_FD6_Pos (6U)
# define CAN_F21DATA1_FD6_Msk (0x1U << CAN_F21DATA1_FD6_Pos) /*!< 0x00000040 */
# define CAN_F21DATA1_FD6 CAN_F21DATA1_FD6_Msk /*!< Filter bit 6 */
# define CAN_F21DATA1_FD7_Pos (7U)
# define CAN_F21DATA1_FD7_Msk (0x1U << CAN_F21DATA1_FD7_Pos) /*!< 0x00000080 */
# define CAN_F21DATA1_FD7 CAN_F21DATA1_FD7_Msk /*!< Filter bit 7 */
# define CAN_F21DATA1_FD8_Pos (8U)
# define CAN_F21DATA1_FD8_Msk (0x1U << CAN_F21DATA1_FD8_Pos) /*!< 0x00000100 */
# define CAN_F21DATA1_FD8 CAN_F21DATA1_FD8_Msk /*!< Filter bit 8 */
# define CAN_F21DATA1_FD9_Pos (9U)
# define CAN_F21DATA1_FD9_Msk (0x1U << CAN_F21DATA1_FD9_Pos) /*!< 0x00000200 */
# define CAN_F21DATA1_FD9 CAN_F21DATA1_FD9_Msk /*!< Filter bit 9 */
# define CAN_F21DATA1_FD10_Pos (10U)
# define CAN_F21DATA1_FD10_Msk (0x1U << CAN_F21DATA1_FD10_Pos) /*!< 0x00000400 */
# define CAN_F21DATA1_FD10 CAN_F21DATA1_FD10_Msk /*!< Filter bit 10 */
# define CAN_F21DATA1_FD11_Pos (11U)
# define CAN_F21DATA1_FD11_Msk (0x1U << CAN_F21DATA1_FD11_Pos) /*!< 0x00000800 */
# define CAN_F21DATA1_FD11 CAN_F21DATA1_FD11_Msk /*!< Filter bit 11 */
# define CAN_F21DATA1_FD12_Pos (12U)
# define CAN_F21DATA1_FD12_Msk (0x1U << CAN_F21DATA1_FD12_Pos) /*!< 0x00001000 */
# define CAN_F21DATA1_FD12 CAN_F21DATA1_FD12_Msk /*!< Filter bit 12 */
# define CAN_F21DATA1_FD13_Pos (13U)
# define CAN_F21DATA1_FD13_Msk (0x1U << CAN_F21DATA1_FD13_Pos) /*!< 0x00002000 */
# define CAN_F21DATA1_FD13 CAN_F21DATA1_FD13_Msk /*!< Filter bit 13 */
# define CAN_F21DATA1_FD14_Pos (14U)
# define CAN_F21DATA1_FD14_Msk (0x1U << CAN_F21DATA1_FD14_Pos) /*!< 0x00004000 */
# define CAN_F21DATA1_FD14 CAN_F21DATA1_FD14_Msk /*!< Filter bit 14 */
# define CAN_F21DATA1_FD15_Pos (15U)
# define CAN_F21DATA1_FD15_Msk (0x1U << CAN_F21DATA1_FD15_Pos) /*!< 0x00008000 */
# define CAN_F21DATA1_FD15 CAN_F21DATA1_FD15_Msk /*!< Filter bit 15 */
# define CAN_F21DATA1_FD16_Pos (16U)
# define CAN_F21DATA1_FD16_Msk (0x1U << CAN_F21DATA1_FD16_Pos) /*!< 0x00010000 */
# define CAN_F21DATA1_FD16 CAN_F21DATA1_FD16_Msk /*!< Filter bit 16 */
# define CAN_F21DATA1_FD17_Pos (17U)
# define CAN_F21DATA1_FD17_Msk (0x1U << CAN_F21DATA1_FD17_Pos) /*!< 0x00020000 */
# define CAN_F21DATA1_FD17 CAN_F21DATA1_FD17_Msk /*!< Filter bit 17 */
# define CAN_F21DATA1_FD18_Pos (18U)
# define CAN_F21DATA1_FD18_Msk (0x1U << CAN_F21DATA1_FD18_Pos) /*!< 0x00040000 */
# define CAN_F21DATA1_FD18 CAN_F21DATA1_FD18_Msk /*!< Filter bit 18 */
# define CAN_F21DATA1_FD19_Pos (19U)
# define CAN_F21DATA1_FD19_Msk (0x1U << CAN_F21DATA1_FD19_Pos) /*!< 0x00080000 */
# define CAN_F21DATA1_FD19 CAN_F21DATA1_FD19_Msk /*!< Filter bit 19 */
# define CAN_F21DATA1_FD20_Pos (20U)
# define CAN_F21DATA1_FD20_Msk (0x1U << CAN_F21DATA1_FD20_Pos) /*!< 0x00100000 */
# define CAN_F21DATA1_FD20 CAN_F21DATA1_FD20_Msk /*!< Filter bit 20 */
# define CAN_F21DATA1_FD21_Pos (21U)
# define CAN_F21DATA1_FD21_Msk (0x1U << CAN_F21DATA1_FD21_Pos) /*!< 0x00200000 */
# define CAN_F21DATA1_FD21 CAN_F21DATA1_FD21_Msk /*!< Filter bit 21 */
# define CAN_F21DATA1_FD22_Pos (22U)
# define CAN_F21DATA1_FD22_Msk (0x1U << CAN_F21DATA1_FD22_Pos) /*!< 0x00400000 */
# define CAN_F21DATA1_FD22 CAN_F21DATA1_FD22_Msk /*!< Filter bit 22 */
# define CAN_F21DATA1_FD23_Pos (23U)
# define CAN_F21DATA1_FD23_Msk (0x1U << CAN_F21DATA1_FD23_Pos) /*!< 0x00800000 */
# define CAN_F21DATA1_FD23 CAN_F21DATA1_FD23_Msk /*!< Filter bit 23 */
# define CAN_F21DATA1_FD24_Pos (24U)
# define CAN_F21DATA1_FD24_Msk (0x1U << CAN_F21DATA1_FD24_Pos) /*!< 0x01000000 */
# define CAN_F21DATA1_FD24 CAN_F21DATA1_FD24_Msk /*!< Filter bit 24 */
# define CAN_F21DATA1_FD25_Pos (25U)
# define CAN_F21DATA1_FD25_Msk (0x1U << CAN_F21DATA1_FD25_Pos) /*!< 0x02000000 */
# define CAN_F21DATA1_FD25 CAN_F21DATA1_FD25_Msk /*!< Filter bit 25 */
# define CAN_F21DATA1_FD26_Pos (26U)
# define CAN_F21DATA1_FD26_Msk (0x1U << CAN_F21DATA1_FD26_Pos) /*!< 0x04000000 */
# define CAN_F21DATA1_FD26 CAN_F21DATA1_FD26_Msk /*!< Filter bit 26 */
# define CAN_F21DATA1_FD27_Pos (27U)
# define CAN_F21DATA1_FD27_Msk (0x1U << CAN_F21DATA1_FD27_Pos) /*!< 0x08000000 */
# define CAN_F21DATA1_FD27 CAN_F21DATA1_FD27_Msk /*!< Filter bit 27 */
# define CAN_F21DATA1_FD28_Pos (28U)
# define CAN_F21DATA1_FD28_Msk (0x1U << CAN_F21DATA1_FD28_Pos) /*!< 0x10000000 */
# define CAN_F21DATA1_FD28 CAN_F21DATA1_FD28_Msk /*!< Filter bit 28 */
# define CAN_F21DATA1_FD29_Pos (29U)
# define CAN_F21DATA1_FD29_Msk (0x1U << CAN_F21DATA1_FD29_Pos) /*!< 0x20000000 */
# define CAN_F21DATA1_FD29 CAN_F21DATA1_FD29_Msk /*!< Filter bit 29 */
# define CAN_F21DATA1_FD30_Pos (30U)
# define CAN_F21DATA1_FD30_Msk (0x1U << CAN_F21DATA1_FD30_Pos) /*!< 0x40000000 */
# define CAN_F21DATA1_FD30 CAN_F21DATA1_FD30_Msk /*!< Filter bit 30 */
# define CAN_F21DATA1_FD31_Pos (31U)
# define CAN_F21DATA1_FD31_Msk (0x1U << CAN_F21DATA1_FD31_Pos) /*!< 0x80000000 */
# define CAN_F21DATA1_FD31 CAN_F21DATA1_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F22R2 register ******************/
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# define CAN_F22DATA1_FD0_Pos (0U)
# define CAN_F22DATA1_FD0_Msk (0x1U << CAN_F22DATA1_FD0_Pos) /*!< 0x00000001 */
# define CAN_F22DATA1_FD0 CAN_F22DATA1_FD0_Msk /*!< Filter bit 0 */
# define CAN_F22DATA1_FD1_Pos (1U)
# define CAN_F22DATA1_FD1_Msk (0x1U << CAN_F22DATA1_FD1_Pos) /*!< 0x00000002 */
# define CAN_F22DATA1_FD1 CAN_F22DATA1_FD1_Msk /*!< Filter bit 1 */
# define CAN_F22DATA1_FD2_Pos (2U)
# define CAN_F22DATA1_FD2_Msk (0x1U << CAN_F22DATA1_FD2_Pos) /*!< 0x00000004 */
# define CAN_F22DATA1_FD2 CAN_F22DATA1_FD2_Msk /*!< Filter bit 2 */
# define CAN_F22DATA1_FD3_Pos (3U)
# define CAN_F22DATA1_FD3_Msk (0x1U << CAN_F22DATA1_FD3_Pos) /*!< 0x00000008 */
# define CAN_F22DATA1_FD3 CAN_F22DATA1_FD3_Msk /*!< Filter bit 3 */
# define CAN_F22DATA1_FD4_Pos (4U)
# define CAN_F22DATA1_FD4_Msk (0x1U << CAN_F22DATA1_FD4_Pos) /*!< 0x00000010 */
# define CAN_F22DATA1_FD4 CAN_F22DATA1_FD4_Msk /*!< Filter bit 4 */
# define CAN_F22DATA1_FD5_Pos (5U)
# define CAN_F22DATA1_FD5_Msk (0x1U << CAN_F22DATA1_FD5_Pos) /*!< 0x00000020 */
# define CAN_F22DATA1_FD5 CAN_F22DATA1_FD5_Msk /*!< Filter bit 5 */
# define CAN_F22DATA1_FD6_Pos (6U)
# define CAN_F22DATA1_FD6_Msk (0x1U << CAN_F22DATA1_FD6_Pos) /*!< 0x00000040 */
# define CAN_F22DATA1_FD6 CAN_F22DATA1_FD6_Msk /*!< Filter bit 6 */
# define CAN_F22DATA1_FD7_Pos (7U)
# define CAN_F22DATA1_FD7_Msk (0x1U << CAN_F22DATA1_FD7_Pos) /*!< 0x00000080 */
# define CAN_F22DATA1_FD7 CAN_F22DATA1_FD7_Msk /*!< Filter bit 7 */
# define CAN_F22DATA1_FD8_Pos (8U)
# define CAN_F22DATA1_FD8_Msk (0x1U << CAN_F22DATA1_FD8_Pos) /*!< 0x00000100 */
# define CAN_F22DATA1_FD8 CAN_F22DATA1_FD8_Msk /*!< Filter bit 8 */
# define CAN_F22DATA1_FD9_Pos (9U)
# define CAN_F22DATA1_FD9_Msk (0x1U << CAN_F22DATA1_FD9_Pos) /*!< 0x00000200 */
# define CAN_F22DATA1_FD9 CAN_F22DATA1_FD9_Msk /*!< Filter bit 9 */
# define CAN_F22DATA1_FD10_Pos (10U)
# define CAN_F22DATA1_FD10_Msk (0x1U << CAN_F22DATA1_FD10_Pos) /*!< 0x00000400 */
# define CAN_F22DATA1_FD10 CAN_F22DATA1_FD10_Msk /*!< Filter bit 10 */
# define CAN_F22DATA1_FD11_Pos (11U)
# define CAN_F22DATA1_FD11_Msk (0x1U << CAN_F22DATA1_FD11_Pos) /*!< 0x00000800 */
# define CAN_F22DATA1_FD11 CAN_F22DATA1_FD11_Msk /*!< Filter bit 11 */
# define CAN_F22DATA1_FD12_Pos (12U)
# define CAN_F22DATA1_FD12_Msk (0x1U << CAN_F22DATA1_FD12_Pos) /*!< 0x00001000 */
# define CAN_F22DATA1_FD12 CAN_F22DATA1_FD12_Msk /*!< Filter bit 12 */
# define CAN_F22DATA1_FD13_Pos (13U)
# define CAN_F22DATA1_FD13_Msk (0x1U << CAN_F22DATA1_FD13_Pos) /*!< 0x00002000 */
# define CAN_F22DATA1_FD13 CAN_F22DATA1_FD13_Msk /*!< Filter bit 13 */
# define CAN_F22DATA1_FD14_Pos (14U)
# define CAN_F22DATA1_FD14_Msk (0x1U << CAN_F22DATA1_FD14_Pos) /*!< 0x00004000 */
# define CAN_F22DATA1_FD14 CAN_F22DATA1_FD14_Msk /*!< Filter bit 14 */
# define CAN_F22DATA1_FD15_Pos (15U)
# define CAN_F22DATA1_FD15_Msk (0x1U << CAN_F22DATA1_FD15_Pos) /*!< 0x00008000 */
# define CAN_F22DATA1_FD15 CAN_F22DATA1_FD15_Msk /*!< Filter bit 15 */
# define CAN_F22DATA1_FD16_Pos (16U)
# define CAN_F22DATA1_FD16_Msk (0x1U << CAN_F22DATA1_FD16_Pos) /*!< 0x00010000 */
# define CAN_F22DATA1_FD16 CAN_F22DATA1_FD16_Msk /*!< Filter bit 16 */
# define CAN_F22DATA1_FD17_Pos (17U)
# define CAN_F22DATA1_FD17_Msk (0x1U << CAN_F22DATA1_FD17_Pos) /*!< 0x00020000 */
# define CAN_F22DATA1_FD17 CAN_F22DATA1_FD17_Msk /*!< Filter bit 17 */
# define CAN_F22DATA1_FD18_Pos (18U)
# define CAN_F22DATA1_FD18_Msk (0x1U << CAN_F22DATA1_FD18_Pos) /*!< 0x00040000 */
# define CAN_F22DATA1_FD18 CAN_F22DATA1_FD18_Msk /*!< Filter bit 18 */
# define CAN_F22DATA1_FD19_Pos (19U)
# define CAN_F22DATA1_FD19_Msk (0x1U << CAN_F22DATA1_FD19_Pos) /*!< 0x00080000 */
# define CAN_F22DATA1_FD19 CAN_F22DATA1_FD19_Msk /*!< Filter bit 19 */
# define CAN_F22DATA1_FD20_Pos (20U)
# define CAN_F22DATA1_FD20_Msk (0x1U << CAN_F22DATA1_FD20_Pos) /*!< 0x00100000 */
# define CAN_F22DATA1_FD20 CAN_F22DATA1_FD20_Msk /*!< Filter bit 20 */
# define CAN_F22DATA1_FD21_Pos (21U)
# define CAN_F22DATA1_FD21_Msk (0x1U << CAN_F22DATA1_FD21_Pos) /*!< 0x00200000 */
# define CAN_F22DATA1_FD21 CAN_F22DATA1_FD21_Msk /*!< Filter bit 21 */
# define CAN_F22DATA1_FD22_Pos (22U)
# define CAN_F22DATA1_FD22_Msk (0x1U << CAN_F22DATA1_FD22_Pos) /*!< 0x00400000 */
# define CAN_F22DATA1_FD22 CAN_F22DATA1_FD22_Msk /*!< Filter bit 22 */
# define CAN_F22DATA1_FD23_Pos (23U)
# define CAN_F22DATA1_FD23_Msk (0x1U << CAN_F22DATA1_FD23_Pos) /*!< 0x00800000 */
# define CAN_F22DATA1_FD23 CAN_F22DATA1_FD23_Msk /*!< Filter bit 23 */
# define CAN_F22DATA1_FD24_Pos (24U)
# define CAN_F22DATA1_FD24_Msk (0x1U << CAN_F22DATA1_FD24_Pos) /*!< 0x01000000 */
# define CAN_F22DATA1_FD24 CAN_F22DATA1_FD24_Msk /*!< Filter bit 24 */
# define CAN_F22DATA1_FD25_Pos (25U)
# define CAN_F22DATA1_FD25_Msk (0x1U << CAN_F22DATA1_FD25_Pos) /*!< 0x02000000 */
# define CAN_F22DATA1_FD25 CAN_F22DATA1_FD25_Msk /*!< Filter bit 25 */
# define CAN_F22DATA1_FD26_Pos (26U)
# define CAN_F22DATA1_FD26_Msk (0x1U << CAN_F22DATA1_FD26_Pos) /*!< 0x04000000 */
# define CAN_F22DATA1_FD26 CAN_F22DATA1_FD26_Msk /*!< Filter bit 26 */
# define CAN_F22DATA1_FD27_Pos (27U)
# define CAN_F22DATA1_FD27_Msk (0x1U << CAN_F22DATA1_FD27_Pos) /*!< 0x08000000 */
# define CAN_F22DATA1_FD27 CAN_F22DATA1_FD27_Msk /*!< Filter bit 27 */
# define CAN_F22DATA1_FD28_Pos (28U)
# define CAN_F22DATA1_FD28_Msk (0x1U << CAN_F22DATA1_FD28_Pos) /*!< 0x10000000 */
# define CAN_F22DATA1_FD28 CAN_F22DATA1_FD28_Msk /*!< Filter bit 28 */
# define CAN_F22DATA1_FD29_Pos (29U)
# define CAN_F22DATA1_FD29_Msk (0x1U << CAN_F22DATA1_FD29_Pos) /*!< 0x20000000 */
# define CAN_F22DATA1_FD29 CAN_F22DATA1_FD29_Msk /*!< Filter bit 29 */
# define CAN_F22DATA1_FD30_Pos (30U)
# define CAN_F22DATA1_FD30_Msk (0x1U << CAN_F22DATA1_FD30_Pos) /*!< 0x40000000 */
# define CAN_F22DATA1_FD30 CAN_F22DATA1_FD30_Msk /*!< Filter bit 30 */
# define CAN_F22DATA1_FD31_Pos (31U)
# define CAN_F22DATA1_FD31_Msk (0x1U << CAN_F22DATA1_FD31_Pos) /*!< 0x80000000 */
# define CAN_F22DATA1_FD31 CAN_F22DATA1_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F23R2 register ******************/
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# define CAN_F23DATA1_FD0_Pos (0U)
# define CAN_F23DATA1_FD0_Msk (0x1U << CAN_F23DATA1_FD0_Pos) /*!< 0x00000001 */
# define CAN_F23DATA1_FD0 CAN_F23DATA1_FD0_Msk /*!< Filter bit 0 */
# define CAN_F23DATA1_FD1_Pos (1U)
# define CAN_F23DATA1_FD1_Msk (0x1U << CAN_F23DATA1_FD1_Pos) /*!< 0x00000002 */
# define CAN_F23DATA1_FD1 CAN_F23DATA1_FD1_Msk /*!< Filter bit 1 */
# define CAN_F23DATA1_FD2_Pos (2U)
# define CAN_F23DATA1_FD2_Msk (0x1U << CAN_F23DATA1_FD2_Pos) /*!< 0x00000004 */
# define CAN_F23DATA1_FD2 CAN_F23DATA1_FD2_Msk /*!< Filter bit 2 */
# define CAN_F23DATA1_FD3_Pos (3U)
# define CAN_F23DATA1_FD3_Msk (0x1U << CAN_F23DATA1_FD3_Pos) /*!< 0x00000008 */
# define CAN_F23DATA1_FD3 CAN_F23DATA1_FD3_Msk /*!< Filter bit 3 */
# define CAN_F23DATA1_FD4_Pos (4U)
# define CAN_F23DATA1_FD4_Msk (0x1U << CAN_F23DATA1_FD4_Pos) /*!< 0x00000010 */
# define CAN_F23DATA1_FD4 CAN_F23DATA1_FD4_Msk /*!< Filter bit 4 */
# define CAN_F23DATA1_FD5_Pos (5U)
# define CAN_F23DATA1_FD5_Msk (0x1U << CAN_F23DATA1_FD5_Pos) /*!< 0x00000020 */
# define CAN_F23DATA1_FD5 CAN_F23DATA1_FD5_Msk /*!< Filter bit 5 */
# define CAN_F23DATA1_FD6_Pos (6U)
# define CAN_F23DATA1_FD6_Msk (0x1U << CAN_F23DATA1_FD6_Pos) /*!< 0x00000040 */
# define CAN_F23DATA1_FD6 CAN_F23DATA1_FD6_Msk /*!< Filter bit 6 */
# define CAN_F23DATA1_FD7_Pos (7U)
# define CAN_F23DATA1_FD7_Msk (0x1U << CAN_F23DATA1_FD7_Pos) /*!< 0x00000080 */
# define CAN_F23DATA1_FD7 CAN_F23DATA1_FD7_Msk /*!< Filter bit 7 */
# define CAN_F23DATA1_FD8_Pos (8U)
# define CAN_F23DATA1_FD8_Msk (0x1U << CAN_F23DATA1_FD8_Pos) /*!< 0x00000100 */
# define CAN_F23DATA1_FD8 CAN_F23DATA1_FD8_Msk /*!< Filter bit 8 */
# define CAN_F23DATA1_FD9_Pos (9U)
# define CAN_F23DATA1_FD9_Msk (0x1U << CAN_F23DATA1_FD9_Pos) /*!< 0x00000200 */
# define CAN_F23DATA1_FD9 CAN_F23DATA1_FD9_Msk /*!< Filter bit 9 */
# define CAN_F23DATA1_FD10_Pos (10U)
# define CAN_F23DATA1_FD10_Msk (0x1U << CAN_F23DATA1_FD10_Pos) /*!< 0x00000400 */
# define CAN_F23DATA1_FD10 CAN_F23DATA1_FD10_Msk /*!< Filter bit 10 */
# define CAN_F23DATA1_FD11_Pos (11U)
# define CAN_F23DATA1_FD11_Msk (0x1U << CAN_F23DATA1_FD11_Pos) /*!< 0x00000800 */
# define CAN_F23DATA1_FD11 CAN_F23DATA1_FD11_Msk /*!< Filter bit 11 */
# define CAN_F23DATA1_FD12_Pos (12U)
# define CAN_F23DATA1_FD12_Msk (0x1U << CAN_F23DATA1_FD12_Pos) /*!< 0x00001000 */
# define CAN_F23DATA1_FD12 CAN_F23DATA1_FD12_Msk /*!< Filter bit 12 */
# define CAN_F23DATA1_FD13_Pos (13U)
# define CAN_F23DATA1_FD13_Msk (0x1U << CAN_F23DATA1_FD13_Pos) /*!< 0x00002000 */
# define CAN_F23DATA1_FD13 CAN_F23DATA1_FD13_Msk /*!< Filter bit 13 */
# define CAN_F23DATA1_FD14_Pos (14U)
# define CAN_F23DATA1_FD14_Msk (0x1U << CAN_F23DATA1_FD14_Pos) /*!< 0x00004000 */
# define CAN_F23DATA1_FD14 CAN_F23DATA1_FD14_Msk /*!< Filter bit 14 */
# define CAN_F23DATA1_FD15_Pos (15U)
# define CAN_F23DATA1_FD15_Msk (0x1U << CAN_F23DATA1_FD15_Pos) /*!< 0x00008000 */
# define CAN_F23DATA1_FD15 CAN_F23DATA1_FD15_Msk /*!< Filter bit 15 */
# define CAN_F23DATA1_FD16_Pos (16U)
# define CAN_F23DATA1_FD16_Msk (0x1U << CAN_F23DATA1_FD16_Pos) /*!< 0x00010000 */
# define CAN_F23DATA1_FD16 CAN_F23DATA1_FD16_Msk /*!< Filter bit 16 */
# define CAN_F23DATA1_FD17_Pos (17U)
# define CAN_F23DATA1_FD17_Msk (0x1U << CAN_F23DATA1_FD17_Pos) /*!< 0x00020000 */
# define CAN_F23DATA1_FD17 CAN_F23DATA1_FD17_Msk /*!< Filter bit 17 */
# define CAN_F23DATA1_FD18_Pos (18U)
# define CAN_F23DATA1_FD18_Msk (0x1U << CAN_F23DATA1_FD18_Pos) /*!< 0x00040000 */
# define CAN_F23DATA1_FD18 CAN_F23DATA1_FD18_Msk /*!< Filter bit 18 */
# define CAN_F23DATA1_FD19_Pos (19U)
# define CAN_F23DATA1_FD19_Msk (0x1U << CAN_F23DATA1_FD19_Pos) /*!< 0x00080000 */
# define CAN_F23DATA1_FD19 CAN_F23DATA1_FD19_Msk /*!< Filter bit 19 */
# define CAN_F23DATA1_FD20_Pos (20U)
# define CAN_F23DATA1_FD20_Msk (0x1U << CAN_F23DATA1_FD20_Pos) /*!< 0x00100000 */
# define CAN_F23DATA1_FD20 CAN_F23DATA1_FD20_Msk /*!< Filter bit 20 */
# define CAN_F23DATA1_FD21_Pos (21U)
# define CAN_F23DATA1_FD21_Msk (0x1U << CAN_F23DATA1_FD21_Pos) /*!< 0x00200000 */
# define CAN_F23DATA1_FD21 CAN_F23DATA1_FD21_Msk /*!< Filter bit 21 */
# define CAN_F23DATA1_FD22_Pos (22U)
# define CAN_F23DATA1_FD22_Msk (0x1U << CAN_F23DATA1_FD22_Pos) /*!< 0x00400000 */
# define CAN_F23DATA1_FD22 CAN_F23DATA1_FD22_Msk /*!< Filter bit 22 */
# define CAN_F23DATA1_FD23_Pos (23U)
# define CAN_F23DATA1_FD23_Msk (0x1U << CAN_F23DATA1_FD23_Pos) /*!< 0x00800000 */
# define CAN_F23DATA1_FD23 CAN_F23DATA1_FD23_Msk /*!< Filter bit 23 */
# define CAN_F23DATA1_FD24_Pos (24U)
# define CAN_F23DATA1_FD24_Msk (0x1U << CAN_F23DATA1_FD24_Pos) /*!< 0x01000000 */
# define CAN_F23DATA1_FD24 CAN_F23DATA1_FD24_Msk /*!< Filter bit 24 */
# define CAN_F23DATA1_FD25_Pos (25U)
# define CAN_F23DATA1_FD25_Msk (0x1U << CAN_F23DATA1_FD25_Pos) /*!< 0x02000000 */
# define CAN_F23DATA1_FD25 CAN_F23DATA1_FD25_Msk /*!< Filter bit 25 */
# define CAN_F23DATA1_FD26_Pos (26U)
# define CAN_F23DATA1_FD26_Msk (0x1U << CAN_F23DATA1_FD26_Pos) /*!< 0x04000000 */
# define CAN_F23DATA1_FD26 CAN_F23DATA1_FD26_Msk /*!< Filter bit 26 */
# define CAN_F23DATA1_FD27_Pos (27U)
# define CAN_F23DATA1_FD27_Msk (0x1U << CAN_F23DATA1_FD27_Pos) /*!< 0x08000000 */
# define CAN_F23DATA1_FD27 CAN_F23DATA1_FD27_Msk /*!< Filter bit 27 */
# define CAN_F23DATA1_FD28_Pos (28U)
# define CAN_F23DATA1_FD28_Msk (0x1U << CAN_F23DATA1_FD28_Pos) /*!< 0x10000000 */
# define CAN_F23DATA1_FD28 CAN_F23DATA1_FD28_Msk /*!< Filter bit 28 */
# define CAN_F23DATA1_FD29_Pos (29U)
# define CAN_F23DATA1_FD29_Msk (0x1U << CAN_F23DATA1_FD29_Pos) /*!< 0x20000000 */
# define CAN_F23DATA1_FD29 CAN_F23DATA1_FD29_Msk /*!< Filter bit 29 */
# define CAN_F23DATA1_FD30_Pos (30U)
# define CAN_F23DATA1_FD30_Msk (0x1U << CAN_F23DATA1_FD30_Pos) /*!< 0x40000000 */
# define CAN_F23DATA1_FD30 CAN_F23DATA1_FD30_Msk /*!< Filter bit 30 */
# define CAN_F23DATA1_FD31_Pos (31U)
# define CAN_F23DATA1_FD31_Msk (0x1U << CAN_F23DATA1_FD31_Pos) /*!< 0x80000000 */
# define CAN_F23DATA1_FD31 CAN_F23DATA1_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F24R2 register ******************/
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# define CAN_F24DATA1_FD0_Pos (0U)
# define CAN_F24DATA1_FD0_Msk (0x1U << CAN_F24DATA1_FD0_Pos) /*!< 0x00000001 */
# define CAN_F24DATA1_FD0 CAN_F24DATA1_FD0_Msk /*!< Filter bit 0 */
# define CAN_F24DATA1_FD1_Pos (1U)
# define CAN_F24DATA1_FD1_Msk (0x1U << CAN_F24DATA1_FD1_Pos) /*!< 0x00000002 */
# define CAN_F24DATA1_FD1 CAN_F24DATA1_FD1_Msk /*!< Filter bit 1 */
# define CAN_F24DATA1_FD2_Pos (2U)
# define CAN_F24DATA1_FD2_Msk (0x1U << CAN_F24DATA1_FD2_Pos) /*!< 0x00000004 */
# define CAN_F24DATA1_FD2 CAN_F24DATA1_FD2_Msk /*!< Filter bit 2 */
# define CAN_F24DATA1_FD3_Pos (3U)
# define CAN_F24DATA1_FD3_Msk (0x1U << CAN_F24DATA1_FD3_Pos) /*!< 0x00000008 */
# define CAN_F24DATA1_FD3 CAN_F24DATA1_FD3_Msk /*!< Filter bit 3 */
# define CAN_F24DATA1_FD4_Pos (4U)
# define CAN_F24DATA1_FD4_Msk (0x1U << CAN_F24DATA1_FD4_Pos) /*!< 0x00000010 */
# define CAN_F24DATA1_FD4 CAN_F24DATA1_FD4_Msk /*!< Filter bit 4 */
# define CAN_F24DATA1_FD5_Pos (5U)
# define CAN_F24DATA1_FD5_Msk (0x1U << CAN_F24DATA1_FD5_Pos) /*!< 0x00000020 */
# define CAN_F24DATA1_FD5 CAN_F24DATA1_FD5_Msk /*!< Filter bit 5 */
# define CAN_F24DATA1_FD6_Pos (6U)
# define CAN_F24DATA1_FD6_Msk (0x1U << CAN_F24DATA1_FD6_Pos) /*!< 0x00000040 */
# define CAN_F24DATA1_FD6 CAN_F24DATA1_FD6_Msk /*!< Filter bit 6 */
# define CAN_F24DATA1_FD7_Pos (7U)
# define CAN_F24DATA1_FD7_Msk (0x1U << CAN_F24DATA1_FD7_Pos) /*!< 0x00000080 */
# define CAN_F24DATA1_FD7 CAN_F24DATA1_FD7_Msk /*!< Filter bit 7 */
# define CAN_F24DATA1_FD8_Pos (8U)
# define CAN_F24DATA1_FD8_Msk (0x1U << CAN_F24DATA1_FD8_Pos) /*!< 0x00000100 */
# define CAN_F24DATA1_FD8 CAN_F24DATA1_FD8_Msk /*!< Filter bit 8 */
# define CAN_F24DATA1_FD9_Pos (9U)
# define CAN_F24DATA1_FD9_Msk (0x1U << CAN_F24DATA1_FD9_Pos) /*!< 0x00000200 */
# define CAN_F24DATA1_FD9 CAN_F24DATA1_FD9_Msk /*!< Filter bit 9 */
# define CAN_F24DATA1_FD10_Pos (10U)
# define CAN_F24DATA1_FD10_Msk (0x1U << CAN_F24DATA1_FD10_Pos) /*!< 0x00000400 */
# define CAN_F24DATA1_FD10 CAN_F24DATA1_FD10_Msk /*!< Filter bit 10 */
# define CAN_F24DATA1_FD11_Pos (11U)
# define CAN_F24DATA1_FD11_Msk (0x1U << CAN_F24DATA1_FD11_Pos) /*!< 0x00000800 */
# define CAN_F24DATA1_FD11 CAN_F24DATA1_FD11_Msk /*!< Filter bit 11 */
# define CAN_F24DATA1_FD12_Pos (12U)
# define CAN_F24DATA1_FD12_Msk (0x1U << CAN_F24DATA1_FD12_Pos) /*!< 0x00001000 */
# define CAN_F24DATA1_FD12 CAN_F24DATA1_FD12_Msk /*!< Filter bit 12 */
# define CAN_F24DATA1_FD13_Pos (13U)
# define CAN_F24DATA1_FD13_Msk (0x1U << CAN_F24DATA1_FD13_Pos) /*!< 0x00002000 */
# define CAN_F24DATA1_FD13 CAN_F24DATA1_FD13_Msk /*!< Filter bit 13 */
# define CAN_F24DATA1_FD14_Pos (14U)
# define CAN_F24DATA1_FD14_Msk (0x1U << CAN_F24DATA1_FD14_Pos) /*!< 0x00004000 */
# define CAN_F24DATA1_FD14 CAN_F24DATA1_FD14_Msk /*!< Filter bit 14 */
# define CAN_F24DATA1_FD15_Pos (15U)
# define CAN_F24DATA1_FD15_Msk (0x1U << CAN_F24DATA1_FD15_Pos) /*!< 0x00008000 */
# define CAN_F24DATA1_FD15 CAN_F24DATA1_FD15_Msk /*!< Filter bit 15 */
# define CAN_F24DATA1_FD16_Pos (16U)
# define CAN_F24DATA1_FD16_Msk (0x1U << CAN_F24DATA1_FD16_Pos) /*!< 0x00010000 */
# define CAN_F24DATA1_FD16 CAN_F24DATA1_FD16_Msk /*!< Filter bit 16 */
# define CAN_F24DATA1_FD17_Pos (17U)
# define CAN_F24DATA1_FD17_Msk (0x1U << CAN_F24DATA1_FD17_Pos) /*!< 0x00020000 */
# define CAN_F24DATA1_FD17 CAN_F24DATA1_FD17_Msk /*!< Filter bit 17 */
# define CAN_F24DATA1_FD18_Pos (18U)
# define CAN_F24DATA1_FD18_Msk (0x1U << CAN_F24DATA1_FD18_Pos) /*!< 0x00040000 */
# define CAN_F24DATA1_FD18 CAN_F24DATA1_FD18_Msk /*!< Filter bit 18 */
# define CAN_F24DATA1_FD19_Pos (19U)
# define CAN_F24DATA1_FD19_Msk (0x1U << CAN_F24DATA1_FD19_Pos) /*!< 0x00080000 */
# define CAN_F24DATA1_FD19 CAN_F24DATA1_FD19_Msk /*!< Filter bit 19 */
# define CAN_F24DATA1_FD20_Pos (20U)
# define CAN_F24DATA1_FD20_Msk (0x1U << CAN_F24DATA1_FD20_Pos) /*!< 0x00100000 */
# define CAN_F24DATA1_FD20 CAN_F24DATA1_FD20_Msk /*!< Filter bit 20 */
# define CAN_F24DATA1_FD21_Pos (21U)
# define CAN_F24DATA1_FD21_Msk (0x1U << CAN_F24DATA1_FD21_Pos) /*!< 0x00200000 */
# define CAN_F24DATA1_FD21 CAN_F24DATA1_FD21_Msk /*!< Filter bit 21 */
# define CAN_F24DATA1_FD22_Pos (22U)
# define CAN_F24DATA1_FD22_Msk (0x1U << CAN_F24DATA1_FD22_Pos) /*!< 0x00400000 */
# define CAN_F24DATA1_FD22 CAN_F24DATA1_FD22_Msk /*!< Filter bit 22 */
# define CAN_F24DATA1_FD23_Pos (23U)
# define CAN_F24DATA1_FD23_Msk (0x1U << CAN_F24DATA1_FD23_Pos) /*!< 0x00800000 */
# define CAN_F24DATA1_FD23 CAN_F24DATA1_FD23_Msk /*!< Filter bit 23 */
# define CAN_F24DATA1_FD24_Pos (24U)
# define CAN_F24DATA1_FD24_Msk (0x1U << CAN_F24DATA1_FD24_Pos) /*!< 0x01000000 */
# define CAN_F24DATA1_FD24 CAN_F24DATA1_FD24_Msk /*!< Filter bit 24 */
# define CAN_F24DATA1_FD25_Pos (25U)
# define CAN_F24DATA1_FD25_Msk (0x1U << CAN_F24DATA1_FD25_Pos) /*!< 0x02000000 */
# define CAN_F24DATA1_FD25 CAN_F24DATA1_FD25_Msk /*!< Filter bit 25 */
# define CAN_F24DATA1_FD26_Pos (26U)
# define CAN_F24DATA1_FD26_Msk (0x1U << CAN_F24DATA1_FD26_Pos) /*!< 0x04000000 */
# define CAN_F24DATA1_FD26 CAN_F24DATA1_FD26_Msk /*!< Filter bit 26 */
# define CAN_F24DATA1_FD27_Pos (27U)
# define CAN_F24DATA1_FD27_Msk (0x1U << CAN_F24DATA1_FD27_Pos) /*!< 0x08000000 */
# define CAN_F24DATA1_FD27 CAN_F24DATA1_FD27_Msk /*!< Filter bit 27 */
# define CAN_F24DATA1_FD28_Pos (28U)
# define CAN_F24DATA1_FD28_Msk (0x1U << CAN_F24DATA1_FD28_Pos) /*!< 0x10000000 */
# define CAN_F24DATA1_FD28 CAN_F24DATA1_FD28_Msk /*!< Filter bit 28 */
# define CAN_F24DATA1_FD29_Pos (29U)
# define CAN_F24DATA1_FD29_Msk (0x1U << CAN_F24DATA1_FD29_Pos) /*!< 0x20000000 */
# define CAN_F24DATA1_FD29 CAN_F24DATA1_FD29_Msk /*!< Filter bit 29 */
# define CAN_F24DATA1_FD30_Pos (30U)
# define CAN_F24DATA1_FD30_Msk (0x1U << CAN_F24DATA1_FD30_Pos) /*!< 0x40000000 */
# define CAN_F24DATA1_FD30 CAN_F24DATA1_FD30_Msk /*!< Filter bit 30 */
# define CAN_F24DATA1_FD31_Pos (31U)
# define CAN_F24DATA1_FD31_Msk (0x1U << CAN_F24DATA1_FD31_Pos) /*!< 0x80000000 */
# define CAN_F24DATA1_FD31 CAN_F24DATA1_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F25R2 register ******************/
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# define CAN_F25DATA1_FD0_Pos (0U)
# define CAN_F25DATA1_FD0_Msk (0x1U << CAN_F25DATA1_FD0_Pos) /*!< 0x00000001 */
# define CAN_F25DATA1_FD0 CAN_F25DATA1_FD0_Msk /*!< Filter bit 0 */
# define CAN_F25DATA1_FD1_Pos (1U)
# define CAN_F25DATA1_FD1_Msk (0x1U << CAN_F25DATA1_FD1_Pos) /*!< 0x00000002 */
# define CAN_F25DATA1_FD1 CAN_F25DATA1_FD1_Msk /*!< Filter bit 1 */
# define CAN_F25DATA1_FD2_Pos (2U)
# define CAN_F25DATA1_FD2_Msk (0x1U << CAN_F25DATA1_FD2_Pos) /*!< 0x00000004 */
# define CAN_F25DATA1_FD2 CAN_F25DATA1_FD2_Msk /*!< Filter bit 2 */
# define CAN_F25DATA1_FD3_Pos (3U)
# define CAN_F25DATA1_FD3_Msk (0x1U << CAN_F25DATA1_FD3_Pos) /*!< 0x00000008 */
# define CAN_F25DATA1_FD3 CAN_F25DATA1_FD3_Msk /*!< Filter bit 3 */
# define CAN_F25DATA1_FD4_Pos (4U)
# define CAN_F25DATA1_FD4_Msk (0x1U << CAN_F25DATA1_FD4_Pos) /*!< 0x00000010 */
# define CAN_F25DATA1_FD4 CAN_F25DATA1_FD4_Msk /*!< Filter bit 4 */
# define CAN_F25DATA1_FD5_Pos (5U)
# define CAN_F25DATA1_FD5_Msk (0x1U << CAN_F25DATA1_FD5_Pos) /*!< 0x00000020 */
# define CAN_F25DATA1_FD5 CAN_F25DATA1_FD5_Msk /*!< Filter bit 5 */
# define CAN_F25DATA1_FD6_Pos (6U)
# define CAN_F25DATA1_FD6_Msk (0x1U << CAN_F25DATA1_FD6_Pos) /*!< 0x00000040 */
# define CAN_F25DATA1_FD6 CAN_F25DATA1_FD6_Msk /*!< Filter bit 6 */
# define CAN_F25DATA1_FD7_Pos (7U)
# define CAN_F25DATA1_FD7_Msk (0x1U << CAN_F25DATA1_FD7_Pos) /*!< 0x00000080 */
# define CAN_F25DATA1_FD7 CAN_F25DATA1_FD7_Msk /*!< Filter bit 7 */
# define CAN_F25DATA1_FD8_Pos (8U)
# define CAN_F25DATA1_FD8_Msk (0x1U << CAN_F25DATA1_FD8_Pos) /*!< 0x00000100 */
# define CAN_F25DATA1_FD8 CAN_F25DATA1_FD8_Msk /*!< Filter bit 8 */
# define CAN_F25DATA1_FD9_Pos (9U)
# define CAN_F25DATA1_FD9_Msk (0x1U << CAN_F25DATA1_FD9_Pos) /*!< 0x00000200 */
# define CAN_F25DATA1_FD9 CAN_F25DATA1_FD9_Msk /*!< Filter bit 9 */
# define CAN_F25DATA1_FD10_Pos (10U)
# define CAN_F25DATA1_FD10_Msk (0x1U << CAN_F25DATA1_FD10_Pos) /*!< 0x00000400 */
# define CAN_F25DATA1_FD10 CAN_F25DATA1_FD10_Msk /*!< Filter bit 10 */
# define CAN_F25DATA1_FD11_Pos (11U)
# define CAN_F25DATA1_FD11_Msk (0x1U << CAN_F25DATA1_FD11_Pos) /*!< 0x00000800 */
# define CAN_F25DATA1_FD11 CAN_F25DATA1_FD11_Msk /*!< Filter bit 11 */
# define CAN_F25DATA1_FD12_Pos (12U)
# define CAN_F25DATA1_FD12_Msk (0x1U << CAN_F25DATA1_FD12_Pos) /*!< 0x00001000 */
# define CAN_F25DATA1_FD12 CAN_F25DATA1_FD12_Msk /*!< Filter bit 12 */
# define CAN_F25DATA1_FD13_Pos (13U)
# define CAN_F25DATA1_FD13_Msk (0x1U << CAN_F25DATA1_FD13_Pos) /*!< 0x00002000 */
# define CAN_F25DATA1_FD13 CAN_F25DATA1_FD13_Msk /*!< Filter bit 13 */
# define CAN_F25DATA1_FD14_Pos (14U)
# define CAN_F25DATA1_FD14_Msk (0x1U << CAN_F25DATA1_FD14_Pos) /*!< 0x00004000 */
# define CAN_F25DATA1_FD14 CAN_F25DATA1_FD14_Msk /*!< Filter bit 14 */
# define CAN_F25DATA1_FD15_Pos (15U)
# define CAN_F25DATA1_FD15_Msk (0x1U << CAN_F25DATA1_FD15_Pos) /*!< 0x00008000 */
# define CAN_F25DATA1_FD15 CAN_F25DATA1_FD15_Msk /*!< Filter bit 15 */
# define CAN_F25DATA1_FD16_Pos (16U)
# define CAN_F25DATA1_FD16_Msk (0x1U << CAN_F25DATA1_FD16_Pos) /*!< 0x00010000 */
# define CAN_F25DATA1_FD16 CAN_F25DATA1_FD16_Msk /*!< Filter bit 16 */
# define CAN_F25DATA1_FD17_Pos (17U)
# define CAN_F25DATA1_FD17_Msk (0x1U << CAN_F25DATA1_FD17_Pos) /*!< 0x00020000 */
# define CAN_F25DATA1_FD17 CAN_F25DATA1_FD17_Msk /*!< Filter bit 17 */
# define CAN_F25DATA1_FD18_Pos (18U)
# define CAN_F25DATA1_FD18_Msk (0x1U << CAN_F25DATA1_FD18_Pos) /*!< 0x00040000 */
# define CAN_F25DATA1_FD18 CAN_F25DATA1_FD18_Msk /*!< Filter bit 18 */
# define CAN_F25DATA1_FD19_Pos (19U)
# define CAN_F25DATA1_FD19_Msk (0x1U << CAN_F25DATA1_FD19_Pos) /*!< 0x00080000 */
# define CAN_F25DATA1_FD19 CAN_F25DATA1_FD19_Msk /*!< Filter bit 19 */
# define CAN_F25DATA1_FD20_Pos (20U)
# define CAN_F25DATA1_FD20_Msk (0x1U << CAN_F25DATA1_FD20_Pos) /*!< 0x00100000 */
# define CAN_F25DATA1_FD20 CAN_F25DATA1_FD20_Msk /*!< Filter bit 20 */
# define CAN_F25DATA1_FD21_Pos (21U)
# define CAN_F25DATA1_FD21_Msk (0x1U << CAN_F25DATA1_FD21_Pos) /*!< 0x00200000 */
# define CAN_F25DATA1_FD21 CAN_F25DATA1_FD21_Msk /*!< Filter bit 21 */
# define CAN_F25DATA1_FD22_Pos (22U)
# define CAN_F25DATA1_FD22_Msk (0x1U << CAN_F25DATA1_FD22_Pos) /*!< 0x00400000 */
# define CAN_F25DATA1_FD22 CAN_F25DATA1_FD22_Msk /*!< Filter bit 22 */
# define CAN_F25DATA1_FD23_Pos (23U)
# define CAN_F25DATA1_FD23_Msk (0x1U << CAN_F25DATA1_FD23_Pos) /*!< 0x00800000 */
# define CAN_F25DATA1_FD23 CAN_F25DATA1_FD23_Msk /*!< Filter bit 23 */
# define CAN_F25DATA1_FD24_Pos (24U)
# define CAN_F25DATA1_FD24_Msk (0x1U << CAN_F25DATA1_FD24_Pos) /*!< 0x01000000 */
# define CAN_F25DATA1_FD24 CAN_F25DATA1_FD24_Msk /*!< Filter bit 24 */
# define CAN_F25DATA1_FD25_Pos (25U)
# define CAN_F25DATA1_FD25_Msk (0x1U << CAN_F25DATA1_FD25_Pos) /*!< 0x02000000 */
# define CAN_F25DATA1_FD25 CAN_F25DATA1_FD25_Msk /*!< Filter bit 25 */
# define CAN_F25DATA1_FD26_Pos (26U)
# define CAN_F25DATA1_FD26_Msk (0x1U << CAN_F25DATA1_FD26_Pos) /*!< 0x04000000 */
# define CAN_F25DATA1_FD26 CAN_F25DATA1_FD26_Msk /*!< Filter bit 26 */
# define CAN_F25DATA1_FD27_Pos (27U)
# define CAN_F25DATA1_FD27_Msk (0x1U << CAN_F25DATA1_FD27_Pos) /*!< 0x08000000 */
# define CAN_F25DATA1_FD27 CAN_F25DATA1_FD27_Msk /*!< Filter bit 27 */
# define CAN_F25DATA1_FD28_Pos (28U)
# define CAN_F25DATA1_FD28_Msk (0x1U << CAN_F25DATA1_FD28_Pos) /*!< 0x10000000 */
# define CAN_F25DATA1_FD28 CAN_F25DATA1_FD28_Msk /*!< Filter bit 28 */
# define CAN_F25DATA1_FD29_Pos (29U)
# define CAN_F25DATA1_FD29_Msk (0x1U << CAN_F25DATA1_FD29_Pos) /*!< 0x20000000 */
# define CAN_F25DATA1_FD29 CAN_F25DATA1_FD29_Msk /*!< Filter bit 29 */
# define CAN_F25DATA1_FD30_Pos (30U)
# define CAN_F25DATA1_FD30_Msk (0x1U << CAN_F25DATA1_FD30_Pos) /*!< 0x40000000 */
# define CAN_F25DATA1_FD30 CAN_F25DATA1_FD30_Msk /*!< Filter bit 30 */
# define CAN_F25DATA1_FD31_Pos (31U)
# define CAN_F25DATA1_FD31_Msk (0x1U << CAN_F25DATA1_FD31_Pos) /*!< 0x80000000 */
# define CAN_F25DATA1_FD31 CAN_F25DATA1_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F26R2 register ******************/
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# define CAN_F26DATA1_FD0_Pos (0U)
# define CAN_F26DATA1_FD0_Msk (0x1U << CAN_F26DATA1_FD0_Pos) /*!< 0x00000001 */
# define CAN_F26DATA1_FD0 CAN_F26DATA1_FD0_Msk /*!< Filter bit 0 */
# define CAN_F26DATA1_FD1_Pos (1U)
# define CAN_F26DATA1_FD1_Msk (0x1U << CAN_F26DATA1_FD1_Pos) /*!< 0x00000002 */
# define CAN_F26DATA1_FD1 CAN_F26DATA1_FD1_Msk /*!< Filter bit 1 */
# define CAN_F26DATA1_FD2_Pos (2U)
# define CAN_F26DATA1_FD2_Msk (0x1U << CAN_F26DATA1_FD2_Pos) /*!< 0x00000004 */
# define CAN_F26DATA1_FD2 CAN_F26DATA1_FD2_Msk /*!< Filter bit 2 */
# define CAN_F26DATA1_FD3_Pos (3U)
# define CAN_F26DATA1_FD3_Msk (0x1U << CAN_F26DATA1_FD3_Pos) /*!< 0x00000008 */
# define CAN_F26DATA1_FD3 CAN_F26DATA1_FD3_Msk /*!< Filter bit 3 */
# define CAN_F26DATA1_FD4_Pos (4U)
# define CAN_F26DATA1_FD4_Msk (0x1U << CAN_F26DATA1_FD4_Pos) /*!< 0x00000010 */
# define CAN_F26DATA1_FD4 CAN_F26DATA1_FD4_Msk /*!< Filter bit 4 */
# define CAN_F26DATA1_FD5_Pos (5U)
# define CAN_F26DATA1_FD5_Msk (0x1U << CAN_F26DATA1_FD5_Pos) /*!< 0x00000020 */
# define CAN_F26DATA1_FD5 CAN_F26DATA1_FD5_Msk /*!< Filter bit 5 */
# define CAN_F26DATA1_FD6_Pos (6U)
# define CAN_F26DATA1_FD6_Msk (0x1U << CAN_F26DATA1_FD6_Pos) /*!< 0x00000040 */
# define CAN_F26DATA1_FD6 CAN_F26DATA1_FD6_Msk /*!< Filter bit 6 */
# define CAN_F26DATA1_FD7_Pos (7U)
# define CAN_F26DATA1_FD7_Msk (0x1U << CAN_F26DATA1_FD7_Pos) /*!< 0x00000080 */
# define CAN_F26DATA1_FD7 CAN_F26DATA1_FD7_Msk /*!< Filter bit 7 */
# define CAN_F26DATA1_FD8_Pos (8U)
# define CAN_F26DATA1_FD8_Msk (0x1U << CAN_F26DATA1_FD8_Pos) /*!< 0x00000100 */
# define CAN_F26DATA1_FD8 CAN_F26DATA1_FD8_Msk /*!< Filter bit 8 */
# define CAN_F26DATA1_FD9_Pos (9U)
# define CAN_F26DATA1_FD9_Msk (0x1U << CAN_F26DATA1_FD9_Pos) /*!< 0x00000200 */
# define CAN_F26DATA1_FD9 CAN_F26DATA1_FD9_Msk /*!< Filter bit 9 */
# define CAN_F26DATA1_FD10_Pos (10U)
# define CAN_F26DATA1_FD10_Msk (0x1U << CAN_F26DATA1_FD10_Pos) /*!< 0x00000400 */
# define CAN_F26DATA1_FD10 CAN_F26DATA1_FD10_Msk /*!< Filter bit 10 */
# define CAN_F26DATA1_FD11_Pos (11U)
# define CAN_F26DATA1_FD11_Msk (0x1U << CAN_F26DATA1_FD11_Pos) /*!< 0x00000800 */
# define CAN_F26DATA1_FD11 CAN_F26DATA1_FD11_Msk /*!< Filter bit 11 */
# define CAN_F26DATA1_FD12_Pos (12U)
# define CAN_F26DATA1_FD12_Msk (0x1U << CAN_F26DATA1_FD12_Pos) /*!< 0x00001000 */
# define CAN_F26DATA1_FD12 CAN_F26DATA1_FD12_Msk /*!< Filter bit 12 */
# define CAN_F26DATA1_FD13_Pos (13U)
# define CAN_F26DATA1_FD13_Msk (0x1U << CAN_F26DATA1_FD13_Pos) /*!< 0x00002000 */
# define CAN_F26DATA1_FD13 CAN_F26DATA1_FD13_Msk /*!< Filter bit 13 */
# define CAN_F26DATA1_FD14_Pos (14U)
# define CAN_F26DATA1_FD14_Msk (0x1U << CAN_F26DATA1_FD14_Pos) /*!< 0x00004000 */
# define CAN_F26DATA1_FD14 CAN_F26DATA1_FD14_Msk /*!< Filter bit 14 */
# define CAN_F26DATA1_FD15_Pos (15U)
# define CAN_F26DATA1_FD15_Msk (0x1U << CAN_F26DATA1_FD15_Pos) /*!< 0x00008000 */
# define CAN_F26DATA1_FD15 CAN_F26DATA1_FD15_Msk /*!< Filter bit 15 */
# define CAN_F26DATA1_FD16_Pos (16U)
# define CAN_F26DATA1_FD16_Msk (0x1U << CAN_F26DATA1_FD16_Pos) /*!< 0x00010000 */
# define CAN_F26DATA1_FD16 CAN_F26DATA1_FD16_Msk /*!< Filter bit 16 */
# define CAN_F26DATA1_FD17_Pos (17U)
# define CAN_F26DATA1_FD17_Msk (0x1U << CAN_F26DATA1_FD17_Pos) /*!< 0x00020000 */
# define CAN_F26DATA1_FD17 CAN_F26DATA1_FD17_Msk /*!< Filter bit 17 */
# define CAN_F26DATA1_FD18_Pos (18U)
# define CAN_F26DATA1_FD18_Msk (0x1U << CAN_F26DATA1_FD18_Pos) /*!< 0x00040000 */
# define CAN_F26DATA1_FD18 CAN_F26DATA1_FD18_Msk /*!< Filter bit 18 */
# define CAN_F26DATA1_FD19_Pos (19U)
# define CAN_F26DATA1_FD19_Msk (0x1U << CAN_F26DATA1_FD19_Pos) /*!< 0x00080000 */
# define CAN_F26DATA1_FD19 CAN_F26DATA1_FD19_Msk /*!< Filter bit 19 */
# define CAN_F26DATA1_FD20_Pos (20U)
# define CAN_F26DATA1_FD20_Msk (0x1U << CAN_F26DATA1_FD20_Pos) /*!< 0x00100000 */
# define CAN_F26DATA1_FD20 CAN_F26DATA1_FD20_Msk /*!< Filter bit 20 */
# define CAN_F26DATA1_FD21_Pos (21U)
# define CAN_F26DATA1_FD21_Msk (0x1U << CAN_F26DATA1_FD21_Pos) /*!< 0x00200000 */
# define CAN_F26DATA1_FD21 CAN_F26DATA1_FD21_Msk /*!< Filter bit 21 */
# define CAN_F26DATA1_FD22_Pos (22U)
# define CAN_F26DATA1_FD22_Msk (0x1U << CAN_F26DATA1_FD22_Pos) /*!< 0x00400000 */
# define CAN_F26DATA1_FD22 CAN_F26DATA1_FD22_Msk /*!< Filter bit 22 */
# define CAN_F26DATA1_FD23_Pos (23U)
# define CAN_F26DATA1_FD23_Msk (0x1U << CAN_F26DATA1_FD23_Pos) /*!< 0x00800000 */
# define CAN_F26DATA1_FD23 CAN_F26DATA1_FD23_Msk /*!< Filter bit 23 */
# define CAN_F26DATA1_FD24_Pos (24U)
# define CAN_F26DATA1_FD24_Msk (0x1U << CAN_F26DATA1_FD24_Pos) /*!< 0x01000000 */
# define CAN_F26DATA1_FD24 CAN_F26DATA1_FD24_Msk /*!< Filter bit 24 */
# define CAN_F26DATA1_FD25_Pos (25U)
# define CAN_F26DATA1_FD25_Msk (0x1U << CAN_F26DATA1_FD25_Pos) /*!< 0x02000000 */
# define CAN_F26DATA1_FD25 CAN_F26DATA1_FD25_Msk /*!< Filter bit 25 */
# define CAN_F26DATA1_FD26_Pos (26U)
# define CAN_F26DATA1_FD26_Msk (0x1U << CAN_F26DATA1_FD26_Pos) /*!< 0x04000000 */
# define CAN_F26DATA1_FD26 CAN_F26DATA1_FD26_Msk /*!< Filter bit 26 */
# define CAN_F26DATA1_FD27_Pos (27U)
# define CAN_F26DATA1_FD27_Msk (0x1U << CAN_F26DATA1_FD27_Pos) /*!< 0x08000000 */
# define CAN_F26DATA1_FD27 CAN_F26DATA1_FD27_Msk /*!< Filter bit 27 */
# define CAN_F26DATA1_FD28_Pos (28U)
# define CAN_F26DATA1_FD28_Msk (0x1U << CAN_F26DATA1_FD28_Pos) /*!< 0x10000000 */
# define CAN_F26DATA1_FD28 CAN_F26DATA1_FD28_Msk /*!< Filter bit 28 */
# define CAN_F26DATA1_FD29_Pos (29U)
# define CAN_F26DATA1_FD29_Msk (0x1U << CAN_F26DATA1_FD29_Pos) /*!< 0x20000000 */
# define CAN_F26DATA1_FD29 CAN_F26DATA1_FD29_Msk /*!< Filter bit 29 */
# define CAN_F26DATA1_FD30_Pos (30U)
# define CAN_F26DATA1_FD30_Msk (0x1U << CAN_F26DATA1_FD30_Pos) /*!< 0x40000000 */
# define CAN_F26DATA1_FD30 CAN_F26DATA1_FD30_Msk /*!< Filter bit 30 */
# define CAN_F26DATA1_FD31_Pos (31U)
# define CAN_F26DATA1_FD31_Msk (0x1U << CAN_F26DATA1_FD31_Pos) /*!< 0x80000000 */
# define CAN_F26DATA1_FD31 CAN_F26DATA1_FD31_Msk /*!< Filter bit 31 */
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/******************* Bit definition for CAN_F27R2 register ******************/
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# define CAN_F27DATA1_FD0_Pos (0U)
# define CAN_F27DATA1_FD0_Msk (0x1U << CAN_F27DATA1_FD0_Pos) /*!< 0x00000001 */
# define CAN_F27DATA1_FD0 CAN_F27DATA1_FD0_Msk /*!< Filter bit 0 */
# define CAN_F27DATA1_FD1_Pos (1U)
# define CAN_F27DATA1_FD1_Msk (0x1U << CAN_F27DATA1_FD1_Pos) /*!< 0x00000002 */
# define CAN_F27DATA1_FD1 CAN_F27DATA1_FD1_Msk /*!< Filter bit 1 */
# define CAN_F27DATA1_FD2_Pos (2U)
# define CAN_F27DATA1_FD2_Msk (0x1U << CAN_F27DATA1_FD2_Pos) /*!< 0x00000004 */
# define CAN_F27DATA1_FD2 CAN_F27DATA1_FD2_Msk /*!< Filter bit 2 */
# define CAN_F27DATA1_FD3_Pos (3U)
# define CAN_F27DATA1_FD3_Msk (0x1U << CAN_F27DATA1_FD3_Pos) /*!< 0x00000008 */
# define CAN_F27DATA1_FD3 CAN_F27DATA1_FD3_Msk /*!< Filter bit 3 */
# define CAN_F27DATA1_FD4_Pos (4U)
# define CAN_F27DATA1_FD4_Msk (0x1U << CAN_F27DATA1_FD4_Pos) /*!< 0x00000010 */
# define CAN_F27DATA1_FD4 CAN_F27DATA1_FD4_Msk /*!< Filter bit 4 */
# define CAN_F27DATA1_FD5_Pos (5U)
# define CAN_F27DATA1_FD5_Msk (0x1U << CAN_F27DATA1_FD5_Pos) /*!< 0x00000020 */
# define CAN_F27DATA1_FD5 CAN_F27DATA1_FD5_Msk /*!< Filter bit 5 */
# define CAN_F27DATA1_FD6_Pos (6U)
# define CAN_F27DATA1_FD6_Msk (0x1U << CAN_F27DATA1_FD6_Pos) /*!< 0x00000040 */
# define CAN_F27DATA1_FD6 CAN_F27DATA1_FD6_Msk /*!< Filter bit 6 */
# define CAN_F27DATA1_FD7_Pos (7U)
# define CAN_F27DATA1_FD7_Msk (0x1U << CAN_F27DATA1_FD7_Pos) /*!< 0x00000080 */
# define CAN_F27DATA1_FD7 CAN_F27DATA1_FD7_Msk /*!< Filter bit 7 */
# define CAN_F27DATA1_FD8_Pos (8U)
# define CAN_F27DATA1_FD8_Msk (0x1U << CAN_F27DATA1_FD8_Pos) /*!< 0x00000100 */
# define CAN_F27DATA1_FD8 CAN_F27DATA1_FD8_Msk /*!< Filter bit 8 */
# define CAN_F27DATA1_FD9_Pos (9U)
# define CAN_F27DATA1_FD9_Msk (0x1U << CAN_F27DATA1_FD9_Pos) /*!< 0x00000200 */
# define CAN_F27DATA1_FD9 CAN_F27DATA1_FD9_Msk /*!< Filter bit 9 */
# define CAN_F27DATA1_FD10_Pos (10U)
# define CAN_F27DATA1_FD10_Msk (0x1U << CAN_F27DATA1_FD10_Pos) /*!< 0x00000400 */
# define CAN_F27DATA1_FD10 CAN_F27DATA1_FD10_Msk /*!< Filter bit 10 */
# define CAN_F27DATA1_FD11_Pos (11U)
# define CAN_F27DATA1_FD11_Msk (0x1U << CAN_F27DATA1_FD11_Pos) /*!< 0x00000800 */
# define CAN_F27DATA1_FD11 CAN_F27DATA1_FD11_Msk /*!< Filter bit 11 */
# define CAN_F27DATA1_FD12_Pos (12U)
# define CAN_F27DATA1_FD12_Msk (0x1U << CAN_F27DATA1_FD12_Pos) /*!< 0x00001000 */
# define CAN_F27DATA1_FD12 CAN_F27DATA1_FD12_Msk /*!< Filter bit 12 */
# define CAN_F27DATA1_FD13_Pos (13U)
# define CAN_F27DATA1_FD13_Msk (0x1U << CAN_F27DATA1_FD13_Pos) /*!< 0x00002000 */
# define CAN_F27DATA1_FD13 CAN_F27DATA1_FD13_Msk /*!< Filter bit 13 */
# define CAN_F27DATA1_FD14_Pos (14U)
# define CAN_F27DATA1_FD14_Msk (0x1U << CAN_F27DATA1_FD14_Pos) /*!< 0x00004000 */
# define CAN_F27DATA1_FD14 CAN_F27DATA1_FD14_Msk /*!< Filter bit 14 */
# define CAN_F27DATA1_FD15_Pos (15U)
# define CAN_F27DATA1_FD15_Msk (0x1U << CAN_F27DATA1_FD15_Pos) /*!< 0x00008000 */
# define CAN_F27DATA1_FD15 CAN_F27DATA1_FD15_Msk /*!< Filter bit 15 */
# define CAN_F27DATA1_FD16_Pos (16U)
# define CAN_F27DATA1_FD16_Msk (0x1U << CAN_F27DATA1_FD16_Pos) /*!< 0x00010000 */
# define CAN_F27DATA1_FD16 CAN_F27DATA1_FD16_Msk /*!< Filter bit 16 */
# define CAN_F27DATA1_FD17_Pos (17U)
# define CAN_F27DATA1_FD17_Msk (0x1U << CAN_F27DATA1_FD17_Pos) /*!< 0x00020000 */
# define CAN_F27DATA1_FD17 CAN_F27DATA1_FD17_Msk /*!< Filter bit 17 */
# define CAN_F27DATA1_FD18_Pos (18U)
# define CAN_F27DATA1_FD18_Msk (0x1U << CAN_F27DATA1_FD18_Pos) /*!< 0x00040000 */
# define CAN_F27DATA1_FD18 CAN_F27DATA1_FD18_Msk /*!< Filter bit 18 */
# define CAN_F27DATA1_FD19_Pos (19U)
# define CAN_F27DATA1_FD19_Msk (0x1U << CAN_F27DATA1_FD19_Pos) /*!< 0x00080000 */
# define CAN_F27DATA1_FD19 CAN_F27DATA1_FD19_Msk /*!< Filter bit 19 */
# define CAN_F27DATA1_FD20_Pos (20U)
# define CAN_F27DATA1_FD20_Msk (0x1U << CAN_F27DATA1_FD20_Pos) /*!< 0x00100000 */
# define CAN_F27DATA1_FD20 CAN_F27DATA1_FD20_Msk /*!< Filter bit 20 */
# define CAN_F27DATA1_FD21_Pos (21U)
# define CAN_F27DATA1_FD21_Msk (0x1U << CAN_F27DATA1_FD21_Pos) /*!< 0x00200000 */
# define CAN_F27DATA1_FD21 CAN_F27DATA1_FD21_Msk /*!< Filter bit 21 */
# define CAN_F27DATA1_FD22_Pos (22U)
# define CAN_F27DATA1_FD22_Msk (0x1U << CAN_F27DATA1_FD22_Pos) /*!< 0x00400000 */
# define CAN_F27DATA1_FD22 CAN_F27DATA1_FD22_Msk /*!< Filter bit 22 */
# define CAN_F27DATA1_FD23_Pos (23U)
# define CAN_F27DATA1_FD23_Msk (0x1U << CAN_F27DATA1_FD23_Pos) /*!< 0x00800000 */
# define CAN_F27DATA1_FD23 CAN_F27DATA1_FD23_Msk /*!< Filter bit 23 */
# define CAN_F27DATA1_FD24_Pos (24U)
# define CAN_F27DATA1_FD24_Msk (0x1U << CAN_F27DATA1_FD24_Pos) /*!< 0x01000000 */
# define CAN_F27DATA1_FD24 CAN_F27DATA1_FD24_Msk /*!< Filter bit 24 */
# define CAN_F27DATA1_FD25_Pos (25U)
# define CAN_F27DATA1_FD25_Msk (0x1U << CAN_F27DATA1_FD25_Pos) /*!< 0x02000000 */
# define CAN_F27DATA1_FD25 CAN_F27DATA1_FD25_Msk /*!< Filter bit 25 */
# define CAN_F27DATA1_FD26_Pos (26U)
# define CAN_F27DATA1_FD26_Msk (0x1U << CAN_F27DATA1_FD26_Pos) /*!< 0x04000000 */
# define CAN_F27DATA1_FD26 CAN_F27DATA1_FD26_Msk /*!< Filter bit 26 */
# define CAN_F27DATA1_FD27_Pos (27U)
# define CAN_F27DATA1_FD27_Msk (0x1U << CAN_F27DATA1_FD27_Pos) /*!< 0x08000000 */
# define CAN_F27DATA1_FD27 CAN_F27DATA1_FD27_Msk /*!< Filter bit 27 */
# define CAN_F27DATA1_FD28_Pos (28U)
# define CAN_F27DATA1_FD28_Msk (0x1U << CAN_F27DATA1_FD28_Pos) /*!< 0x10000000 */
# define CAN_F27DATA1_FD28 CAN_F27DATA1_FD28_Msk /*!< Filter bit 28 */
# define CAN_F27DATA1_FD29_Pos (29U)
# define CAN_F27DATA1_FD29_Msk (0x1U << CAN_F27DATA1_FD29_Pos) /*!< 0x20000000 */
# define CAN_F27DATA1_FD29 CAN_F27DATA1_FD29_Msk /*!< Filter bit 29 */
# define CAN_F27DATA1_FD30_Pos (30U)
# define CAN_F27DATA1_FD30_Msk (0x1U << CAN_F27DATA1_FD30_Pos) /*!< 0x40000000 */
# define CAN_F27DATA1_FD30 CAN_F27DATA1_FD30_Msk /*!< Filter bit 30 */
# define CAN_F27DATA1_FD31_Pos (31U)
# define CAN_F27DATA1_FD31_Msk (0x1U << CAN_F27DATA1_FD31_Pos) /*!< 0x80000000 */
# define CAN_F27DATA1_FD31 CAN_F27DATA1_FD31_Msk /*!< Filter bit 31 */
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/******************************************************************************/
/* */
/* Serial Peripheral Interface */
/* */
/******************************************************************************/
/*
* @ brief Specific device feature definitions ( not present on all devices in the STM32F1 serie )
*/
# define SPI_I2S_SUPPORT /*!< I2S support */
# define I2S2_I2S3_CLOCK_FEATURE
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/******************* Bit definition for SPI_CTL0 register ********************/
# define SPI_CTL0_CKPH_Pos (0U)
# define SPI_CTL0_CKPH_Msk (0x1U << SPI_CTL0_CKPH_Pos) /*!< 0x00000001 */
# define SPI_CTL0_CKPH SPI_CTL0_CKPH_Msk /*!< Clock Phase */
# define SPI_CTL0_CKPL_Pos (1U)
# define SPI_CTL0_CKPL_Msk (0x1U << SPI_CTL0_CKPL_Pos) /*!< 0x00000002 */
# define SPI_CTL0_CKPL SPI_CTL0_CKPL_Msk /*!< Clock Polarity */
# define SPI_CTL0_MSTMOD_Pos (2U)
# define SPI_CTL0_MSTMOD_Msk (0x1U << SPI_CTL0_MSTMOD_Pos) /*!< 0x00000004 */
# define SPI_CTL0_MSTMOD SPI_CTL0_MSTMOD_Msk /*!< Master Selection */
# define SPI_CTL0_PSC_Pos (3U)
# define SPI_CTL0_PSC_Msk (0x7U << SPI_CTL0_PSC_Pos) /*!< 0x00000038 */
# define SPI_CTL0_PSC SPI_CTL0_PSC_Msk /*!< BR[2:0] bits (Baud Rate Control) */
# define SPI_CTL0_PSC_0 (0x1U << SPI_CTL0_PSC_Pos) /*!< 0x00000008 */
# define SPI_CTL0_PSC_1 (0x2U << SPI_CTL0_PSC_Pos) /*!< 0x00000010 */
# define SPI_CTL0_PSC_2 (0x4U << SPI_CTL0_PSC_Pos) /*!< 0x00000020 */
# define SPI_CTL0_SPIEN_Pos (6U)
# define SPI_CTL0_SPIEN_Msk (0x1U << SPI_CTL0_SPIEN_Pos) /*!< 0x00000040 */
# define SPI_CTL0_SPIEN SPI_CTL0_SPIEN_Msk /*!< SPI Enable */
# define SPI_CTL0_LF_Pos (7U)
# define SPI_CTL0_LF_Msk (0x1U << SPI_CTL0_LF_Pos) /*!< 0x00000080 */
# define SPI_CTL0_LF SPI_CTL0_LF_Msk /*!< Frame Format */
# define SPI_CTL0_SWNSS_Pos (8U)
# define SPI_CTL0_SWNSS_Msk (0x1U << SPI_CTL0_SWNSS_Pos) /*!< 0x00000100 */
# define SPI_CTL0_SWNSS SPI_CTL0_SWNSS_Msk /*!< Internal slave select */
# define SPI_CTL0_SWNSSEN_Pos (9U)
# define SPI_CTL0_SWNSSEN_Msk (0x1U << SPI_CTL0_SWNSSEN_Pos) /*!< 0x00000200 */
# define SPI_CTL0_SWNSSEN SPI_CTL0_SWNSSEN_Msk /*!< Software slave management */
# define SPI_CTL0_RO_Pos (10U)
# define SPI_CTL0_RO_Msk (0x1U << SPI_CTL0_RO_Pos) /*!< 0x00000400 */
# define SPI_CTL0_RO SPI_CTL0_RO_Msk /*!< Receive only */
# define SPI_CTL0_FF16_Pos (11U)
# define SPI_CTL0_FF16_Msk (0x1U << SPI_CTL0_FF16_Pos) /*!< 0x00000800 */
# define SPI_CTL0_FF16 SPI_CTL0_FF16_Msk /*!< Data Frame Format */
# define SPI_CTL0_CRCNT_Pos (12U)
# define SPI_CTL0_CRCNT_Msk (0x1U << SPI_CTL0_CRCNT_Pos) /*!< 0x00001000 */
# define SPI_CTL0_CRCNT SPI_CTL0_CRCNT_Msk /*!< Transmit CRC next */
# define SPI_CTL0_CRCEN_Pos (13U)
# define SPI_CTL0_CRCEN_Msk (0x1U << SPI_CTL0_CRCEN_Pos) /*!< 0x00002000 */
# define SPI_CTL0_CRCEN SPI_CTL0_CRCEN_Msk /*!< Hardware CRC calculation enable */
# define SPI_CTL0_BDOEN_Pos (14U)
# define SPI_CTL0_BDOEN_Msk (0x1U << SPI_CTL0_BDOEN_Pos) /*!< 0x00004000 */
# define SPI_CTL0_BDOEN SPI_CTL0_BDOEN_Msk /*!< Output enable in bidirectional mode */
# define SPI_CTL0_BDEN_Pos (15U)
# define SPI_CTL0_BDEN_Msk (0x1U << SPI_CTL0_BDEN_Pos) /*!< 0x00008000 */
# define SPI_CTL0_BDEN SPI_CTL0_BDEN_Msk /*!< Bidirectional data mode enable */
/******************* Bit definition for SPI_CTL1 register ********************/
# define SPI_CTL1_DMAREN_Pos (0U)
# define SPI_CTL1_DMAREN_Msk (0x1U << SPI_CTL1_DMAREN_Pos) /*!< 0x00000001 */
# define SPI_CTL1_DMAREN SPI_CTL1_DMAREN_Msk /*!< Rx Buffer DMA Enable */
# define SPI_CTL1_DMATEN_Pos (1U)
# define SPI_CTL1_DMATEN_Msk (0x1U << SPI_CTL1_DMATEN_Pos) /*!< 0x00000002 */
# define SPI_CTL1_DMATEN SPI_CTL1_DMATEN_Msk /*!< Tx Buffer DMA Enable */
# define SPI_CTL1_NSSDRV_Pos (2U)
# define SPI_CTL1_NSSDRV_Msk (0x1U << SPI_CTL1_NSSDRV_Pos) /*!< 0x00000004 */
# define SPI_CTL1_NSSDRV SPI_CTL1_NSSDRV_Msk /*!< SS Output Enable */
# define SPI_CTL1_NSSP_Pos (3U)
# define SPI_CTL1_NSSP_Msk (0x1U << SPI_CTL1_NSSP_Pos) /*!< 0x00000004 */
# define SPI_CTL1_NSSP SPI_CTL1_NSSP_Msk /*!< SS Output Enable */
# define SPI_CTL1_TMOD_Pos (4U)
# define SPI_CTL1_TMOD_Msk (0x1U << SPI_CTL1_TMOD_Pos) /*!< 0x00000004 */
# define SPI_CTL1_TMOD SPI_CTL1_TMOD_Msk /*!< SS Output Enable */
# define SPI_CTL1_ERRIE_Pos (5U)
# define SPI_CTL1_ERRIE_Msk (0x1U << SPI_CTL1_ERRIE_Pos) /*!< 0x00000020 */
# define SPI_CTL1_ERRIE SPI_CTL1_ERRIE_Msk /*!< Error Interrupt Enable */
# define SPI_CTL1_RBNEIE_Pos (6U)
# define SPI_CTL1_RBNEIE_Msk (0x1U << SPI_CTL1_RBNEIE_Pos) /*!< 0x00000040 */
# define SPI_CTL1_RBNEIE SPI_CTL1_RBNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
# define SPI_CTL1_TBEIE_Pos (7U)
# define SPI_CTL1_TBEIE_Msk (0x1U << SPI_CTL1_TBEIE_Pos) /*!< 0x00000080 */
# define SPI_CTL1_TBEIE SPI_CTL1_TBEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
/******************** Bit definition for SPI_STAT register ********************/
# define SPI_STAT_RBNE_Pos (0U)
# define SPI_STAT_RBNE_Msk (0x1U << SPI_STAT_RBNE_Pos) /*!< 0x00000001 */
# define SPI_STAT_RBNE SPI_STAT_RBNE_Msk /*!< Receive buffer Not Empty */
# define SPI_STAT_TBE_Pos (1U)
# define SPI_STAT_TBE_Msk (0x1U << SPI_STAT_TBE_Pos) /*!< 0x00000002 */
# define SPI_STAT_TBE SPI_STAT_TBE_Msk /*!< Transmit buffer Empty */
# define SPI_STAT_I2SCH_Pos (2U)
# define SPI_STAT_I2SCH_Msk (0x1U << SPI_STAT_I2SCH_Pos) /*!< 0x00000004 */
# define SPI_STAT_I2SCH SPI_STAT_I2SCH_Msk /*!< Channel side */
# define SPI_STAT_TXURERR_Pos (3U)
# define SPI_STAT_TXURERR_Msk (0x1U << SPI_STAT_TXURERR_Pos) /*!< 0x00000008 */
# define SPI_STAT_TXURERR SPI_STAT_TXURERR_Msk /*!< Underrun flag */
# define SPI_STAT_CRCERR_Pos (4U)
# define SPI_STAT_CRCERR_Msk (0x1U << SPI_STAT_CRCERR_Pos) /*!< 0x00000010 */
# define SPI_STAT_CRCERR SPI_STAT_CRCERR_Msk /*!< CRC Error flag */
# define SPI_STAT_CONFERR_Pos (5U)
# define SPI_STAT_CONFERR_Msk (0x1U << SPI_STAT_CONFERR_Pos) /*!< 0x00000020 */
# define SPI_STAT_CONFERR SPI_STAT_CONFERR_Msk /*!< Mode fault */
# define SPI_STAT_RXORERR_Pos (6U)
# define SPI_STAT_RXORERR_Msk (0x1U << SPI_STAT_RXORERR_Pos) /*!< 0x00000040 */
# define SPI_STAT_RXORERR SPI_STAT_RXORERR_Msk /*!< Overrun flag */
# define SPI_STAT_TRANS_Pos (7U)
# define SPI_STAT_TRANS_Msk (0x1U << SPI_STAT_TRANS_Pos) /*!< 0x00000080 */
# define SPI_STAT_TRANS SPI_STAT_TRANS_Msk /*!< Busy flag */
# define SPI_STAT_FERR_Pos (8U)
# define SPI_STAT_FERR_Msk (0x1U << SPI_STAT_FERR_Pos) /*!< 0x00000080 */
# define SPI_STAT_FERR SPI_STAT_FERR_Msk /*!< Busy flag */
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/******************** Bit definition for SPI_DR register ********************/
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# define SPI_DATA_SPI_DATA_Pos (0U)
# define SPI_DATA_SPI_DATA_Msk (0xFFFFU << SPI_DATA_SPI_DATA_Pos) /*!< 0x0000FFFF */
# define SPI_DATA_SPI_DATA SPI_DATA_SPI_DATA_Msk /*!< Data Register */
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/******************* Bit definition for SPI_CRCPOLY register ******************/
# define SPI_CRCPOLY_CRCPOLY_Pos (0U)
# define SPI_CRCPOLY_CRCPOLY_Msk (0xFFFFU << SPI_CRCPOLY_CRCPOLY_Pos) /*!< 0x0000FFFF */
# define SPI_CRCPOLY_CRCPOLY SPI_CRCPOLY_CRCPOLY_Msk /*!< CRC polynomial register */
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/****************** Bit definition for SPI_RXCRCR register ******************/
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# define SPI_RCRC_RCRC_Pos (0U)
# define SPI_RCRC_RCRC_Msk (0xFFFFU << SPI_RCRC_RCRC_Pos) /*!< 0x0000FFFF */
# define SPI_RCRC_RCRC SPI_RCRC_RCRC_Msk /*!< Rx CRC Register */
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/****************** Bit definition for SPI_TXCRCR register ******************/
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# define SPI_TCRC_TCRC_Pos (0U)
# define SPI_TCRC_TCRC_Msk (0xFFFFU << SPI_TCRC_TCRC_Pos) /*!< 0x0000FFFF */
# define SPI_TCRC_TCRC SPI_TCRC_TCRC_Msk /*!< Tx CRC Register */
/****************** Bit definition for SPI_I2SCTL register *****************/
# define SPI_I2SCTL_CHLEN_Pos (0U)
# define SPI_I2SCTL_CHLEN_Msk (0x1U << SPI_I2SCTL_CHLEN_Pos) /*!< 0x00000001 */
# define SPI_I2SCTL_CHLEN SPI_I2SCTL_CHLEN_Msk /*!< Channel length (number of bits per audio channel) */
# define SPI_I2SCTL_DTLEN_Pos (1U)
# define SPI_I2SCTL_DTLEN_Msk (0x3U << SPI_I2SCTL_DTLEN_Pos) /*!< 0x00000006 */
# define SPI_I2SCTL_DTLEN SPI_I2SCTL_DTLEN_Msk /*!< DATLEN[1:0] bits (Data length to be transferred) */
# define SPI_I2SCTL_DTLEN_0 (0x1U << SPI_I2SCTL_DTLEN_Pos) /*!< 0x00000002 */
# define SPI_I2SCTL_DTLEN_1 (0x2U << SPI_I2SCTL_DTLEN_Pos) /*!< 0x00000004 */
# define SPI_I2SCTL_CKPL_Pos (3U)
# define SPI_I2SCTL_CKPL_Msk (0x1U << SPI_I2SCTL_CKPL_Pos) /*!< 0x00000008 */
# define SPI_I2SCTL_CKPL SPI_I2SCTL_CKPL_Msk /*!< steady state clock polarity */
# define SPI_I2SCTL_I2SSTD_Pos (4U)
# define SPI_I2SCTL_I2SSTD_Msk (0x3U << SPI_I2SCTL_I2SSTD_Pos) /*!< 0x00000030 */
# define SPI_I2SCTL_I2SSTD SPI_I2SCTL_I2SSTD_Msk /*!< I2SSTD[1:0] bits (I2S standard selection) */
# define SPI_I2SCTL_I2SSTD_0 (0x1U << SPI_I2SCTL_I2SSTD_Pos) /*!< 0x00000010 */
# define SPI_I2SCTL_I2SSTD_1 (0x2U << SPI_I2SCTL_I2SSTD_Pos) /*!< 0x00000020 */
# define SPI_I2SCTL_PCMSMOD_Pos (7U)
# define SPI_I2SCTL_PCMSMOD_Msk (0x1U << SPI_I2SCTL_PCMSMOD_Pos) /*!< 0x00000080 */
# define SPI_I2SCTL_PCMSMOD SPI_I2SCTL_PCMSMOD_Msk /*!< PCM frame synchronization */
# define SPI_I2SCTL_I2SOPMOD_Pos (8U)
# define SPI_I2SCTL_I2SOPMOD_Msk (0x3U << SPI_I2SCTL_I2SOPMOD_Pos) /*!< 0x00000300 */
# define SPI_I2SCTL_I2SOPMOD SPI_I2SCTL_I2SOPMOD_Msk /*!< I2SCFG[1:0] bits (I2S configuration mode) */
# define SPI_I2SCTL_I2SOPMOD_0 (0x1U << SPI_I2SCTL_I2SOPMOD_Pos) /*!< 0x00000100 */
# define SPI_I2SCTL_I2SOPMOD_1 (0x2U << SPI_I2SCTL_I2SOPMOD_Pos) /*!< 0x00000200 */
# define SPI_I2SCTL_I2SEN_Pos (10U)
# define SPI_I2SCTL_I2SEN_Msk (0x1U << SPI_I2SCTL_I2SEN_Pos) /*!< 0x00000400 */
# define SPI_I2SCTL_I2SEN SPI_I2SCTL_I2SEN_Msk /*!< I2S Enable */
# define SPI_I2SCTL_I2SSEL_Pos (11U)
# define SPI_I2SCTL_I2SSEL_Msk (0x1U << SPI_I2SCTL_I2SSEL_Pos) /*!< 0x00000800 */
# define SPI_I2SCTL_I2SSEL SPI_I2SCTL_I2SSEL_Msk /*!< I2S mode selection */
/****************** Bit definition for SPI_I2SPSC register *******************/
# define SPI_I2SPSC_DIV_Pos (0U)
# define SPI_I2SPSC_DIV_Msk (0xFFU << SPI_I2SPSC_DIV_Pos) /*!< 0x000000FF */
# define SPI_I2SPSC_DIV SPI_I2SPSC_DIV_Msk /*!< I2S Linear prescaler */
# define SPI_I2SPSC_OF_Pos (8U)
# define SPI_I2SPSC_OF_Msk (0x1U << SPI_I2SPSC_OF_Pos) /*!< 0x00000100 */
# define SPI_I2SPSC_OF SPI_I2SPSC_OF_Msk /*!< Odd factor for the prescaler */
# define SPI_I2SPSC_MCKOEN_Pos (9U)
# define SPI_I2SPSC_MCKOEN_Msk (0x1U << SPI_I2SPSC_MCKOEN_Pos) /*!< 0x00000200 */
# define SPI_I2SPSC_MCKOEN SPI_I2SPSC_MCKOEN_Msk /*!< Master Clock Output Enable */
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/******************************************************************************/
/* */
/* Inter-integrated Circuit Interface */
/* */
/******************************************************************************/
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/******************* Bit definition for I2C_CTL0 register ********************/
# define I2C_CTL0_I2CEN_Pos (0U)
# define I2C_CTL0_I2CEN_Msk (0x1U << I2C_CTL0_I2CEN_Pos) /*!< 0x00000001 */
# define I2C_CTL0_I2CEN I2C_CTL0_I2CEN_Msk /*!< Peripheral Enable */
# define I2C_CTL0_SMBEN_Pos (1U)
# define I2C_CTL0_SMBEN_Msk (0x1U << I2C_CTL0_SMBEN_Pos) /*!< 0x00000002 */
# define I2C_CTL0_SMBEN I2C_CTL0_SMBEN_Msk /*!< SMBus Mode */
# define I2C_CTL0_SMBSEL_Pos (3U)
# define I2C_CTL0_SMBSEL_Msk (0x1U << I2C_CTL0_SMBSEL_Pos) /*!< 0x00000008 */
# define I2C_CTL0_SMBSEL I2C_CTL0_SMBSEL_Msk /*!< SMBus Type */
# define I2C_CTL0_ARPEN_Pos (4U)
# define I2C_CTL0_ARPEN_Msk (0x1U << I2C_CTL0_ARPEN_Pos) /*!< 0x00000010 */
# define I2C_CTL0_ARPEN I2C_CTL0_ARPEN_Msk /*!< ARP Enable */
# define I2C_CTL0_PECTRANSEN_Pos (5U)
# define I2C_CTL0_PECTRANSEN_Msk (0x1U << I2C_CTL0_PECTRANSEN_Pos) /*!< 0x00000020 */
# define I2C_CTL0_PECTRANSEN I2C_CTL0_PECTRANSEN_Msk /*!< PEC Enable */
# define I2C_CTL0_GCEN_Pos (6U)
# define I2C_CTL0_GCEN_Msk (0x1U << I2C_CTL0_GCEN_Pos) /*!< 0x00000040 */
# define I2C_CTL0_GCEN I2C_CTL0_GCEN_Msk /*!< General Call Enable */
# define I2C_CTL0_SS_Pos (7U)
# define I2C_CTL0_SS_Msk (0x1U << I2C_CTL0_SS_Pos) /*!< 0x00000080 */
# define I2C_CTL0_SS I2C_CTL0_SS_Msk /*!< Clock Stretching Disable (Slave mode) */
# define I2C_CTL0_START_Pos (8U)
# define I2C_CTL0_START_Msk (0x1U << I2C_CTL0_START_Pos) /*!< 0x00000100 */
# define I2C_CTL0_START I2C_CTL0_START_Msk /*!< Start Generation */
# define I2C_CTL0_STOP_Pos (9U)
# define I2C_CTL0_STOP_Msk (0x1U << I2C_CTL0_STOP_Pos) /*!< 0x00000200 */
# define I2C_CTL0_STOP I2C_CTL0_STOP_Msk /*!< Stop Generation */
# define I2C_CTL0_ACKEN_Pos (10U)
# define I2C_CTL0_ACKEN_Msk (0x1U << I2C_CTL0_ACKEN_Pos) /*!< 0x00000400 */
# define I2C_CTL0_ACKEN I2C_CTL0_ACKEN_Msk /*!< Acknowledge Enable */
# define I2C_CTL0_POAP_Pos (11U)
# define I2C_CTL0_POAP_Msk (0x1U << I2C_CTL0_POAP_Pos) /*!< 0x00000800 */
# define I2C_CTL0_POAP I2C_CTL0_POAP_Msk /*!< Acknowledge/PEC Position (for data reception) */
# define I2C_CTL0_I2CENC_Pos (12U)
# define I2C_CTL0_I2CENC_Msk (0x1U << I2C_CTL0_I2CENC_Pos) /*!< 0x00001000 */
# define I2C_CTL0_I2CENC I2C_CTL0_I2CENC_Msk /*!< Packet Error Checking */
# define I2C_CTL0_SALT_Pos (13U)
# define I2C_CTL0_SALT_Msk (0x1U << I2C_CTL0_SALT_Pos) /*!< 0x00002000 */
# define I2C_CTL0_SALT I2C_CTL0_SALT_Msk /*!< SMBus Alert */
# define I2C_CTL0_SRESET_Pos (15U)
# define I2C_CTL0_SRESET_Msk (0x1U << I2C_CTL0_SRESET_Pos) /*!< 0x00008000 */
# define I2C_CTL0_SRESET I2C_CTL0_SRESET_Msk /*!< Software Reset */
/******************* Bit definition for I2C_CTL1 register ********************/
# define I2C_CTL1_I2CCLK_Pos (0U)
# define I2C_CTL1_I2CCLK_Msk (0x3FU << I2C_CTL1_I2CCLK_Pos) /*!< 0x0000003F */
# define I2C_CTL1_I2CCLK I2C_CTL1_I2CCLK_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
# define I2C_CTL1_I2CCLK_0 (0x01U << I2C_CTL1_I2CCLK_Pos) /*!< 0x00000001 */
# define I2C_CTL1_I2CCLK_1 (0x02U << I2C_CTL1_I2CCLK_Pos) /*!< 0x00000002 */
# define I2C_CTL1_I2CCLK_2 (0x04U << I2C_CTL1_I2CCLK_Pos) /*!< 0x00000004 */
# define I2C_CTL1_I2CCLK_3 (0x08U << I2C_CTL1_I2CCLK_Pos) /*!< 0x00000008 */
# define I2C_CTL1_I2CCLK_4 (0x10U << I2C_CTL1_I2CCLK_Pos) /*!< 0x00000010 */
# define I2C_CTL1_I2CCLK_5 (0x20U << I2C_CTL1_I2CCLK_Pos) /*!< 0x00000020 */
# define I2C_CTL1_ERRIE_Pos (8U)
# define I2C_CTL1_ERRIE_Msk (0x1U << I2C_CTL1_ERRIE_Pos) /*!< 0x00000100 */
# define I2C_CTL1_ERRIE I2C_CTL1_ERRIE_Msk /*!< Error Interrupt Enable */
# define I2C_CTL1_EVIE_Pos (9U)
# define I2C_CTL1_EVIE_Msk (0x1U << I2C_CTL1_EVIE_Pos) /*!< 0x00000200 */
# define I2C_CTL1_EVIE I2C_CTL1_EVIE_Msk /*!< Event Interrupt Enable */
# define I2C_CTL1_BUFIE_Pos (10U)
# define I2C_CTL1_BUFIE_Msk (0x1U << I2C_CTL1_BUFIE_Pos) /*!< 0x00000400 */
# define I2C_CTL1_BUFIE I2C_CTL1_BUFIE_Msk /*!< Buffer Interrupt Enable */
# define I2C_CTL1_DMAON_Pos (11U)
# define I2C_CTL1_DMAON_Msk (0x1U << I2C_CTL1_DMAON_Pos) /*!< 0x00000800 */
# define I2C_CTL1_DMAON I2C_CTL1_DMAON_Msk /*!< DMA Requests Enable */
# define I2C_CTL1_DMALST_Pos (12U)
# define I2C_CTL1_DMALST_Msk (0x1U << I2C_CTL1_DMALST_Pos) /*!< 0x00001000 */
# define I2C_CTL1_DMALST I2C_CTL1_DMALST_Msk /*!< DMA Last Transfer */
/******************* Bit definition for I2C_SADDR0 register *******************/
# define I2C_SADDR0_ADDRESS1_7 0x000000FEU /*!< Interface Address */
# define I2C_SADDR0_ADDRESS8_9 0x00000300U /*!< Interface Address */
# define I2C_SADDR0_ADDRESS0_Pos (0U)
# define I2C_SADDR0_ADDRESS0_Msk (0x1U << I2C_SADDR0_ADDRESS0_Pos) /*!< 0x00000001 */
# define I2C_SADDR0_ADDRESS0 I2C_SADDR0_ADDRESS0_Msk /*!< Bit 0 */
# define I2C_SADDR0_ADDRESS1_Pos (1U)
# define I2C_SADDR0_ADDRESS1_Msk (0x1U << I2C_SADDR0_ADDRESS1_Pos) /*!< 0x00000002 */
# define I2C_SADDR0_ADDRESS1 I2C_SADDR0_ADDRESS1_Msk /*!< Bit 1 */
# define I2C_SADDR0_ADDRESS2_Pos (2U)
# define I2C_SADDR0_ADDRESS2_Msk (0x1U << I2C_SADDR0_ADDRESS2_Pos) /*!< 0x00000004 */
# define I2C_SADDR0_ADDRESS2 I2C_SADDR0_ADDRESS2_Msk /*!< Bit 2 */
# define I2C_SADDR0_ADDRESS3_Pos (3U)
# define I2C_SADDR0_ADDRESS3_Msk (0x1U << I2C_SADDR0_ADDRESS3_Pos) /*!< 0x00000008 */
# define I2C_SADDR0_ADDRESS3 I2C_SADDR0_ADDRESS3_Msk /*!< Bit 3 */
# define I2C_SADDR0_ADDRESS4_Pos (4U)
# define I2C_SADDR0_ADDRESS4_Msk (0x1U << I2C_SADDR0_ADDRESS4_Pos) /*!< 0x00000010 */
# define I2C_SADDR0_ADDRESS4 I2C_SADDR0_ADDRESS4_Msk /*!< Bit 4 */
# define I2C_SADDR0_ADDRESS5_Pos (5U)
# define I2C_SADDR0_ADDRESS5_Msk (0x1U << I2C_SADDR0_ADDRESS5_Pos) /*!< 0x00000020 */
# define I2C_SADDR0_ADDRESS5 I2C_SADDR0_ADDRESS5_Msk /*!< Bit 5 */
# define I2C_SADDR0_ADDRESS6_Pos (6U)
# define I2C_SADDR0_ADDRESS6_Msk (0x1U << I2C_SADDR0_ADDRESS6_Pos) /*!< 0x00000040 */
# define I2C_SADDR0_ADDRESS6 I2C_SADDR0_ADDRESS6_Msk /*!< Bit 6 */
# define I2C_SADDR0_ADDRESS7_Pos (7U)
# define I2C_SADDR0_ADDRESS7_Msk (0x1U << I2C_SADDR0_ADDRESS7_Pos) /*!< 0x00000080 */
# define I2C_SADDR0_ADDRESS7 I2C_SADDR0_ADDRESS7_Msk /*!< Bit 7 */
# define I2C_SADDR0_ADDRESS8_Pos (8U)
# define I2C_SADDR0_ADDRESS8_Msk (0x1U << I2C_SADDR0_ADDRESS8_Pos) /*!< 0x00000100 */
# define I2C_SADDR0_ADDRESS8 I2C_SADDR0_ADDRESS8_Msk /*!< Bit 8 */
# define I2C_SADDR0_ADDRESS9_Pos (9U)
# define I2C_SADDR0_ADDRESS9_Msk (0x1U << I2C_SADDR0_ADDRESS9_Pos) /*!< 0x00000200 */
# define I2C_SADDR0_ADDRESS9 I2C_SADDR0_ADDRESS9_Msk /*!< Bit 9 */
# define I2C_SADDR0_ADDRESSMODE_Pos (15U)
# define I2C_SADDR0_ADDRESSMODE_Msk (0x1U << I2C_SADDR0_ADDRESSMODE_Pos) /*!< 0x00008000 */
# define I2C_SADDR0_ADDRESSMODE I2C_SADDR0_ADDRESSMODE_Msk /*!< Addressing Mode (Slave mode) */
/******************* Bit definition for I2C_SADDR1 register *******************/
# define I2C_SADDR1_DUADEN_Pos (0U)
# define I2C_SADDR1_DUADEN_Msk (0x1U << I2C_SADDR1_DUADEN_Pos) /*!< 0x00000001 */
# define I2C_SADDR1_DUADEN I2C_SADDR1_DUADEN_Msk /*!< Dual addressing mode enable */
# define I2C_SADDR1_ADDRESS2_Pos (1U)
# define I2C_SADDR1_ADDRESS2_Msk (0x7FU << I2C_SADDR1_ADDRESS2_Pos) /*!< 0x000000FE */
# define I2C_SADDR1_ADDRESS2 I2C_SADDR1_ADDRESS2_Msk /*!< Interface address */
/******************** Bit definition for I2C_DATA register ********************/
# define I2C_DATA_TRB_Pos (0U)
# define I2C_DATA_TRB_Msk (0xFFU << I2C_DATA_TRB_Pos) /*!< 0x000000FF */
# define I2C_DATA_TRB I2C_DATA_TRB_Msk /*!< 8-bit Data Register */
/******************* Bit definition for I2C_STAT0 register ********************/
# define I2C_STAT0_SBSEND_Pos (0U)
# define I2C_STAT0_SBSEND_Msk (0x1U << I2C_STAT0_SBSEND_Pos) /*!< 0x00000001 */
# define I2C_STAT0_SBSEND I2C_STAT0_SBSEND_Msk /*!< Start Bit (Master mode) */
# define I2C_STAT0_ADDSEND_Pos (1U)
# define I2C_STAT0_ADDSEND_Msk (0x1U << I2C_STAT0_ADDSEND_Pos) /*!< 0x00000002 */
# define I2C_STAT0_ADDSEND I2C_STAT0_ADDSEND_Msk /*!< Address sent (master mode)/matched (slave mode) */
# define I2C_STAT0_BTC_Pos (2U)
# define I2C_STAT0_BTC_Msk (0x1U << I2C_STAT0_BTC_Pos) /*!< 0x00000004 */
# define I2C_STAT0_BTC I2C_STAT0_BTC_Msk /*!< Byte Transfer Finished */
# define I2C_STAT0_ADD10SEND_Pos (3U)
# define I2C_STAT0_ADD10SEND_Msk (0x1U << I2C_STAT0_ADD10SEND_Pos) /*!< 0x00000008 */
# define I2C_STAT0_ADD10SEND I2C_STAT0_ADD10SEND_Msk /*!< 10-bit header sent (Master mode) */
# define I2C_STAT0_STPDET_Pos (4U)
# define I2C_STAT0_STPDET_Msk (0x1U << I2C_STAT0_STPDET_Pos) /*!< 0x00000010 */
# define I2C_STAT0_STPDET I2C_STAT0_STPDET_Msk /*!< Stop detection (Slave mode) */
# define I2C_STAT0_RBNE_Pos (6U)
# define I2C_STAT0_RBNE_Msk (0x1U << I2C_STAT0_RBNE_Pos) /*!< 0x00000040 */
# define I2C_STAT0_RBNE I2C_STAT0_RBNE_Msk /*!< Data Register not Empty (receivers) */
# define I2C_STAT0_TBE_Pos (7U)
# define I2C_STAT0_TBE_Msk (0x1U << I2C_STAT0_TBE_Pos) /*!< 0x00000080 */
# define I2C_STAT0_TBE I2C_STAT0_TBE_Msk /*!< Data Register Empty (transmitters) */
# define I2C_STAT0_BERR_Pos (8U)
# define I2C_STAT0_BERR_Msk (0x1U << I2C_STAT0_BERR_Pos) /*!< 0x00000100 */
# define I2C_STAT0_BERR I2C_STAT0_BERR_Msk /*!< Bus Error */
# define I2C_STAT0_LOSTARB_Pos (9U)
# define I2C_STAT0_LOSTARB_Msk (0x1U << I2C_STAT0_LOSTARB_Pos) /*!< 0x00000200 */
# define I2C_STAT0_LOSTARB I2C_STAT0_LOSTARB_Msk /*!< Arbitration Lost (master mode) */
# define I2C_STAT0_AERR_Pos (10U)
# define I2C_STAT0_AERR_Msk (0x1U << I2C_STAT0_AERR_Pos) /*!< 0x00000400 */
# define I2C_STAT0_AERR I2C_STAT0_AERR_Msk /*!< Acknowledge Failure */
# define I2C_STAT0_OUERR_Pos (11U)
# define I2C_STAT0_OUERR_Msk (0x1U << I2C_STAT0_OUERR_Pos) /*!< 0x00000800 */
# define I2C_STAT0_OUERR I2C_STAT0_OUERR_Msk /*!< Overrun/Underrun */
# define I2C_STAT0_PECERR_Pos (12U)
# define I2C_STAT0_PECERR_Msk (0x1U << I2C_STAT0_PECERR_Pos) /*!< 0x00001000 */
# define I2C_STAT0_PECERR I2C_STAT0_PECERR_Msk /*!< PEC Error in reception */
# define I2C_STAT0_SMBTO_Pos (14U)
# define I2C_STAT0_SMBTO_Msk (0x1U << I2C_STAT0_SMBTO_Pos) /*!< 0x00004000 */
# define I2C_STAT0_SMBTO I2C_STAT0_SMBTO_Msk /*!< Timeout or Tlow Error */
# define I2C_STAT0_SMBALT_Pos (15U)
# define I2C_STAT0_SMBALT_Msk (0x1U << I2C_STAT0_SMBALT_Pos) /*!< 0x00008000 */
# define I2C_STAT0_SMBALT I2C_STAT0_SMBALT_Msk /*!< SMBus Alert */
/******************* Bit definition for I2C_STAT1 register ********************/
# define I2C_STAT1_MASTER_Pos (0U)
# define I2C_STAT1_MASTER_Msk (0x1U << I2C_STAT1_MASTER_Pos) /*!< 0x00000001 */
# define I2C_STAT1_MASTER I2C_STAT1_MASTER_Msk /*!< Master/Slave */
# define I2C_STAT1_I2CBSY_Pos (1U)
# define I2C_STAT1_I2CBSY_Msk (0x1U << I2C_STAT1_I2CBSY_Pos) /*!< 0x00000002 */
# define I2C_STAT1_I2CBSY I2C_STAT1_I2CBSY_Msk /*!< Bus Busy */
# define I2C_STAT1_TR_Pos (2U)
# define I2C_STAT1_TR_Msk (0x1U << I2C_STAT1_TR_Pos) /*!< 0x00000004 */
# define I2C_STAT1_TR I2C_STAT1_TR_Msk /*!< Transmitter/Receiver */
# define I2C_STAT1_RXGC_Pos (4U)
# define I2C_STAT1_RXGC_Msk (0x1U << I2C_STAT1_RXGC_Pos) /*!< 0x00000010 */
# define I2C_STAT1_RXGC I2C_STAT1_RXGC_Msk /*!< General Call Address (Slave mode) */
# define I2C_STAT1_DEFSMB_Pos (5U)
# define I2C_STAT1_DEFSMB_Msk (0x1U << I2C_STAT1_DEFSMB_Pos) /*!< 0x00000020 */
# define I2C_STAT1_DEFSMB I2C_STAT1_DEFSMB_Msk /*!< SMBus Device Default Address (Slave mode) */
# define I2C_STAT1_HSTSMB_Pos (6U)
# define I2C_STAT1_HSTSMB_Msk (0x1U << I2C_STAT1_HSTSMB_Pos) /*!< 0x00000040 */
# define I2C_STAT1_HSTSMB I2C_STAT1_HSTSMB_Msk /*!< SMBus Host Header (Slave mode) */
# define I2C_STAT1_DUMODF_Pos (7U)
# define I2C_STAT1_DUMODF_Msk (0x1U << I2C_STAT1_DUMODF_Pos) /*!< 0x00000080 */
# define I2C_STAT1_DUMODF I2C_STAT1_DUMODF_Msk /*!< Dual Flag (Slave mode) */
# define I2C_STAT1_PECV_Pos (8U)
# define I2C_STAT1_PECV_Msk (0xFFU << I2C_STAT1_PECV_Pos) /*!< 0x0000FF00 */
# define I2C_STAT1_PECV I2C_STAT1_PECV_Msk /*!< Packet Error Checking Register */
/******************* Bit definition for I2C_CKCFG register ********************/
# define I2C_CKCFG_CLKC_Pos (0U)
# define I2C_CKCFG_CLKC_Msk (0xFFFU << I2C_CKCFG_CLKC_Pos) /*!< 0x00000FFF */
# define I2C_CKCFG_CLKC I2C_CKCFG_CLKC_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */
# define I2C_CKCFG_DTCY_Pos (14U)
# define I2C_CKCFG_DTCY_Msk (0x1U << I2C_CKCFG_DTCY_Pos) /*!< 0x00004000 */
# define I2C_CKCFG_DTCY I2C_CKCFG_DTCY_Msk /*!< Fast Mode Duty Cycle */
# define I2C_CKCFG_FAST_Pos (15U)
# define I2C_CKCFG_FAST_Msk (0x1U << I2C_CKCFG_FAST_Pos) /*!< 0x00008000 */
# define I2C_CKCFG_FAST I2C_CKCFG_FAST_Msk /*!< I2C Master Mode Selection */
/****************** Bit definition for I2C_RT register *******************/
# define I2C_RT_RISETIME_Pos (0U)
# define I2C_RT_RISETIME_Msk (0x3FU << I2C_RT_RISETIME_Pos) /*!< 0x0000003F */
# define I2C_RT_RISETIME I2C_RT_RISETIME_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
/****************** Bit definition for I2C_FMPCFG register *******************/
# define I2C_FMPCFG_FMPEN_Pos (0U)
# define I2C_FMPCFG_FMPEN_Msk (0x1U << I2C_FMPCFG_FMPEN_Pos) /*!< 0x0000003F */
# define I2C_FMPCFG_FMPEN I2C_FMPCFG_FMPEN_Msk /*!< Fast mode plus enable */
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/******************************************************************************/
/* */
/* Universal Synchronous Asynchronous Receiver Transmitter */
/* */
/******************************************************************************/
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/******************* Bit definition for USART_STAT register *******************/
# define USART_STAT_PERR_Pos (0U)
# define USART_STAT_PERR_Msk (0x1U << USART_STAT_PERR_Pos) /*!< 0x00000001 */
# define USART_STAT_PERR USART_STAT_PERR_Msk /*!< Parity Error */
# define USART_STAT_FERR_Pos (1U)
# define USART_STAT_FERR_Msk (0x1U << USART_STAT_FERR_Pos) /*!< 0x00000002 */
# define USART_STAT_FERR USART_STAT_FERR_Msk /*!< Framing Error */
# define USART_STAT_NERR_Pos (2U)
# define USART_STAT_NERR_Msk (0x1U << USART_STAT_NERR_Pos) /*!< 0x00000004 */
# define USART_STAT_NERR USART_STAT_NERR_Msk /*!< Noise Error Flag */
# define USART_STAT_ORERR_Pos (3U)
# define USART_STAT_ORERR_Msk (0x1U << USART_STAT_ORERR_Pos) /*!< 0x00000008 */
# define USART_STAT_ORERR USART_STAT_ORERR_Msk /*!< OverRun Error */
# define USART_STAT_IDLEF_Pos (4U)
# define USART_STAT_IDLEF_Msk (0x1U << USART_STAT_IDLEF_Pos) /*!< 0x00000010 */
# define USART_STAT_IDLEF USART_STAT_IDLEF_Msk /*!< IDLE line detected */
# define USART_STAT_RBNE_Pos (5U)
# define USART_STAT_RBNE_Msk (0x1U << USART_STAT_RBNE_Pos) /*!< 0x00000020 */
# define USART_STAT_RBNE USART_STAT_RBNE_Msk /*!< Read Data Register Not Empty */
# define USART_STAT_TC_Pos (6U)
# define USART_STAT_TC_Msk (0x1U << USART_STAT_TC_Pos) /*!< 0x00000040 */
# define USART_STAT_TC USART_STAT_TC_Msk /*!< Transmission Complete */
# define USART_STAT_TBE_Pos (7U)
# define USART_STAT_TBE_Msk (0x1U << USART_STAT_TBE_Pos) /*!< 0x00000080 */
# define USART_STAT_TBE USART_STAT_TBE_Msk /*!< Transmit Data Register Empty */
# define USART_STAT_LBDF_Pos (8U)
# define USART_STAT_LBDF_Msk (0x1U << USART_STAT_LBDF_Pos) /*!< 0x00000100 */
# define USART_STAT_LBDF USART_STAT_LBDF_Msk /*!< LIN Break Detection Flag */
# define USART_STAT_CTSF_Pos (9U)
# define USART_STAT_CTSF_Msk (0x1U << USART_STAT_CTSF_Pos) /*!< 0x00000200 */
# define USART_STAT_CTSF USART_STAT_CTSF_Msk /*!< CTS Flag */
/******************* Bit definition for USART_DATA register *******************/
# define USART_DATA_DATA_Pos (0U)
# define USART_DATA_DATA_Msk (0x1FFU << USART_DATA_DATA_Pos) /*!< 0x000001FF */
# define USART_DATA_DATA USART_DATA_DATA_Msk /*!< Data value */
/****************** Bit definition for USART_BAUD register *******************/
# define USART_BAUD_FRADIV_Pos (0U)
# define USART_BAUD_FRADIV_Msk (0xFU << USART_BAUD_FRADIV_Pos) /*!< 0x0000000F */
# define USART_BAUD_FRADIV USART_BAUD_FRADIV_Msk /*!< Fraction of USARTDIV */
# define USART_BAUD_INTDIV_Pos (4U)
# define USART_BAUD_INTDIV_Msk (0xFFFU << USART_BAUD_INTDIV_Pos) /*!< 0x0000FFF0 */
# define USART_BAUD_INTDIV USART_BAUD_INTDIV_Msk /*!< Mantissa of USARTDIV */
/****************** Bit definition for USART_CTL0 register *******************/
# define USART_CTL0_SBKCMD_Pos (0U)
# define USART_CTL0_SBKCMD_Msk (0x1U << USART_CTL0_SBKCMD_Pos) /*!< 0x00000001 */
# define USART_CTL0_SBKCMD USART_CTL0_SBKCMD_Msk /*!< Send Break */
# define USART_CTL0_RWU_Pos (1U)
# define USART_CTL0_RWU_Msk (0x1U << USART_CTL0_RWU_Pos) /*!< 0x00000002 */
# define USART_CTL0_RWU USART_CTL0_RWU_Msk /*!< Receiver wakeup */
# define USART_CTL0_REN_Pos (2U)
# define USART_CTL0_REN_Msk (0x1U << USART_CTL0_REN_Pos) /*!< 0x00000004 */
# define USART_CTL0_REN USART_CTL0_REN_Msk /*!< Receiver Enable */
# define USART_CTL0_TEN_Pos (3U)
# define USART_CTL0_TEN_Msk (0x1U << USART_CTL0_TEN_Pos) /*!< 0x00000008 */
# define USART_CTL0_TEN USART_CTL0_TEN_Msk /*!< Transmitter Enable */
# define USART_CTL0_IDLEIE_Pos (4U)
# define USART_CTL0_IDLEIE_Msk (0x1U << USART_CTL0_IDLEIE_Pos) /*!< 0x00000010 */
# define USART_CTL0_IDLEIE USART_CTL0_IDLEIE_Msk /*!< IDLE Interrupt Enable */
# define USART_CTL0_RBNEIE_Pos (5U)
# define USART_CTL0_RBNEIE_Msk (0x1U << USART_CTL0_RBNEIE_Pos) /*!< 0x00000020 */
# define USART_CTL0_RBNEIE USART_CTL0_RBNEIE_Msk /*!< RXNE Interrupt Enable */
# define USART_CTL0_TCIE_Pos (6U)
# define USART_CTL0_TCIE_Msk (0x1U << USART_CTL0_TCIE_Pos) /*!< 0x00000040 */
# define USART_CTL0_TCIE USART_CTL0_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
# define USART_CTL0_TBEIE_Pos (7U)
# define USART_CTL0_TBEIE_Msk (0x1U << USART_CTL0_TBEIE_Pos) /*!< 0x00000080 */
# define USART_CTL0_TBEIE USART_CTL0_TBEIE_Msk /*!< PE Interrupt Enable */
# define USART_CTL0_PERRIE_Pos (8U)
# define USART_CTL0_PERRIE_Msk (0x1U << USART_CTL0_PERRIE_Pos) /*!< 0x00000100 */
# define USART_CTL0_PERRIE USART_CTL0_PERRIE_Msk /*!< PE Interrupt Enable */
# define USART_CTL0_PM_Pos (9U)
# define USART_CTL0_PM_Msk (0x1U << USART_CTL0_PM_Pos) /*!< 0x00000200 */
# define USART_CTL0_PM USART_CTL0_PM_Msk /*!< Parity Selection */
# define USART_CTL0_PCEN_Pos (10U)
# define USART_CTL0_PCEN_Msk (0x1U << USART_CTL0_PCEN_Pos) /*!< 0x00000400 */
# define USART_CTL0_PCEN USART_CTL0_PCEN_Msk /*!< Parity Control Enable */
# define USART_CTL0_WM_Pos (11U)
# define USART_CTL0_WM_Msk (0x1U << USART_CTL0_WM_Pos) /*!< 0x00000800 */
# define USART_CTL0_WM USART_CTL0_WM_Msk /*!< Wakeup method */
# define USART_CTL0_WL_Pos (12U)
# define USART_CTL0_WL_Msk (0x1U << USART_CTL0_WL_Pos) /*!< 0x00001000 */
# define USART_CTL0_WL USART_CTL0_WL_Msk /*!< Word length */
# define USART_CTL0_UEN_Pos (13U)
# define USART_CTL0_UEN_Msk (0x1U << USART_CTL0_UEN_Pos) /*!< 0x00002000 */
# define USART_CTL0_UEN USART_CTL0_UEN_Msk /*!< USART Enable */
/****************** Bit definition for USART_CTL1 register *******************/
# define USART_CTL1_ADDR_Pos (0U)
# define USART_CTL1_ADDR_Msk (0xFU << USART_CTL1_ADDR_Pos) /*!< 0x0000000F */
# define USART_CTL1_ADDR USART_CTL1_ADDR_Msk /*!< Address of the USART node */
# define USART_CTL1_LBLEN_Pos (5U)
# define USART_CTL1_LBLEN_Msk (0x1U << USART_CTL1_LBLEN_Pos) /*!< 0x00000020 */
# define USART_CTL1_LBLEN USART_CTL1_LBLEN_Msk /*!< LIN Break Detection Length */
# define USART_CTL1_LBDIE_Pos (6U)
# define USART_CTL1_LBDIE_Msk (0x1U << USART_CTL1_LBDIE_Pos) /*!< 0x00000040 */
# define USART_CTL1_LBDIE USART_CTL1_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
# define USART_CTL1_CLEN_Pos (8U)
# define USART_CTL1_CLEN_Msk (0x1U << USART_CTL1_CLEN_Pos) /*!< 0x00000100 */
# define USART_CTL1_CLEN USART_CTL1_CLEN_Msk /*!< Last Bit Clock pulse */
# define USART_CTL1_CPH_Pos (9U)
# define USART_CTL1_CPH_Msk (0x1U << USART_CTL1_CPH_Pos) /*!< 0x00000200 */
# define USART_CTL1_CPH USART_CTL1_CPH_Msk /*!< Clock Phase */
# define USART_CTL1_CPL_Pos (10U)
# define USART_CTL1_CPL_Msk (0x1U << USART_CTL1_CPL_Pos) /*!< 0x00000400 */
# define USART_CTL1_CPL USART_CTL1_CPL_Msk /*!< Clock Polarity */
# define USART_CTL1_CKEN_Pos (11U)
# define USART_CTL1_CKEN_Msk (0x1U << USART_CTL1_CKEN_Pos) /*!< 0x00000800 */
# define USART_CTL1_CKEN USART_CTL1_CKEN_Msk /*!< Clock Enable */
# define USART_CTL1_STB_Pos (12U)
# define USART_CTL1_STB_Msk (0x3U << USART_CTL1_STB_Pos) /*!< 0x00003000 */
# define USART_CTL1_STB USART_CTL1_STB_Msk /*!< STOP[1:0] bits (STOP bits) */
# define USART_CTL1_STB_0 (0x1U << USART_CTL1_STB_Pos) /*!< 0x00001000 */
# define USART_CTL1_STB_1 (0x2U << USART_CTL1_STB_Pos) /*!< 0x00002000 */
# define USART_CTL1_LMEN_Pos (14U)
# define USART_CTL1_LMEN_Msk (0x1U << USART_CTL1_LMEN_Pos) /*!< 0x00004000 */
# define USART_CTL1_LMEN USART_CTL1_LMEN_Msk /*!< LIN mode enable */
/****************** Bit definition for USART_CTL2 register *******************/
# define USART_CTL2_ERRIE_Pos (0U)
# define USART_CTL2_ERRIE_Msk (0x1U << USART_CTL2_ERRIE_Pos) /*!< 0x00000001 */
# define USART_CTL2_ERRIE USART_CTL2_ERRIE_Msk /*!< Error Interrupt Enable */
# define USART_CTL2_IREN_Pos (1U)
# define USART_CTL2_IREN_Msk (0x1U << USART_CTL2_IREN_Pos) /*!< 0x00000002 */
# define USART_CTL2_IREN USART_CTL2_IREN_Msk /*!< IrDA mode Enable */
# define USART_CTL2_IRLP_Pos (2U)
# define USART_CTL2_IRLP_Msk (0x1U << USART_CTL2_IRLP_Pos) /*!< 0x00000004 */
# define USART_CTL2_IRLP USART_CTL2_IRLP_Msk /*!< IrDA Low-Power */
# define USART_CTL2_HDEN_Pos (3U)
# define USART_CTL2_HDEN_Msk (0x1U << USART_CTL2_HDEN_Pos) /*!< 0x00000008 */
# define USART_CTL2_HDEN USART_CTL2_HDEN_Msk /*!< Half-Duplex Selection */
# define USART_CTL2_NKEN_Pos (4U)
# define USART_CTL2_NKEN_Msk (0x1U << USART_CTL2_NKEN_Pos) /*!< 0x00000010 */
# define USART_CTL2_NKEN USART_CTL2_NKEN_Msk /*!< Smartcard NACK enable */
# define USART_CTL2_SCEN_Pos (5U)
# define USART_CTL2_SCEN_Msk (0x1U << USART_CTL2_SCEN_Pos) /*!< 0x00000020 */
# define USART_CTL2_SCEN USART_CTL2_SCEN_Msk /*!< Smartcard mode enable */
# define USART_CTL2_DENR_Pos (6U)
# define USART_CTL2_DENR_Msk (0x1U << USART_CTL2_DENR_Pos) /*!< 0x00000040 */
# define USART_CTL2_DENR USART_CTL2_DENR_Msk /*!< DMA Enable Receiver */
# define USART_CTL2_DENT_Pos (7U)
# define USART_CTL2_DENT_Msk (0x1U << USART_CTL2_DENT_Pos) /*!< 0x00000080 */
# define USART_CTL2_DENT USART_CTL2_DENT_Msk /*!< DMA Enable Transmitter */
# define USART_CTL2_RTSEN_Pos (8U)
# define USART_CTL2_RTSEN_Msk (0x1U << USART_CTL2_RTSEN_Pos) /*!< 0x00000100 */
# define USART_CTL2_RTSEN USART_CTL2_RTSEN_Msk /*!< RTS Enable */
# define USART_CTL2_CTSEN_Pos (9U)
# define USART_CTL2_CTSEN_Msk (0x1U << USART_CTL2_CTSEN_Pos) /*!< 0x00000200 */
# define USART_CTL2_CTSEN USART_CTL2_CTSEN_Msk /*!< CTS Enable */
# define USART_CTL2_CTSIE_Pos (10U)
# define USART_CTL2_CTSIE_Msk (0x1U << USART_CTL2_CTSIE_Pos) /*!< 0x00000400 */
# define USART_CTL2_CTSIE USART_CTL2_CTSIE_Msk /*!< CTS Interrupt Enable */
/****************** Bit definition for USART_GP register ******************/
# define USART_GP_PSC_Pos (0U)
# define USART_GP_PSC_Msk (0xFFU << USART_GP_PSC_Pos) /*!< 0x000000FF */
# define USART_GP_PSC USART_GP_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
# define USART_GP_PSC_0 (0x01U << USART_GP_PSC_Pos) /*!< 0x00000001 */
# define USART_GP_PSC_1 (0x02U << USART_GP_PSC_Pos) /*!< 0x00000002 */
# define USART_GP_PSC_2 (0x04U << USART_GP_PSC_Pos) /*!< 0x00000004 */
# define USART_GP_PSC_3 (0x08U << USART_GP_PSC_Pos) /*!< 0x00000008 */
# define USART_GP_PSC_4 (0x10U << USART_GP_PSC_Pos) /*!< 0x00000010 */
# define USART_GP_PSC_5 (0x20U << USART_GP_PSC_Pos) /*!< 0x00000020 */
# define USART_GP_PSC_6 (0x40U << USART_GP_PSC_Pos) /*!< 0x00000040 */
# define USART_GP_PSC_7 (0x80U << USART_GP_PSC_Pos) /*!< 0x00000080 */
# define USART_GP_GUAT_Pos (8U)
# define USART_GP_GUAT_Msk (0xFFU << USART_GP_GUAT_Pos) /*!< 0x0000FF00 */
# define USART_GP_GUAT USART_GP_GUAT_Msk /*!< Guard time value */
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/******************************************************************************/
/* */
/* Debug MCU */
/* */
/******************************************************************************/
/**************** Bit definition for DBGMCU_IDCODE register *****************/
# define DBGMCU_IDCODE_DEV_ID_Pos (0U)
# define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
# define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
# define DBGMCU_IDCODE_REV_ID_Pos (16U)
# define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
# define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
# define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
# define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
# define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
# define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
# define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
# define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
# define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
# define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
# define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
# define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
# define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
# define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
# define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
# define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
# define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
# define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
/****************** Bit definition for DBGMCU_CR register *******************/
# define DBGMCU_CR_DBG_SLEEP_Pos (0U)
# define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
# define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
# define DBGMCU_CR_DBG_STOP_Pos (1U)
# define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
# define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
# define DBGMCU_CR_DBG_STANDBY_Pos (2U)
# define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
# define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
# define DBGMCU_CR_TRACE_IOEN_Pos (5U)
# define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
# define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */
# define DBGMCU_CR_TRACE_MODE_Pos (6U)
# define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
# define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
# define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
# define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
# define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U)
# define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */
# define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
# define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U)
# define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */
# define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
# define DBGMCU_CR_DBG_TIM1_STOP_Pos (10U)
# define DBGMCU_CR_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM1_STOP_Pos) /*!< 0x00000400 */
# define DBGMCU_CR_DBG_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */
# define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U)
# define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */
# define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
# define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U)
# define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */
# define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
# define DBGMCU_CR_DBG_TIM4_STOP_Pos (13U)
# define DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM4_STOP_Pos) /*!< 0x00002000 */
# define DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
# define DBGMCU_CR_DBG_CAN1_STOP_Pos (14U)
# define DBGMCU_CR_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_CR_DBG_CAN1_STOP_Pos) /*!< 0x00004000 */
# define DBGMCU_CR_DBG_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP_Msk /*!< Debug CAN1 stopped when Core is halted */
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# define DBGMCU_CR_DBG_I2C0_SMBUS_TIMEOUT_Pos (15U)
# define DBGMCU_CR_DBG_I2C0_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C0_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */
# define DBGMCU_CR_DBG_I2C0_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C0_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
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# define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (16U)
# define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */
# define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
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# define DBGMCU_CR_DBG_TIM5_STOP_Pos (18U)
# define DBGMCU_CR_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM5_STOP_Pos) /*!< 0x00040000 */
# define DBGMCU_CR_DBG_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */
# define DBGMCU_CR_DBG_TIM6_STOP_Pos (19U)
# define DBGMCU_CR_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM6_STOP_Pos) /*!< 0x00080000 */
# define DBGMCU_CR_DBG_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
# define DBGMCU_CR_DBG_TIM7_STOP_Pos (20U)
# define DBGMCU_CR_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM7_STOP_Pos) /*!< 0x00100000 */
# define DBGMCU_CR_DBG_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
# define DBGMCU_CR_DBG_CAN2_STOP_Pos (21U)
# define DBGMCU_CR_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_CR_DBG_CAN2_STOP_Pos) /*!< 0x00200000 */
# define DBGMCU_CR_DBG_CAN2_STOP DBGMCU_CR_DBG_CAN2_STOP_Msk /*!< Debug CAN2 stopped when Core is halted */
# define DBGMCU_CR_DBG_TIM9_STOP_Pos (28U)
# define DBGMCU_CR_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM9_STOP_Pos) /*!< 0x10000000 */
# define DBGMCU_CR_DBG_TIM9_STOP DBGMCU_CR_DBG_TIM9_STOP_Msk /*!< Debug TIM9 stopped when Core is halted */
# define DBGMCU_CR_DBG_TIM10_STOP_Pos (29U)
# define DBGMCU_CR_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM10_STOP_Pos) /*!< 0x20000000 */
# define DBGMCU_CR_DBG_TIM10_STOP DBGMCU_CR_DBG_TIM10_STOP_Msk /*!< Debug TIM10 stopped when Core is halted */
# define DBGMCU_CR_DBG_TIM11_STOP_Pos (30U)
# define DBGMCU_CR_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM11_STOP_Pos) /*!< 0x40000000 */
# define DBGMCU_CR_DBG_TIM11_STOP DBGMCU_CR_DBG_TIM11_STOP_Msk /*!< Debug TIM11 stopped when Core is halted */
/******************************************************************************/
/* */
/* FLASH and Option Bytes Registers */
/* */
/******************************************************************************/
/******************* Bit definition for FLASH_ACR register ******************/
# define FLASH_ACR_LATENCY_Pos (0U)
# define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
# define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY[2:0] bits (Latency) */
# define FLASH_ACR_LATENCY_0 (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
# define FLASH_ACR_LATENCY_1 (0x2U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
# define FLASH_ACR_LATENCY_2 (0x4U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
# define FLASH_ACR_HLFCYA_Pos (3U)
# define FLASH_ACR_HLFCYA_Msk (0x1U << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */
# define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */
# define FLASH_ACR_PRFTBE_Pos (4U)
# define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */
# define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */
# define FLASH_ACR_PRFTBS_Pos (5U)
# define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */
# define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */
/****************** Bit definition for FLASH_KEYR register ******************/
# define FLASH_KEYR_FKEYR_Pos (0U)
# define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
# define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */
# define RDP_KEY_Pos (0U)
# define RDP_KEY_Msk (0xA5U << RDP_KEY_Pos) /*!< 0x000000A5 */
# define RDP_KEY RDP_KEY_Msk /*!< RDP Key */
# define FLASH_KEY1_Pos (0U)
# define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */
# define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */
# define FLASH_KEY2_Pos (0U)
# define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */
# define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */
/***************** Bit definition for FLASH_OPTKEYR register ****************/
# define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
# define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
# define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */
# define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
# define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
/****************** Bit definition for FLASH_SR register ********************/
# define FLASH_SR_BSY_Pos (0U)
# define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
# define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
# define FLASH_SR_PGERR_Pos (2U)
# define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */
# define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */
# define FLASH_SR_WRPRTERR_Pos (4U)
# define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */
# define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */
# define FLASH_SR_EOP_Pos (5U)
# define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */
# define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */
/******************* Bit definition for FLASH_CR register *******************/
# define FLASH_CR_PG_Pos (0U)
# define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
# define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */
# define FLASH_CR_PER_Pos (1U)
# define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
# define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */
# define FLASH_CR_MER_Pos (2U)
# define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
# define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */
# define FLASH_CR_OPTPG_Pos (4U)
# define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */
# define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */
# define FLASH_CR_OPTER_Pos (5U)
# define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */
# define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */
# define FLASH_CR_STRT_Pos (6U)
# define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */
# define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */
# define FLASH_CR_LOCK_Pos (7U)
# define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */
# define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */
# define FLASH_CR_OPTWRE_Pos (9U)
# define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */
# define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */
# define FLASH_CR_ERRIE_Pos (10U)
# define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */
# define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */
# define FLASH_CR_EOPIE_Pos (12U)
# define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */
# define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */
/******************* Bit definition for FLASH_AR register *******************/
# define FLASH_AR_FAR_Pos (0U)
# define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */
# define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */
/****************** Bit definition for FLASH_OBR register *******************/
# define FLASH_OBR_OPTERR_Pos (0U)
# define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */
# define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */
# define FLASH_OBR_RDPRT_Pos (1U)
# define FLASH_OBR_RDPRT_Msk (0x1U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */
# define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */
# define FLASH_OBR_IWDG_SW_Pos (2U)
# define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000004 */
# define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */
# define FLASH_OBR_nRST_STOP_Pos (3U)
# define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000008 */
# define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */
# define FLASH_OBR_nRST_STDBY_Pos (4U)
# define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */
# define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */
# define FLASH_OBR_USER_Pos (2U)
# define FLASH_OBR_USER_Msk (0x7U << FLASH_OBR_USER_Pos) /*!< 0x0000001C */
# define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */
# define FLASH_OBR_DATA0_Pos (10U)
# define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x0003FC00 */
# define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */
# define FLASH_OBR_DATA1_Pos (18U)
# define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0x03FC0000 */
# define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */
/****************** Bit definition for FLASH_WRPR register ******************/
# define FLASH_WRPR_WRP_Pos (0U)
# define FLASH_WRPR_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */
# define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */
/*----------------------------------------------------------------------------*/
/****************** Bit definition for FLASH_RDP register *******************/
# define FLASH_RDP_RDP_Pos (0U)
# define FLASH_RDP_RDP_Msk (0xFFU << FLASH_RDP_RDP_Pos) /*!< 0x000000FF */
# define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /*!< Read protection option byte */
# define FLASH_RDP_nRDP_Pos (8U)
# define FLASH_RDP_nRDP_Msk (0xFFU << FLASH_RDP_nRDP_Pos) /*!< 0x0000FF00 */
# define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /*!< Read protection complemented option byte */
/****************** Bit definition for FLASH_USER register ******************/
# define FLASH_USER_USER_Pos (16U)
# define FLASH_USER_USER_Msk (0xFFU << FLASH_USER_USER_Pos) /*!< 0x00FF0000 */
# define FLASH_USER_USER FLASH_USER_USER_Msk /*!< User option byte */
# define FLASH_USER_nUSER_Pos (24U)
# define FLASH_USER_nUSER_Msk (0xFFU << FLASH_USER_nUSER_Pos) /*!< 0xFF000000 */
# define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /*!< User complemented option byte */
/****************** Bit definition for FLASH_Data0 register *****************/
# define FLASH_DATA0_DATA0_Pos (0U)
# define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */
# define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data storage option byte */
# define FLASH_DATA0_nDATA0_Pos (8U)
# define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */
# define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< User data storage complemented option byte */
/****************** Bit definition for FLASH_Data1 register *****************/
# define FLASH_DATA1_DATA1_Pos (16U)
# define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */
# define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data storage option byte */
# define FLASH_DATA1_nDATA1_Pos (24U)
# define FLASH_DATA1_nDATA1_Msk (0xFFU << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */
# define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< User data storage complemented option byte */
/****************** Bit definition for FLASH_WRP0 register ******************/
# define FLASH_WRP0_WRP0_Pos (0U)
# define FLASH_WRP0_WRP0_Msk (0xFFU << FLASH_WRP0_WRP0_Pos) /*!< 0x000000FF */
# define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */
# define FLASH_WRP0_nWRP0_Pos (8U)
# define FLASH_WRP0_nWRP0_Msk (0xFFU << FLASH_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */
# define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */
/****************** Bit definition for FLASH_WRP1 register ******************/
# define FLASH_WRP1_WRP1_Pos (16U)
# define FLASH_WRP1_WRP1_Msk (0xFFU << FLASH_WRP1_WRP1_Pos) /*!< 0x00FF0000 */
# define FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */
# define FLASH_WRP1_nWRP1_Pos (24U)
# define FLASH_WRP1_nWRP1_Msk (0xFFU << FLASH_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
# define FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
/****************** Bit definition for FLASH_WRP2 register ******************/
# define FLASH_WRP2_WRP2_Pos (0U)
# define FLASH_WRP2_WRP2_Msk (0xFFU << FLASH_WRP2_WRP2_Pos) /*!< 0x000000FF */
# define FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
# define FLASH_WRP2_nWRP2_Pos (8U)
# define FLASH_WRP2_nWRP2_Msk (0xFFU << FLASH_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
# define FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
/****************** Bit definition for FLASH_WRP3 register ******************/
# define FLASH_WRP3_WRP3_Pos (16U)
# define FLASH_WRP3_WRP3_Msk (0xFFU << FLASH_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
# define FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
# define FLASH_WRP3_nWRP3_Pos (24U)
# define FLASH_WRP3_nWRP3_Msk (0xFFU << FLASH_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
# define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
/**
* @ }
*/
/**
* @ }
*/
/** @addtogroup Exported_macro
* @ {
*/
/****************************** ADC Instances *********************************/
# define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
( ( INSTANCE ) = = ADC2 ) )
# define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
# define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
# define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
/****************************** CAN Instances *********************************/
# define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
( ( INSTANCE ) = = CAN2 ) )
/****************************** CRC Instances *********************************/
# define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
/****************************** DAC Instances *********************************/
# define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
/****************************** DMA Instances *********************************/
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# define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA0_Channel0) || \
( ( INSTANCE ) = = DMA0_Channel1 ) | | \
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( ( INSTANCE ) = = DMA0_Channel2 ) | | \
( ( INSTANCE ) = = DMA0_Channel3 ) | | \
( ( INSTANCE ) = = DMA0_Channel4 ) | | \
( ( INSTANCE ) = = DMA0_Channel5 ) | | \
( ( INSTANCE ) = = DMA0_Channel6 ) | | \
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( ( INSTANCE ) = = DMA1_Channel0 ) | | \
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( ( INSTANCE ) = = DMA1_Channel1 ) | | \
( ( INSTANCE ) = = DMA1_Channel2 ) | | \
( ( INSTANCE ) = = DMA1_Channel3 ) | | \
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( ( INSTANCE ) = = DMA1_Channel4 ) )
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/******************************* GPIO Instances *******************************/
# define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
( ( INSTANCE ) = = GPIOB ) | | \
( ( INSTANCE ) = = GPIOC ) | | \
( ( INSTANCE ) = = GPIOD ) | | \
( ( INSTANCE ) = = GPIOE ) )
/**************************** GPIO Alternate Function Instances ***************/
# define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
/**************************** GPIO Lock Instances *****************************/
# define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
/******************************** I2C Instances *******************************/
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# define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C0) || \
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( ( INSTANCE ) = = I2C1 ) )
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/******************************* SMBUS Instances ******************************/
# define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
/******************************** I2S Instances *******************************/
# define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
( ( INSTANCE ) = = SPI3 ) )
/****************************** IWDG Instances ********************************/
# define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
/******************************** SPI Instances *******************************/
# define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
( ( INSTANCE ) = = SPI2 ) | | \
( ( INSTANCE ) = = SPI3 ) )
/****************************** START TIM Instances ***************************/
/****************************** TIM Instances *********************************/
# define IS_TIM_INSTANCE(INSTANCE)\
( ( ( INSTANCE ) = = TIM1 ) | | \
( ( INSTANCE ) = = TIM2 ) | | \
( ( INSTANCE ) = = TIM3 ) | | \
( ( INSTANCE ) = = TIM4 ) | | \
( ( INSTANCE ) = = TIM5 ) | | \
( ( INSTANCE ) = = TIM6 ) | | \
( ( INSTANCE ) = = TIM7 ) )
# define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
# define IS_TIM_CC1_INSTANCE(INSTANCE)\
( ( ( INSTANCE ) = = TIM1 ) | | \
( ( INSTANCE ) = = TIM2 ) | | \
( ( INSTANCE ) = = TIM3 ) | | \
( ( INSTANCE ) = = TIM4 ) | | \
( ( INSTANCE ) = = TIM5 ) )
# define IS_TIM_CC2_INSTANCE(INSTANCE)\
( ( ( INSTANCE ) = = TIM1 ) | | \
( ( INSTANCE ) = = TIM2 ) | | \
( ( INSTANCE ) = = TIM3 ) | | \
( ( INSTANCE ) = = TIM4 ) | | \
( ( INSTANCE ) = = TIM5 ) )
# define IS_TIM_CC3_INSTANCE(INSTANCE)\
( ( ( INSTANCE ) = = TIM1 ) | | \
( ( INSTANCE ) = = TIM2 ) | | \
( ( INSTANCE ) = = TIM3 ) | | \
( ( INSTANCE ) = = TIM4 ) | | \
( ( INSTANCE ) = = TIM5 ) )
# define IS_TIM_CC4_INSTANCE(INSTANCE)\
( ( ( INSTANCE ) = = TIM1 ) | | \
( ( INSTANCE ) = = TIM2 ) | | \
( ( INSTANCE ) = = TIM3 ) | | \
( ( INSTANCE ) = = TIM4 ) | | \
( ( INSTANCE ) = = TIM5 ) )
# define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
( ( ( INSTANCE ) = = TIM1 ) | | \
( ( INSTANCE ) = = TIM2 ) | | \
( ( INSTANCE ) = = TIM3 ) | | \
( ( INSTANCE ) = = TIM4 ) | | \
( ( INSTANCE ) = = TIM5 ) )
# define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
( ( ( INSTANCE ) = = TIM1 ) | | \
( ( INSTANCE ) = = TIM2 ) | | \
( ( INSTANCE ) = = TIM3 ) | | \
( ( INSTANCE ) = = TIM4 ) | | \
( ( INSTANCE ) = = TIM5 ) )
# define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
( ( ( INSTANCE ) = = TIM1 ) | | \
( ( INSTANCE ) = = TIM2 ) | | \
( ( INSTANCE ) = = TIM3 ) | | \
( ( INSTANCE ) = = TIM4 ) | | \
( ( INSTANCE ) = = TIM5 ) )
# define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
( ( ( INSTANCE ) = = TIM1 ) | | \
( ( INSTANCE ) = = TIM2 ) | | \
( ( INSTANCE ) = = TIM3 ) | | \
( ( INSTANCE ) = = TIM4 ) | | \
( ( INSTANCE ) = = TIM5 ) )
# define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
( ( ( INSTANCE ) = = TIM1 ) | | \
( ( INSTANCE ) = = TIM2 ) | | \
( ( INSTANCE ) = = TIM3 ) | | \
( ( INSTANCE ) = = TIM4 ) | | \
( ( INSTANCE ) = = TIM5 ) )
# define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
( ( ( INSTANCE ) = = TIM1 ) | | \
( ( INSTANCE ) = = TIM2 ) | | \
( ( INSTANCE ) = = TIM3 ) | | \
( ( INSTANCE ) = = TIM4 ) | | \
( ( INSTANCE ) = = TIM5 ) )
# define IS_TIM_XOR_INSTANCE(INSTANCE)\
( ( ( INSTANCE ) = = TIM1 ) | | \
( ( INSTANCE ) = = TIM2 ) | | \
( ( INSTANCE ) = = TIM3 ) | | \
( ( INSTANCE ) = = TIM4 ) | | \
( ( INSTANCE ) = = TIM5 ) )
# define IS_TIM_MASTER_INSTANCE(INSTANCE)\
( ( ( INSTANCE ) = = TIM1 ) | | \
( ( INSTANCE ) = = TIM2 ) | | \
( ( INSTANCE ) = = TIM3 ) | | \
( ( INSTANCE ) = = TIM4 ) | | \
( ( INSTANCE ) = = TIM5 ) | | \
( ( INSTANCE ) = = TIM6 ) | | \
( ( INSTANCE ) = = TIM7 ) )
# define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
( ( ( INSTANCE ) = = TIM1 ) | | \
( ( INSTANCE ) = = TIM2 ) | | \
( ( INSTANCE ) = = TIM3 ) | | \
( ( INSTANCE ) = = TIM4 ) | | \
( ( INSTANCE ) = = TIM5 ) )
# define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
( ( ( INSTANCE ) = = TIM1 ) | | \
( ( INSTANCE ) = = TIM2 ) | | \
( ( INSTANCE ) = = TIM3 ) | | \
( ( INSTANCE ) = = TIM4 ) | | \
( ( INSTANCE ) = = TIM5 ) )
# define IS_TIM_BREAK_INSTANCE(INSTANCE)\
( ( INSTANCE ) = = TIM1 )
# define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
( ( ( ( INSTANCE ) = = TIM1 ) & & \
( ( ( CHANNEL ) = = TIM_CHANNEL_1 ) | | \
( ( CHANNEL ) = = TIM_CHANNEL_2 ) | | \
( ( CHANNEL ) = = TIM_CHANNEL_3 ) | | \
( ( CHANNEL ) = = TIM_CHANNEL_4 ) ) ) \
| | \
( ( ( INSTANCE ) = = TIM2 ) & & \
( ( ( CHANNEL ) = = TIM_CHANNEL_1 ) | | \
( ( CHANNEL ) = = TIM_CHANNEL_2 ) | | \
( ( CHANNEL ) = = TIM_CHANNEL_3 ) | | \
( ( CHANNEL ) = = TIM_CHANNEL_4 ) ) ) \
| | \
( ( ( INSTANCE ) = = TIM3 ) & & \
( ( ( CHANNEL ) = = TIM_CHANNEL_1 ) | | \
( ( CHANNEL ) = = TIM_CHANNEL_2 ) | | \
( ( CHANNEL ) = = TIM_CHANNEL_3 ) | | \
( ( CHANNEL ) = = TIM_CHANNEL_4 ) ) ) \
| | \
( ( ( INSTANCE ) = = TIM4 ) & & \
( ( ( CHANNEL ) = = TIM_CHANNEL_1 ) | | \
( ( CHANNEL ) = = TIM_CHANNEL_2 ) | | \
( ( CHANNEL ) = = TIM_CHANNEL_3 ) | | \
( ( CHANNEL ) = = TIM_CHANNEL_4 ) ) ) \
| | \
( ( ( INSTANCE ) = = TIM5 ) & & \
( ( ( CHANNEL ) = = TIM_CHANNEL_1 ) | | \
( ( CHANNEL ) = = TIM_CHANNEL_2 ) | | \
( ( CHANNEL ) = = TIM_CHANNEL_3 ) | | \
( ( CHANNEL ) = = TIM_CHANNEL_4 ) ) ) )
# define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
( ( ( INSTANCE ) = = TIM1 ) & & \
( ( ( CHANNEL ) = = TIM_CHANNEL_1 ) | | \
( ( CHANNEL ) = = TIM_CHANNEL_2 ) | | \
( ( CHANNEL ) = = TIM_CHANNEL_3 ) ) )
# define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
( ( ( INSTANCE ) = = TIM1 ) | | \
( ( INSTANCE ) = = TIM2 ) | | \
( ( INSTANCE ) = = TIM3 ) | | \
( ( INSTANCE ) = = TIM4 ) | | \
( ( INSTANCE ) = = TIM5 ) )
# define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
( ( INSTANCE ) = = TIM1 )
# define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
( ( ( INSTANCE ) = = TIM1 ) | | \
( ( INSTANCE ) = = TIM2 ) | | \
( ( INSTANCE ) = = TIM3 ) | | \
( ( INSTANCE ) = = TIM4 ) | | \
( ( INSTANCE ) = = TIM5 ) )
# define IS_TIM_DMA_INSTANCE(INSTANCE)\
( ( ( INSTANCE ) = = TIM1 ) | | \
( ( INSTANCE ) = = TIM2 ) | | \
( ( INSTANCE ) = = TIM3 ) | | \
( ( INSTANCE ) = = TIM4 ) | | \
( ( INSTANCE ) = = TIM5 ) | | \
( ( INSTANCE ) = = TIM6 ) | | \
( ( INSTANCE ) = = TIM7 ) )
# define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
( ( ( INSTANCE ) = = TIM1 ) | | \
( ( INSTANCE ) = = TIM2 ) | | \
( ( INSTANCE ) = = TIM3 ) | | \
( ( INSTANCE ) = = TIM4 ) | | \
( ( INSTANCE ) = = TIM5 ) )
# define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
( ( INSTANCE ) = = TIM1 )
# define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
( ( INSTANCE ) = = TIM2 ) | | \
( ( INSTANCE ) = = TIM3 ) | | \
( ( INSTANCE ) = = TIM4 ) | | \
( ( INSTANCE ) = = TIM5 ) )
# define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
( ( INSTANCE ) = = TIM2 ) | | \
( ( INSTANCE ) = = TIM3 ) | | \
( ( INSTANCE ) = = TIM4 ) | | \
( ( INSTANCE ) = = TIM5 ) )
# define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U
/****************************** END TIM Instances *****************************/
/******************** USART Instances : Synchronous mode **********************/
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# define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART0) || \
( ( INSTANCE ) = = USART1 ) | | \
( ( INSTANCE ) = = USART2 ) )
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/******************** UART Instances : Asynchronous mode **********************/
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# define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART0) || \
( ( INSTANCE ) = = USART1 ) | | \
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( ( INSTANCE ) = = USART2 ) | | \
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( ( INSTANCE ) = = UART3 ) | | \
( ( INSTANCE ) = = UART4 ) )
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/******************** UART Instances : Half-Duplex mode **********************/
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# define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART0) || \
( ( INSTANCE ) = = USART1 ) | | \
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( ( INSTANCE ) = = USART2 ) | | \
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( ( INSTANCE ) = = UART3 ) | | \
( ( INSTANCE ) = = UART4 ) )
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/******************** UART Instances : LIN mode **********************/
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# define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART0) || \
( ( INSTANCE ) = = USART1 ) | | \
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( ( INSTANCE ) = = USART2 ) | | \
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( ( INSTANCE ) = = UART3 ) | | \
( ( INSTANCE ) = = UART4 ) )
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/****************** UART Instances : Hardware Flow control ********************/
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# define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART0) || \
( ( INSTANCE ) = = USART1 ) | | \
( ( INSTANCE ) = = USART2 ) )
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/********************* UART Instances : Smard card mode ***********************/
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# define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART0) || \
( ( INSTANCE ) = = USART1 ) | | \
( ( INSTANCE ) = = USART2 ) )
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/*********************** UART Instances : IRDA mode ***************************/
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# define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART0) || \
( ( INSTANCE ) = = USART1 ) | | \
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( ( INSTANCE ) = = USART2 ) | | \
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( ( INSTANCE ) = = UART3 ) | | \
( ( INSTANCE ) = = UART4 ) )
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/***************** UART Instances : Multi-Processor mode **********************/
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# define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART0) || \
( ( INSTANCE ) = = USART1 ) | | \
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( ( INSTANCE ) = = USART2 ) | | \
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( ( INSTANCE ) = = UART3 ) | | \
( ( INSTANCE ) = = UART4 ) )
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/***************** UART Instances : DMA mode available **********************/
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# define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART0) || \
( ( INSTANCE ) = = USART1 ) | | \
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( ( INSTANCE ) = = USART2 ) | | \
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( ( INSTANCE ) = = UART3 ) )
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/****************************** RTC Instances *********************************/
# define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
/**************************** WWDG Instances *****************************/
# define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
/****************************** USB Instances ********************************/
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# define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_USBFS)
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# define RCC_HSE_MIN 3000000U
# define RCC_HSE_MAX 25000000U
# define RCC_MAX_FREQUENCY 72000000U
/**
* @ }
*/
/******************************************************************************/
/* For a painless codes migration between the STM32F1xx device product */
/* lines, the aliases defined below are put in place to overcome the */
/* differences in the interrupt handlers and IRQn definitions. */
/* No need to update developed interrupt code when moving across */
/* product lines within the same STM32F1 Family */
/******************************************************************************/
/* Aliases for __IRQn */
# define ADC1_IRQn ADC1_2_IRQn
# define USB_LP_CAN1_RX0_IRQn CAN1_RX0_IRQn
# define USB_LP_IRQn CAN1_RX0_IRQn
# define USB_HP_CAN1_TX_IRQn CAN1_TX_IRQn
# define USB_HP_IRQn CAN1_TX_IRQn
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# define DMA1_Channel3_5_IRQn DMA1_Channel3_IRQn
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# define USBWakeUp_IRQn USBFS_WKUP_IRQn
# define CEC_IRQn USBFS_WKUP_IRQn
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# define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
# define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
# define TIM9_IRQn TIM1_BRK_IRQn
# define TIM11_IRQn TIM1_TRG_COM_IRQn
# define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
# define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
# define TIM10_IRQn TIM1_UP_IRQn
# define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
# define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
# define TIM6_DAC_IRQn TIM6_IRQn
/* Aliases for __IRQHandler */
# define ADC1_IRQHandler ADC1_2_IRQHandler
# define USB_LP_CAN1_RX0_IRQHandler CAN1_RX0_IRQHandler
# define USB_LP_IRQHandler CAN1_RX0_IRQHandler
# define USB_HP_CAN1_TX_IRQHandler CAN1_TX_IRQHandler
# define USB_HP_IRQHandler CAN1_TX_IRQHandler
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# define DMA1_Channel3_5_IRQHandler DMA1_Channel3_IRQHandler
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# define USBWakeUp_IRQHandler USBFS_WKUP_IRQHandler
# define CEC_IRQHandler USBFS_WKUP_IRQHandler
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# define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
# define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
# define TIM9_IRQHandler TIM1_BRK_IRQHandler
# define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
# define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
# define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
# define TIM10_IRQHandler TIM1_UP_IRQHandler
# define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
# define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
# define TIM6_DAC_IRQHandler TIM6_IRQHandler
/**
* @ }
*/
/**
* @ }
*/
# ifdef __cplusplus
}
# endif /* __cplusplus */
# endif /* __STM32F105xC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
