cfdbcfe8d9
Remove CAN peripheral not present on this device
2021-04-06 13:38:22 +02:00
8d45fbc68c
Revert AFIO USART remapping register changes
2021-04-06 13:38:22 +02:00
c9cbc6d03c
No DMA for UART4
2021-04-06 13:38:22 +02:00
9ffb8cf58c
Rename UARTx to start at 0
2021-04-06 13:38:22 +02:00
3edcc0f80b
Rename USARTx to start at 0
2021-04-06 13:38:22 +02:00
031cd8325f
Remove USART peripherals not present in this device
2021-04-06 13:38:22 +02:00
9ddf61ae87
Rename USART registers
2021-04-06 13:38:22 +02:00
22b8934b7f
Rename I2C2 -> I2C1
2021-04-06 13:38:22 +02:00
ff5541e6c7
Rename I2C1 -> I2C0
2021-04-06 13:38:22 +02:00
ef39596f92
Add i2c fast mode plus
2021-04-06 13:38:22 +02:00
1aa20a7fa6
Correct DMA channel macros to start from 0
2021-04-06 13:38:22 +02:00
7178909bb1
Remove STM32F1x specific checks
2021-04-06 13:38:22 +02:00
73949757f4
Add fast mode plus stub
2021-04-06 13:38:22 +02:00
0058d3df0b
Rename I2C registers, add fast mode plus register
2021-04-06 13:38:22 +02:00
5a3ca17dd3
Remove I2C3 peripheral, as it isn't present in this chip
2021-04-06 13:38:22 +02:00
6f1d0ca1b4
Rename missed register, fix rename bug, otg done
2021-04-06 13:38:22 +02:00
27551a2282
Rename OTG device registers
2021-04-06 13:38:22 +02:00
3839d682cf
Rename missing otg host registers
2021-04-06 13:38:22 +02:00
3ef423ca8f
Remove otg stepping, continue rename registers usbfs
2021-04-06 13:38:22 +02:00
05a0aab253
Remove OTG definitions, those are present in gd32_otg.h
2021-04-06 13:38:22 +02:00
9dace8a9ce
Rename otg -> usbfs
2021-04-06 13:38:22 +02:00
3a51ec0bf3
Rename OTG1 -> USBFS
2021-04-06 13:38:22 +02:00
b8976b4fb5
Remove USB HS peripheral, start rename registers
2021-04-06 13:38:22 +02:00
11e6646370
Remove SD card interface defines
2021-04-06 13:38:22 +02:00
29be2ac3c3
Rename AFIO register definitions
2021-04-06 13:38:22 +02:00
2da7835bde
Rename GPIO registers
2021-04-06 13:38:22 +02:00
6a3caa697a
GPIO Remove obsolete ports, rename registers
2021-04-06 13:38:22 +02:00
adb9afc02b
Rename DMA CNDTR CPAR CMAR registers
2021-04-06 13:38:22 +02:00
5cec991524
Rename DMA CCR -> CTL
2021-04-06 13:38:22 +02:00
51b420e395
DMA rename IFCR -> INTC
2021-04-06 13:38:22 +02:00
186264dece
Rename DMA ISR register to INTF
2021-04-06 13:38:22 +02:00
962770882f
Rename DMA interrupt flags
2021-04-06 13:38:22 +02:00
1d3f664311
Add renumbered dma channel definitions
2021-04-06 13:38:22 +02:00
92646d6824
Rename DMA2 -> DMA1 and channels to start at zero
2021-04-06 13:38:22 +02:00
161449d7c3
Rename DMA1 -> DMA0 and channels to start at zero
2021-04-06 13:38:22 +02:00
f53e5a8b44
Remove DMA features not found on gd32vf103
2021-04-06 13:38:21 +02:00
7d90a998bf
Sort and deduplicate trigger handlers
2021-04-06 13:38:21 +02:00
352a6021f1
Rename stm32_ to gd32_ , remove obsolete tim headers
2021-04-06 13:38:21 +02:00
73336cf3b6
Increase idle stacksize, add isr locking/unlocking
2021-04-06 13:38:21 +02:00
a9a4e46916
Replace STM32_ with GD32_
2021-04-06 13:38:21 +02:00
3467aa8ffe
Add STM32 HAL Drivers, already adjusted for eclic interrupts
2021-04-06 13:38:21 +02:00
ecf1e48c89
Add platform makefile
2021-04-06 13:38:21 +02:00
6b195cfc59
Add GD32 registry STM32 renames will follow
2021-04-06 13:38:21 +02:00
479375a731
Add eclic system reset
2021-04-06 13:38:21 +02:00
a44a68bf7d
Add eclic interrupt driver
2021-04-06 13:38:21 +02:00
5abb73e524
Migrate port and startup code to nmsis
2021-04-06 13:38:21 +02:00
bb7a299638
Add RISC-V ECLIC startup and port files
2021-04-06 13:38:21 +02:00
b729125bdd
Add Nucleisys NMSIS sources
2021-04-06 13:38:21 +02:00
2eb784da6d
MIMXRT1062/LLD/USBHSv1: increase USB_DEVICE_CONFIG_ENDPOINTS
...
It should match USB_MAX_ENDPOINTS, but cannot be defined to be USB_MAX_ENDPOINTS
without modifying other NXP SDK files, which I would like to avoid for easier
maintenance.
Instead, we add a preprocessor check where we have both of them defined and
ensure that they match this way :)
2021-04-05 09:00:40 +02:00
a8a9e75aec
branch usb_device_config.h from new project wizard template
...
no changes yet
2021-04-05 08:51:39 +02:00
Stefan Kerkmann
Michael Stapelberg