All individual RP2040 PWM channels are mapped onto distinct ChibiOS PWM
drivers, as this fits driver model which wants an independent timer per
driver.
There were two problems with the previous pin assignments:
1. Due to a copy-and-past error, the pins 13 and 14 were mapped as AF for all ports instead of GPIOA (for SWD) only.
2. All free pins were assigned as analog inputs. This limits the maximum input voltage to +4V (see STM32F411xE datasheet, Table 11), making otherwise 5V-tolerant pins prone to latch-up.
* import helper header
* seperate usb buf init
* move usb init in chibios driver
handle the address set in a more elegant way
* clean up some code
move through sn32_usb
use macros for ep dir
* handle the setup interrupt
* report back the frame no
wake up directly
* further deviate from usbhw.c
call registers directly
use chibios for reset
interrupt party time
* flag update
* switch n/ack to simple macros
* even more native
* bye sonix mess
* bring functions up to the docs
* usb stop, setup error handling
* further cleanup
remove dead code
cleanup headers
add missing connect/dc functionality
bring ep0 init to platform correct
* usb restart is now working
* attempt to fix wakeup
* no more delay on init
* fix the usb wakeup
* improve the wakeup
* make sure the direction is not set before init
* only mess with one ep
* need to enable the bus override too in order to control it
* driver block checks
* allow wakeup time override
* dynamic sram allocation
* remove useless ep naming
* testing: remove packet limits
* guard all i/o ops
* better wakeup/suspend handling
* remove dead code
* code cleanup
* make sure all ep's are handled
When starting a receive operation on an out endpoint it has to be
configured before the out interrupt occurs, or otherwise a sequence
error is the result.
* sn32: 2xx: centralize peripheral clock functions
* sn32: export HCLK for all boards
* sn32: support tickless mode for systick
* sn32: CT: cleanup inclusions
* Revert "sn32: export HCLK for all boards"
This reverts commit 1cae8892e3ce908ef89774a7e83bb921ecd810fc.
* sn32: export HCLK in hal level
* ST: inherit the SN32_HCLK
* 2xx lld: include ct header
* ST: fix systime type
* ST: interrupt should be disabled on init
* st: cleanup
* debug it
* Revert "debug it"
This reverts commit 1dd78e81019aa1233f3402ed251428085470ab79.
* sn32f2xx: make sure clocks match and proper timer init
* add more checks
* always read 32 bits from the counter
* read the first 16 bits directly
* systime_t is 16bits, but MR0 lives in a 32bit register
* testing: use ILRC
* testing: hack
* Revert "testing: hack"
This reverts commit 3821173dd9a6180e3f91a3e81e73e9f92385e273.
* Revert "testing: use ILRC"
we can't do this because hardware limits
This reverts commit 19d3ffefbce8cdd5cd34859cd8befccda6353e58.
* fix assert
* test: hardcode it
* Revert "test: hardcode it"
This reverts commit a75777c44d12844eb0be44c650a1de1602cadaed.
* add preliminary support for the whole SN32F2XX series
* unify CMSIS support, no more ugly hacks
* rename the unified hal to SN32F2XX
* common header amongst the hal, points to device
* add board files for the series
* 240 gets to keep it's own hal for now
* [sn32] ct16: further chibios integration
general purpose and pwm driver
also introduce a reset function
* build ct16 driver
* [sn32] have some isr handling
* 240: config the board for pwm
* Revert "240: config the board for pwm"
probably best to do in pwm driver
This reverts commit c09059a8ba60ea1832ea14f4d557bd8e22df3fd7.
* ct: logic fix. remove unecessary include
* ct: typos + use notifications
* ct: the periodic notification should not stop the timer
* ct: pfpa assignment
* ct: pwm: enable channel only if configured as active
* ct: pwm: periodic tic should track the timer
* derp
* ct: our chip supports IRQ priority level [0-3]
* isr: use the appropriate priority for each device
* ct: pwm: actually handle the channels
* ct: we define the # of channels already so..
* isr: we handle this on the specific drivers
disable for now
* ct: pwm: don't override TC. Call a counter reset
* ct: pwm: Set the prescaler properly
PRE is the max value of PC. PC increments on every tick.
When PC reaches PRE, TC increments and the timer overflows
Periodic timer is software controlled
* ct: gpt: PRE is the interval. Call a counter reset
* ct: Rename reset funtion to be more precise
* ct: pwm: Invert the channel disable logic
* ct: pwm: autoreload on period match
* ct: pwm: we only care for the last 25bits of IC
* ct: gpt: we only care for the last 25bits of IC
* ct: pwm: init config as hw defaults
* ct: pwm: mr24 is the driver callback
* Revert "isr: we handle this on the specific drivers"
This reverts commit 9ca061f170d9523d0e4e42011881f3d0b8dd1599.
* Revert "[sn32] have some isr handling"
This reverts commit cf45020072ea828522f2de2f6d5d2521398a61cd.
* ct: pwm: update the periodic notification
* ct: gpt: use MR0
* ct: priority bump
* Revert "ct: priority bump"
3 is probably fine
This reverts commit d2a861097a43f367ffbd15f6fc5d6747d9f14426.
* sn32: pwm: introduce oneshot mode
enable it with by defining SN32_PWM_USE_ONESHOT TRUE
* pwm: reset: we have a function for that
* explicitly enable pwm channels
* bugfix for bad PWM_OUTPUT_MASK
if it is DISABLED, bad things occur
Only ever identify and use PWM_OUTPUT_ACTIVE_HIGH and PWM_OUTPUT_ACTIVE_LOW
* periodic notification: clear and disable it
* we definitely need this to only run at first init
* ct: pwm: support 23 channel chips
* ct: support 240b and 260 chips
* make the macro check build
* pwm: correctly set the logic level
* pwm: speed improvements
in our shared matrix driver, we only care about the last callback.
having a shortcut to that if no other flag is raised will improve speed
+ident and comment
* Revert "pwm: speed improvements"
This reverts commit e143544b807dd860d26548c803503521450822b8.
Stefan Kerkmann
fauxpark
Fabien Poussin
Joy
Tim Rheinfels
dexter93
Hanya
1Conan
IsaacDynamo
Jack
stdvar